# IBM_PROLOG_BEGIN_TAG 
# This is an automatically generated prolog. 
#  
# bos720 src/bos/usr/sbin/perf/pmapi/events/POWERCOMPAT.dms 1.1.2.2 
#  
# Licensed Materials - Property of IBM 
#  
# COPYRIGHT International Business Machines Corp. 2009,2012 
# All Rights Reserved 
#  
# US Government Users Restricted Rights - Use, duplication or 
# disclosure restricted by GSA ADP Schedule Contract with IBM Corp. 
#  
# IBM_PROLOG_END_TAG 
# Global variables
CACHE_LINE_SIZE = 128;
MEM_LINE_SIZE   = 128;

# Derived metric descriptions
@PMD_RUN_CPI;Run cycles per run instruction
@@PM_RUN_CYC / PM_RUN_INST_CMPL
@@@group=General

@PMD_CYC_PER_GRP;Cycles per group
@@PM_CYC / PM_1PLUS_PPC_CMPL
@@@group=General

@PMD_RUN_CYCLES;Run cycles per cycle;%
@@PM_RUN_CYC / PM_CYC*100
@@@group=General

@PMD_CYC_GRP_DISP;Percentage Cycles a group dispatched;%
@@PM_1PLUS_PPC_DISP / PM_CYC * 100
@@@group=General

@PMD_DL1_ST_MISS_RATIO;Percentage of L1 store misses per L1 store ref;%
@@PM_ST_MISS_L1 / PM_ST_FIN  * 100
@@@group=General

@PMD_L1_ST_MISS_RATE;Percentage of L1 store misses per run instruction;%
@@PM_ST_MISS_L1 * 100 / PM_RUN_INST_CMPL
@@@group=General

@PMD_L1_LD_MISS_RATE;Percentage of L1 demand load misses per run instruction;%
@@PM_LD_MISS_L1 * 100 / PM_RUN_INST_CMPL
@@@group=General

@PMD_BR_MPRED_RATE;Branch misprediction rate;%
@@PM_BR_MPRED_CMPL / PM_RUN_INST_CMPL * 100
@@@group=General

@PMD_DLTB_MISS_RATE;% DTLB miss rate per inst;%
@@PM_DTLB_MISS / PM_RUN_INST_CMPL * 100
@@@group=General

@PMD_ITLB_MISS_RATE;% ITLB miss rate per inst;%
@@PM_ITLB_MISS / PM_RUN_INST_CMPL * 100
@@@group=General

@PMD_DERAT_MISS_RATE;DERAT Miss Rate (per run instruction)(%);%
@@PM_LSU_DERAT_MISS * 100 / PM_RUN_INST_CMPL
@@@group=General

@PMD_FLUSH_RATE;Flush rate (%);%
@@PM_FLUSH * 100 / PM_RUN_INST_CMPL
@@@group=General

@PMD_L2_LD_MISS_RATE;L2 demand Load Miss Rate (per run instruction)(%);%
@@PM_DATA_FROM_L2MISS * 100 / PM_RUN_INST_CMPL
@@@group=General

@PMD_L3_LD_MISS_RATE;L3 demand Load Miss Rate (per run instruction)(%);%
@@PM_DATA_FROM_L3MISS * 100 / PM_RUN_INST_CMPL
@@@group=General

@PMD_L1_INST_MISS_RATE;Instruction Cache Miss Rate (Per run Instruction)(%);%
@@PM_L1_ICACHE_MISS * 100 / PM_RUN_INST_CMPL
@@@group=General

@PMD_GCT_EMPTY_CPI;GCT empty cycles
@@PM_GCT_NOSLOT_CYC/PM_RUN_INST_CMPL
@@@group=CPI_Breakdown

@PMD_BASE_COMPLETION_CPI;Base Completion Cycles
@@PM_1PLUS_PPC_CMPL/PM_RUN_INST_CMPL
@@@group=CPI_Breakdown

@PMD_ST_PER_INST;PCT instruction stores
@@PM_ST_FIN  / PM_RUN_INST_CMPL
@@@group=Instruction_Mix

@PMD_DL1_RELOAD_FROM_L2_MISS_RATE;% of DL1 reloads from L2 per Inst;%
@@PM_DATA_FROM_L2MISS * 100 / PM_RUN_INST_CMPL
@@@group=dL1_Reloads_percentage_per_inst

@PMD_DL1_RELOAD_FROM_L3_MISS_RATE;% of DL1 reloads from L3 per Inst;%
@@PM_DATA_FROM_L3MISS * 100 / PM_RUN_INST_CMPL
@@@group=dL1_Reloads_percentage_per_inst

@PMD_DERAT_MISS_RATIO;DERAT Miss Ratio
@@PM_LSU_DERAT_MISS / PM_RUN_INST_CMPL
@@@group=Translation

@PMD_IERAT_MISS_RATE;IERAT miss rate (%);%
@@PM_IERAT_MISS * 100 / PM_RUN_INST_CMPL
@@@group=Translation

@PMD_DERAT_MISS_RELOAD;% of DERAT misses that result in an ERAT reload;%
@@PM_DTLB_MISS * 100 / PM_LSU_DERAT_MISS
@@@group=PTEG_Reloads_percentage_per_ref