{ IBM_PROLOG_BEGIN_TAG { This is an automatically generated prolog. { { bos72L src/bos/usr/sbin/perf/pmapi/events/POWER9.evs 1.4 { { { { OBJECT CODE ONLY SOURCE MATERIALS { { COPYRIGHT International Business Machines Corp. 2017,2018 { All Rights Reserved { { The source code for this program is not published or otherwise { divested of its trade secrets, irrespective of what has been { deposited with the U.S. Copyright Office. { { IBM_PROLOG_END_TAG 383,387,377,385,1,1 { counter 1} #0,u,g,n,n,n,PM_SUSPENDED,Counter OFF ##0000010000 Counter OFF #1,u,g,n,n,n,PM_CMPLU_STALL_LRQ_OTHER,Finish stall due to LRQ miscellaneous reasons, lost arbitration to LMQ slot, bank collisions, set prediction cleanup, set prediction multihit and others ##0000010004 Finish stall due to LRQ miscellaneous reasons, lost arbitration to LMQ slot, bank collisions, set prediction cleanup, set prediction multihit and others #2,u,g,n,n,n,PM_DISP_HELD,Dispatch Held ##0000010006 Dispatch Held #3,u,g,n,n,n,PM_RUN_SPURR,Run SPURR ##0000010008 Run SPURR #4,u,g,n,n,n,PM_PMC3_REWIND,PMC3 rewind event. A rewind happens when a speculative event (such as latency or CPI stack) is selected on PMC3 and the stall reason or reload source did not match the one programmed in PMC3. When this occurs, the count in PMC3 will not change. ##000001000A PMC3 rewind event. A rewind happens when a speculative event (such as latency or CPI stack) is selected on PMC3 and the stall reason or reload source did not match the one programmed in PMC3. When this occurs, the count in PMC3 will not change. #5,u,g,n,n,n,PM_PMC4_OVERFLOW,Overflow from counter 4 ##0000010010 Overflow from counter 4 #6,u,g,n,n,n,PM_DSLB_MISS,gate_and(sd_pc_c0_comp_valid AND sd_pc_c0_comp_thread(0:1)=tid,sd_pc_c0_comp_ppc_count(0:3)) + gate_and(sd_pc_c1_comp_valid AND sd_pc_c1_comp_thread(0:1)=tid,sd_pc_c1_comp_ppc_count(0:3)) ##0000010016 gate_and(sd_pc_c0_comp_valid AND sd_pc_c0_comp_thread(0:1)=tid,sd_pc_c0_comp_ppc_count(0:3)) + gate_and(sd_pc_c1_comp_valid AND sd_pc_c1_comp_thread(0:1)=tid,sd_pc_c1_comp_ppc_count(0:3)) #7,u,g,n,n,n,PM_IC_DEMAND_CYC,Icache miss demand cycles ##0000010018 Icache miss demand cycles #8,u,g,n,s,n,PM_LSU_SRQ_FULL_CYC,Cycles in which the Store Queue is full on all 4 slices. This is event is not per thread. All the threads will see the same count for this core resource ##000001001A Cycles in which the Store Queue is full on all 4 slices. This is event is not per thread. All the threads will see the same count for this core resource #9,u,g,n,n,n,PM_CMPLU_STALL_THRD,Completion Stalled because the thread was blocked ##000001001C Completion Stalled because the thread was blocked #10,u,g,n,n,n,PM_PMC4_REWIND,PMC4 Rewind Event ##0000010020 PMC4 Rewind Event #11,u,g,n,n,n,PM_PMC2_SAVED,PMC2 Rewind Value saved ##0000010022 PMC2 Rewind Value saved #12,u,g,n,n,n,PM_PMC5_OVERFLOW,Overflow from counter 5 ##0000010024 Overflow from counter 5 #13,u,g,n,n,n,PM_TABLEWALK_CYC,Cycles when an instruction tablewalk is active ##0000010026 Cycles when an instruction tablewalk is active #14,u,g,n,n,n,PM_STALL_END_ICT_EMPTY,The number a times the core transitioned from a stall to ICT-empty for this thread ##0000010028 The number a times the core transitioned from a stall to ICT-empty for this thread #15,u,g,n,n,n,PM_CMPLU_STALL_LARX,Finish stall because the NTF instruction was a larx waiting to be satisfied ##000001002A Finish stall because the NTF instruction was a larx waiting to be satisfied #16,u,g,n,n,n,PM_L1_DCACHE_RELOADED_ALL,L1 data cache reloaded for demand. If MMCR1[16] is 1, prefetches will be included as well ##000001002C L1 data cache reloaded for demand. If MMCR1[16] is 1, prefetches will be included as well #17,u,g,n,n,n,PM_LMQ_MERGE,A demand miss collides with a prefetch for the same line ##000001002E A demand miss collides with a prefetch for the same line #18,u,g,n,n,m,PM_MRK_INST_ISSUED,Marked instruction issued ##0000010132 Marked instruction issued #19,u,g,n,n,m,PM_MRK_BR_2PATH,marked branches which are not strongly biased ##0000010138 marked branches which are not strongly biased #20,u,g,n,n,n,PM_CMPLU_STALL_LSU_FIN,Finish stall because the NTF instruction was an LSU op (other than a load or a store) with all its dependencies met and just going through the LSU pipe to finish ##000001003A Finish stall because the NTF instruction was an LSU op (other than a load or a store) with all its dependencies met and just going through the LSU pipe to finish #21,u,g,n,n,n,PM_CMPLU_STALL_DMISS_L2L3,Completion stall by Dcache miss which resolved in L2/L3 ##000001003C Completion stall by Dcache miss which resolved in L2/L3 #22,u,g,n,n,m,PM_MRK_LD_MISS_EXPOSED_CYC,Marked Load exposed Miss (use edge detect to count #) ##000001013E Marked Load exposed Miss (use edge detect to count #) #23,u,g,n,n,n,PM_DATA_FROM_L2_NO_CONFLICT,The processor's data cache was reloaded from local core's L2 without conflict due to a demand load ##000001C040 The processor's data cache was reloaded from local core's L2 without conflict due to a demand load #24,u,g,n,n,n,PM_DATA_FROM_L2,The processor's data cache was reloaded from local core's L2 due to a demand load ##000001C042 The processor's data cache was reloaded from local core's L2 due to a demand load #25,u,g,n,n,n,PM_DATA_FROM_L3_NO_CONFLICT,The processor's data cache was reloaded from local core's L3 without conflict due to a demand load ##000001C044 The processor's data cache was reloaded from local core's L3 without conflict due to a demand load #26,u,g,n,n,n,PM_DATA_FROM_L31_SHR,The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to a demand load ##000001C046 The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to a demand load #27,u,g,n,n,n,PM_DATA_FROM_ON_CHIP_CACHE,The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a demand load ##000001C048 The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a demand load #28,u,g,n,n,n,PM_DATA_FROM_RL2L3_SHR,The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load ##000001C04A The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load #29,u,g,n,n,n,PM_DATA_FROM_LL4,The processor's data cache was reloaded from the local chip's L4 cache due to a demand load ##000001C04C The processor's data cache was reloaded from the local chip's L4 cache due to a demand load #30,u,g,n,n,n,PM_DATA_FROM_L2MISS_MOD,The processor's data cache was reloaded from a location other than the local core's L2 due to a demand load ##000001C04E The processor's data cache was reloaded from a location other than the local core's L2 due to a demand load #31,u,g,n,n,n,PM_INST_FROM_L2_NO_CONFLICT,The processor's Instruction cache was reloaded from local core's L2 without conflict due to an instruction fetch (not prefetch) ##0000014040 The processor's Instruction cache was reloaded from local core's L2 without conflict due to an instruction fetch (not prefetch) #32,u,g,n,n,n,PM_INST_FROM_L2,The processor's Instruction cache was reloaded from local core's L2 due to an instruction fetch (not prefetch) ##0000014042 The processor's Instruction cache was reloaded from local core's L2 due to an instruction fetch (not prefetch) #33,u,g,n,n,n,PM_INST_FROM_L3_NO_CONFLICT,The processor's Instruction cache was reloaded from local core's L3 without conflict due to an instruction fetch (not prefetch) ##0000014044 The processor's Instruction cache was reloaded from local core's L3 without conflict due to an instruction fetch (not prefetch) #34,u,g,n,n,n,PM_INST_FROM_L31_SHR,The processor's Instruction cache was reloaded with Shared (S) data from another core's L3 on the same chip due to an instruction fetch (not prefetch) ##0000014046 The processor's Instruction cache was reloaded with Shared (S) data from another core's L3 on the same chip due to an instruction fetch (not prefetch) #35,u,g,n,n,n,PM_INST_FROM_ON_CHIP_CACHE,The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to an instruction fetch (not prefetch) ##0000014048 The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to an instruction fetch (not prefetch) #36,u,g,n,n,n,PM_INST_FROM_RL2L3_SHR,The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch) ##000001404A The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch) #37,u,g,n,n,n,PM_INST_FROM_LL4,The processor's Instruction cache was reloaded from the local chip's L4 cache due to an instruction fetch (not prefetch) ##000001404C The processor's Instruction cache was reloaded from the local chip's L4 cache due to an instruction fetch (not prefetch) #38,u,g,n,n,n,PM_INST_FROM_L2MISS,The processor's Instruction cache was reloaded from a location other than the local core's L2 due to an instruction fetch (not prefetch) ##000001404E The processor's Instruction cache was reloaded from a location other than the local core's L2 due to an instruction fetch (not prefetch) #39,u,g,n,n,m,PM_MRK_DATA_FROM_L31_MOD_CYC,Duration in cycles to reload with Modified (M) data from another core's L3 on the same chip due to a marked load ##000001D140 Duration in cycles to reload with Modified (M) data from another core's L3 on the same chip due to a marked load #40,u,g,n,n,m,PM_MRK_DATA_FROM_L31_ECO_SHR_CYC,Duration in cycles to reload with Shared (S) data from another core's ECO L3 on the same chip due to a marked load ##000001D142 Duration in cycles to reload with Shared (S) data from another core's ECO L3 on the same chip due to a marked load #41,u,g,n,n,m,PM_MRK_DATA_FROM_L3_DISP_CONFLICT,The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a marked load ##000001D144 The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a marked load #42,u,g,n,n,m,PM_MRK_DATA_FROM_MEMORY_CYC,Duration in cycles to reload from a memory location including L4 from local remote or distant due to a marked load ##000001D146 Duration in cycles to reload from a memory location including L4 from local remote or distant due to a marked load #43,u,g,n,n,m,PM_MRK_DATA_FROM_RMEM,The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a marked load ##000001D148 The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a marked load #44,u,g,n,n,m,PM_MRK_DATA_FROM_RL2L3_MOD,The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load ##000001D14A The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load #45,u,g,n,n,m,PM_MRK_DATA_FROM_LL4,The processor's data cache was reloaded from the local chip's L4 cache due to a marked load ##000001D14C The processor's data cache was reloaded from the local chip's L4 cache due to a marked load #46,u,g,n,n,m,PM_MRK_DATA_FROM_OFF_CHIP_CACHE_CYC,Duration in cycles to reload either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load ##000001D14E Duration in cycles to reload either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load #47,u,g,n,n,n,PM_IPTEG_FROM_L2_NO_CONFLICT,A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a instruction side request ##0000015040 A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a instruction side request #48,u,g,n,n,n,PM_IPTEG_FROM_L2,A Page Table Entry was loaded into the TLB from local core's L2 due to a instruction side request ##0000015042 A Page Table Entry was loaded into the TLB from local core's L2 due to a instruction side request #49,u,g,n,n,n,PM_IPTEG_FROM_L3_NO_CONFLICT,A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a instruction side request ##0000015044 A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a instruction side request #50,u,g,n,n,n,PM_IPTEG_FROM_L31_SHR,A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a instruction side request ##0000015046 A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a instruction side request #51,u,g,n,n,n,PM_IPTEG_FROM_ON_CHIP_CACHE,A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a instruction side request ##0000015048 A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a instruction side request #52,u,g,n,n,n,PM_IPTEG_FROM_RL2L3_SHR,A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request ##000001504A A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request #53,u,g,n,n,n,PM_IPTEG_FROM_LL4,A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a instruction side request ##000001504C A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a instruction side request #54,u,g,n,n,n,PM_IPTEG_FROM_L2MISS,A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a instruction side request ##000001504E A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a instruction side request #55,u,g,n,n,n,PM_DPTEG_FROM_L2_NO_CONFLICT,A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000001E040 A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #56,u,g,n,n,n,PM_DPTEG_FROM_L2,A Page Table Entry was loaded into the TLB from local core's L2 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000001E042 A Page Table Entry was loaded into the TLB from local core's L2 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #57,u,g,n,n,n,PM_DPTEG_FROM_L3_NO_CONFLICT,A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000001E044 A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #58,u,g,n,n,n,PM_DPTEG_FROM_L31_SHR,A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000001E046 A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #59,u,g,n,n,n,PM_DPTEG_FROM_ON_CHIP_CACHE,A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000001E048 A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #60,u,g,n,n,n,PM_DPTEG_FROM_RL2L3_SHR,A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000001E04A A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #61,u,g,n,n,n,PM_DPTEG_FROM_LL4,A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000001E04C A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #62,u,g,n,n,n,PM_DPTEG_FROM_L2MISS,A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000001E04E A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #63,u,g,n,n,m,PM_MRK_DPTEG_FROM_L2_NO_CONFLICT,A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000001F140 A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #64,u,g,n,n,m,PM_MRK_DPTEG_FROM_L2,A Page Table Entry was loaded into the TLB from local core's L2 due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000001F142 A Page Table Entry was loaded into the TLB from local core's L2 due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #65,u,g,n,n,m,PM_MRK_DPTEG_FROM_L3_NO_CONFLICT,A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000001F144 A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #66,u,g,n,n,m,PM_MRK_DPTEG_FROM_L31_SHR,A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000001F146 A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #67,u,g,n,n,m,PM_MRK_DPTEG_FROM_ON_CHIP_CACHE,A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000001F148 A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #68,u,g,n,n,m,PM_MRK_DPTEG_FROM_RL2L3_SHR,A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000001F14A A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #69,u,g,n,n,m,PM_MRK_DPTEG_FROM_LL4,A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000001F14C A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #70,u,g,n,n,m,PM_MRK_DPTEG_FROM_L2MISS,A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000001F14E A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #71,u,g,n,n,n,PM_CHIP_PUMP_CPRED,Initial and Final Pump Scope was chip pump (prediction=correct) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) ##0000010050 Initial and Final Pump Scope was chip pump (prediction=correct) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) #72,u,g,n,n,n,PM_GRP_PUMP_MPRED_RTY,Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) ##0000010052 Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) #73,u,g,n,n,n,PM_PUMP_CPRED,Pump prediction correct. Counts across all types of pumps for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) ##0000010054 Pump prediction correct. Counts across all types of pumps for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) #74,u,g,n,n,n,PM_MEM_READ,Reads from Memory from this thread (includes data/inst/xlate/l1prefetch/inst prefetch). Includes L4 ##0000010056 Reads from Memory from this thread (includes data/inst/xlate/l1prefetch/inst prefetch). Includes L4 #75,u,g,n,n,n,PM_MEM_LOC_THRESH_IFU,Local Memory above threshold for IFU speculation control ##0000010058 Local Memory above threshold for IFU speculation control #76,u,g,n,n,n,PM_CMPLU_STALL_DFLONG,Finish stall because the NTF instruction was a multi-cycle instruction issued to the Decimal Floating Point execution pipe and waiting to finish. Includes decimal floating point instructions + 128 bit binary floating point instructions. Qualified by multicycle ##000001005A Finish stall because the NTF instruction was a multi-cycle instruction issued to the Decimal Floating Point execution pipe and waiting to finish. Includes decimal floating point instructions + 128 bit binary floating point instructions. Qualified by multicycle #77,u,g,n,n,n,PM_CMPLU_STALL_DP,Finish stall because the NTF instruction was a scalar instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Not qualified multicycle. Qualified by NOT vector ##000001005C Finish stall because the NTF instruction was a scalar instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Not qualified multicycle. Qualified by NOT vector #78,u,g,n,n,m,PM_MRK_FAB_RSP_RD_T_INTV,Sampled Read got a T intervention ##000001015E Sampled Read got a T intervention #79,u,g,n,n,n,PM_DATA_CHIP_PUMP_CPRED,Initial and Final Pump Scope was chip pump (prediction=correct) for a demand load ##000001C050 Initial and Final Pump Scope was chip pump (prediction=correct) for a demand load #80,u,g,n,n,n,PM_DATA_GRP_PUMP_MPRED_RTY,Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a demand load ##000001C052 Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a demand load #81,u,g,n,n,n,PM_DATA_PUMP_CPRED,Pump prediction correct. Counts across all types of pumps for a demand load ##000001C054 Pump prediction correct. Counts across all types of pumps for a demand load #82,u,g,n,n,n,PM_DERAT_MISS_4K,Data ERAT Miss (Data TLB Access) page size 4K ##000001C056 Data ERAT Miss (Data TLB Access) page size 4K #83,u,g,n,n,n,PM_MEM_LOC_THRESH_LSU_MED,Local memory above threshold for data prefetch ##000001C05E Local memory above threshold for data prefetch #84,u,g,n,n,n,PM_INST_CHIP_PUMP_CPRED,Initial and Final Pump Scope was chip pump (prediction=correct) for an instruction fetch ##0000014050 Initial and Final Pump Scope was chip pump (prediction=correct) for an instruction fetch #85,u,g,n,n,n,PM_INST_GRP_PUMP_MPRED_RTY,Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for an instruction fetch ##0000014052 Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for an instruction fetch #86,u,g,n,n,n,PM_INST_PUMP_CPRED,Pump prediction correct. Counts across all types of pumps for an instruction fetch ##0000014054 Pump prediction correct. Counts across all types of pumps for an instruction fetch #87,u,g,n,n,m,PM_MRK_DATA_FROM_L2_CYC,Duration in cycles to reload from local core's L2 due to a marked load ##0000014156 Duration in cycles to reload from local core's L2 due to a marked load #88,u,g,n,n,m,PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC,Duration in cycles to reload from local core's L2 without conflict due to a marked load ##0000014158 Duration in cycles to reload from local core's L2 without conflict due to a marked load #89,u,g,n,n,m,PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC,Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load ##000001415A Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load #90,u,g,n,n,m,PM_MRK_DATA_FROM_L3_MEPF_CYC,Duration in cycles to reload from local core's L3 without dispatch conflicts hit on Mepf state due to a marked load ##000001415C Duration in cycles to reload from local core's L3 without dispatch conflicts hit on Mepf state due to a marked load #91,u,g,n,n,m,PM_MRK_DATA_FROM_L3MISS_CYC,Duration in cycles to reload from a location other than the local core's L3 due to a marked load ##000001415E Duration in cycles to reload from a location other than the local core's L3 due to a marked load #92,u,g,n,n,m,PM_MRK_DATA_FROM_DL2L3_SHR,The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load ##000001D150 The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load #93,u,g,n,n,m,PM_MRK_DATA_FROM_DL4,The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a marked load ##000001D152 The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a marked load #94,u,g,n,n,m,PM_MRK_DATA_FROM_L21_SHR_CYC,Duration in cycles to reload with Shared (S) data from another core's L2 on the same chip due to a marked load ##000001D154 Duration in cycles to reload with Shared (S) data from another core's L2 on the same chip due to a marked load #95,u,g,n,n,m,PM_MRK_LD_MISS_L1_CYC,Marked ld latency ##000001D156 Marked ld latency #96,u,g,n,n,n,PM_DARQ0_10_12_ENTRIES,Cycles in which 10 or more DARQ entries (out of 12) are in use ##000001D058 Cycles in which 10 or more DARQ entries (out of 12) are in use #97,u,g,n,s,m,PM_MRK_RUN_CYC,Run cycles in which a marked instruction is in the pipeline ##000001D15E Run cycles in which a marked instruction is in the pipeline #98,u,g,n,n,m,PM_SYNC_MRK_PROBE_NOP,Marked probeNops which can cause synchronous interrupts ##0000015150 Marked probeNops which can cause synchronous interrupts #99,u,g,n,n,m,PM_SYNC_MRK_BR_LINK,Marked Branch and link branch that can cause a synchronous interrupt ##0000015152 Marked Branch and link branch that can cause a synchronous interrupt #100,u,g,n,n,m,PM_SYNC_MRK_L3MISS,Marked L3 misses that can throw a synchronous interrupt ##0000015154 Marked L3 misses that can throw a synchronous interrupt #101,u,g,n,n,m,PM_SYNC_MRK_FX_DIVIDE,Marked fixed point divide that can cause a synchronous interrupt ##0000015156 Marked fixed point divide that can cause a synchronous interrupt #102,u,g,n,n,m,PM_SYNC_MRK_L2HIT,Marked L2 Hits that can throw a synchronous interrupt ##0000015158 Marked L2 Hits that can throw a synchronous interrupt #103,u,g,n,n,m,PM_SYNC_MRK_L2MISS,Marked L2 Miss that can throw a synchronous interrupt ##000001515A Marked L2 Miss that can throw a synchronous interrupt #104,u,g,n,n,m,PM_SYNC_MRK_BR_MPRED,Marked Branch mispredict that can cause a synchronous interrupt ##000001515C Marked Branch mispredict that can cause a synchronous interrupt #105,u,g,n,n,n,PM_CMPLU_STALL_TEND,Finish stall because the NTF instruction was a tend instruction awaiting response from L2 ##000001E050 Finish stall because the NTF instruction was a tend instruction awaiting response from L2 #106,u,g,n,n,n,PM_CMPLU_STALL_SLB,Finish stall because the NTF instruction was awaiting L2 response for an SLB ##000001E052 Finish stall because the NTF instruction was awaiting L2 response for an SLB #107,u,g,n,n,n,PM_CMPLU_STALL,Nothing completed and ICT not empty ##000001E054 Nothing completed and ICT not empty #108,u,g,n,n,n,PM_CMPLU_STALL_FLUSH_ANY_THREAD,Cycles in which the NTC instruction is not allowed to complete because any of the 4 threads in the same core suffered a flush, which blocks completion ##000001E056 Cycles in which the NTC instruction is not allowed to complete because any of the 4 threads in the same core suffered a flush, which blocks completion #109,u,g,n,n,n,PM_STCX_FAIL,stcx failed ##000001E058 stcx failed #110,u,g,n,n,n,PM_CMPLU_STALL_ANY_SYNC,Cycles in which the NTC sync instruction (isync, lwsync or hwsync) is not allowed to complete ##000001E05A Cycles in which the NTC sync instruction (isync, lwsync or hwsync) is not allowed to complete #111,u,g,n,n,n,PM_CMPLU_STALL_NESTED_TBEGIN,Completion stall because the ISU is updating the TEXASR to keep track of the nested tbegin. This is a short delay, and it includes ROT ##000001E05C Completion stall because the ISU is updating the TEXASR to keep track of the nested tbegin. This is a short delay, and it includes ROT #112,u,g,n,n,m,PM_MRK_L2_TM_REQ_ABORT,TM abort ##000001E15E TM abort #113,u,g,n,n,m,PM_MRK_ST_L2DISP_TO_CMPL_CYC,cycles from L2 rc disp to l2 rc completion ##000001F150 cycles from L2 rc disp to l2 rc completion #114,u,g,n,n,m,PM_MRK_FAB_RSP_BKILL_CYC,cycles L2 RC took for a bkill ##000001F152 cycles L2 RC took for a bkill #115,u,g,n,n,n,PM_TLB_HIT,Number of times the TLB had the data required by the instruction. Applies to both HPT and RPT ##000001F054 Number of times the TLB had the data required by the instruction. Applies to both HPT and RPT #116,u,g,n,n,n,PM_RADIX_PWC_L2_PTE_FROM_L2,A Page Table Entry was reloaded to a level 2 page walk cache from the core's L2 data cache. This implies that level 3 and level 4 PWC accesses were not necessary for this translation ##000001F058 A Page Table Entry was reloaded to a level 2 page walk cache from the core's L2 data cache. This implies that level 3 and level 4 PWC accesses were not necessary for this translation #117,u,g,n,n,n,PM_RADIX_PWC_L4_PTE_FROM_L2,A Page Table Entry was reloaded to a level 4 page walk cache from the core's L2 data cache. This is the deepest level of PWC possible for a translation ##000001F05A A Page Table Entry was reloaded to a level 4 page walk cache from the core's L2 data cache. This is the deepest level of PWC possible for a translation #118,u,g,n,n,n,PM_RADIX_PWC_L3_PDE_FROM_L3,A Page Directory Entry was reloaded to a level 3 page walk cache from the core's L3 data cache ##000001F05C A Page Directory Entry was reloaded to a level 3 page walk cache from the core's L3 data cache #119,u,g,n,n,m,PM_MRK_PROBE_NOP_CMPL,Marked probeNops completed ##000001F15E Marked probeNops completed #120,u,g,n,n,n,PM_TM_TRANS_RUN_CYC,run cycles in transactional state ##0000010060 run cycles in transactional state #121,u,g,n,n,n,PM_LD_L3MISS_PEND_CYC,Cycles L3 miss was pending for this thread ##0000010062 Cycles L3 miss was pending for this thread #122,u,g,n,n,n,PM_ICT_NOSLOT_DISP_HELD_TBEGIN,the NTC instruction is being held at dispatch because it is a tbegin instruction and there is an older tbegin in the pipeline that must complete before the younger tbegin can dispatch ##0000010064 the NTC instruction is being held at dispatch because it is a tbegin instruction and there is an older tbegin in the pipeline that must complete before the younger tbegin can dispatch #123,u,g,n,n,n,PM_BRU_FIN,Branch Instruction Finished ##0000010068 Branch Instruction Finished #124,u,g,n,n,n,PM_NTC_ISSUE_HELD_DARQ_FULL,The NTC instruction is being held at dispatch because there are no slots in the DARQ for it ##000001006A The NTC instruction is being held at dispatch because there are no slots in the DARQ for it #125,u,g,n,n,n,PM_RUN_CYC_ST_MODE,Cycles run latch is set and core is in ST mode ##000001006C Cycles run latch is set and core is in ST mode #126,u,g,n,n,m,PM_MRK_BR_CMPL,Branch Instruction completed ##000001016E Branch Instruction completed #127,u,g,n,n,m,PM_MRK_INST_DISP,The thread has dispatched a randomly sampled marked instruction ##00000101E0 The thread has dispatched a randomly sampled marked instruction #128,u,g,n,n,m,PM_MRK_BR_TAKEN_CMPL,Marked Branch Taken completed ##00000101E2 Marked Branch Taken completed #129,u,g,n,n,m,PM_MRK_L1_ICACHE_MISS,sampled Instruction suffered an icache Miss ##00000101E4 sampled Instruction suffered an icache Miss #130,u,g,t,n,n,PM_THRESH_EXC_4096,Threshold counter exceed a count of 4096 ##00000101E6 Threshold counter exceed a count of 4096 #131,u,g,t,n,n,PM_THRESH_EXC_256,Threshold counter exceed a count of 256 ##00000101E8 Threshold counter exceed a count of 256 #132,u,g,n,n,m,PM_MRK_L1_RELOAD_VALID,Marked demand reload ##00000101EA Marked demand reload #133,u,g,t,n,n,PM_THRESH_MET,threshold exceeded ##00000101EC threshold exceeded #134,u,g,n,s,n,PM_CYC,Cycles ##00000100F0 Cycles #135,u,g,n,n,n,PM_1PLUS_PPC_CMPL,1 or more ppc insts finished ##00000100F2 1 or more ppc insts finished #136,u,g,n,n,n,PM_IERAT_RELOAD,Number of I-ERAT reloads ##00000100F6 Number of I-ERAT reloads #137,u,g,n,n,n,PM_ICT_NOSLOT_CYC,Number of cycles the ICT has no itags assigned to this thread ##00000100F8 Number of cycles the ICT has no itags assigned to this thread #138,u,g,n,s,n,PM_ANY_THRD_RUN_CYC,Cycles in which at least one thread has the run latch set ##00000100FA Cycles in which at least one thread has the run latch set #139,u,g,n,n,n,PM_LD_REF_L1,All L1 D cache load references counted at finish, gated by reject ##00000100FC All L1 D cache load references counted at finish, gated by reject #140,u,g,n,n,n,PM_INST_CMPL,PPC instructions completed ##00000100FE PPC instructions completed #141,u,g,n,n,n,PM_EE_OFF_EXT_INT,CyclesMSR[EE] is off and external interrupts are active ##0000002080 CyclesMSR[EE] is off and external interrupts are active #142,u,g,n,n,n,PM_FLUSH_DISP,Dispatch flush ##0000002880 Dispatch flush #143,u,g,n,n,n,PM_FLUSH_HB_RESTORE_CYC,Cycles in which no new instructions can be dispatched to the ICT after a flush. History buffer recovery ##0000002084 Cycles in which no new instructions can be dispatched to the ICT after a flush. History buffer recovery #144,u,g,n,n,n,PM_ISYNC,Isync completion count per thread ##0000002884 Isync completion count per thread #145,u,g,n,n,n,PM_FLUSH_DISP_SB,Dispatch Flush: Scoreboard ##0000002088 Dispatch Flush: Scoreboard #146,u,g,n,n,n,PM_FLUSH_DISP_TLBIE,Dispatch Flush: TLBIE ##0000002888 Dispatch Flush: TLBIE #147,u,g,n,n,n,PM_CLB_HELD,CLB (control logic block - indicates quadword fetch block) Hold: Any Reason ##000000208C CLB (control logic block - indicates quadword fetch block) Hold: Any Reason #148,u,g,n,n,n,PM_DISP_CLB_HELD_BAL,Dispatch/CLB Hold: Balance Flush ##000000288C Dispatch/CLB Hold: Balance Flush #149,u,g,n,n,n,PM_DISP_CLB_HELD_SB,Dispatch/CLB Hold: Scoreboard ##0000002090 Dispatch/CLB Hold: Scoreboard #150,u,g,n,n,n,PM_DISP_CLB_HELD_TLBIE,Dispatch Hold: Due to TLBIE ##0000002890 Dispatch Hold: Due to TLBIE #151,u,g,n,n,n,PM_TM_OUTER_TBEGIN,Completion time outer tbegin ##0000002094 Completion time outer tbegin #152,u,g,n,n,n,PM_TM_OUTER_TEND,Completion time outer tend ##0000002894 Completion time outer tend #153,u,g,n,n,n,PM_TM_NESTED_TEND,Completion time nested tend ##0000002098 Completion time nested tend #154,u,g,n,n,n,PM_TM_TABORT_TRECLAIM,Completion time tabortnoncd, tabortcd, treclaim ##0000002898 Completion time tabortnoncd, tabortcd, treclaim #155,u,g,n,n,n,PM_TM_FAV_TBEGIN,Dispatch time Favored tbegin ##000000209C Dispatch time Favored tbegin #156,u,g,n,n,n,PM_TM_NON_FAV_TBEGIN,Dispatch time non favored tbegin ##000000289C Dispatch time non favored tbegin #157,u,g,n,n,n,PM_TM_NESTED_TBEGIN,Completion Tm nested tbegin ##00000020A0 Completion Tm nested tbegin #158,u,g,n,n,n,PM_TM_TSUSPEND,TM suspend instruction completed ##00000028A0 TM suspend instruction completed #159,u,g,n,n,n,PM_TM_TRESUME,TM resume instruction completed ##00000020A4 TM resume instruction completed #160,u,g,n,n,n,PM_MRK_TEND_FAIL,Nested or not nested tend failed for a marked tend instruction ##00000028A4 Nested or not nested tend failed for a marked tend instruction #161,u,g,n,n,n,PM_TM_FAIL_FOOTPRINT_OVERFLOW,TM aborted because the tracking limit for transactional storage accesses was exceeded.. Asynchronous ##00000020A8 TM aborted because the tracking limit for transactional storage accesses was exceeded.. Asynchronous #162,u,g,n,n,n,PM_TM_FAIL_CONF_NON_TM,TM aborted because a conflict occurred with a non-transactional access by another processor ##00000028A8 TM aborted because a conflict occurred with a non-transactional access by another processor #163,u,g,n,n,n,PM_TM_FAIL_CONF_TM,TM aborted because a conflict occurred with another transaction. ##00000020AC TM aborted because a conflict occurred with another transaction. #164,u,g,n,n,n,PM_TM_FAIL_SELF,TM aborted because a self-induced conflict occurred in Suspended state, due to one of the following: a store to a storage location that was previously accessed transactionally ##00000028AC TM aborted because a self-induced conflict occurred in Suspended state, due to one of the following: a store to a storage location that was previously accessed transactionally #165,u,g,n,n,n,PM_LSU_FLUSH_NEXT,LSU flush next reported at flush time. Sometimes these also come with an exception ##00000020B0 LSU flush next reported at flush time. Sometimes these also come with an exception #166,u,g,n,n,n,PM_DISP_HELD_TBEGIN,This outer tbegin transaction cannot be dispatched until the previous tend instruction completes ##00000028B0 This outer tbegin transaction cannot be dispatched until the previous tend instruction completes #167,u,g,n,n,n,PM_ISU0_ISS_HOLD_ALL,All ISU rejects ##0000003080 All ISU rejects #168,u,g,n,n,n,PM_ISU2_ISS_HOLD_ALL,All ISU rejects ##0000003880 All ISU rejects #169,u,g,n,n,n,PM_ISU1_ISS_HOLD_ALL,All ISU rejects ##0000003084 All ISU rejects #170,u,g,n,n,n,PM_ISU3_ISS_HOLD_ALL,All ISU rejects ##0000003884 All ISU rejects #171,u,g,n,n,n,PM_LS0_LD_VECTOR_FIN,LS0 finished load vector op ##000000C080 LS0 finished load vector op #172,u,g,n,n,n,PM_LS1_LD_VECTOR_FIN,LS1 finished load vector op ##000000C880 LS1 finished load vector op #173,u,g,n,n,n,PM_LS2_LD_VECTOR_FIN,LS2 finished load vector op ##000000C084 LS2 finished load vector op #174,u,g,n,n,n,PM_LS3_LD_VECTOR_FIN,LS3 finished load vector op ##000000C884 LS3 finished load vector op #175,u,g,n,n,n,PM_LSU_DTLB_MISS_4K,Data TLB Miss page size 4K ##000000C088 Data TLB Miss page size 4K #176,u,g,n,n,n,PM_LSU_DTLB_MISS_64K,Data TLB Miss page size 64K ##000000C888 Data TLB Miss page size 64K #177,u,g,n,n,n,PM_LSU_DTLB_MISS_16M_2M,Data TLB Miss page size 16M (HPT) or 2M (Radix) ##000000C08C Data TLB Miss page size 16M (HPT) or 2M (Radix) #178,u,g,n,n,n,PM_LSU_DTLB_MISS_16G_1G,Data TLB Miss page size 16G (HPT) or 1G (Radix) ##000000C88C Data TLB Miss page size 16G (HPT) or 1G (Radix) #179,u,g,n,n,n,PM_LSU_STCX,STCX sent to nest, i.e. total ##000000C090 STCX sent to nest, i.e. total #180,u,g,n,n,n,PM_LSU_NCST,Asserts when a i=1 store op is sent to the nest. No record of issue pipe (LS0/LS1) is maintained so this is for both pipes. Probably don't need separate LS0 and LS1 ##000000C890 Asserts when a i=1 store op is sent to the nest. No record of issue pipe (LS0/LS1) is maintained so this is for both pipes. Probably don't need separate LS0 and LS1 #181,u,g,n,n,n,PM_LS0_UNALIGNED_LD,Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty ##000000C094 Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty #182,u,g,n,n,n,PM_LS1_UNALIGNED_LD,Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty ##000000C894 Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty #183,u,g,n,n,n,PM_LS2_UNALIGNED_LD,Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty ##000000C098 Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty #184,u,g,n,n,n,PM_LS3_UNALIGNED_LD,Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty ##000000C898 Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty #185,u,g,n,n,n,PM_LS0_LAUNCH_HELD_PREF,Number of times a load or store instruction was unable to launch/relaunch because a high priority prefetch used that relaunch cycle ##000000C09C Number of times a load or store instruction was unable to launch/relaunch because a high priority prefetch used that relaunch cycle #186,u,g,n,n,n,PM_LS1_LAUNCH_HELD_PREF,Number of times a load or store instruction was unable to launch/relaunch because a high priority prefetch used that relaunch cycle ##000000C89C Number of times a load or store instruction was unable to launch/relaunch because a high priority prefetch used that relaunch cycle #187,u,g,n,n,n,PM_LSU0_FALSE_LHS,False LHS match detected ##000000C0A0 False LHS match detected #188,u,g,n,n,n,PM_LSU1_FALSE_LHS,False LHS match detected ##000000C8A0 False LHS match detected #189,u,g,n,n,n,PM_LSU2_FALSE_LHS,False LHS match detected ##000000C0A4 False LHS match detected #190,u,g,n,n,n,PM_LSU3_FALSE_LHS,False LHS match detected ##000000C8A4 False LHS match detected #191,u,g,n,n,n,PM_LSU_FLUSH_CI,Load was not issued to LSU as a cache inhibited (non-cacheable) load but it was later determined to be cache inhibited ##000000C0A8 Load was not issued to LSU as a cache inhibited (non-cacheable) load but it was later determined to be cache inhibited #192,u,g,n,n,n,PM_LSU_FLUSH_ATOMIC,Quad-word loads (lq) are considered atomic because they always span at least 2 slices. If a snoop or store from another thread changes the data the load is accessing between the 2 or 3 pieces of the lq instruction, the lq will be flushed ##000000C8A8 Quad-word loads (lq) are considered atomic because they always span at least 2 slices. If a snoop or store from another thread changes the data the load is accessing between the 2 or 3 pieces of the lq instruction, the lq will be flushed #193,u,g,n,n,n,PM_LSU_FLUSH_EMSH,An ERAT miss was detected after a set-p hit. Erat tracker indicates fail due to tlbmiss and the instruction gets flushed because the instruction was working on the wrong address ##000000C0AC An ERAT miss was detected after a set-p hit. Erat tracker indicates fail due to tlbmiss and the instruction gets flushed because the instruction was working on the wrong address #194,u,g,n,n,n,PM_LSU_FLUSH_RELAUNCH_MISS,If a load that has already returned data and has to relaunch for any reason then gets a miss (erat, setp, data cache), it will often be flushed at relaunch time because the data might be inconsistent ##000000C8AC If a load that has already returned data and has to relaunch for any reason then gets a miss (erat, setp, data cache), it will often be flushed at relaunch time because the data might be inconsistent #195,u,g,n,n,n,PM_LSU_FLUSH_UE,Correctable ECC error on reload data, reported at critical data forward time ##000000C0B0 Correctable ECC error on reload data, reported at critical data forward time #196,u,g,n,n,n,PM_LSU_FLUSH_LHS,Effective Address alias flush : no EA match but Real Address match. If the data has not yet been returned for this load, the instruction will just be rejected, but if it has returned data, it will be flushed ##000000C8B0 Effective Address alias flush : no EA match but Real Address match. If the data has not yet been returned for this load, the instruction will just be rejected, but if it has returned data, it will be flushed #197,u,g,n,n,n,PM_LSU_FLUSH_WRK_ARND,LSU workaround flush. These flushes are setup with programmable scan only latches to perform various actions when the flush macro receives a trigger from the dbg macros. These actions include things like flushing the next op encountered for a particular thread or flushing the next op that is NTC op that is encountered on a particular slice. The kind of flush that the workaround is setup to perform is highly variable. ##000000C0B4 LSU workaround flush. These flushes are setup with programmable scan only latches to perform various actions when the flush macro receives a trigger from the dbg macros. These actions include things like flushing the next op encountered for a particular thread or flushing the next op that is NTC op that is encountered on a particular slice. The kind of flush that the workaround is setup to perform is highly variable. #198,u,g,n,n,n,PM_LSU_FLUSH_LHL_SHL,The instruction was flushed because of a sequential load/store consistency. If a load or store hits on an older load that has either been snooped (for loads) or has stale data (for stores). ##000000C8B4 The instruction was flushed because of a sequential load/store consistency. If a load or store hits on an older load that has either been snooped (for loads) or has stale data (for stores). #199,u,g,n,n,n,PM_LSU_FLUSH_SAO,A load-hit-load condition with Strong Address Ordering will have address compare disabled and flush ##000000C0B8 A load-hit-load condition with Strong Address Ordering will have address compare disabled and flush #200,u,g,n,n,n,PM_LSU_FLUSH_LARX_STCX,A larx is flushed because an older larx has an LMQ reservation for the same thread. A stcx is flushed because an older stcx is in the LMQ. The flush happens when the older larx/stcx relaunches ##000000C8B8 A larx is flushed because an older larx has an LMQ reservation for the same thread. A stcx is flushed because an older stcx is in the LMQ. The flush happens when the older larx/stcx relaunches #201,u,g,n,n,n,PM_LSU_FLUSH_OTHER,Other LSU flushes including: Sync (sync ack from L2 caused search of LRQ for oldest snooped load, This will either signal a Precise Flush of the oldest snooped loa or a Flush Next PPC) ##000000C0BC Other LSU flushes including: Sync (sync ack from L2 caused search of LRQ for oldest snooped load, This will either signal a Precise Flush of the oldest snooped loa or a Flush Next PPC) #202,u,g,n,n,n,PM_STCX_SUCCESS_CMPL,Number of stcx instructions that completed successfully ##000000C8BC Number of stcx instructions that completed successfully #203,u,g,n,n,n,PM_LSU0_LDMX_FIN,New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): "The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region." This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56]). ##000000D088 New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): "The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region." This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56]). #204,u,g,n,n,n,PM_LSU1_LDMX_FIN,New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): "The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region." This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56]). ##000000D888 New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): "The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region." This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56]). #205,u,g,n,n,n,PM_LSU2_LDMX_FIN,New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): "The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region." This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56]). ##000000D08C New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): "The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region." This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56]). #206,u,g,n,n,n,PM_LSU3_LDMX_FIN,New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): "The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region." This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56]). ##000000D88C New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): "The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region." This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56]). #207,u,g,n,n,n,PM_LS0_DC_COLLISIONS,Read-write data cache collisions ##000000D090 Read-write data cache collisions #208,u,g,n,n,n,PM_LS1_DC_COLLISIONS,Read-write data cache collisions ##000000D890 Read-write data cache collisions #209,u,g,n,n,n,PM_LS2_DC_COLLISIONS,Read-write data cache collisions ##000000D094 Read-write data cache collisions #210,u,g,n,n,n,PM_LS3_DC_COLLISIONS,Read-write data cache collisions ##000000D894 Read-write data cache collisions #211,u,g,n,n,n,PM_LSU_FLUSH_ATOMIC,Quad-word loads (lq) are considered atomic because they always span at least 2 slices. If a snoop or store from another thread changes the data the load is accessing between the 2 or 3 pieces of the lq instruction, the lq will be flushed ##000000D198 Quad-word loads (lq) are considered atomic because they always span at least 2 slices. If a snoop or store from another thread changes the data the load is accessing between the 2 or 3 pieces of the lq instruction, the lq will be flushed #212,u,g,n,n,n,PM_LSU_FLUSH_EMSH,An ERAT miss was detected after a set-p hit. Erat tracker indicates fail due to tlbmiss and the instruction gets flushed because the instruction was working on the wrong address ##000000D998 An ERAT miss was detected after a set-p hit. Erat tracker indicates fail due to tlbmiss and the instruction gets flushed because the instruction was working on the wrong address #213,u,g,n,n,n,PM_LSU_FLUSH_RELAUNCH_MISS,If a load that has already returned data and has to relaunch for any reason then gets a miss (erat, setp, data cache), it will often be flushed at relaunch time because the data might be inconsistent ##000000D19C If a load that has already returned data and has to relaunch for any reason then gets a miss (erat, setp, data cache), it will often be flushed at relaunch time because the data might be inconsistent #214,u,g,n,n,n,PM_LSU_FLUSH_UE,Correctable ECC error on reload data, reported at critical data forward time ##000000D99C Correctable ECC error on reload data, reported at critical data forward time #215,u,g,n,n,n,PM_LSU_FLUSH_LHS,Effective Address alias flush : no EA match but Real Address match. If the data has not yet been returned for this load, the instruction will just be rejected, but if it has returned data, it will be flushed ##000000D1A0 Effective Address alias flush : no EA match but Real Address match. If the data has not yet been returned for this load, the instruction will just be rejected, but if it has returned data, it will be flushed #216,u,g,n,n,n,PM_LSU_FLUSH_LHL_SHL,The instruction was flushed because of a sequential load/store consistency. If a load or store hits on an older load that has either been snooped (for loads) or has stale data (for stores). ##000000D9A0 The instruction was flushed because of a sequential load/store consistency. If a load or store hits on an older load that has either been snooped (for loads) or has stale data (for stores). #217,u,g,n,n,n,PM_LSU_FLUSH_SAO,A load-hit-load condition with Strong Address Ordering will have address compare disabled and flush ##000000D1A4 A load-hit-load condition with Strong Address Ordering will have address compare disabled and flush #218,u,g,n,n,n,PM_LSU_FLUSH_LARX_STCX,A larx is flushed because an older larx has an LMQ reservation for the same thread. A stcx is flushed because an older stcx is in the LMQ. The flush happens when the older larx/stcx relaunches ##000000D9A4 A larx is flushed because an older larx has an LMQ reservation for the same thread. A stcx is flushed because an older stcx is in the LMQ. The flush happens when the older larx/stcx relaunches #219,u,g,n,n,n,PM_DSLB_MISS,Data SLB Miss - Total of all segment sizes ##000000D0A8 Data SLB Miss - Total of all segment sizes #220,u,g,n,n,n,PM_ISLB_MISS,Instruction SLB Miss - Total of all segment sizes ##000000D8A8 Instruction SLB Miss - Total of all segment sizes #221,u,g,n,n,n,PM_SRQ_SYNC_CYC,A sync is in the S2Q (edge detect to count) ##000000D0AC A sync is in the S2Q (edge detect to count) #222,u,g,n,n,n,PM_LWSYNC, ##000000D8AC #223,u,g,n,n,n,PM_HWSYNC, ##000000D0B0 #224,u,g,n,n,n,PM_PTESYNC, ##000000D8B0 #225,u,g,n,n,n,PM_LSU0_SRQ_S0_VALID_CYC,Slot 0 of SRQ valid ##000000D0B4 Slot 0 of SRQ valid #226,u,g,n,n,n,PM_LSU0_LRQ_S0_VALID_CYC,Slot 0 of LRQ valid ##000000D8B4 Slot 0 of LRQ valid #227,u,g,n,s,n,PM_LSU_LMQ_FULL_CYC,Counts the number of cycles the LMQ is full ##000000D0B8 Counts the number of cycles the LMQ is full #228,u,g,n,n,n,PM_LSU0_LMQ_S0_VALID,Slot 0 of LMQ valid ##000000D8B8 Slot 0 of LMQ valid #229,u,g,n,s,n,PM_LSU0_1_LRQF_FULL_CYC,Counts the number of cycles the LRQF is full. LRQF is the queue that holds loads between finish and completion. If it fills up, instructions stay in LRQ until completion, potentially backing up the LRQ ##000000D0BC Counts the number of cycles the LRQF is full. LRQF is the queue that holds loads between finish and completion. If it fills up, instructions stay in LRQ until completion, potentially backing up the LRQ #230,u,g,n,s,n,PM_LSU2_3_LRQF_FULL_CYC,Counts the number of cycles the LRQF is full. LRQF is the queue that holds loads between finish and completion. If it fills up, instructions stay in LRQ until completion, potentially backing up the LRQ ##000000D8BC Counts the number of cycles the LRQF is full. LRQF is the queue that holds loads between finish and completion. If it fills up, instructions stay in LRQ until completion, potentially backing up the LRQ #231,u,g,n,s,n,PM_S2Q_FULL,Cycles during which the S2Q is full ##000000E080 Cycles during which the S2Q is full #232,u,g,n,n,n,PM_L1_SW_PREF,Software L1 Prefetches, including SW Transient Prefetches ##000000E880 Software L1 Prefetches, including SW Transient Prefetches #233,u,g,n,n,n,PM_LS0_ERAT_MISS_PREF,LS0 Erat miss due to prefetch ##000000E084 LS0 Erat miss due to prefetch #234,u,g,n,n,n,PM_LS1_ERAT_MISS_PREF,LS1 Erat miss due to prefetch ##000000E884 LS1 Erat miss due to prefetch #235,u,g,n,n,n,PM_LS2_ERAT_MISS_PREF,LS0 Erat miss due to prefetch ##000000E088 LS0 Erat miss due to prefetch #236,u,g,n,n,n,PM_LS3_ERAT_MISS_PREF,LS1 Erat miss due to prefetch ##000000E888 LS1 Erat miss due to prefetch #237,u,g,n,n,n,PM_LSU0_ERAT_HIT,Primary ERAT hit. There is no secondary ERAT ##000000E08C Primary ERAT hit. There is no secondary ERAT #238,u,g,n,n,n,PM_LSU1_ERAT_HIT,Primary ERAT hit. There is no secondary ERAT ##000000E88C Primary ERAT hit. There is no secondary ERAT #239,u,g,n,n,n,PM_LSU2_ERAT_HIT,Primary ERAT hit. There is no secondary ERAT ##000000E090 Primary ERAT hit. There is no secondary ERAT #240,u,g,n,n,n,PM_LSU3_ERAT_HIT,Primary ERAT hit. There is no secondary ERAT ##000000E890 Primary ERAT hit. There is no secondary ERAT #241,u,g,n,n,n,PM_LSU0_TM_L1_HIT,Load tm hit in L1 ##000000E094 Load tm hit in L1 #242,u,g,n,n,n,PM_LSU1_TM_L1_HIT,Load tm hit in L1 ##000000E894 Load tm hit in L1 #243,u,g,n,n,n,PM_LSU2_TM_L1_HIT,Load tm hit in L1 ##000000E098 Load tm hit in L1 #244,u,g,n,n,n,PM_LSU3_TM_L1_HIT,Load tm hit in L1 ##000000E898 Load tm hit in L1 #245,u,g,n,n,n,PM_LSU0_TM_L1_MISS,Load tm L1 miss ##000000E09C Load tm L1 miss #246,u,g,n,n,n,PM_LSU1_TM_L1_MISS,Load tm L1 miss ##000000E89C Load tm L1 miss #247,u,g,n,n,n,PM_LSU2_TM_L1_MISS,Load tm L1 miss ##000000E0A0 Load tm L1 miss #248,u,g,n,n,n,PM_LSU3_TM_L1_MISS,Load tm L1 miss ##000000E8A0 Load tm L1 miss #249,u,g,n,n,n,PM_TMA_REQ_L2, addrs only req to L2 only on the first one,Indication that Load footprint is not expanding ##000000E0A4 addrs only req to L2 only on the first one,Indication that Load footprint is not expanding #250,u,g,n,n,n,PM_TM_FAIL_TLBIE,Transaction failed because there was a TLBIE hit in the bloom filter ##000000E0AC Transaction failed because there was a TLBIE hit in the bloom filter #251,u,g,n,n,n,PM_TM_FAIL_TX_CONFLICT,Transactional conflict from LSU, gets reported to TEXASR ##000000E8AC Transactional conflict from LSU, gets reported to TEXASR #252,u,g,n,n,n,PM_TM_FAIL_NON_TX_CONFLICT,Non transactional conflict from LSU, gets reported to TEXASR ##000000E0B0 Non transactional conflict from LSU, gets reported to TEXASR #253,u,g,n,n,n,PM_TEND_PEND_CYC,TEND latency per thread ##000000E8B0 TEND latency per thread #254,u,g,n,n,n,PM_LS0_TM_DISALLOW,A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it ##000000E0B4 A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it #255,u,g,n,n,n,PM_LS1_TM_DISALLOW,A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it ##000000E8B4 A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it #256,u,g,n,n,n,PM_LS2_TM_DISALLOW,A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it ##000000E0B8 A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it #257,u,g,n,n,n,PM_LS3_TM_DISALLOW,A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it ##000000E8B8 A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it #258,u,g,n,n,n,PM_LS0_PTE_TABLEWALK_CYC,Cycles when a tablewalk is pending on this thread on table 0 ##000000E0BC Cycles when a tablewalk is pending on this thread on table 0 #259,u,g,n,n,n,PM_LS1_PTE_TABLEWALK_CYC,Cycles when a tablewalk is pending on this thread on table 1 ##000000E8BC Cycles when a tablewalk is pending on this thread on table 1 #260,u,g,n,n,n,PM_LSU_STCX_FAIL, ##000000F080 #261,u,g,n,s,n,PM_SNOOP_TLBIE,TLBIE snoop ##000000F880 TLBIE snoop #262,u,g,n,n,n,PM_PTE_PREFETCH,PTE prefetches ##000000F084 PTE prefetches #263,u,g,n,n,n,PM_TABLEWALK_CYC_PREF,tablewalk qualified for pte prefetches ##000000F884 tablewalk qualified for pte prefetches #264,u,g,n,n,n,PM_LSU0_STORE_REJECT,All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met ##000000F088 All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met #265,u,g,n,n,n,PM_LSU1_STORE_REJECT,All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met ##000000F888 All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met #266,u,g,n,n,n,PM_LSU2_STORE_REJECT,All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met ##000000F08C All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met #267,u,g,n,n,n,PM_LSU3_STORE_REJECT,All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met ##000000F88C All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met #268,u,g,n,n,n,PM_LSU0_L1_CAM_CANCEL,ls0 l1 tm cam cancel ##000000F090 ls0 l1 tm cam cancel #269,u,g,n,n,n,PM_LSU1_L1_CAM_CANCEL,ls1 l1 tm cam cancel ##000000F890 ls1 l1 tm cam cancel #270,u,g,n,n,n,PM_LSU2_L1_CAM_CANCEL,ls2 l1 tm cam cancel ##000000F094 ls2 l1 tm cam cancel #271,u,g,n,n,n,PM_LSU3_L1_CAM_CANCEL,ls3 l1 tm cam cancel ##000000F894 ls3 l1 tm cam cancel #272,u,g,n,n,n,PM_XLATE_HPT_MODE,LSU reports every cycle the thread is in HPT translation mode (as opposed to radix mode) ##000000F098 LSU reports every cycle the thread is in HPT translation mode (as opposed to radix mode) #273,u,g,n,n,n,PM_XLATE_RADIX_MODE,LSU reports every cycle the thread is in radix translation mode (as opposed to HPT mode) ##000000F898 LSU reports every cycle the thread is in radix translation mode (as opposed to HPT mode) #274,u,g,n,n,n,PM_XLATE_MISS,The LSU requested a line from L2 for translation. It may be satisfied from any source beyond L2. Includes speculative instructions. Includes instruction, prefetch and demand ##000000F89C The LSU requested a line from L2 for translation. It may be satisfied from any source beyond L2. Includes speculative instructions. Includes instruction, prefetch and demand #275,u,g,n,n,n,PM_DATA_STORE,All ops that drain from s2q to L2 containing data ##000000F0A0 All ops that drain from s2q to L2 containing data #276,u,g,n,n,n,PM_NON_DATA_STORE,All ops that drain from s2q to L2 and contain no data ##000000F8A0 All ops that drain from s2q to L2 and contain no data #277,u,g,n,n,n,PM_DC_PREF_HW_ALLOC,Prefetch stream allocated by the hardware prefetch mechanism ##000000F0A4 Prefetch stream allocated by the hardware prefetch mechanism #278,u,g,n,n,n,PM_DC_PREF_SW_ALLOC,Prefetch stream allocated by software prefetching ##000000F8A4 Prefetch stream allocated by software prefetching #279,u,g,n,n,n,PM_DC_PREF_CONF,A demand load referenced a line in an active prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. Includes forwards and backwards streams ##000000F0A8 A demand load referenced a line in an active prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. Includes forwards and backwards streams #280,u,g,n,n,n,PM_DC_PREF_FUZZY_CONF,A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up) ##000000F8A8 A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up) #281,u,g,n,n,n,PM_DC_PREF_STRIDED_CONF,A demand load referenced a line in an active strided prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. ##000000F0AC A demand load referenced a line in an active strided prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. #282,u,g,n,n,n,PM_DC_DEALLOC_NO_CONF,A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up) ##000000F8AC A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up) #283,u,g,n,n,n,PM_L3_LD_PREF,L3 load prefetch, sourced from a hardware or software stream, was sent to the nest ##000000F0B0 L3 load prefetch, sourced from a hardware or software stream, was sent to the nest #284,u,g,n,n,n,PM_L3_SW_PREF,L3 load prefetch, sourced from a software prefetch stream, was sent to the nest ##000000F8B0 L3 load prefetch, sourced from a software prefetch stream, was sent to the nest #285,u,g,n,n,n,PM_DC_PREF_CONS_ALLOC,Prefetch stream allocated in the conservative phase by either the hardware prefetch mechanism or software prefetch. The sum of this pair subtracted from the total number of allocs will give the total allocs in normal phase ##000000F0B4 Prefetch stream allocated in the conservative phase by either the hardware prefetch mechanism or software prefetch. The sum of this pair subtracted from the total number of allocs will give the total allocs in normal phase #286,u,g,n,n,n,PM_DC_PREF_XCONS_ALLOC,Prefetch stream allocated in the Ultra conservative phase by either the hardware prefetch mechanism or software prefetch ##000000F8B4 Prefetch stream allocated in the Ultra conservative phase by either the hardware prefetch mechanism or software prefetch #287,u,g,n,n,n,PM_LS0_UNALIGNED_ST,Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty ##000000F0B8 Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty #288,u,g,n,n,n,PM_LS1_UNALIGNED_ST,Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty ##000000F8B8 Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty #289,u,g,n,n,n,PM_LS2_UNALIGNED_ST,Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty ##000000F0BC Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty #290,u,g,n,n,n,PM_LS3_UNALIGNED_ST,Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty ##000000F8BC Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty #291,u,g,n,n,n,PM_INST_FROM_L1,Instruction fetches from L1. L1 instruction hit ##0000004080 Instruction fetches from L1. L1 instruction hit #292,u,g,n,n,n,PM_BANK_CONFLICT,Read blocked due to interleave conflict. The ifar logic will detect an interleave conflict and kill the data that was read that cycle. ##0000004880 Read blocked due to interleave conflict. The ifar logic will detect an interleave conflict and kill the data that was read that cycle. #293,u,g,n,n,n,PM_EAT_FULL_CYC,Cycles No room in EAT ##0000004084 Cycles No room in EAT #294,u,g,n,n,n,PM_IBUF_FULL_CYC,Cycles No room in ibuff ##0000004884 Cycles No room in ibuff #295,u,g,n,n,n,PM_IC_DEMAND_REQ,Demand Instruction fetch request ##0000004088 Demand Instruction fetch request #296,u,g,n,n,n,PM_IC_PREF_REQ,Instruction prefetch requests ##0000004888 Instruction prefetch requests #297,u,g,n,n,n,PM_L1_DEMAND_WRITE,Instruction Demand sectors written into IL1 ##000000408C Instruction Demand sectors written into IL1 #298,u,g,n,n,n,PM_IC_PREF_WRITE,Instruction prefetch written into IL1 ##000000488C Instruction prefetch written into IL1 #299,u,g,n,n,n,PM_IC_PREF_CANCEL_PAGE,Prefetch Canceled due to page boundary ##0000004090 Prefetch Canceled due to page boundary #300,u,g,n,n,n,PM_IC_PREF_CANCEL_HIT,Prefetch Canceled due to icache hit ##0000004890 Prefetch Canceled due to icache hit #301,u,g,n,n,n,PM_IC_PREF_CANCEL_L2,L2 Squashed a demand or prefetch request ##0000004094 L2 Squashed a demand or prefetch request #302,u,g,n,n,n,PM_IC_RELOAD_PRIVATE,Reloading line was brought in private for a specific thread. Most lines are brought in shared for all eight threads. If RA does not match then invalidates and then brings it shared to other thread. In P7 line brought in private , then line was invalidat ##0000004894 Reloading line was brought in private for a specific thread. Most lines are brought in shared for all eight threads. If RA does not match then invalidates and then brings it shared to other thread. In P7 line brought in private , then line was invalidat #303,u,g,n,n,n,PM_IC_DEMAND_L2_BHT_REDIRECT, L2 I cache demand request due to BHT redirect, branch redirect ( 2 bubbles 3 cycles) ##0000004098 L2 I cache demand request due to BHT redirect, branch redirect ( 2 bubbles 3 cycles) #304,u,g,n,n,n,PM_IC_DEMAND_L2_BR_REDIRECT, L2 I cache demand request due to branch Mispredict ( 15 cycle path) ##0000004898 L2 I cache demand request due to branch Mispredict ( 15 cycle path) #305,u,g,n,n,n,PM_BR_PRED,Conditional Branch Executed in which the HW predicted the Direction or Target. Includes taken and not taken and is counted at execution time ##000000409C Conditional Branch Executed in which the HW predicted the Direction or Target. Includes taken and not taken and is counted at execution time #306,u,g,n,n,n,PM_BR_CORECT_PRED_TAKEN_CMPL,Conditional Branch Completed in which the HW correctly predicted the direction as taken. Counted at completion time ##000000489C Conditional Branch Completed in which the HW correctly predicted the direction as taken. Counted at completion time #307,u,g,n,n,n,PM_BR_UNCOND,Unconditional Branch Completed. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was covenrted to a Resolve. ##00000040A0 Unconditional Branch Completed. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was covenrted to a Resolve. #308,u,g,n,n,n,PM_BR_PRED_PCACHE,Conditional branch completed that used pattern cache prediction ##00000048A0 Conditional branch completed that used pattern cache prediction #309,u,g,n,n,n,PM_BR_PRED_CCACHE,Conditional Branch Completed that used the Count Cache for Target Prediction ##00000040A4 Conditional Branch Completed that used the Count Cache for Target Prediction #310,u,g,n,n,n,PM_STOP_FETCH_PENDING_CYC,Fetching is stopped due to an incoming instruction that will result in a flush ##00000048A4 Fetching is stopped due to an incoming instruction that will result in a flush #311,u,g,n,n,n,PM_BR_PRED_LSTACK,Conditional Branch Completed that used the Link Stack for Target Prediction ##00000040A8 Conditional Branch Completed that used the Link Stack for Target Prediction #312,u,g,n,n,n,PM_DECODE_FUSION_LD_ST_DISP,32-bit displacement D-form and 16-bit displacement X-form ##00000048A8 32-bit displacement D-form and 16-bit displacement X-form #313,u,g,n,n,n,PM_BR_MPRED_CCACHE,Conditional Branch Completed that was Mispredicted due to the Count Cache Target Prediction ##00000040AC Conditional Branch Completed that was Mispredicted due to the Count Cache Target Prediction #314,u,g,n,n,n,PM_BR_MPRED_LSTACK,Conditional Branch Completed that was Mispredicted due to the Link Stack Target Prediction ##00000048AC Conditional Branch Completed that was Mispredicted due to the Link Stack Target Prediction #315,u,g,n,n,n,PM_BR_PRED_TAKEN_CR,Conditional Branch that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and branches ##00000040B0 Conditional Branch that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and branches #316,u,g,n,n,n,PM_BR_MPRED_PCACHE,Conditional Branch Completed that was Mispredicted due to pattern cache prediction ##00000048B0 Conditional Branch Completed that was Mispredicted due to pattern cache prediction #317,u,g,n,n,n,PM_BR_PRED_TA,Conditional Branch Completed that had its target address predicted. Only XL-form branches set this event. This equal the sum of CCACHE, LSTACK, and PCACHE ##00000040B4 Conditional Branch Completed that had its target address predicted. Only XL-form branches set this event. This equal the sum of CCACHE, LSTACK, and PCACHE #318,u,g,n,n,n,PM_DECODE_FUSION_CONST_GEN,32-bit constant generation ##00000048B4 32-bit constant generation #319,u,g,n,n,n,PM_BR_MPRED_TAKEN_CR,A Conditional Branch that resolved to taken was mispredicted as not taken (due to the BHT Direction Prediction). ##00000040B8 A Conditional Branch that resolved to taken was mispredicted as not taken (due to the BHT Direction Prediction). #320,u,g,n,n,n,PM_BR_MPRED_TAKEN_TA,Conditional Branch Completed that was Mispredicted due to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that resolved Taken set this event. ##00000048B8 Conditional Branch Completed that was Mispredicted due to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that resolved Taken set this event. #321,u,g,n,n,n,PM_THRD_PRIO_0_1_CYC, Cycles thread running at priority level 0 or 1 ##00000040BC Cycles thread running at priority level 0 or 1 #322,u,g,n,n,n,PM_THRD_PRIO_2_3_CYC, Cycles thread running at priority level 2 or 3 ##00000048BC Cycles thread running at priority level 2 or 3 #323,u,g,n,n,n,PM_THRD_PRIO_4_5_CYC, Cycles thread running at priority level 4 or 5 ##0000005080 Cycles thread running at priority level 4 or 5 #324,u,g,n,n,n,PM_THRD_PRIO_6_7_CYC, Cycles thread running at priority level 6 or 7 ##0000005880 Cycles thread running at priority level 6 or 7 #325,u,g,n,n,n,PM_IC_INVALIDATE,Ic line invalidated ##0000005888 Ic line invalidated #326,u,g,n,n,n,PM_SHL_CREATED,Store-Hit-Load Table Entry Created ##000000508C Store-Hit-Load Table Entry Created #327,u,g,n,n,n,PM_SHL_ST_DEP_CREATED,Store-Hit-Load Table Read Hit with entry Enabled ##000000588C Store-Hit-Load Table Read Hit with entry Enabled #328,u,g,n,n,n,PM_IC_MISS_ICBI,threaded version, IC Misses where we got EA dir hit but no sector valids were on. ICBI took line out ##0000005094 threaded version, IC Misses where we got EA dir hit but no sector valids were on. ICBI took line out #329,u,g,n,n,n,PM_LINK_STACK_WRONG_ADD_PRED,Link stack predicts wrong address, because of link stack design limitation or software violating the coding conventions ##0000005098 Link stack predicts wrong address, because of link stack design limitation or software violating the coding conventions #330,u,g,n,n,n,PM_LINK_STACK_INVALID_PTR,It is most often caused by certain types of flush where the pointer is not available. Can result in the data in the link stack becoming unusable. ##0000005898 It is most often caused by certain types of flush where the pointer is not available. Can result in the data in the link stack becoming unusable. #331,u,g,n,n,n,PM_LINK_STACK_CORRECT,Link stack predicts right address ##00000058A0 Link stack predicts right address #332,u,g,n,n,n,PM_FLUSH_MPRED,Branch mispredict flushes. Includes target and address misprecition ##00000050A4 Branch mispredict flushes. Includes target and address misprecition #333,u,g,n,n,n,PM_FLUSH_LSU,LSU flushes. Includes all lsu flushes ##00000058A4 LSU flushes. Includes all lsu flushes #334,u,g,n,n,n,PM_EAT_FORCE_MISPRED,XL-form branch was mispredicted due to the predicted target address missing from EAT. The EAT forces a mispredict in this case since there is no predicated target to validate. This is a rare case that may occur when the EAT is full and a branch is issued ##00000050A8 XL-form branch was mispredicted due to the predicted target address missing from EAT. The EAT forces a mispredict in this case since there is no predicated target to validate. This is a rare case that may occur when the EAT is full and a branch is issued #335,u,g,n,n,n,PM_DECODE_HOLD_ICT_FULL,Counts the number of cycles in which the IFU was not able to decode and transmit one or more instructions because all itags were in use. This means the ICT is full for this thread ##00000058A8 Counts the number of cycles in which the IFU was not able to decode and transmit one or more instructions because all itags were in use. This means the ICT is full for this thread #336,u,g,n,n,n,PM_BTAC_BAD_RESULT,BTAC thinks branch will be taken but it is either predicted not-taken by the BHT, or the target address is wrong (less common). In both cases, a redirect will happen ##00000050B0 BTAC thinks branch will be taken but it is either predicted not-taken by the BHT, or the target address is wrong (less common). In both cases, a redirect will happen #337,u,g,n,n,n,PM_BTAC_GOOD_RESULT,BTAC predicts a taken branch and the BHT agrees, and the target address is correct ##00000058B0 BTAC predicts a taken branch and the BHT agrees, and the target address is correct #338,u,g,n,n,n,PM_TAGE_CORRECT_TAKEN_CMPL,The TAGE overrode BHT direction prediction and it was correct. Counted at completion for taken branches only ##00000050B4 The TAGE overrode BHT direction prediction and it was correct. Counted at completion for taken branches only #339,u,g,n,n,n,PM_TAGE_CORRECT,The TAGE overrode BHT direction prediction and it was correct. Includes taken and not taken and is counted at execution time ##00000058B4 The TAGE overrode BHT direction prediction and it was correct. Includes taken and not taken and is counted at execution time #340,u,g,n,n,n,PM_TAGE_OVERRIDE_WRONG,The TAGE overrode BHT direction prediction but it was incorrect. Counted at completion for taken branches only ##00000050B8 The TAGE overrode BHT direction prediction but it was incorrect. Counted at completion for taken branches only #341,u,g,n,n,n,PM_TAGE_OVERRIDE_WRONG_SPEC,The TAGE overrode BHT direction prediction and it was correct. Includes taken and not taken and is counted at execution time ##00000058B8 The TAGE overrode BHT direction prediction and it was correct. Includes taken and not taken and is counted at execution time #342,u,g,n,s,n,PM_L3_PF_MISS_L3,L3 PF missed in L3 ##00000160A0 L3 PF missed in L3 #343,u,g,n,s,n,PM_L3_CO_MEPF,L3 CO of line in Mep state (includes casthrough to memory). The Mepf state indicates that a line was brought in to satisfy an L3 prefetch request ##00000168A0 L3 CO of line in Mep state (includes casthrough to memory). The Mepf state indicates that a line was brought in to satisfy an L3 prefetch request #344,u,g,n,n,n,PM_L3_HIT,L3 Hits (L2 miss hitting L3, including data/instrn/xlate) ##00000160A4 L3 Hits (L2 miss hitting L3, including data/instrn/xlate) #345,u,g,n,n,n,PM_L3_MISS,L3 Misses (L2 miss also missing L3, including data/instrn/xlate) ##00000168A4 L3 Misses (L2 miss also missing L3, including data/instrn/xlate) #346,u,g,n,s,n,PM_TM_SC_CO,L3 castout of line that was StoreCopy (original value of speculatively written line) in a "Transaction" ##00000160A6 L3 castout of line that was StoreCopy (original value of speculatively written line) in a "Transaction" #347,u,g,n,s,n,PM_TM_CAM_OVERFLOW,L3 TM CAM is full when a L2 castout of TM_SC line occurs. Line is pushed to memory ##00000168A6 L3 TM CAM is full when a L2 castout of TM_SC line occurs. Line is pushed to memory #348,u,g,n,n,n,PM_L3_WI_USAGE,Lifetime, sample of Write Inject machine 0 valid ##00000168A8 Lifetime, sample of Write Inject machine 0 valid #349,u,g,n,s,n,PM_L3_P0_LCO_NO_DATA,Dataless L3 LCO sent port 0 ##00000160AA Dataless L3 LCO sent port 0 #350,u,g,n,s,n,PM_L3_P1_LCO_NO_DATA,Dataless L3 LCO sent port 1 ##00000168AA Dataless L3 LCO sent port 1 #351,u,g,n,s,n,PM_L3_SN_USAGE,Rotating sample of 16 snoop valids ##00000160AC Rotating sample of 16 snoop valids #352,u,g,n,s,n,PM_L3_CI_USAGE,Rotating sample of 16 CI or CO actives ##00000168AC Rotating sample of 16 CI or CO actives #353,u,g,n,s,n,PM_L3_P0_PF_RTY,L3 PF received retry port 0, every retry counted ##00000160AE L3 PF received retry port 0, every retry counted #354,u,g,n,n,n,PM_L3_P1_PF_RTY,L3 PF received retry port 1, every retry counted ##00000168AE L3 PF received retry port 1, every retry counted #355,u,g,n,s,n,PM_L3_P0_NODE_PUMP,L3 PF sent with nodal scope port 0, counts even retried requests ##00000160B0 L3 PF sent with nodal scope port 0, counts even retried requests #356,u,g,n,s,n,PM_L3_P1_NODE_PUMP,L3 PF sent with nodal scope port 1, counts even retried requests ##00000168B0 L3 PF sent with nodal scope port 1, counts even retried requests #357,u,g,n,s,n,PM_L3_LOC_GUESS_CORRECT,Prefetch scope predictor selected LNS and was correct ##00000160B2 Prefetch scope predictor selected LNS and was correct #358,u,g,n,s,n,PM_L3_GRP_GUESS_CORRECT,Prefetch scope predictor selected GS or NNS and was correct ##00000168B2 Prefetch scope predictor selected GS or NNS and was correct #359,u,g,n,s,n,PM_L3_P0_LCO_RTY,L3 initiated LCO received retry on port 0 (can try 4 times) ##00000160B4 L3 initiated LCO received retry on port 0 (can try 4 times) #360,u,g,n,s,n,PM_L3_P1_LCO_RTY,L3 initiated LCO received retry on port 1 (can try 4 times) ##00000168B4 L3 initiated LCO received retry on port 1 (can try 4 times) #361,u,g,n,s,n,PM_L3_WI0_BUSY,Rotating sample of 8 WI valid ##00000160B6 Rotating sample of 8 WI valid #362,u,g,n,n,n,PM_L2_LD,All successful D-side Load dispatches for this thread (L2 miss + L2 hits) ##0000016080 All successful D-side Load dispatches for this thread (L2 miss + L2 hits) #363,u,g,n,n,n,PM_L2_ST,All successful D-side store dispatches for this thread (L2 miss + L2 hits) ##0000016880 All successful D-side store dispatches for this thread (L2 miss + L2 hits) #364,u,g,n,s,n,PM_L2_CASTOUT_MOD,L2 Castouts - Modified (M,Mu,Me) ##0000016082 L2 Castouts - Modified (M,Mu,Me) #365,u,g,n,s,n,PM_L2_CASTOUT_SHR,L2 Castouts - Shared (Tx,Sx) ##0000016882 L2 Castouts - Shared (Tx,Sx) #366,u,g,n,n,n,PM_L2_RCLD_DISP, All D-side-Ld or I-side-instruction-fetch dispatch attempts for this thread ##0000016084 All D-side-Ld or I-side-instruction-fetch dispatch attempts for this thread #367,u,g,n,n,n,PM_L2_RCLD_DISP_FAIL_ADDR, All D-side-Ld or I-side-instruction-fetch dispatch attempts for this thread that failed due to an address collision conflicts with an L2 machines already working on this line (e.g. ld-hit-stq or Read-claim/Castout/Snoop machines) ##0000016884 All D-side-Ld or I-side-instruction-fetch dispatch attempts for this thread that failed due to an address collision conflicts with an L2 machines already working on this line (e.g. ld-hit-stq or Read-claim/Castout/Snoop machines) #368,u,g,n,s,n,PM_L2_SN_M_WR_DONE,SNP dispatched for a write and was M (true M) ##0000016086 SNP dispatched for a write and was M (true M) #369,u,g,n,s,n,PM_CO_DISP_FAIL,CO dispatch failed due to all CO machines being busy ##0000016886 CO dispatch failed due to all CO machines being busy #370,u,g,n,s,n,PM_L2_LOC_GUESS_CORRECT,L2 guess local (LNS) and guess was correct (ie data local) ##0000016088 L2 guess local (LNS) and guess was correct (ie data local) #371,u,g,n,s,n,PM_L2_LOC_GUESS_WRONG,L2 guess local (LNS) and guess was not correct (ie data not on chip) ##0000016888 L2 guess local (LNS) and guess was not correct (ie data not on chip) #372,u,g,n,n,n,PM_ISIDE_DISP, All I-side-instruction-fetch dispatch attempts for this thread ##000001688A All I-side-instruction-fetch dispatch attempts for this thread #373,u,g,n,s,n,PM_RC0_BUSY,RC mach 0 Busy. Used by PMU to sample ave RC lifetime (mach0 used as sample point) ##000001608C RC mach 0 Busy. Used by PMU to sample ave RC lifetime (mach0 used as sample point) #374,u,g,n,s,n,PM_RC_USAGE,Continuous 16 cycle (2to1) window where this signals rotates thru sampling each RC machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running ##000001688C Continuous 16 cycle (2to1) window where this signals rotates thru sampling each RC machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running #375,u,g,n,s,n,PM_ST_CAUSED_FAIL,Non-TM Store caused any thread to fail ##000001608E Non-TM Store caused any thread to fail #376,u,g,n,s,n,PM_TM_LD_CAUSED_FAIL,Non-TM Load caused any thread to fail ##000001688E Non-TM Load caused any thread to fail #377,u,g,n,s,n,PM_SN0_BUSY,SN mach 0 Busy. Used by PMU to sample ave SN lifetime (mach0 used as sample point) ##0000016090 SN mach 0 Busy. Used by PMU to sample ave SN lifetime (mach0 used as sample point) #378,u,g,n,s,n,PM_L1PF_L2MEMACC,Valid when first beat of data comes in for an L1PF where data came from memory ##0000016890 Valid when first beat of data comes in for an L1PF where data came from memory #379,u,g,n,n,n,PM_L2_LD_MISS_128B,All successful D-side load dispatches that were an L2 miss (NOT Sx,Tx,Mx) for this thread and the RC calculated the request should be for 128B (i.e., M=0) ##0000016092 All successful D-side load dispatches that were an L2 miss (NOT Sx,Tx,Mx) for this thread and the RC calculated the request should be for 128B (i.e., M=0) #380,u,g,n,n,n,PM_L2_ST_MISS_128B,All successful D-side store dispatches that were an L2 miss (NOT Sx,Tx,Mx) for this thread and the RC calculated the request should be for 128B (i.e., M=0) ##0000016892 All successful D-side store dispatches that were an L2 miss (NOT Sx,Tx,Mx) for this thread and the RC calculated the request should be for 128B (i.e., M=0) #381,u,g,n,n,n,PM_L2_LD_DISP, All successful D-side-Ld or I-side-instruction-fetch dispatches for this thread ##000001609E All successful D-side-Ld or I-side-instruction-fetch dispatches for this thread #382,u,g,n,n,n,PM_L2_ST_DISP, All successful D-side store dispatches for this thread ##000001689E All successful D-side store dispatches for this thread $$$$$$$$ { counter 2} #0,u,g,n,n,n,PM_SUSPENDED,Counter OFF ##0000020000 Counter OFF #1,u,g,n,s,n,PM_CYC,Cycles ##000002001E Cycles #2,u,g,n,n,n,PM_INST_CMPL,PPC instructions completed ##0000020002 PPC instructions completed #3,u,g,n,n,n,PM_DISP_HELD_ISSQ_FULL,Dispatch held due to Issue q full. Includes issue queue and branch queue ##0000020006 Dispatch held due to Issue q full. Includes issue queue and branch queue #4,u,g,n,s,n,PM_ICT_EMPTY_CYC,Cycles in which the ICT is completely empty. No itags are assigned to any thread ##0000020008 Cycles in which the ICT is completely empty. No itags are assigned to any thread #5,u,g,n,n,n,PM_HV_CYC,Cycles in which msr_hv is high. Note that this event does not take msr_pr into consideration ##000002000A Cycles in which msr_hv is high. Note that this event does not take msr_pr into consideration #6,u,g,n,s,n,PM_THRD_ALL_RUN_CYC,Cycles in which all the threads have the run latch set ##000002000C Cycles in which all the threads have the run latch set #7,u,g,n,s,n,PM_FXU_BUSY,Cycles in which all 4 FXUs are busy. The FXU is running at capacity ##000002000E Cycles in which all 4 FXUs are busy. The FXU is running at capacity #8,u,g,n,n,n,PM_PMC1_OVERFLOW,Overflow from counter 1 ##0000020010 Overflow from counter 1 #9,u,g,n,n,m,PM_MRK_L2_RC_DISP,Marked Instruction RC dispatched in L2 ##0000020114 Marked Instruction RC dispatched in L2 #10,u,g,n,n,n,PM_ST_FIN,Store finish count. Includes speculative activity ##0000020016 Store finish count. Includes speculative activity #11,u,g,n,n,n,PM_ST_FWD,Store forwards that finished ##0000020018 Store forwards that finished #12,u,g,n,n,n,PM_NTC_ALL_FIN,Cycles after instruction finished to instruction completed. ##000002001A Cycles after instruction finished to instruction completed. #13,u,g,n,n,m,PM_MRK_NTC_CYC,Cycles during which the marked instruction is next to complete (completion is held up because the marked instruction hasn't completed yet) ##000002011C Cycles during which the marked instruction is next to complete (completion is held up because the marked instruction hasn't completed yet) #14,u,g,n,n,n,PM_CMPLU_STALL_LSU,Completion stall by LSU instruction ##000002C010 Completion stall by LSU instruction #15,u,g,n,n,n,PM_CMPLU_STALL_DCACHE_MISS,Finish stall because the NTF instruction was a load that missed the L1 and was waiting for the data to return from the nest ##000002C012 Finish stall because the NTF instruction was a load that missed the L1 and was waiting for the data to return from the nest #16,u,g,n,n,n,PM_CMPLU_STALL_STORE_FINISH,Finish stall because the NTF instruction was a store with all its dependencies met, just waiting to go through the LSU pipe to finish ##000002C014 Finish stall because the NTF instruction was a store with all its dependencies met, just waiting to go through the LSU pipe to finish #17,u,g,n,n,n,PM_CMPLU_STALL_PASTE,Finish stall because the NTF instruction was a paste waiting for response from L2 ##000002C016 Finish stall because the NTF instruction was a paste waiting for response from L2 #18,u,g,n,n,n,PM_CMPLU_STALL_DMISS_L21_L31,Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3) ##000002C018 Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3) #19,u,g,n,n,n,PM_CMPLU_STALL_LHS,Finish stall because the NTF instruction was a load that hit on an older store and it was waiting for store data ##000002C01A Finish stall because the NTF instruction was a load that hit on an older store and it was waiting for store data #20,u,g,n,n,n,PM_CMPLU_STALL_DMISS_REMOTE,Completion stall by Dcache miss which resolved from remote chip (cache or memory) ##000002C01C Completion stall by Dcache miss which resolved from remote chip (cache or memory) #21,u,g,n,n,n,PM_CMPLU_STALL_SYNC_PMU_INT,Cycles in which the NTC instruction is waiting for a synchronous PMU interrupt ##000002C01E Cycles in which the NTC instruction is waiting for a synchronous PMU interrupt #22,u,g,n,n,n,PM_CMPLU_STALL_DFU,Finish stall because the NTF instruction was issued to the Decimal Floating Point execution pipe and waiting to finish. Includes decimal floating point instructions + 128 bit binary floating point instructions. Not qualified by multicycle ##000002D012 Finish stall because the NTF instruction was issued to the Decimal Floating Point execution pipe and waiting to finish. Includes decimal floating point instructions + 128 bit binary floating point instructions. Not qualified by multicycle #23,u,g,n,n,n,PM_CMPLU_STALL_LRQ_FULL,Finish stall because the NTF instruction was a load that was held in LSAQ (load-store address queue) because the LRQ (load-reorder queue) was full ##000002D014 Finish stall because the NTF instruction was a load that was held in LSAQ (load-store address queue) because the LRQ (load-reorder queue) was full #24,u,g,n,n,n,PM_CMPLU_STALL_FXU,Finish stall due to a scalar fixed point or CR instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes ##000002D016 Finish stall due to a scalar fixed point or CR instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes #25,u,g,n,n,n,PM_CMPLU_STALL_EXEC_UNIT,Completion stall due to execution units (FXU/VSU/CRU) ##000002D018 Completion stall due to execution units (FXU/VSU/CRU) #26,u,g,n,n,n,PM_ICT_NOSLOT_IC_MISS,Ict empty for this thread due to Icache Miss ##000002D01A Ict empty for this thread due to Icache Miss #27,u,g,n,n,n,PM_CMPLU_STALL_STCX,Finish stall because the NTF instruction was a stcx waiting for response from L2 ##000002D01C Finish stall because the NTF instruction was a stcx waiting for response from L2 #28,u,g,n,n,n,PM_ICT_NOSLOT_DISP_HELD_ISSQ,Ict empty for this thread due to dispatch hold on this thread due to Issue q full, BRQ full, XVCF Full, Count cache, Link, Tar full ##000002D01E Ict empty for this thread due to dispatch hold on this thread due to Issue q full, BRQ full, XVCF Full, Count cache, Link, Tar full #29,u,g,n,n,n,PM_TM_TX_PASS_RUN_CYC,cycles spent in successful transactions ##000002E012 cycles spent in successful transactions #30,u,g,n,n,n,PM_STCX_FIN,Number of stcx instructions finished. This includes instructions in the speculative path of a branch that may be flushed ##000002E014 Number of stcx instructions finished. This includes instructions in the speculative path of a branch that may be flushed #31,u,g,n,n,n,PM_NTC_ISSUE_HELD_ARB,The NTC instruction is being held at dispatch because it lost arbitration onto the issue pipe to another instruction (from the same thread or a different thread) ##000002E016 The NTC instruction is being held at dispatch because it lost arbitration onto the issue pipe to another instruction (from the same thread or a different thread) #32,u,g,n,n,n,PM_CMPLU_STALL_VFXLONG,Completion stall due to a long latency vector fixed point instruction (division, square root) ##000002E018 Completion stall due to a long latency vector fixed point instruction (division, square root) #33,u,g,n,n,n,PM_CMPLU_STALL_LSU_FLUSH_NEXT,Completion stall of one cycle because the LSU requested to flush the next iop in the sequence. It takes 1 cycle for the ISU to process this request before the LSU instruction is allowed to complete ##000002E01A Completion stall of one cycle because the LSU requested to flush the next iop in the sequence. It takes 1 cycle for the ISU to process this request before the LSU instruction is allowed to complete #34,u,g,n,n,n,PM_CMPLU_STALL_TLBIE,Finish stall because the NTF instruction was a tlbie waiting for response from L2 ##000002E01C Finish stall because the NTF instruction was a tlbie waiting for response from L2 #35,u,g,n,n,n,PM_CMPLU_STALL_NTC_FLUSH,Completion stall due to ntc flush ##000002E01E Completion stall due to ntc flush #36,u,g,n,n,m,PM_MRK_DATA_FROM_L2_NO_CONFLICT,The processor's data cache was reloaded from local core's L2 without conflict due to a marked load ##000002C120 The processor's data cache was reloaded from local core's L2 without conflict due to a marked load #37,u,g,n,n,m,PM_MRK_DATA_FROM_L3_DISP_CONFLICT_CYC,Duration in cycles to reload from local core's L3 with dispatch conflict due to a marked load ##000002C122 Duration in cycles to reload from local core's L3 with dispatch conflict due to a marked load #38,u,g,n,n,m,PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER,The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a marked load ##000002C124 The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a marked load #39,u,g,n,n,m,PM_MRK_DATA_FROM_L2,The processor's data cache was reloaded from local core's L2 due to a marked load ##000002C126 The processor's data cache was reloaded from local core's L2 due to a marked load #40,u,g,n,n,m,PM_MRK_DATA_FROM_DL2L3_SHR_CYC,Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load ##000002C128 Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load #41,u,g,n,n,m,PM_MRK_DATA_FROM_RMEM_CYC,Duration in cycles to reload from another chip's memory on the same Node or Group ( Remote) due to a marked load ##000002C12A Duration in cycles to reload from another chip's memory on the same Node or Group ( Remote) due to a marked load #42,u,g,n,n,m,PM_MRK_DATA_FROM_DL4_CYC,Duration in cycles to reload from another chip's L4 on a different Node or Group (Distant) due to a marked load ##000002C12C Duration in cycles to reload from another chip's L4 on a different Node or Group (Distant) due to a marked load #43,u,g,n,n,m,PM_MRK_DATA_FROM_LL4_CYC,Duration in cycles to reload from the local chip's L4 cache due to a marked load ##000002C12E Duration in cycles to reload from the local chip's L4 cache due to a marked load #44,u,g,n,n,m,PM_MRK_DATA_FROM_OFF_CHIP_CACHE,The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load ##000002D120 The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load #45,u,g,n,n,n,PM_RADIX_PWC_L1_PDE_FROM_L2,A Page Directory Entry was reloaded to a level 1 page walk cache from the core's L2 data cache ##000002D026 A Page Directory Entry was reloaded to a level 1 page walk cache from the core's L2 data cache #46,u,g,n,n,n,PM_RADIX_PWC_L2_PDE_FROM_L2,A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 data cache ##000002D028 A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 data cache #47,u,g,n,n,n,PM_RADIX_PWC_L3_PDE_FROM_L2,A Page Directory Entry was reloaded to a level 3 page walk cache from the core's L2 data cache ##000002D02A A Page Directory Entry was reloaded to a level 3 page walk cache from the core's L2 data cache #48,u,g,n,n,n,PM_RADIX_PWC_L3_PTE_FROM_L2,A Page Table Entry was reloaded to a level 3 page walk cache from the core's L2 data cache. This implies that a level 4 PWC access was not necessary for this translation ##000002D02E A Page Table Entry was reloaded to a level 3 page walk cache from the core's L2 data cache. This implies that a level 4 PWC access was not necessary for this translation #49,u,g,n,n,m,PM_MRK_INST_DECODED,An instruction was marked at decode time. Random Instruction Sampling (RIS) only ##0000020130 An instruction was marked at decode time. Random Instruction Sampling (RIS) only #50,u,g,n,n,m,PM_MRK_DFU_FIN,Decimal Unit marked Instruction Finish ##0000020132 Decimal Unit marked Instruction Finish #51,u,g,n,n,m,PM_MRK_FXU_FIN,fxu marked instr finish ##0000020134 fxu marked instr finish #52,u,g,n,n,n,PM_BR_2PATH,Branches that are not strongly biased ##0000020036 Branches that are not strongly biased #53,u,g,n,n,m,PM_MRK_ST_NEST,Marked store sent to nest ##0000020138 Marked store sent to nest #54,u,g,n,n,m,PM_MRK_BRU_FIN,bru marked instr finish ##000002013A bru marked instr finish #55,u,g,n,s,n,PM_LSU_LMQ_SRQ_EMPTY_CYC,Cycles in which the LSU is empty for all threads (lmq and srq are completely empty) ##000002003E Cycles in which the LSU is empty for all threads (lmq and srq are completely empty) #56,u,g,n,n,n,PM_DATA_FROM_L2_MEPF,The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to a demand load ##000002C040 The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to a demand load #57,u,g,n,n,n,PM_DATA_FROM_L3_MEPF,The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to a demand load ##000002C042 The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to a demand load #58,u,g,n,n,n,PM_DATA_FROM_L31_MOD,The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to a demand load ##000002C044 The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to a demand load #59,u,g,n,n,n,PM_DATA_FROM_RL2L3_MOD,The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load ##000002C046 The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load #60,u,g,n,n,n,PM_DATA_FROM_LMEM,The processor's data cache was reloaded from the local chip's Memory due to a demand load ##000002C048 The processor's data cache was reloaded from the local chip's Memory due to a demand load #61,u,g,n,n,n,PM_DATA_FROM_RL4,The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a demand load ##000002C04A The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a demand load #62,u,g,n,n,n,PM_LD_MISS_L1_FIN,Number of load instructions that finished with an L1 miss. Note that even if a load spans multiple slices this event will increment only once per load op. ##000002C04E Number of load instructions that finished with an L1 miss. Note that even if a load spans multiple slices this event will increment only once per load op. #63,u,g,n,n,n,PM_INST_FROM_L2_MEPF,The processor's Instruction cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to an instruction fetch (not prefetch) ##0000024040 The processor's Instruction cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to an instruction fetch (not prefetch) #64,u,g,n,n,n,PM_INST_FROM_L3_MEPF,The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to an instruction fetch (not prefetch) ##0000024042 The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to an instruction fetch (not prefetch) #65,u,g,n,n,n,PM_INST_FROM_L31_MOD,The processor's Instruction cache was reloaded with Modified (M) data from another core's L3 on the same chip due to an instruction fetch (not prefetch) ##0000024044 The processor's Instruction cache was reloaded with Modified (M) data from another core's L3 on the same chip due to an instruction fetch (not prefetch) #66,u,g,n,n,n,PM_INST_FROM_RL2L3_MOD,The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch) ##0000024046 The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch) #67,u,g,n,n,n,PM_INST_FROM_LMEM,The processor's Instruction cache was reloaded from the local chip's Memory due to an instruction fetch (not prefetch) ##0000024048 The processor's Instruction cache was reloaded from the local chip's Memory due to an instruction fetch (not prefetch) #68,u,g,n,n,n,PM_INST_FROM_RL4,The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to an instruction fetch (not prefetch) ##000002404A The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to an instruction fetch (not prefetch) #69,u,g,n,n,n,PM_INST_FROM_MEMORY,The processor's Instruction cache was reloaded from a memory location including L4 from local remote or distant due to an instruction fetch (not prefetch) ##000002404C The processor's Instruction cache was reloaded from a memory location including L4 from local remote or distant due to an instruction fetch (not prefetch) #70,u,g,n,n,m,PM_MRK_DATA_FROM_L3_MEPF,The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load ##000002D142 The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load #71,u,g,n,n,m,PM_MRK_DATA_FROM_L31_MOD,The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to a marked load ##000002D144 The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to a marked load #72,u,g,n,n,m,PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST,The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a marked load ##000002D148 The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a marked load #73,u,g,n,n,m,PM_MRK_DATA_FROM_RL2L3_MOD_CYC,Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load ##000002D14A Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load #74,u,g,n,n,m,PM_MRK_DATA_FROM_L31_ECO_SHR,The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a marked load ##000002D14C The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a marked load #75,u,g,n,n,m,PM_MRK_DATA_FROM_L21_SHR,The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a marked load ##000002D14E The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a marked load #76,u,g,n,n,n,PM_IPTEG_FROM_L2_MEPF,A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a instruction side request ##0000025040 A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a instruction side request #77,u,g,n,n,n,PM_IPTEG_FROM_L3_MEPF,A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a instruction side request ##0000025042 A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a instruction side request #78,u,g,n,n,n,PM_IPTEG_FROM_L31_MOD,A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a instruction side request ##0000025044 A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a instruction side request #79,u,g,n,n,n,PM_IPTEG_FROM_RL2L3_MOD,A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request ##0000025046 A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request #80,u,g,n,n,n,PM_IPTEG_FROM_LMEM,A Page Table Entry was loaded into the TLB from the local chip's Memory due to a instruction side request ##0000025048 A Page Table Entry was loaded into the TLB from the local chip's Memory due to a instruction side request #81,u,g,n,n,n,PM_IPTEG_FROM_RL4,A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction side request ##000002504A A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction side request #82,u,g,n,n,n,PM_IPTEG_FROM_MEMORY,A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a instruction side request ##000002504C A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a instruction side request #83,u,g,n,n,n,PM_DPTEG_FROM_L2_MEPF,A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000002E040 A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #84,u,g,n,n,n,PM_DPTEG_FROM_L3_MEPF,A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000002E042 A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #85,u,g,n,n,n,PM_DPTEG_FROM_L31_MOD,A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000002E044 A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #86,u,g,n,n,n,PM_DPTEG_FROM_RL2L3_MOD,A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000002E046 A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #87,u,g,n,n,n,PM_DPTEG_FROM_LMEM,A Page Table Entry was loaded into the TLB from the local chip's Memory due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000002E048 A Page Table Entry was loaded into the TLB from the local chip's Memory due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #88,u,g,n,n,n,PM_DPTEG_FROM_RL4,A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000002E04A A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #89,u,g,n,n,n,PM_DPTEG_FROM_MEMORY,A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000002E04C A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #90,u,g,n,n,m,PM_MRK_DPTEG_FROM_L2_MEPF,A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000002F140 A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #91,u,g,n,n,m,PM_MRK_DPTEG_FROM_L3_MEPF,A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000002F142 A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #92,u,g,n,n,m,PM_MRK_DPTEG_FROM_L31_MOD,A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000002F144 A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #93,u,g,n,n,m,PM_MRK_DPTEG_FROM_RL2L3_MOD,A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000002F146 A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #94,u,g,n,n,m,PM_MRK_DPTEG_FROM_LMEM,A Page Table Entry was loaded into the TLB from the local chip's Memory due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000002F148 A Page Table Entry was loaded into the TLB from the local chip's Memory due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #95,u,g,n,n,m,PM_MRK_DPTEG_FROM_RL4,A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000002F14A A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #96,u,g,n,n,m,PM_MRK_DPTEG_FROM_MEMORY,A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000002F14C A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #97,u,g,n,n,n,PM_GRP_PUMP_CPRED,Initial and Final Pump Scope and data sourced across this scope was group pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) ##0000020050 Initial and Final Pump Scope and data sourced across this scope was group pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) #98,u,g,n,n,n,PM_GRP_PUMP_MPRED,Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) ##0000020052 Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) #99,u,g,n,n,n,PM_L1_PREF,A data line was written to the L1 due to a hardware or software prefetch ##0000020054 A data line was written to the L1 due to a hardware or software prefetch #100,u,g,n,n,n,PM_TAKEN_BR_MPRED_CMPL,Total number of taken branches that were incorrectly predicted as not-taken. This event counts branches completed and does not include speculative instructions ##0000020056 Total number of taken branches that were incorrectly predicted as not-taken. This event counts branches completed and does not include speculative instructions #101,u,g,n,n,n,PM_DARQ1_10_12_ENTRIES,Cycles in which 10 or more DARQ1 entries (out of 12) are in use ##0000020058 Cycles in which 10 or more DARQ1 entries (out of 12) are in use #102,u,g,n,n,n,PM_DARQ1_7_9_ENTRIES,Cycles in which 7 to 9 DARQ1 entries (out of 12) are in use ##000002005A Cycles in which 7 to 9 DARQ1 entries (out of 12) are in use #103,u,g,n,n,m,PM_MRK_FAB_RSP_RWITM_RTY,Sampled store did a rwitm and got a rty ##000002015E Sampled store did a rwitm and got a rty #104,u,g,n,n,n,PM_DATA_GRP_PUMP_CPRED,Initial and Final Pump Scope was group pump (prediction=correct) for a demand load ##000002C050 Initial and Final Pump Scope was group pump (prediction=correct) for a demand load #105,u,g,n,n,n,PM_DATA_GRP_PUMP_MPRED,Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for a demand load ##000002C052 Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for a demand load #106,u,g,n,n,n,PM_DERAT_MISS_64K,Data ERAT Miss (Data TLB Access) page size 64K ##000002C054 Data ERAT Miss (Data TLB Access) page size 64K #107,u,g,n,n,n,PM_MEM_PREF,Memory prefetch for this thread. Includes L4 ##000002C058 Memory prefetch for this thread. Includes L4 #108,u,g,n,n,n,PM_INST_GRP_PUMP_CPRED,Initial and Final Pump Scope was group pump (prediction=correct) for an instruction fetch (demand only) ##000002C05C Initial and Final Pump Scope was group pump (prediction=correct) for an instruction fetch (demand only) #109,u,g,n,n,n,PM_INST_GRP_PUMP_MPRED,Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for an instruction fetch (demand only) ##000002C05E Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for an instruction fetch (demand only) #110,u,g,n,n,n,PM_IOPS_CMPL,Internal Operations completed ##0000024050 Internal Operations completed #111,u,g,n,n,n,PM_FXU_IDLE,Cycles in which FXU0, FXU1, FXU2, and FXU3 are all idle ##0000024052 Cycles in which FXU0, FXU1, FXU2, and FXU3 are all idle #112,u,g,t,n,n,PM_THRESH_ACC,This event increments every time the threshold event counter ticks. Thresholding must be enabled (via MMCRA) and the thresholding start event must occur for this counter to increment. It will stop incrementing when the thresholding stop event occurs or when thresholding is disabled, until the next time a configured thresholding start event occurs. ##0000024154 This event increments every time the threshold event counter ticks. Thresholding must be enabled (via MMCRA) and the thresholding start event must occur for this counter to increment. It will stop incrementing when the thresholding stop event occurs or when thresholding is disabled, until the next time a configured thresholding start event occurs. #113,u,g,n,n,m,PM_MRK_STCX_FIN,Number of marked stcx instructions finished. This includes instructions in the speculative path of a branch that may be flushed ##0000024156 Number of marked stcx instructions finished. This includes instructions in the speculative path of a branch that may be flushed #114,u,g,n,n,m,PM_MRK_INST,An instruction was marked. Includes both Random Instruction Sampling (RIS) at decode time and Random Event Sampling (RES) at the time the configured event happens ##0000024158 An instruction was marked. Includes both Random Instruction Sampling (RIS) at decode time and Random Event Sampling (RES) at the time the configured event happens #115,u,g,n,n,n,PM_NTC_FIN,Cycles in which the oldest instruction in the pipeline (NTC) finishes. This event is used to account for cycles in which work is being completed in the CPI stack ##000002405A Cycles in which the oldest instruction in the pipeline (NTC) finishes. This event is used to account for cycles in which work is being completed in the CPI stack #116,u,g,n,n,m,PM_MRK_DERAT_MISS_4K,Marked Data ERAT Miss (Data TLB Access) page size 4K ##000002D150 Marked Data ERAT Miss (Data TLB Access) page size 4K #117,u,g,n,n,m,PM_MRK_DERAT_MISS_64K,Marked Data ERAT Miss (Data TLB Access) page size 64K ##000002D154 Marked Data ERAT Miss (Data TLB Access) page size 64K #118,u,g,n,n,n,PM_VSU_FIN,VSU instruction finished. Up to 4 per cycle ##000002505C VSU instruction finished. Up to 4 per cycle #119,u,g,n,n,n,PM_BACK_BR_CMPL,Branch instruction completed with a target address less than current instruction address ##000002505E Branch instruction completed with a target address less than current instruction address #120,u,g,n,n,n,PM_DARQ0_7_9_ENTRIES,Cycles in which 7,8, or 9 DARQ entries (out of 12) are in use ##000002E050 Cycles in which 7,8, or 9 DARQ entries (out of 12) are in use #121,u,g,n,n,n,PM_TM_PASSED,Number of TM transactions that passed ##000002E052 Number of TM transactions that passed #122,u,g,n,n,n,PM_LRQ_REJECT,Internal LSU reject from LRQ. Rejects cause the load to go back to LRQ, but it stays contained within the LSU once it gets issued. This event counts the number of times the LRQ attempts to relaunch an instruction after a reject. Any load can suffer multiple rejects ##000002E05A Internal LSU reject from LRQ. Rejects cause the load to go back to LRQ, but it stays contained within the LSU once it gets issued. This event counts the number of times the LRQ attempts to relaunch an instruction after a reject. Any load can suffer multiple rejects #123,u,g,n,n,n,PM_LSU_REJECT_ERAT_MISS,LSU Reject due to ERAT (up to 4 per cycles) ##000002E05C LSU Reject due to ERAT (up to 4 per cycles) #124,u,g,n,n,n,PM_LMQ_EMPTY_CYC,Cycles in which the LMQ has no pending load misses for this thread ##000002E05E Cycles in which the LMQ has no pending load misses for this thread #125,u,g,n,n,m,PM_MRK_FAB_RSP_DCLAIM_CYC,cycles L2 RC took for a dclaim ##000002F152 cycles L2 RC took for a dclaim #126,u,g,n,n,n,PM_IERAT_RELOAD_4K,IERAT reloaded (after a miss) for 4K pages ##0000020064 IERAT reloaded (after a miss) for 4K pages #127,u,g,n,n,n,PM_TLB_MISS,TLB Miss (I + D) ##0000020066 TLB Miss (I + D) #128,u,g,n,n,n,PM_RUN_CYC_SMT4_MODE,Cycles in which this thread's run latch is set and the core is in SMT4 mode ##000002006C Cycles in which this thread's run latch is set and the core is in SMT4 mode #129,u,g,n,n,m,PM_MRK_DATA_FROM_MEMORY,The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked load ##00000201E0 The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked load #130,u,g,n,n,m,PM_MRK_LD_MISS_L1,Marked DL1 Demand Miss counted at exec time. Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load. ##00000201E2 Marked DL1 Demand Miss counted at exec time. Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load. #131,u,g,n,n,m,PM_MRK_DATA_FROM_L3MISS,The processor's data cache was reloaded from a location other than the local core's L3 due to a marked load ##00000201E4 The processor's data cache was reloaded from a location other than the local core's L3 due to a marked load #132,u,g,t,n,n,PM_THRESH_EXC_32,Threshold counter exceeded a value of 32 ##00000201E6 Threshold counter exceeded a value of 32 #133,u,g,t,n,n,PM_THRESH_EXC_512,Threshold counter exceeded a value of 512 ##00000201E8 Threshold counter exceeded a value of 512 #134,u,g,n,n,n,PM_ST_CMPL,Stores completed from S2Q (2nd-level store queue). ##00000200F0 Stores completed from S2Q (2nd-level store queue). #135,u,g,n,n,n,PM_INST_DISP,PPC Dispatched ##00000200F2 PPC Dispatched #136,u,g,n,n,n,PM_RUN_CYC,Run_cycles ##00000200F4 Run_cycles #137,u,g,n,n,n,PM_LSU_DERAT_MISS,DERAT Reloaded due to a DERAT miss ##00000200F6 DERAT Reloaded due to a DERAT miss #138,u,g,n,n,n,PM_EXT_INT,external interrupt ##00000200F8 external interrupt #139,u,g,n,n,n,PM_BR_TAKEN_CMPL,New event for Branch Taken ##00000200FA New event for Branch Taken #140,u,g,n,n,n,PM_L1_ICACHE_MISS,Demand iCache Miss ##00000200FD Demand iCache Miss #141,u,g,n,n,n,PM_DATA_FROM_L2MISS,Demand LD - L2 Miss (not L2 hit) ##00000200FE Demand LD - L2 Miss (not L2 hit) #142,u,g,n,n,n,PM_EE_OFF_EXT_INT,CyclesMSR[EE] is off and external interrupts are active ##0000002080 CyclesMSR[EE] is off and external interrupts are active #143,u,g,n,n,n,PM_FLUSH_DISP,Dispatch flush ##0000002880 Dispatch flush #144,u,g,n,n,n,PM_FLUSH_HB_RESTORE_CYC,Cycles in which no new instructions can be dispatched to the ICT after a flush. History buffer recovery ##0000002084 Cycles in which no new instructions can be dispatched to the ICT after a flush. History buffer recovery #145,u,g,n,n,n,PM_ISYNC,Isync completion count per thread ##0000002884 Isync completion count per thread #146,u,g,n,n,n,PM_FLUSH_DISP_SB,Dispatch Flush: Scoreboard ##0000002088 Dispatch Flush: Scoreboard #147,u,g,n,n,n,PM_FLUSH_DISP_TLBIE,Dispatch Flush: TLBIE ##0000002888 Dispatch Flush: TLBIE #148,u,g,n,n,n,PM_CLB_HELD,CLB (control logic block - indicates quadword fetch block) Hold: Any Reason ##000000208C CLB (control logic block - indicates quadword fetch block) Hold: Any Reason #149,u,g,n,n,n,PM_DISP_CLB_HELD_BAL,Dispatch/CLB Hold: Balance Flush ##000000288C Dispatch/CLB Hold: Balance Flush #150,u,g,n,n,n,PM_DISP_CLB_HELD_SB,Dispatch/CLB Hold: Scoreboard ##0000002090 Dispatch/CLB Hold: Scoreboard #151,u,g,n,n,n,PM_DISP_CLB_HELD_TLBIE,Dispatch Hold: Due to TLBIE ##0000002890 Dispatch Hold: Due to TLBIE #152,u,g,n,n,n,PM_TM_OUTER_TBEGIN,Completion time outer tbegin ##0000002094 Completion time outer tbegin #153,u,g,n,n,n,PM_TM_OUTER_TEND,Completion time outer tend ##0000002894 Completion time outer tend #154,u,g,n,n,n,PM_TM_NESTED_TEND,Completion time nested tend ##0000002098 Completion time nested tend #155,u,g,n,n,n,PM_TM_TABORT_TRECLAIM,Completion time tabortnoncd, tabortcd, treclaim ##0000002898 Completion time tabortnoncd, tabortcd, treclaim #156,u,g,n,n,n,PM_TM_FAV_TBEGIN,Dispatch time Favored tbegin ##000000209C Dispatch time Favored tbegin #157,u,g,n,n,n,PM_TM_NON_FAV_TBEGIN,Dispatch time non favored tbegin ##000000289C Dispatch time non favored tbegin #158,u,g,n,n,n,PM_TM_NESTED_TBEGIN,Completion Tm nested tbegin ##00000020A0 Completion Tm nested tbegin #159,u,g,n,n,n,PM_TM_TSUSPEND,TM suspend instruction completed ##00000028A0 TM suspend instruction completed #160,u,g,n,n,n,PM_TM_TRESUME,TM resume instruction completed ##00000020A4 TM resume instruction completed #161,u,g,n,n,n,PM_MRK_TEND_FAIL,Nested or not nested tend failed for a marked tend instruction ##00000028A4 Nested or not nested tend failed for a marked tend instruction #162,u,g,n,n,n,PM_TM_FAIL_FOOTPRINT_OVERFLOW,TM aborted because the tracking limit for transactional storage accesses was exceeded.. Asynchronous ##00000020A8 TM aborted because the tracking limit for transactional storage accesses was exceeded.. Asynchronous #163,u,g,n,n,n,PM_TM_FAIL_CONF_NON_TM,TM aborted because a conflict occurred with a non-transactional access by another processor ##00000028A8 TM aborted because a conflict occurred with a non-transactional access by another processor #164,u,g,n,n,n,PM_TM_FAIL_CONF_TM,TM aborted because a conflict occurred with another transaction. ##00000020AC TM aborted because a conflict occurred with another transaction. #165,u,g,n,n,n,PM_TM_FAIL_SELF,TM aborted because a self-induced conflict occurred in Suspended state, due to one of the following: a store to a storage location that was previously accessed transactionally ##00000028AC TM aborted because a self-induced conflict occurred in Suspended state, due to one of the following: a store to a storage location that was previously accessed transactionally #166,u,g,n,n,n,PM_LSU_FLUSH_NEXT,LSU flush next reported at flush time. Sometimes these also come with an exception ##00000020B0 LSU flush next reported at flush time. Sometimes these also come with an exception #167,u,g,n,n,n,PM_DISP_HELD_TBEGIN,This outer tbegin transaction cannot be dispatched until the previous tend instruction completes ##00000028B0 This outer tbegin transaction cannot be dispatched until the previous tend instruction completes #168,u,g,n,n,n,PM_ISU0_ISS_HOLD_ALL,All ISU rejects ##0000003080 All ISU rejects #169,u,g,n,n,n,PM_ISU2_ISS_HOLD_ALL,All ISU rejects ##0000003880 All ISU rejects #170,u,g,n,n,n,PM_ISU1_ISS_HOLD_ALL,All ISU rejects ##0000003084 All ISU rejects #171,u,g,n,n,n,PM_ISU3_ISS_HOLD_ALL,All ISU rejects ##0000003884 All ISU rejects #172,u,g,n,n,n,PM_LS0_LD_VECTOR_FIN,LS0 finished load vector op ##000000C080 LS0 finished load vector op #173,u,g,n,n,n,PM_LS1_LD_VECTOR_FIN,LS1 finished load vector op ##000000C880 LS1 finished load vector op #174,u,g,n,n,n,PM_LS2_LD_VECTOR_FIN,LS2 finished load vector op ##000000C084 LS2 finished load vector op #175,u,g,n,n,n,PM_LS3_LD_VECTOR_FIN,LS3 finished load vector op ##000000C884 LS3 finished load vector op #176,u,g,n,n,n,PM_LSU_DTLB_MISS_4K,Data TLB Miss page size 4K ##000000C088 Data TLB Miss page size 4K #177,u,g,n,n,n,PM_LSU_DTLB_MISS_64K,Data TLB Miss page size 64K ##000000C888 Data TLB Miss page size 64K #178,u,g,n,n,n,PM_LSU_DTLB_MISS_16M_2M,Data TLB Miss page size 16M (HPT) or 2M (Radix) ##000000C08C Data TLB Miss page size 16M (HPT) or 2M (Radix) #179,u,g,n,n,n,PM_LSU_DTLB_MISS_16G_1G,Data TLB Miss page size 16G (HPT) or 1G (Radix) ##000000C88C Data TLB Miss page size 16G (HPT) or 1G (Radix) #180,u,g,n,n,n,PM_LSU_STCX,STCX sent to nest, i.e. total ##000000C090 STCX sent to nest, i.e. total #181,u,g,n,n,n,PM_LSU_NCST,Asserts when a i=1 store op is sent to the nest. No record of issue pipe (LS0/LS1) is maintained so this is for both pipes. Probably don't need separate LS0 and LS1 ##000000C890 Asserts when a i=1 store op is sent to the nest. No record of issue pipe (LS0/LS1) is maintained so this is for both pipes. Probably don't need separate LS0 and LS1 #182,u,g,n,n,n,PM_LS0_UNALIGNED_LD,Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty ##000000C094 Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty #183,u,g,n,n,n,PM_LS1_UNALIGNED_LD,Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty ##000000C894 Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty #184,u,g,n,n,n,PM_LS2_UNALIGNED_LD,Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty ##000000C098 Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty #185,u,g,n,n,n,PM_LS3_UNALIGNED_LD,Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty ##000000C898 Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty #186,u,g,n,n,n,PM_LS0_LAUNCH_HELD_PREF,Number of times a load or store instruction was unable to launch/relaunch because a high priority prefetch used that relaunch cycle ##000000C09C Number of times a load or store instruction was unable to launch/relaunch because a high priority prefetch used that relaunch cycle #187,u,g,n,n,n,PM_LS1_LAUNCH_HELD_PREF,Number of times a load or store instruction was unable to launch/relaunch because a high priority prefetch used that relaunch cycle ##000000C89C Number of times a load or store instruction was unable to launch/relaunch because a high priority prefetch used that relaunch cycle #188,u,g,n,n,n,PM_LSU0_FALSE_LHS,False LHS match detected ##000000C0A0 False LHS match detected #189,u,g,n,n,n,PM_LSU1_FALSE_LHS,False LHS match detected ##000000C8A0 False LHS match detected #190,u,g,n,n,n,PM_LSU2_FALSE_LHS,False LHS match detected ##000000C0A4 False LHS match detected #191,u,g,n,n,n,PM_LSU3_FALSE_LHS,False LHS match detected ##000000C8A4 False LHS match detected #192,u,g,n,n,n,PM_LSU_FLUSH_CI,Load was not issued to LSU as a cache inhibited (non-cacheable) load but it was later determined to be cache inhibited ##000000C0A8 Load was not issued to LSU as a cache inhibited (non-cacheable) load but it was later determined to be cache inhibited #193,u,g,n,n,n,PM_LSU_FLUSH_ATOMIC,Quad-word loads (lq) are considered atomic because they always span at least 2 slices. If a snoop or store from another thread changes the data the load is accessing between the 2 or 3 pieces of the lq instruction, the lq will be flushed ##000000C8A8 Quad-word loads (lq) are considered atomic because they always span at least 2 slices. If a snoop or store from another thread changes the data the load is accessing between the 2 or 3 pieces of the lq instruction, the lq will be flushed #194,u,g,n,n,n,PM_LSU_FLUSH_EMSH,An ERAT miss was detected after a set-p hit. Erat tracker indicates fail due to tlbmiss and the instruction gets flushed because the instruction was working on the wrong address ##000000C0AC An ERAT miss was detected after a set-p hit. Erat tracker indicates fail due to tlbmiss and the instruction gets flushed because the instruction was working on the wrong address #195,u,g,n,n,n,PM_LSU_FLUSH_RELAUNCH_MISS,If a load that has already returned data and has to relaunch for any reason then gets a miss (erat, setp, data cache), it will often be flushed at relaunch time because the data might be inconsistent ##000000C8AC If a load that has already returned data and has to relaunch for any reason then gets a miss (erat, setp, data cache), it will often be flushed at relaunch time because the data might be inconsistent #196,u,g,n,n,n,PM_LSU_FLUSH_UE,Correctable ECC error on reload data, reported at critical data forward time ##000000C0B0 Correctable ECC error on reload data, reported at critical data forward time #197,u,g,n,n,n,PM_LSU_FLUSH_LHS,Effective Address alias flush : no EA match but Real Address match. If the data has not yet been returned for this load, the instruction will just be rejected, but if it has returned data, it will be flushed ##000000C8B0 Effective Address alias flush : no EA match but Real Address match. If the data has not yet been returned for this load, the instruction will just be rejected, but if it has returned data, it will be flushed #198,u,g,n,n,n,PM_LSU_FLUSH_WRK_ARND,LSU workaround flush. These flushes are setup with programmable scan only latches to perform various actions when the flush macro receives a trigger from the dbg macros. These actions include things like flushing the next op encountered for a particular thread or flushing the next op that is NTC op that is encountered on a particular slice. The kind of flush that the workaround is setup to perform is highly variable. ##000000C0B4 LSU workaround flush. These flushes are setup with programmable scan only latches to perform various actions when the flush macro receives a trigger from the dbg macros. These actions include things like flushing the next op encountered for a particular thread or flushing the next op that is NTC op that is encountered on a particular slice. The kind of flush that the workaround is setup to perform is highly variable. #199,u,g,n,n,n,PM_LSU_FLUSH_LHL_SHL,The instruction was flushed because of a sequential load/store consistency. If a load or store hits on an older load that has either been snooped (for loads) or has stale data (for stores). ##000000C8B4 The instruction was flushed because of a sequential load/store consistency. If a load or store hits on an older load that has either been snooped (for loads) or has stale data (for stores). #200,u,g,n,n,n,PM_LSU_FLUSH_SAO,A load-hit-load condition with Strong Address Ordering will have address compare disabled and flush ##000000C0B8 A load-hit-load condition with Strong Address Ordering will have address compare disabled and flush #201,u,g,n,n,n,PM_LSU_FLUSH_LARX_STCX,A larx is flushed because an older larx has an LMQ reservation for the same thread. A stcx is flushed because an older stcx is in the LMQ. The flush happens when the older larx/stcx relaunches ##000000C8B8 A larx is flushed because an older larx has an LMQ reservation for the same thread. A stcx is flushed because an older stcx is in the LMQ. The flush happens when the older larx/stcx relaunches #202,u,g,n,n,n,PM_LSU_FLUSH_OTHER,Other LSU flushes including: Sync (sync ack from L2 caused search of LRQ for oldest snooped load, This will either signal a Precise Flush of the oldest snooped loa or a Flush Next PPC) ##000000C0BC Other LSU flushes including: Sync (sync ack from L2 caused search of LRQ for oldest snooped load, This will either signal a Precise Flush of the oldest snooped loa or a Flush Next PPC) #203,u,g,n,n,n,PM_STCX_SUCCESS_CMPL,Number of stcx instructions that completed successfully ##000000C8BC Number of stcx instructions that completed successfully #204,u,g,n,n,n,PM_LSU0_LDMX_FIN,New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): "The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region." This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56]). ##000000D088 New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): "The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region." This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56]). #205,u,g,n,n,n,PM_LSU1_LDMX_FIN,New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): "The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region." This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56]). ##000000D888 New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): "The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region." This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56]). #206,u,g,n,n,n,PM_LSU2_LDMX_FIN,New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): "The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region." This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56]). ##000000D08C New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): "The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region." This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56]). #207,u,g,n,n,n,PM_LSU3_LDMX_FIN,New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): "The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region." This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56]). ##000000D88C New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): "The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region." This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56]). #208,u,g,n,n,n,PM_LS0_DC_COLLISIONS,Read-write data cache collisions ##000000D090 Read-write data cache collisions #209,u,g,n,n,n,PM_LS1_DC_COLLISIONS,Read-write data cache collisions ##000000D890 Read-write data cache collisions #210,u,g,n,n,n,PM_LS2_DC_COLLISIONS,Read-write data cache collisions ##000000D094 Read-write data cache collisions #211,u,g,n,n,n,PM_LS3_DC_COLLISIONS,Read-write data cache collisions ##000000D894 Read-write data cache collisions #212,u,g,n,n,n,PM_LSU_FLUSH_ATOMIC,Quad-word loads (lq) are considered atomic because they always span at least 2 slices. If a snoop or store from another thread changes the data the load is accessing between the 2 or 3 pieces of the lq instruction, the lq will be flushed ##000000D198 Quad-word loads (lq) are considered atomic because they always span at least 2 slices. If a snoop or store from another thread changes the data the load is accessing between the 2 or 3 pieces of the lq instruction, the lq will be flushed #213,u,g,n,n,n,PM_LSU_FLUSH_EMSH,An ERAT miss was detected after a set-p hit. Erat tracker indicates fail due to tlbmiss and the instruction gets flushed because the instruction was working on the wrong address ##000000D998 An ERAT miss was detected after a set-p hit. Erat tracker indicates fail due to tlbmiss and the instruction gets flushed because the instruction was working on the wrong address #214,u,g,n,n,n,PM_LSU_FLUSH_RELAUNCH_MISS,If a load that has already returned data and has to relaunch for any reason then gets a miss (erat, setp, data cache), it will often be flushed at relaunch time because the data might be inconsistent ##000000D19C If a load that has already returned data and has to relaunch for any reason then gets a miss (erat, setp, data cache), it will often be flushed at relaunch time because the data might be inconsistent #215,u,g,n,n,n,PM_LSU_FLUSH_UE,Correctable ECC error on reload data, reported at critical data forward time ##000000D99C Correctable ECC error on reload data, reported at critical data forward time #216,u,g,n,n,n,PM_LSU_FLUSH_LHS,Effective Address alias flush : no EA match but Real Address match. If the data has not yet been returned for this load, the instruction will just be rejected, but if it has returned data, it will be flushed ##000000D1A0 Effective Address alias flush : no EA match but Real Address match. If the data has not yet been returned for this load, the instruction will just be rejected, but if it has returned data, it will be flushed #217,u,g,n,n,n,PM_LSU_FLUSH_LHL_SHL,The instruction was flushed because of a sequential load/store consistency. If a load or store hits on an older load that has either been snooped (for loads) or has stale data (for stores). ##000000D9A0 The instruction was flushed because of a sequential load/store consistency. If a load or store hits on an older load that has either been snooped (for loads) or has stale data (for stores). #218,u,g,n,n,n,PM_LSU_FLUSH_SAO,A load-hit-load condition with Strong Address Ordering will have address compare disabled and flush ##000000D1A4 A load-hit-load condition with Strong Address Ordering will have address compare disabled and flush #219,u,g,n,n,n,PM_LSU_FLUSH_LARX_STCX,A larx is flushed because an older larx has an LMQ reservation for the same thread. A stcx is flushed because an older stcx is in the LMQ. The flush happens when the older larx/stcx relaunches ##000000D9A4 A larx is flushed because an older larx has an LMQ reservation for the same thread. A stcx is flushed because an older stcx is in the LMQ. The flush happens when the older larx/stcx relaunches #220,u,g,n,n,n,PM_DSLB_MISS,Data SLB Miss - Total of all segment sizes ##000000D0A8 Data SLB Miss - Total of all segment sizes #221,u,g,n,n,n,PM_ISLB_MISS,Instruction SLB Miss - Total of all segment sizes ##000000D8A8 Instruction SLB Miss - Total of all segment sizes #222,u,g,n,n,n,PM_SRQ_SYNC_CYC,A sync is in the S2Q (edge detect to count) ##000000D0AC A sync is in the S2Q (edge detect to count) #223,u,g,n,n,n,PM_LWSYNC, ##000000D8AC #224,u,g,n,n,n,PM_HWSYNC, ##000000D0B0 #225,u,g,n,n,n,PM_PTESYNC, ##000000D8B0 #226,u,g,n,n,n,PM_LSU0_SRQ_S0_VALID_CYC,Slot 0 of SRQ valid ##000000D0B4 Slot 0 of SRQ valid #227,u,g,n,n,n,PM_LSU0_LRQ_S0_VALID_CYC,Slot 0 of LRQ valid ##000000D8B4 Slot 0 of LRQ valid #228,u,g,n,s,n,PM_LSU_LMQ_FULL_CYC,Counts the number of cycles the LMQ is full ##000000D0B8 Counts the number of cycles the LMQ is full #229,u,g,n,n,n,PM_LSU0_LMQ_S0_VALID,Slot 0 of LMQ valid ##000000D8B8 Slot 0 of LMQ valid #230,u,g,n,s,n,PM_LSU0_1_LRQF_FULL_CYC,Counts the number of cycles the LRQF is full. LRQF is the queue that holds loads between finish and completion. If it fills up, instructions stay in LRQ until completion, potentially backing up the LRQ ##000000D0BC Counts the number of cycles the LRQF is full. LRQF is the queue that holds loads between finish and completion. If it fills up, instructions stay in LRQ until completion, potentially backing up the LRQ #231,u,g,n,s,n,PM_LSU2_3_LRQF_FULL_CYC,Counts the number of cycles the LRQF is full. LRQF is the queue that holds loads between finish and completion. If it fills up, instructions stay in LRQ until completion, potentially backing up the LRQ ##000000D8BC Counts the number of cycles the LRQF is full. LRQF is the queue that holds loads between finish and completion. If it fills up, instructions stay in LRQ until completion, potentially backing up the LRQ #232,u,g,n,s,n,PM_S2Q_FULL,Cycles during which the S2Q is full ##000000E080 Cycles during which the S2Q is full #233,u,g,n,n,n,PM_L1_SW_PREF,Software L1 Prefetches, including SW Transient Prefetches ##000000E880 Software L1 Prefetches, including SW Transient Prefetches #234,u,g,n,n,n,PM_LS0_ERAT_MISS_PREF,LS0 Erat miss due to prefetch ##000000E084 LS0 Erat miss due to prefetch #235,u,g,n,n,n,PM_LS1_ERAT_MISS_PREF,LS1 Erat miss due to prefetch ##000000E884 LS1 Erat miss due to prefetch #236,u,g,n,n,n,PM_LS2_ERAT_MISS_PREF,LS0 Erat miss due to prefetch ##000000E088 LS0 Erat miss due to prefetch #237,u,g,n,n,n,PM_LS3_ERAT_MISS_PREF,LS1 Erat miss due to prefetch ##000000E888 LS1 Erat miss due to prefetch #238,u,g,n,n,n,PM_LSU0_ERAT_HIT,Primary ERAT hit. There is no secondary ERAT ##000000E08C Primary ERAT hit. There is no secondary ERAT #239,u,g,n,n,n,PM_LSU1_ERAT_HIT,Primary ERAT hit. There is no secondary ERAT ##000000E88C Primary ERAT hit. There is no secondary ERAT #240,u,g,n,n,n,PM_LSU2_ERAT_HIT,Primary ERAT hit. There is no secondary ERAT ##000000E090 Primary ERAT hit. There is no secondary ERAT #241,u,g,n,n,n,PM_LSU3_ERAT_HIT,Primary ERAT hit. There is no secondary ERAT ##000000E890 Primary ERAT hit. There is no secondary ERAT #242,u,g,n,n,n,PM_LSU0_TM_L1_HIT,Load tm hit in L1 ##000000E094 Load tm hit in L1 #243,u,g,n,n,n,PM_LSU1_TM_L1_HIT,Load tm hit in L1 ##000000E894 Load tm hit in L1 #244,u,g,n,n,n,PM_LSU2_TM_L1_HIT,Load tm hit in L1 ##000000E098 Load tm hit in L1 #245,u,g,n,n,n,PM_LSU3_TM_L1_HIT,Load tm hit in L1 ##000000E898 Load tm hit in L1 #246,u,g,n,n,n,PM_LSU0_TM_L1_MISS,Load tm L1 miss ##000000E09C Load tm L1 miss #247,u,g,n,n,n,PM_LSU1_TM_L1_MISS,Load tm L1 miss ##000000E89C Load tm L1 miss #248,u,g,n,n,n,PM_LSU2_TM_L1_MISS,Load tm L1 miss ##000000E0A0 Load tm L1 miss #249,u,g,n,n,n,PM_LSU3_TM_L1_MISS,Load tm L1 miss ##000000E8A0 Load tm L1 miss #250,u,g,n,n,n,PM_TMA_REQ_L2, addrs only req to L2 only on the first one,Indication that Load footprint is not expanding ##000000E0A4 addrs only req to L2 only on the first one,Indication that Load footprint is not expanding #251,u,g,n,n,n,PM_TM_FAIL_TLBIE,Transaction failed because there was a TLBIE hit in the bloom filter ##000000E0AC Transaction failed because there was a TLBIE hit in the bloom filter #252,u,g,n,n,n,PM_TM_FAIL_TX_CONFLICT,Transactional conflict from LSU, gets reported to TEXASR ##000000E8AC Transactional conflict from LSU, gets reported to TEXASR #253,u,g,n,n,n,PM_TM_FAIL_NON_TX_CONFLICT,Non transactional conflict from LSU, gets reported to TEXASR ##000000E0B0 Non transactional conflict from LSU, gets reported to TEXASR #254,u,g,n,n,n,PM_TEND_PEND_CYC,TEND latency per thread ##000000E8B0 TEND latency per thread #255,u,g,n,n,n,PM_LS0_TM_DISALLOW,A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it ##000000E0B4 A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it #256,u,g,n,n,n,PM_LS1_TM_DISALLOW,A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it ##000000E8B4 A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it #257,u,g,n,n,n,PM_LS2_TM_DISALLOW,A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it ##000000E0B8 A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it #258,u,g,n,n,n,PM_LS3_TM_DISALLOW,A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it ##000000E8B8 A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it #259,u,g,n,n,n,PM_LS0_PTE_TABLEWALK_CYC,Cycles when a tablewalk is pending on this thread on table 0 ##000000E0BC Cycles when a tablewalk is pending on this thread on table 0 #260,u,g,n,n,n,PM_LS1_PTE_TABLEWALK_CYC,Cycles when a tablewalk is pending on this thread on table 1 ##000000E8BC Cycles when a tablewalk is pending on this thread on table 1 #261,u,g,n,n,n,PM_LSU_STCX_FAIL, ##000000F080 #262,u,g,n,s,n,PM_SNOOP_TLBIE,TLBIE snoop ##000000F880 TLBIE snoop #263,u,g,n,n,n,PM_PTE_PREFETCH,PTE prefetches ##000000F084 PTE prefetches #264,u,g,n,n,n,PM_TABLEWALK_CYC_PREF,tablewalk qualified for pte prefetches ##000000F884 tablewalk qualified for pte prefetches #265,u,g,n,n,n,PM_LSU0_STORE_REJECT,All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met ##000000F088 All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met #266,u,g,n,n,n,PM_LSU1_STORE_REJECT,All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met ##000000F888 All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met #267,u,g,n,n,n,PM_LSU2_STORE_REJECT,All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met ##000000F08C All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met #268,u,g,n,n,n,PM_LSU3_STORE_REJECT,All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met ##000000F88C All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met #269,u,g,n,n,n,PM_LSU0_L1_CAM_CANCEL,ls0 l1 tm cam cancel ##000000F090 ls0 l1 tm cam cancel #270,u,g,n,n,n,PM_LSU1_L1_CAM_CANCEL,ls1 l1 tm cam cancel ##000000F890 ls1 l1 tm cam cancel #271,u,g,n,n,n,PM_LSU2_L1_CAM_CANCEL,ls2 l1 tm cam cancel ##000000F094 ls2 l1 tm cam cancel #272,u,g,n,n,n,PM_LSU3_L1_CAM_CANCEL,ls3 l1 tm cam cancel ##000000F894 ls3 l1 tm cam cancel #273,u,g,n,n,n,PM_XLATE_HPT_MODE,LSU reports every cycle the thread is in HPT translation mode (as opposed to radix mode) ##000000F098 LSU reports every cycle the thread is in HPT translation mode (as opposed to radix mode) #274,u,g,n,n,n,PM_XLATE_RADIX_MODE,LSU reports every cycle the thread is in radix translation mode (as opposed to HPT mode) ##000000F898 LSU reports every cycle the thread is in radix translation mode (as opposed to HPT mode) #275,u,g,n,n,n,PM_XLATE_MISS,The LSU requested a line from L2 for translation. It may be satisfied from any source beyond L2. Includes speculative instructions. Includes instruction, prefetch and demand ##000000F89C The LSU requested a line from L2 for translation. It may be satisfied from any source beyond L2. Includes speculative instructions. Includes instruction, prefetch and demand #276,u,g,n,n,n,PM_DATA_STORE,All ops that drain from s2q to L2 containing data ##000000F0A0 All ops that drain from s2q to L2 containing data #277,u,g,n,n,n,PM_NON_DATA_STORE,All ops that drain from s2q to L2 and contain no data ##000000F8A0 All ops that drain from s2q to L2 and contain no data #278,u,g,n,n,n,PM_DC_PREF_HW_ALLOC,Prefetch stream allocated by the hardware prefetch mechanism ##000000F0A4 Prefetch stream allocated by the hardware prefetch mechanism #279,u,g,n,n,n,PM_DC_PREF_SW_ALLOC,Prefetch stream allocated by software prefetching ##000000F8A4 Prefetch stream allocated by software prefetching #280,u,g,n,n,n,PM_DC_PREF_CONF,A demand load referenced a line in an active prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. Includes forwards and backwards streams ##000000F0A8 A demand load referenced a line in an active prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. Includes forwards and backwards streams #281,u,g,n,n,n,PM_DC_PREF_FUZZY_CONF,A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up) ##000000F8A8 A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up) #282,u,g,n,n,n,PM_DC_PREF_STRIDED_CONF,A demand load referenced a line in an active strided prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. ##000000F0AC A demand load referenced a line in an active strided prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. #283,u,g,n,n,n,PM_DC_DEALLOC_NO_CONF,A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up) ##000000F8AC A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up) #284,u,g,n,n,n,PM_L3_LD_PREF,L3 load prefetch, sourced from a hardware or software stream, was sent to the nest ##000000F0B0 L3 load prefetch, sourced from a hardware or software stream, was sent to the nest #285,u,g,n,n,n,PM_L3_SW_PREF,L3 load prefetch, sourced from a software prefetch stream, was sent to the nest ##000000F8B0 L3 load prefetch, sourced from a software prefetch stream, was sent to the nest #286,u,g,n,n,n,PM_DC_PREF_CONS_ALLOC,Prefetch stream allocated in the conservative phase by either the hardware prefetch mechanism or software prefetch. The sum of this pair subtracted from the total number of allocs will give the total allocs in normal phase ##000000F0B4 Prefetch stream allocated in the conservative phase by either the hardware prefetch mechanism or software prefetch. The sum of this pair subtracted from the total number of allocs will give the total allocs in normal phase #287,u,g,n,n,n,PM_DC_PREF_XCONS_ALLOC,Prefetch stream allocated in the Ultra conservative phase by either the hardware prefetch mechanism or software prefetch ##000000F8B4 Prefetch stream allocated in the Ultra conservative phase by either the hardware prefetch mechanism or software prefetch #288,u,g,n,n,n,PM_LS0_UNALIGNED_ST,Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty ##000000F0B8 Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty #289,u,g,n,n,n,PM_LS1_UNALIGNED_ST,Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty ##000000F8B8 Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty #290,u,g,n,n,n,PM_LS2_UNALIGNED_ST,Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty ##000000F0BC Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty #291,u,g,n,n,n,PM_LS3_UNALIGNED_ST,Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty ##000000F8BC Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty #292,u,g,n,n,n,PM_INST_FROM_L1,Instruction fetches from L1. L1 instruction hit ##0000004080 Instruction fetches from L1. L1 instruction hit #293,u,g,n,n,n,PM_BANK_CONFLICT,Read blocked due to interleave conflict. The ifar logic will detect an interleave conflict and kill the data that was read that cycle. ##0000004880 Read blocked due to interleave conflict. The ifar logic will detect an interleave conflict and kill the data that was read that cycle. #294,u,g,n,n,n,PM_EAT_FULL_CYC,Cycles No room in EAT ##0000004084 Cycles No room in EAT #295,u,g,n,n,n,PM_IBUF_FULL_CYC,Cycles No room in ibuff ##0000004884 Cycles No room in ibuff #296,u,g,n,n,n,PM_IC_DEMAND_REQ,Demand Instruction fetch request ##0000004088 Demand Instruction fetch request #297,u,g,n,n,n,PM_IC_PREF_REQ,Instruction prefetch requests ##0000004888 Instruction prefetch requests #298,u,g,n,n,n,PM_L1_DEMAND_WRITE,Instruction Demand sectors written into IL1 ##000000408C Instruction Demand sectors written into IL1 #299,u,g,n,n,n,PM_IC_PREF_WRITE,Instruction prefetch written into IL1 ##000000488C Instruction prefetch written into IL1 #300,u,g,n,n,n,PM_IC_PREF_CANCEL_PAGE,Prefetch Canceled due to page boundary ##0000004090 Prefetch Canceled due to page boundary #301,u,g,n,n,n,PM_IC_PREF_CANCEL_HIT,Prefetch Canceled due to icache hit ##0000004890 Prefetch Canceled due to icache hit #302,u,g,n,n,n,PM_IC_PREF_CANCEL_L2,L2 Squashed a demand or prefetch request ##0000004094 L2 Squashed a demand or prefetch request #303,u,g,n,n,n,PM_IC_RELOAD_PRIVATE,Reloading line was brought in private for a specific thread. Most lines are brought in shared for all eight threads. If RA does not match then invalidates and then brings it shared to other thread. In P7 line brought in private , then line was invalidat ##0000004894 Reloading line was brought in private for a specific thread. Most lines are brought in shared for all eight threads. If RA does not match then invalidates and then brings it shared to other thread. In P7 line brought in private , then line was invalidat #304,u,g,n,n,n,PM_IC_DEMAND_L2_BHT_REDIRECT, L2 I cache demand request due to BHT redirect, branch redirect ( 2 bubbles 3 cycles) ##0000004098 L2 I cache demand request due to BHT redirect, branch redirect ( 2 bubbles 3 cycles) #305,u,g,n,n,n,PM_IC_DEMAND_L2_BR_REDIRECT, L2 I cache demand request due to branch Mispredict ( 15 cycle path) ##0000004898 L2 I cache demand request due to branch Mispredict ( 15 cycle path) #306,u,g,n,n,n,PM_BR_PRED,Conditional Branch Executed in which the HW predicted the Direction or Target. Includes taken and not taken and is counted at execution time ##000000409C Conditional Branch Executed in which the HW predicted the Direction or Target. Includes taken and not taken and is counted at execution time #307,u,g,n,n,n,PM_BR_CORECT_PRED_TAKEN_CMPL,Conditional Branch Completed in which the HW correctly predicted the direction as taken. Counted at completion time ##000000489C Conditional Branch Completed in which the HW correctly predicted the direction as taken. Counted at completion time #308,u,g,n,n,n,PM_BR_UNCOND,Unconditional Branch Completed. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was covenrted to a Resolve. ##00000040A0 Unconditional Branch Completed. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was covenrted to a Resolve. #309,u,g,n,n,n,PM_BR_PRED_PCACHE,Conditional branch completed that used pattern cache prediction ##00000048A0 Conditional branch completed that used pattern cache prediction #310,u,g,n,n,n,PM_BR_PRED_CCACHE,Conditional Branch Completed that used the Count Cache for Target Prediction ##00000040A4 Conditional Branch Completed that used the Count Cache for Target Prediction #311,u,g,n,n,n,PM_STOP_FETCH_PENDING_CYC,Fetching is stopped due to an incoming instruction that will result in a flush ##00000048A4 Fetching is stopped due to an incoming instruction that will result in a flush #312,u,g,n,n,n,PM_BR_PRED_LSTACK,Conditional Branch Completed that used the Link Stack for Target Prediction ##00000040A8 Conditional Branch Completed that used the Link Stack for Target Prediction #313,u,g,n,n,n,PM_DECODE_FUSION_LD_ST_DISP,32-bit displacement D-form and 16-bit displacement X-form ##00000048A8 32-bit displacement D-form and 16-bit displacement X-form #314,u,g,n,n,n,PM_BR_MPRED_CCACHE,Conditional Branch Completed that was Mispredicted due to the Count Cache Target Prediction ##00000040AC Conditional Branch Completed that was Mispredicted due to the Count Cache Target Prediction #315,u,g,n,n,n,PM_BR_MPRED_LSTACK,Conditional Branch Completed that was Mispredicted due to the Link Stack Target Prediction ##00000048AC Conditional Branch Completed that was Mispredicted due to the Link Stack Target Prediction #316,u,g,n,n,n,PM_BR_PRED_TAKEN_CR,Conditional Branch that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and branches ##00000040B0 Conditional Branch that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and branches #317,u,g,n,n,n,PM_BR_MPRED_PCACHE,Conditional Branch Completed that was Mispredicted due to pattern cache prediction ##00000048B0 Conditional Branch Completed that was Mispredicted due to pattern cache prediction #318,u,g,n,n,n,PM_BR_PRED_TA,Conditional Branch Completed that had its target address predicted. Only XL-form branches set this event. This equal the sum of CCACHE, LSTACK, and PCACHE ##00000040B4 Conditional Branch Completed that had its target address predicted. Only XL-form branches set this event. This equal the sum of CCACHE, LSTACK, and PCACHE #319,u,g,n,n,n,PM_DECODE_FUSION_CONST_GEN,32-bit constant generation ##00000048B4 32-bit constant generation #320,u,g,n,n,n,PM_BR_MPRED_TAKEN_CR,A Conditional Branch that resolved to taken was mispredicted as not taken (due to the BHT Direction Prediction). ##00000040B8 A Conditional Branch that resolved to taken was mispredicted as not taken (due to the BHT Direction Prediction). #321,u,g,n,n,n,PM_BR_MPRED_TAKEN_TA,Conditional Branch Completed that was Mispredicted due to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that resolved Taken set this event. ##00000048B8 Conditional Branch Completed that was Mispredicted due to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that resolved Taken set this event. #322,u,g,n,n,n,PM_THRD_PRIO_0_1_CYC, Cycles thread running at priority level 0 or 1 ##00000040BC Cycles thread running at priority level 0 or 1 #323,u,g,n,n,n,PM_THRD_PRIO_2_3_CYC, Cycles thread running at priority level 2 or 3 ##00000048BC Cycles thread running at priority level 2 or 3 #324,u,g,n,n,n,PM_THRD_PRIO_4_5_CYC, Cycles thread running at priority level 4 or 5 ##0000005080 Cycles thread running at priority level 4 or 5 #325,u,g,n,n,n,PM_THRD_PRIO_6_7_CYC, Cycles thread running at priority level 6 or 7 ##0000005880 Cycles thread running at priority level 6 or 7 #326,u,g,n,n,n,PM_IC_INVALIDATE,Ic line invalidated ##0000005888 Ic line invalidated #327,u,g,n,n,n,PM_SHL_CREATED,Store-Hit-Load Table Entry Created ##000000508C Store-Hit-Load Table Entry Created #328,u,g,n,n,n,PM_SHL_ST_DEP_CREATED,Store-Hit-Load Table Read Hit with entry Enabled ##000000588C Store-Hit-Load Table Read Hit with entry Enabled #329,u,g,n,n,n,PM_IC_MISS_ICBI,threaded version, IC Misses where we got EA dir hit but no sector valids were on. ICBI took line out ##0000005094 threaded version, IC Misses where we got EA dir hit but no sector valids were on. ICBI took line out #330,u,g,n,n,n,PM_LINK_STACK_WRONG_ADD_PRED,Link stack predicts wrong address, because of link stack design limitation or software violating the coding conventions ##0000005098 Link stack predicts wrong address, because of link stack design limitation or software violating the coding conventions #331,u,g,n,n,n,PM_LINK_STACK_INVALID_PTR,It is most often caused by certain types of flush where the pointer is not available. Can result in the data in the link stack becoming unusable. ##0000005898 It is most often caused by certain types of flush where the pointer is not available. Can result in the data in the link stack becoming unusable. #332,u,g,n,n,n,PM_LINK_STACK_CORRECT,Link stack predicts right address ##00000058A0 Link stack predicts right address #333,u,g,n,n,n,PM_FLUSH_MPRED,Branch mispredict flushes. Includes target and address misprecition ##00000050A4 Branch mispredict flushes. Includes target and address misprecition #334,u,g,n,n,n,PM_FLUSH_LSU,LSU flushes. Includes all lsu flushes ##00000058A4 LSU flushes. Includes all lsu flushes #335,u,g,n,n,n,PM_EAT_FORCE_MISPRED,XL-form branch was mispredicted due to the predicted target address missing from EAT. The EAT forces a mispredict in this case since there is no predicated target to validate. This is a rare case that may occur when the EAT is full and a branch is issued ##00000050A8 XL-form branch was mispredicted due to the predicted target address missing from EAT. The EAT forces a mispredict in this case since there is no predicated target to validate. This is a rare case that may occur when the EAT is full and a branch is issued #336,u,g,n,n,n,PM_DECODE_HOLD_ICT_FULL,Counts the number of cycles in which the IFU was not able to decode and transmit one or more instructions because all itags were in use. This means the ICT is full for this thread ##00000058A8 Counts the number of cycles in which the IFU was not able to decode and transmit one or more instructions because all itags were in use. This means the ICT is full for this thread #337,u,g,n,n,n,PM_BTAC_BAD_RESULT,BTAC thinks branch will be taken but it is either predicted not-taken by the BHT, or the target address is wrong (less common). In both cases, a redirect will happen ##00000050B0 BTAC thinks branch will be taken but it is either predicted not-taken by the BHT, or the target address is wrong (less common). In both cases, a redirect will happen #338,u,g,n,n,n,PM_BTAC_GOOD_RESULT,BTAC predicts a taken branch and the BHT agrees, and the target address is correct ##00000058B0 BTAC predicts a taken branch and the BHT agrees, and the target address is correct #339,u,g,n,n,n,PM_TAGE_CORRECT_TAKEN_CMPL,The TAGE overrode BHT direction prediction and it was correct. Counted at completion for taken branches only ##00000050B4 The TAGE overrode BHT direction prediction and it was correct. Counted at completion for taken branches only #340,u,g,n,n,n,PM_TAGE_CORRECT,The TAGE overrode BHT direction prediction and it was correct. Includes taken and not taken and is counted at execution time ##00000058B4 The TAGE overrode BHT direction prediction and it was correct. Includes taken and not taken and is counted at execution time #341,u,g,n,n,n,PM_TAGE_OVERRIDE_WRONG,The TAGE overrode BHT direction prediction but it was incorrect. Counted at completion for taken branches only ##00000050B8 The TAGE overrode BHT direction prediction but it was incorrect. Counted at completion for taken branches only #342,u,g,n,n,n,PM_TAGE_OVERRIDE_WRONG_SPEC,The TAGE overrode BHT direction prediction and it was correct. Includes taken and not taken and is counted at execution time ##00000058B8 The TAGE overrode BHT direction prediction and it was correct. Includes taken and not taken and is counted at execution time #343,u,g,n,s,n,PM_L3_CO_MEM,L3 CO to memory OR of port 0 and 1 (lossy = may undercount if two cresp come in the same cyc) ##00000260A0 L3 CO to memory OR of port 0 and 1 (lossy = may undercount if two cresp come in the same cyc) #344,u,g,n,s,n,PM_L3_CO_L31,L3 CO to L3.1 OR of port 0 and 1 (lossy = may undercount if two cresps come in the same cyc) ##00000268A0 L3 CO to L3.1 OR of port 0 and 1 (lossy = may undercount if two cresps come in the same cyc) #345,u,g,n,s,n,PM_L3_CI_HIT,L3 Castins Hit (total count) ##00000260A2 L3 Castins Hit (total count) #346,u,g,n,s,n,PM_L3_CI_MISS,L3 castins miss (total count) ##00000268A2 L3 castins miss (total count) #347,u,g,n,n,n,PM_L3_LD_HIT,L3 Hits for demand LDs ##00000260A4 L3 Hits for demand LDs #348,u,g,n,n,n,PM_L3_LD_MISS,L3 Misses for demand LDs ##00000268A4 L3 Misses for demand LDs #349,u,g,n,s,n,PM_NON_TM_RST_SC,Non-TM snoop hits line in L3 that is TM_SC state and causes it to be invalidated ##00000260A6 Non-TM snoop hits line in L3 that is TM_SC state and causes it to be invalidated #350,u,g,n,s,n,PM_TM_RST_SC,TM snoop hits line in L3 that is TM_SC state and causes it to be invalidated ##00000268A6 TM snoop hits line in L3 that is TM_SC state and causes it to be invalidated #351,u,g,n,n,n,PM_L3_PF_HIT_L3,L3 PF hit in L3 (abandoned) ##00000260A8 L3 PF hit in L3 (abandoned) #352,u,g,n,n,n,PM_RD_HIT_PF,RD machine hit L3 PF machine ##00000268A8 RD machine hit L3 PF machine #353,u,g,n,s,n,PM_L3_P0_LCO_DATA,LCO sent with data port 0 ##00000260AA LCO sent with data port 0 #354,u,g,n,s,n,PM_L3_P1_LCO_DATA,LCO sent with data port 1 ##00000268AA LCO sent with data port 1 #355,u,g,n,s,n,PM_L3_PF_USAGE,Rotating sample of 32 PF actives ##00000260AC Rotating sample of 32 PF actives #356,u,g,n,s,n,PM_L3_RD_USAGE,Rotating sample of 16 RD actives ##00000268AC Rotating sample of 16 RD actives #357,u,g,n,n,n,PM_L3_P2_PF_RTY,L3 PF received retry port 2, every retry counted ##00000260AE L3 PF received retry port 2, every retry counted #358,u,g,n,n,n,PM_L3_P3_PF_RTY,L3 PF received retry port 3, every retry counted ##00000268AE L3 PF received retry port 3, every retry counted #359,u,g,n,s,n,PM_L3_P0_GRP_PUMP,L3 PF sent with grp scope port 0, counts even retried requests ##00000260B0 L3 PF sent with grp scope port 0, counts even retried requests #360,u,g,n,s,n,PM_L3_P1_GRP_PUMP,L3 PF sent with grp scope port 1, counts even retried requests ##00000268B0 L3 PF sent with grp scope port 1, counts even retried requests #361,u,g,n,s,n,PM_L3_SYS_GUESS_CORRECT,Prefetch scope predictor selected VGS or RNS and was correct ##00000260B2 Prefetch scope predictor selected VGS or RNS and was correct #362,u,g,n,s,n,PM_L3_LOC_GUESS_WRONG,Prefetch scope predictor selected LNS, but was wrong ##00000268B2 Prefetch scope predictor selected LNS, but was wrong #363,u,g,n,s,n,PM_L3_P2_LCO_RTY,L3 initiated LCO received retry on port 2 (can try 4 times) ##00000260B4 L3 initiated LCO received retry on port 2 (can try 4 times) #364,u,g,n,s,n,PM_L3_P3_LCO_RTY,L3 initiated LCO received retry on port 3 (can try 4 times) ##00000268B4 L3 initiated LCO received retry on port 3 (can try 4 times) #365,u,g,n,s,n,PM_L3_WI0_BUSY,Rotating sample of 8 WI valid (duplicate) ##00000260B6 Rotating sample of 8 WI valid (duplicate) #366,u,g,n,n,n,PM_L2_LD_MISS,All successful D-Side Load dispatches that were an L2 miss for this thread ##0000026080 All successful D-Side Load dispatches that were an L2 miss for this thread #367,u,g,n,n,n,PM_L2_ST_MISS,All successful D-Side Store dispatches that were an L2 miss for this thread ##0000026880 All successful D-Side Store dispatches that were an L2 miss for this thread #368,u,g,n,s,n,PM_L2_IC_INV,I-cache Invalidates sent over the realod bus to the core ##0000026082 I-cache Invalidates sent over the realod bus to the core #369,u,g,n,s,n,PM_L2_DC_INV,D-cache invalidates sent over the reload bus to the core ##0000026882 D-cache invalidates sent over the reload bus to the core #370,u,g,n,n,n,PM_L2_RCLD_DISP_FAIL_OTHER, All D-side-Ld or I-side-instruction-fetch dispatch attempts for this thread that failed due to reasons other than an address collision conflicts with an L2 machines (e.g. Read-Claim/Snoop machine not available) ##0000026084 All D-side-Ld or I-side-instruction-fetch dispatch attempts for this thread that failed due to reasons other than an address collision conflicts with an L2 machines (e.g. Read-Claim/Snoop machine not available) #371,u,g,n,s,n,PM_DSIDE_MRU_TOUCH, D-side L2 MRU touch commands sent to the L2 ##0000026884 D-side L2 MRU touch commands sent to the L2 #372,u,g,n,s,n,PM_CO_TM_SC_FOOTPRINT,L2 did a cleanifdirty CO to the L3 (ie created an SC line in the L3) OR L2 TM_store hit dirty HPC line and L3 indicated SC line formed in L3 on RDR bus ##0000026086 L2 did a cleanifdirty CO to the L3 (ie created an SC line in the L3) OR L2 TM_store hit dirty HPC line and L3 indicated SC line formed in L3 on RDR bus #373,u,g,n,s,n,PM_L2_GRP_GUESS_CORRECT,L2 guess grp (GS or NNS) and guess was correct (data intra-group AND ^on-chip) ##0000026088 L2 guess grp (GS or NNS) and guess was correct (data intra-group AND ^on-chip) #374,u,g,n,s,n,PM_L2_GRP_GUESS_WRONG,L2 guess grp (GS or NNS) and guess was not correct (ie data on-chip OR beyond-group) ##0000026888 L2 guess grp (GS or NNS) and guess was not correct (ie data on-chip OR beyond-group) #375,u,g,n,n,n,PM_ISIDE_DISP_FAIL_ADDR, All I-side-instruction-fetch dispatch attempts for this thread that failed due to an address collision conflict with an L2 machine already working on this line (e.g. ld-hit-stq or RC/CO/SN machines) ##000002608A All I-side-instruction-fetch dispatch attempts for this thread that failed due to an address collision conflict with an L2 machine already working on this line (e.g. ld-hit-stq or RC/CO/SN machines) #376,u,g,n,n,n,PM_ISIDE_DISP_FAIL_OTHER, All I-side-instruction-fetch dispatch attempts for this thread that failed due to reasons other than an address collision conflict with an L2 machine (e.g. no available RC/CO machines) ##000002688A All I-side-instruction-fetch dispatch attempts for this thread that failed due to reasons other than an address collision conflict with an L2 machine (e.g. no available RC/CO machines) #377,u,g,n,s,n,PM_RC0_BUSY,RC mach 0 Busy. Used by PMU to sample ave RC lifetime (mach0 used as sample point) ##000002608C RC mach 0 Busy. Used by PMU to sample ave RC lifetime (mach0 used as sample point) #378,u,g,n,s,n,PM_CO_USAGE,Continuous 16 cycle (2to1) window where this signals rotates thru sampling each CO machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running ##000002688C Continuous 16 cycle (2to1) window where this signals rotates thru sampling each CO machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running #379,u,g,n,s,n,PM_TM_LD_CONF,TM Load (fav or non-fav) ran into conflict (failed) ##000002608E TM Load (fav or non-fav) ran into conflict (failed) #380,u,g,n,s,n,PM_TM_FAV_CAUSED_FAIL,TM Load (fav) caused another thread to fail ##000002688E TM Load (fav) caused another thread to fail #381,u,g,n,s,n,PM_SN0_BUSY,SN mach 0 Busy. Used by PMU to sample ave SN lifetime (mach0 used as sample point) ##0000026090 SN mach 0 Busy. Used by PMU to sample ave SN lifetime (mach0 used as sample point) #382,u,g,n,s,n,PM_ISIDE_L2MEMACC,Valid when first beat of data comes in for an I-side fetch where data came from memory ##0000026890 Valid when first beat of data comes in for an I-side fetch where data came from memory #383,u,g,n,n,n,PM_L2_LD_MISS_64B,All successful D-side load dispatches that were an L2 miss (NOT Sx,Tx,Mx) for this thread and the RC calculated the request should be for 64B(i.e., M=1) ##0000026092 All successful D-side load dispatches that were an L2 miss (NOT Sx,Tx,Mx) for this thread and the RC calculated the request should be for 64B(i.e., M=1) #384,u,g,n,n,n,PM_L2_ST_MISS_64B,All successful D-side store dispatches that were an L2 miss (NOT Sx,Tx,Mx) for this thread and the RC calculated the request should be for 64B (i.e., M=1) ##0000026892 All successful D-side store dispatches that were an L2 miss (NOT Sx,Tx,Mx) for this thread and the RC calculated the request should be for 64B (i.e., M=1) #385,u,g,n,n,n,PM_L2_LD_HIT, All successful D-side-Ld or I-side-instruction-fetch dispatches for this thread that were L2 hits ##000002609E All successful D-side-Ld or I-side-instruction-fetch dispatches for this thread that were L2 hits #386,u,g,n,n,n,PM_L2_ST_HIT, All successful D-side store dispatches for this thread that were L2 hits ##000002689E All successful D-side store dispatches for this thread that were L2 hits $$$$$$$$ { counter 3} #0,u,g,n,n,n,PM_SUSPENDED,Counter OFF ##0000030000 Counter OFF #1,u,g,n,s,n,PM_CYC,Cycles ##000003001E Cycles #2,u,g,n,n,n,PM_INST_CMPL,PPC instructions completed ##0000030002 PPC instructions completed #3,u,g,n,n,n,PM_INST_DISP,PPC Dispatched ##00000300F2 PPC Dispatched #4,u,g,n,n,n,PM_CMPLU_STALL_EMQ_FULL,Finish stall because the next to finish instruction suffered an ERAT miss and the EMQ was full ##0000030004 Finish stall because the next to finish instruction suffered an ERAT miss and the EMQ was full #5,u,g,n,n,n,PM_CMPLU_STALL_OTHER_CMPL,Instructions the core completed while this tread was stalled ##0000030006 Instructions the core completed while this tread was stalled #6,u,g,n,n,n,PM_DISP_STARVED,Dispatched Starved ##0000030008 Dispatched Starved #7,u,g,n,n,n,PM_CMPLU_STALL_PM,Finish stall because the NTF instruction was issued to the Permute execution pipe and waiting to finish. Includes permute and decimal fixed point instructions (128 bit BCD arithmetic) + a few 128 bit fixpoint add/subtract instructions with carry. Not qualified by vector or multicycle ##000003000A Finish stall because the NTF instruction was issued to the Permute execution pipe and waiting to finish. Includes permute and decimal fixed point instructions (128 bit BCD arithmetic) + a few 128 bit fixpoint add/subtract instructions with carry. Not qualified by vector or multicycle #8,u,g,n,s,n,PM_FREQ_DOWN,Power Management: Below Threshold B ##000003000C Power Management: Below Threshold B #9,u,g,n,n,n,PM_FXU_1PLUS_BUSY,At least one of the 4 FXU units is busy ##000003000E At least one of the 4 FXU units is busy #10,u,g,n,n,n,PM_PMC2_OVERFLOW,Overflow from counter 2 ##0000030010 Overflow from counter 2 #11,u,g,n,n,n,PM_FLUSH_COMPLETION,The instruction that was next to complete did not complete because it suffered a flush ##0000030012 The instruction that was next to complete did not complete because it suffered a flush #12,u,g,n,n,n,PM_CMPLU_STALL_STORE_FIN_ARB,Finish stall because the NTF instruction was a store waiting for a slot in the store finish pipe. This means the instruction is ready to finish but there are instructions ahead of it, using the finish pipe ##0000030014 Finish stall because the NTF instruction was a store waiting for a slot in the store finish pipe. This means the instruction is ready to finish but there are instructions ahead of it, using the finish pipe #13,u,g,n,n,n,PM_CMPLU_STALL_SRQ_FULL,Finish stall because the NTF instruction was a store that was held in LSAQ because the SRQ was full ##0000030016 Finish stall because the NTF instruction was a store that was held in LSAQ because the SRQ was full #14,u,g,n,n,n,PM_ICT_NOSLOT_DISP_HELD_HB_FULL,Ict empty for this thread due to dispatch holds because the History Buffer was full. Could be GPR/VSR/VMR/FPR/CR/XVF ##0000030018 Ict empty for this thread due to dispatch holds because the History Buffer was full. Could be GPR/VSR/VMR/FPR/CR/XVF #15,u,g,n,n,n,PM_DATA_TABLEWALK_CYC,Data Tablewalk Cycles. Could be 1 or 2 active tablewalks. Includes data prefetches. ##000003001A Data Tablewalk Cycles. Could be 1 or 2 active tablewalks. Includes data prefetches. #16,u,g,n,n,n,PM_LSU_REJECT_LMQ_FULL,LSU Reject due to LMQ full (up to 4 per cycles) ##000003001C LSU Reject due to LMQ full (up to 4 per cycles) #17,u,g,n,n,n,PM_PMC2_REWIND,PMC2 Rewind Event (did not match condition) ##0000030020 PMC2 Rewind Event (did not match condition) #18,u,g,n,n,n,PM_PMC4_SAVED,PMC4 Rewind Value saved (matched condition) ##0000030022 PMC4 Rewind Value saved (matched condition) #19,u,g,n,n,n,PM_PMC6_OVERFLOW,Overflow from counter 6 ##0000030024 Overflow from counter 6 #20,u,g,n,n,n,PM_CMPLU_STALL_STORE_DATA,Finish stall because the next to finish instruction was a store waiting on data ##0000030026 Finish stall because the next to finish instruction was a store waiting on data #21,u,g,n,n,n,PM_CMPLU_STALL_SPEC_FINISH,Finish stall while waiting for the non-speculative finish of either a stcx waiting for its result or a load waiting for non-critical sectors of data and ECC ##0000030028 Finish stall while waiting for the non-speculative finish of either a stcx waiting for its result or a load waiting for non-critical sectors of data and ECC #22,u,g,n,n,m,PM_MRK_L2_RC_DONE,Marked RC done ##000003012A Marked RC done #23,u,g,n,n,m,PM_MRK_ST_FWD,Marked st forwards ##000003012C Marked st forwards #24,u,g,n,n,m,PM_MRK_INST_FIN,marked instruction finished ##0000030130 marked instruction finished #25,u,g,n,n,m,PM_MRK_VSU_FIN,VSU marked instr finish ##0000030132 VSU marked instr finish #26,u,g,n,n,m,PM_MRK_ST_CMPL_INT,marked store finished with intervention ##0000030134 marked store finished with intervention #27,u,g,n,n,n,PM_CMPLU_STALL_DMISS_LMEM,Completion stall due to cache miss that resolves in local memory ##0000030038 Completion stall due to cache miss that resolves in local memory #28,u,g,n,n,n,PM_CMPLU_STALL_EXCEPTION,Cycles in which the NTC instruction is not allowed to complete because it was interrupted by ANY exception, which has to be serviced before the instruction can complete ##000003003A Cycles in which the NTC instruction is not allowed to complete because it was interrupted by ANY exception, which has to be serviced before the instruction can complete #29,u,g,n,n,n,PM_CMPLU_STALL_NESTED_TEND,Completion stall because the ISU is updating the TEXASR to keep track of the nested tend and decrement the TEXASR nested level. This is a short delay ##000003003C Completion stall because the ISU is updating the TEXASR to keep track of the nested tend and decrement the TEXASR nested level. This is a short delay #30,u,g,n,n,m,PM_MRK_STALL_CMPLU_CYC,Number of cycles the marked instruction is experiencing a stall while it is next to complete (NTC) ##000003013E Number of cycles the marked instruction is experiencing a stall while it is next to complete (NTC) #31,u,g,n,n,n,PM_DATA_FROM_L2_DISP_CONFLICT_LDHITST,The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a demand load ##000003C040 The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a demand load #32,u,g,n,n,n,PM_DATA_FROM_L3_DISP_CONFLICT,The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a demand load ##000003C042 The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a demand load #33,u,g,n,n,n,PM_DATA_FROM_L31_ECO_SHR,The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a demand load ##000003C044 The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a demand load #34,u,g,n,n,n,PM_DATA_FROM_L21_SHR,The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a demand load ##000003C046 The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a demand load #35,u,g,n,n,n,PM_DATA_FROM_DL2L3_SHR,The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load ##000003C048 The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load #36,u,g,n,n,n,PM_DATA_FROM_RMEM,The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a demand load ##000003C04A The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a demand load #37,u,g,n,n,n,PM_DATA_FROM_DL4,The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a demand load ##000003C04C The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a demand load #38,u,g,n,n,n,PM_INST_FROM_L2_DISP_CONFLICT_LDHITST,The processor's Instruction cache was reloaded from local core's L2 with load hit store conflict due to an instruction fetch (not prefetch) ##0000034040 The processor's Instruction cache was reloaded from local core's L2 with load hit store conflict due to an instruction fetch (not prefetch) #39,u,g,n,n,n,PM_INST_FROM_L3_DISP_CONFLICT,The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to an instruction fetch (not prefetch) ##0000034042 The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to an instruction fetch (not prefetch) #40,u,g,n,n,n,PM_INST_FROM_L31_ECO_SHR,The processor's Instruction cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to an instruction fetch (not prefetch) ##0000034044 The processor's Instruction cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to an instruction fetch (not prefetch) #41,u,g,n,n,n,PM_INST_FROM_L21_SHR,The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due to an instruction fetch (not prefetch) ##0000034046 The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due to an instruction fetch (not prefetch) #42,u,g,n,n,n,PM_INST_FROM_DL2L3_SHR,The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction fetch (not prefetch) ##0000034048 The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction fetch (not prefetch) #43,u,g,n,n,n,PM_INST_FROM_RMEM,The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to an instruction fetch (not prefetch) ##000003404A The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to an instruction fetch (not prefetch) #44,u,g,n,n,n,PM_INST_FROM_DL4,The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to an instruction fetch (not prefetch) ##000003404C The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to an instruction fetch (not prefetch) #45,u,g,n,n,m,PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER_CYC,Duration in cycles to reload from local core's L2 with dispatch conflict due to a marked load ##000003D140 Duration in cycles to reload from local core's L2 with dispatch conflict due to a marked load #46,u,g,n,n,m,PM_MRK_DATA_FROM_LMEM,The processor's data cache was reloaded from the local chip's Memory due to a marked load ##000003D142 The processor's data cache was reloaded from the local chip's Memory due to a marked load #47,u,g,n,n,m,PM_MRK_DATA_FROM_L2_MEPF_CYC,Duration in cycles to reload from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load ##000003D144 Duration in cycles to reload from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load #48,u,g,n,n,m,PM_MRK_DATA_FROM_L3_NO_CONFLICT,The processor's data cache was reloaded from local core's L3 without conflict due to a marked load ##000003D146 The processor's data cache was reloaded from local core's L3 without conflict due to a marked load #49,u,g,n,n,m,PM_MRK_DATA_FROM_L21_MOD_CYC,Duration in cycles to reload with Modified (M) data from another core's L2 on the same chip due to a marked load ##000003D148 Duration in cycles to reload with Modified (M) data from another core's L2 on the same chip due to a marked load #50,u,g,n,n,m,PM_MRK_DATA_FROM_DMEM,The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a marked load ##000003D14C The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a marked load #51,u,g,n,n,m,PM_MRK_DATA_FROM_DL2L3_MOD,The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load ##000003D14E The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load #52,u,g,n,n,n,PM_IPTEG_FROM_L3_DISP_CONFLICT,A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a instruction side request ##0000035042 A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a instruction side request #53,u,g,n,n,n,PM_IPTEG_FROM_L31_ECO_SHR,A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a instruction side request ##0000035044 A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a instruction side request #54,u,g,n,n,n,PM_IPTEG_FROM_L21_SHR,A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a instruction side request ##0000035046 A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a instruction side request #55,u,g,n,n,n,PM_IPTEG_FROM_DL2L3_SHR,A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request ##0000035048 A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request #56,u,g,n,n,n,PM_IPTEG_FROM_RMEM,A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a instruction side request ##000003504A A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a instruction side request #57,u,g,n,n,n,PM_IPTEG_FROM_DL4,A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a instruction side request ##000003504C A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a instruction side request #58,u,g,n,n,n,PM_DARQ0_4_6_ENTRIES,Cycles in which 4, 5, or 6 DARQ entries (out of 12) are in use ##000003504E Cycles in which 4, 5, or 6 DARQ entries (out of 12) are in use #59,u,g,n,n,n,PM_DPTEG_FROM_L3_DISP_CONFLICT,A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000003E042 A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #60,u,g,n,n,n,PM_DPTEG_FROM_L31_ECO_SHR,A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000003E044 A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #61,u,g,n,n,n,PM_DPTEG_FROM_L21_SHR,A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000003E046 A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #62,u,g,n,n,n,PM_DPTEG_FROM_DL2L3_SHR,A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000003E048 A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #63,u,g,n,n,n,PM_DPTEG_FROM_RMEM,A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000003E04A A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #64,u,g,n,n,n,PM_DPTEG_FROM_DL4,A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000003E04C A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #65,u,g,n,n,m,PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT,A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000003F142 A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #66,u,g,n,n,m,PM_MRK_DPTEG_FROM_L31_ECO_SHR,A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000003F144 A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #67,u,g,n,n,m,PM_MRK_DPTEG_FROM_L21_SHR,A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000003F146 A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #68,u,g,n,n,m,PM_MRK_DPTEG_FROM_DL2L3_SHR,A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000003F148 A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #69,u,g,n,n,m,PM_MRK_DPTEG_FROM_RMEM,A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000003F14A A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #70,u,g,n,n,m,PM_MRK_DPTEG_FROM_DL4,A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000003F14C A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #71,u,g,n,n,n,PM_SYS_PUMP_CPRED,Initial and Final Pump Scope was system pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) ##0000030050 Initial and Final Pump Scope was system pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) #72,u,g,n,n,n,PM_SYS_PUMP_MPRED,Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) ##0000030052 Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) #73,u,g,n,n,m,PM_MRK_FAB_RSP_DCLAIM,Marked store had to do a dclaim ##0000030154 Marked store had to do a dclaim #74,u,g,n,n,n,PM_TM_ABORTS,Number of TM transactions aborted ##0000030056 Number of TM transactions aborted #75,u,g,n,n,n,PM_TLBIE_FIN,tlbie finished ##0000030058 tlbie finished #76,u,g,n,s,n,PM_ISQ_0_8_ENTRIES,Cycles in which 8 or less Issue Queue entries are in use. This is a shared event, not per thread ##000003005A Cycles in which 8 or less Issue Queue entries are in use. This is a shared event, not per thread #77,u,g,n,s,n,PM_BFU_BUSY,Cycles in which all 4 Binary Floating Point units are busy. The BFU is running at capacity ##000003005C Cycles in which all 4 Binary Floating Point units are busy. The BFU is running at capacity #78,u,g,n,n,m,PM_MRK_FAB_RSP_CLAIM_RTY,Sampled store did a rwitm and got a rty ##000003015E Sampled store did a rwitm and got a rty #79,u,g,n,n,n,PM_DATA_SYS_PUMP_CPRED,Initial and Final Pump Scope was system pump (prediction=correct) for a demand load ##000003C050 Initial and Final Pump Scope was system pump (prediction=correct) for a demand load #80,u,g,n,n,n,PM_DATA_SYS_PUMP_MPRED,Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for a demand load ##000003C052 Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for a demand load #81,u,g,n,n,n,PM_DERAT_MISS_16M_2M,Data ERAT Miss (Data TLB Access) page size 16M (HPT mode) or 2M (Radix mode) ##000003C054 Data ERAT Miss (Data TLB Access) page size 16M (HPT mode) or 2M (Radix mode) #82,u,g,n,n,n,PM_LARX_FIN,Larx finished ##000003C058 Larx finished #83,u,g,n,n,n,PM_CMPLU_STALL_VDPLONG,Finish stall because the NTF instruction was a scalar multi-cycle instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Qualified by NOT vector AND multicycle ##000003C05A Finish stall because the NTF instruction was a scalar multi-cycle instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Qualified by NOT vector AND multicycle #84,u,g,n,n,n,PM_CMPLU_STALL_VFXU,Finish stall due to a vector fixed point instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes ##000003C05C Finish stall due to a vector fixed point instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes #85,u,g,n,n,n,PM_MEM_RWITM,Memory Read With Intent to Modify for this thread ##000003C05E Memory Read With Intent to Modify for this thread #86,u,g,n,n,n,PM_INST_SYS_PUMP_CPRED,Initial and Final Pump Scope was system pump (prediction=correct) for an instruction fetch ##0000034050 Initial and Final Pump Scope was system pump (prediction=correct) for an instruction fetch #87,u,g,n,n,n,PM_INST_SYS_PUMP_MPRED,Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for an instruction fetch ##0000034052 Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for an instruction fetch #88,u,g,n,n,n,PM_PARTIAL_ST_FIN,Any store finished by an LSU slice ##0000034054 Any store finished by an LSU slice #89,u,g,n,n,n,PM_CMPLU_STALL_LSU_MFSPR,Finish stall because the NTF instruction was a mfspr instruction targeting an LSU SPR and it was waiting for the register data to be returned ##0000034056 Finish stall because the NTF instruction was a mfspr instruction targeting an LSU SPR and it was waiting for the register data to be returned #90,u,g,n,n,n,PM_ICT_NOSLOT_BR_MPRED_ICMISS,Ict empty for this thread due to Icache Miss and branch mispred ##0000034058 Ict empty for this thread due to Icache Miss and branch mispred #91,u,g,n,n,n,PM_CMPLU_STALL_DPLONG,Finish stall because the NTF instruction was a scalar multi-cycle instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Qualified by NOT vector AND multicycle ##000003405C Finish stall because the NTF instruction was a scalar multi-cycle instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Qualified by NOT vector AND multicycle #92,u,g,n,n,m,PM_MRK_DERAT_MISS_16M_2M,Marked Data ERAT Miss (Data TLB Access) page size 16M (hpt mode) or 2M (radix mode) ##000003D154 Marked Data ERAT Miss (Data TLB Access) page size 16M (hpt mode) or 2M (radix mode) #93,u,g,n,n,n,PM_VSU_DP_FSQRT_FDIV,vector versions of fdiv,fsqrt ##000003D058 vector versions of fdiv,fsqrt #94,u,g,n,n,n,PM_NTC_ISSUE_HELD_OTHER,The NTC instruction is being held at dispatch during regular pipeline cycles, or because the VSU is busy with multi-cycle instructions, or because of a write-back collision with VSU ##000003D05A The NTC instruction is being held at dispatch during regular pipeline cycles, or because the VSU is busy with multi-cycle instructions, or because of a write-back collision with VSU #95,u,g,n,n,n,PM_DISP_HELD_HB_FULL,Dispatch held due to History Buffer full. Could be GPR/VSR/VMR/FPR/CR/XVF ##000003D05C Dispatch held due to History Buffer full. Could be GPR/VSR/VMR/FPR/CR/XVF #96,u,g,n,n,n,PM_MULT_MRK,mult marked instr ##000003D15E mult marked instr #97,u,g,n,n,m,PM_MRK_DATA_FROM_RL2L3_SHR,The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load ##0000035150 The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load #98,u,g,n,n,m,PM_MRK_DATA_FROM_L2MISS_CYC,Duration in cycles to reload from a location other than the local core's L2 due to a marked load ##0000035152 Duration in cycles to reload from a location other than the local core's L2 due to a marked load #99,u,g,n,n,m,PM_MRK_DATA_FROM_L3_CYC,Duration in cycles to reload from local core's L3 due to a marked load ##0000035154 Duration in cycles to reload from local core's L3 due to a marked load #100,u,g,n,n,m,PM_MRK_DATA_FROM_L31_SHR_CYC,Duration in cycles to reload with Shared (S) data from another core's L3 on the same chip due to a marked load ##0000035156 Duration in cycles to reload with Shared (S) data from another core's L3 on the same chip due to a marked load #101,u,g,n,n,m,PM_MRK_DATA_FROM_L31_ECO_MOD_CYC,Duration in cycles to reload with Modified (M) data from another core's ECO L3 on the same chip due to a marked load ##0000035158 Duration in cycles to reload with Modified (M) data from another core's ECO L3 on the same chip due to a marked load #102,u,g,n,n,m,PM_MRK_DATA_FROM_ON_CHIP_CACHE_CYC,Duration in cycles to reload either shared or modified data from another core's L2/L3 on the same chip due to a marked load ##000003515A Duration in cycles to reload either shared or modified data from another core's L2/L3 on the same chip due to a marked load #103,u,g,n,n,m,PM_MRK_DATA_FROM_RL4,The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a marked load ##000003515C The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a marked load #104,u,g,n,n,m,PM_MRK_BACK_BR_CMPL,Marked branch instruction completed with a target address less than current instruction address ##000003515E Marked branch instruction completed with a target address less than current instruction address #105,u,g,n,n,n,PM_DARQ1_4_6_ENTRIES,Cycles in which 4, 5, or 6 DARQ1 entries (out of 12) are in use ##000003E050 Cycles in which 4, 5, or 6 DARQ1 entries (out of 12) are in use #106,u,g,n,n,n,PM_ICT_NOSLOT_IC_L3,Ict empty for this thread due to icache misses that were sourced from the local L3 ##000003E052 Ict empty for this thread due to icache misses that were sourced from the local L3 #107,u,g,n,n,n,PM_LD_MISS_L1,Load Missed L1, counted at execution time (can be greater than loads finished). LMQ merges are not included in this count. i.e. if a load instruction misses on an address that is already allocated on the LMQ, this event will not increment for that load). Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load. ##000003E054 Load Missed L1, counted at execution time (can be greater than loads finished). LMQ merges are not included in this count. i.e. if a load instruction misses on an address that is already allocated on the LMQ, this event will not increment for that load). Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load. #108,u,g,n,n,m,PM_MRK_STCX_FAIL,marked stcx failed ##000003E158 marked stcx failed #109,u,g,n,n,n,PM_L3_CO_MEPF,L3 castouts in Mepf state for this thread ##000003E05E L3 castouts in Mepf state for this thread #110,u,g,n,n,m,PM_MRK_ST_DRAIN_TO_L2DISP_CYC,cycles to drain st from core to L2 ##000003F150 cycles to drain st from core to L2 #111,u,g,n,n,n,PM_RADIX_PWC_L4_PTE_FROM_L3MISS,A Page Table Entry was reloaded to a level 4 page walk cache from beyond the core's L3 data cache. This is the deepest level of PWC possible for a translation. The source could be local/remote/distant memory or another core's cache ##000003F054 A Page Table Entry was reloaded to a level 4 page walk cache from beyond the core's L3 data cache. This is the deepest level of PWC possible for a translation. The source could be local/remote/distant memory or another core's cache #112,u,g,n,n,n,PM_RADIX_PWC_L1_PDE_FROM_L3,A Page Directory Entry was reloaded to a level 1 page walk cache from the core's L3 data cache ##000003F058 A Page Directory Entry was reloaded to a level 1 page walk cache from the core's L3 data cache #113,u,g,n,n,n,PM_RADIX_PWC_L2_PDE_FROM_L3,A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L3 data cache ##000003F05A A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L3 data cache #114,u,g,n,n,n,PM_RADIX_PWC_L3_PTE_FROM_L3,A Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 data cache. This implies that a level 4 PWC access was not necessary for this translation ##000003F05E A Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 data cache. This implies that a level 4 PWC access was not necessary for this translation #115,u,g,n,n,n,PM_TM_TRANS_RUN_INST,Run instructions completed in transactional state (gated by the run latch) ##0000030060 Run instructions completed in transactional state (gated by the run latch) #116,u,g,n,n,m,PM_MRK_LSU_DERAT_MISS,Marked derat reload (miss) for any page size ##0000030162 Marked derat reload (miss) for any page size #117,u,g,n,s,n,PM_DARQ_STORE_XMIT,The DARQ attempted to transmit a store into an LSAQ or SRQ entry. Includes rejects. Not qualified by thread, so it includes counts for the whole core ##0000030064 The DARQ attempted to transmit a store into an LSAQ or SRQ entry. Includes rejects. Not qualified by thread, so it includes counts for the whole core #118,u,g,n,n,n,PM_LSU_FIN,LSU Finished a PPC instruction (up to 4 per cycle) ##0000030066 LSU Finished a PPC instruction (up to 4 per cycle) #119,u,g,n,n,n,PM_L1_ICACHE_RELOADED_PREF,Counts all Icache prefetch reloads ( includes demand turned into prefetch) ##0000030068 Counts all Icache prefetch reloads ( includes demand turned into prefetch) #120,u,g,n,n,n,PM_IERAT_RELOAD_64K,IERAT Reloaded (Miss) for a 64k page ##000003006A IERAT Reloaded (Miss) for a 64k page #121,u,g,n,s,n,PM_NEST_REF_CLK,Multiply by 4 to obtain the number of PB cycles ##000003006E Multiply by 4 to obtain the number of PB cycles #122,u,g,n,n,m,PM_MRK_ST_CMPL,Marked store completed and sent to nest ##00000301E2 Marked store completed and sent to nest #123,u,g,n,n,m,PM_MRK_BR_MPRED_CMPL,Marked Branch Mispredicted ##00000301E4 Marked Branch Mispredicted #124,u,g,n,n,m,PM_MRK_DERAT_MISS,Erat Miss (TLB Access) All page sizes ##00000301E6 Erat Miss (TLB Access) All page sizes #125,u,g,t,n,n,PM_THRESH_EXC_64,Threshold counter exceeded a value of 64 ##00000301E8 Threshold counter exceeded a value of 64 #126,u,g,t,n,n,PM_THRESH_EXC_1024,Threshold counter exceeded a value of 1024 ##00000301EA Threshold counter exceeded a value of 1024 #127,u,g,n,n,n,PM_ST_MISS_L1,Store Missed L1 ##00000300F0 Store Missed L1 #128,u,g,n,n,n,PM_THRD_CONC_RUN_INST,PPC Instructions Finished by this thread when all threads in the core had the run-latch set ##00000300F4 PPC Instructions Finished by this thread when all threads in the core had the run-latch set #129,u,g,n,n,n,PM_L1_DCACHE_RELOAD_VALID,DL1 reloaded due to Demand Load ##00000300F6 DL1 reloaded due to Demand Load #130,u,g,n,s,n,PM_TB_BIT_TRANS,timebase event ##00000300F8 timebase event #131,u,g,n,n,n,PM_INST_FROM_L3MISS,Marked instruction was reloaded from a location beyond the local chiplet ##00000300FA Marked instruction was reloaded from a location beyond the local chiplet #132,u,g,n,n,n,PM_DTLB_MISS,Data PTEG reload ##00000300FC Data PTEG reload #133,u,g,n,n,n,PM_DATA_FROM_L3MISS,Demand LD - L3 Miss (not L2 hit and not L3 hit) ##00000300FE Demand LD - L3 Miss (not L2 hit and not L3 hit) #134,u,g,n,n,n,PM_EE_OFF_EXT_INT,CyclesMSR[EE] is off and external interrupts are active ##0000002080 CyclesMSR[EE] is off and external interrupts are active #135,u,g,n,n,n,PM_FLUSH_DISP,Dispatch flush ##0000002880 Dispatch flush #136,u,g,n,n,n,PM_FLUSH_HB_RESTORE_CYC,Cycles in which no new instructions can be dispatched to the ICT after a flush. History buffer recovery ##0000002084 Cycles in which no new instructions can be dispatched to the ICT after a flush. History buffer recovery #137,u,g,n,n,n,PM_ISYNC,Isync completion count per thread ##0000002884 Isync completion count per thread #138,u,g,n,n,n,PM_FLUSH_DISP_SB,Dispatch Flush: Scoreboard ##0000002088 Dispatch Flush: Scoreboard #139,u,g,n,n,n,PM_FLUSH_DISP_TLBIE,Dispatch Flush: TLBIE ##0000002888 Dispatch Flush: TLBIE #140,u,g,n,n,n,PM_CLB_HELD,CLB (control logic block - indicates quadword fetch block) Hold: Any Reason ##000000208C CLB (control logic block - indicates quadword fetch block) Hold: Any Reason #141,u,g,n,n,n,PM_DISP_CLB_HELD_BAL,Dispatch/CLB Hold: Balance Flush ##000000288C Dispatch/CLB Hold: Balance Flush #142,u,g,n,n,n,PM_DISP_CLB_HELD_SB,Dispatch/CLB Hold: Scoreboard ##0000002090 Dispatch/CLB Hold: Scoreboard #143,u,g,n,n,n,PM_DISP_CLB_HELD_TLBIE,Dispatch Hold: Due to TLBIE ##0000002890 Dispatch Hold: Due to TLBIE #144,u,g,n,n,n,PM_TM_OUTER_TBEGIN,Completion time outer tbegin ##0000002094 Completion time outer tbegin #145,u,g,n,n,n,PM_TM_OUTER_TEND,Completion time outer tend ##0000002894 Completion time outer tend #146,u,g,n,n,n,PM_TM_NESTED_TEND,Completion time nested tend ##0000002098 Completion time nested tend #147,u,g,n,n,n,PM_TM_TABORT_TRECLAIM,Completion time tabortnoncd, tabortcd, treclaim ##0000002898 Completion time tabortnoncd, tabortcd, treclaim #148,u,g,n,n,n,PM_TM_FAV_TBEGIN,Dispatch time Favored tbegin ##000000209C Dispatch time Favored tbegin #149,u,g,n,n,n,PM_TM_NON_FAV_TBEGIN,Dispatch time non favored tbegin ##000000289C Dispatch time non favored tbegin #150,u,g,n,n,n,PM_TM_NESTED_TBEGIN,Completion Tm nested tbegin ##00000020A0 Completion Tm nested tbegin #151,u,g,n,n,n,PM_TM_TSUSPEND,TM suspend instruction completed ##00000028A0 TM suspend instruction completed #152,u,g,n,n,n,PM_TM_TRESUME,TM resume instruction completed ##00000020A4 TM resume instruction completed #153,u,g,n,n,n,PM_MRK_TEND_FAIL,Nested or not nested tend failed for a marked tend instruction ##00000028A4 Nested or not nested tend failed for a marked tend instruction #154,u,g,n,n,n,PM_TM_FAIL_FOOTPRINT_OVERFLOW,TM aborted because the tracking limit for transactional storage accesses was exceeded.. Asynchronous ##00000020A8 TM aborted because the tracking limit for transactional storage accesses was exceeded.. Asynchronous #155,u,g,n,n,n,PM_TM_FAIL_CONF_NON_TM,TM aborted because a conflict occurred with a non-transactional access by another processor ##00000028A8 TM aborted because a conflict occurred with a non-transactional access by another processor #156,u,g,n,n,n,PM_TM_FAIL_CONF_TM,TM aborted because a conflict occurred with another transaction. ##00000020AC TM aborted because a conflict occurred with another transaction. #157,u,g,n,n,n,PM_TM_FAIL_SELF,TM aborted because a self-induced conflict occurred in Suspended state, due to one of the following: a store to a storage location that was previously accessed transactionally ##00000028AC TM aborted because a self-induced conflict occurred in Suspended state, due to one of the following: a store to a storage location that was previously accessed transactionally #158,u,g,n,n,n,PM_LSU_FLUSH_NEXT,LSU flush next reported at flush time. Sometimes these also come with an exception ##00000020B0 LSU flush next reported at flush time. Sometimes these also come with an exception #159,u,g,n,n,n,PM_DISP_HELD_TBEGIN,This outer tbegin transaction cannot be dispatched until the previous tend instruction completes ##00000028B0 This outer tbegin transaction cannot be dispatched until the previous tend instruction completes #160,u,g,n,n,n,PM_ISU0_ISS_HOLD_ALL,All ISU rejects ##0000003080 All ISU rejects #161,u,g,n,n,n,PM_ISU2_ISS_HOLD_ALL,All ISU rejects ##0000003880 All ISU rejects #162,u,g,n,n,n,PM_ISU1_ISS_HOLD_ALL,All ISU rejects ##0000003084 All ISU rejects #163,u,g,n,n,n,PM_ISU3_ISS_HOLD_ALL,All ISU rejects ##0000003884 All ISU rejects #164,u,g,n,n,n,PM_LS0_LD_VECTOR_FIN,LS0 finished load vector op ##000000C080 LS0 finished load vector op #165,u,g,n,n,n,PM_LS1_LD_VECTOR_FIN,LS1 finished load vector op ##000000C880 LS1 finished load vector op #166,u,g,n,n,n,PM_LS2_LD_VECTOR_FIN,LS2 finished load vector op ##000000C084 LS2 finished load vector op #167,u,g,n,n,n,PM_LS3_LD_VECTOR_FIN,LS3 finished load vector op ##000000C884 LS3 finished load vector op #168,u,g,n,n,n,PM_LSU_DTLB_MISS_4K,Data TLB Miss page size 4K ##000000C088 Data TLB Miss page size 4K #169,u,g,n,n,n,PM_LSU_DTLB_MISS_64K,Data TLB Miss page size 64K ##000000C888 Data TLB Miss page size 64K #170,u,g,n,n,n,PM_LSU_DTLB_MISS_16M_2M,Data TLB Miss page size 16M (HPT) or 2M (Radix) ##000000C08C Data TLB Miss page size 16M (HPT) or 2M (Radix) #171,u,g,n,n,n,PM_LSU_DTLB_MISS_16G_1G,Data TLB Miss page size 16G (HPT) or 1G (Radix) ##000000C88C Data TLB Miss page size 16G (HPT) or 1G (Radix) #172,u,g,n,n,n,PM_LSU_STCX,STCX sent to nest, i.e. total ##000000C090 STCX sent to nest, i.e. total #173,u,g,n,n,n,PM_LSU_NCST,Asserts when a i=1 store op is sent to the nest. No record of issue pipe (LS0/LS1) is maintained so this is for both pipes. Probably don't need separate LS0 and LS1 ##000000C890 Asserts when a i=1 store op is sent to the nest. No record of issue pipe (LS0/LS1) is maintained so this is for both pipes. Probably don't need separate LS0 and LS1 #174,u,g,n,n,n,PM_LS0_UNALIGNED_LD,Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty ##000000C094 Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty #175,u,g,n,n,n,PM_LS1_UNALIGNED_LD,Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty ##000000C894 Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty #176,u,g,n,n,n,PM_LS2_UNALIGNED_LD,Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty ##000000C098 Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty #177,u,g,n,n,n,PM_LS3_UNALIGNED_LD,Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty ##000000C898 Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty #178,u,g,n,n,n,PM_LS0_LAUNCH_HELD_PREF,Number of times a load or store instruction was unable to launch/relaunch because a high priority prefetch used that relaunch cycle ##000000C09C Number of times a load or store instruction was unable to launch/relaunch because a high priority prefetch used that relaunch cycle #179,u,g,n,n,n,PM_LS1_LAUNCH_HELD_PREF,Number of times a load or store instruction was unable to launch/relaunch because a high priority prefetch used that relaunch cycle ##000000C89C Number of times a load or store instruction was unable to launch/relaunch because a high priority prefetch used that relaunch cycle #180,u,g,n,n,n,PM_LSU0_FALSE_LHS,False LHS match detected ##000000C0A0 False LHS match detected #181,u,g,n,n,n,PM_LSU1_FALSE_LHS,False LHS match detected ##000000C8A0 False LHS match detected #182,u,g,n,n,n,PM_LSU2_FALSE_LHS,False LHS match detected ##000000C0A4 False LHS match detected #183,u,g,n,n,n,PM_LSU3_FALSE_LHS,False LHS match detected ##000000C8A4 False LHS match detected #184,u,g,n,n,n,PM_LSU_FLUSH_CI,Load was not issued to LSU as a cache inhibited (non-cacheable) load but it was later determined to be cache inhibited ##000000C0A8 Load was not issued to LSU as a cache inhibited (non-cacheable) load but it was later determined to be cache inhibited #185,u,g,n,n,n,PM_LSU_FLUSH_ATOMIC,Quad-word loads (lq) are considered atomic because they always span at least 2 slices. If a snoop or store from another thread changes the data the load is accessing between the 2 or 3 pieces of the lq instruction, the lq will be flushed ##000000C8A8 Quad-word loads (lq) are considered atomic because they always span at least 2 slices. If a snoop or store from another thread changes the data the load is accessing between the 2 or 3 pieces of the lq instruction, the lq will be flushed #186,u,g,n,n,n,PM_LSU_FLUSH_EMSH,An ERAT miss was detected after a set-p hit. Erat tracker indicates fail due to tlbmiss and the instruction gets flushed because the instruction was working on the wrong address ##000000C0AC An ERAT miss was detected after a set-p hit. Erat tracker indicates fail due to tlbmiss and the instruction gets flushed because the instruction was working on the wrong address #187,u,g,n,n,n,PM_LSU_FLUSH_RELAUNCH_MISS,If a load that has already returned data and has to relaunch for any reason then gets a miss (erat, setp, data cache), it will often be flushed at relaunch time because the data might be inconsistent ##000000C8AC If a load that has already returned data and has to relaunch for any reason then gets a miss (erat, setp, data cache), it will often be flushed at relaunch time because the data might be inconsistent #188,u,g,n,n,n,PM_LSU_FLUSH_UE,Correctable ECC error on reload data, reported at critical data forward time ##000000C0B0 Correctable ECC error on reload data, reported at critical data forward time #189,u,g,n,n,n,PM_LSU_FLUSH_LHS,Effective Address alias flush : no EA match but Real Address match. If the data has not yet been returned for this load, the instruction will just be rejected, but if it has returned data, it will be flushed ##000000C8B0 Effective Address alias flush : no EA match but Real Address match. If the data has not yet been returned for this load, the instruction will just be rejected, but if it has returned data, it will be flushed #190,u,g,n,n,n,PM_LSU_FLUSH_WRK_ARND,LSU workaround flush. These flushes are setup with programmable scan only latches to perform various actions when the flush macro receives a trigger from the dbg macros. These actions include things like flushing the next op encountered for a particular thread or flushing the next op that is NTC op that is encountered on a particular slice. The kind of flush that the workaround is setup to perform is highly variable. ##000000C0B4 LSU workaround flush. These flushes are setup with programmable scan only latches to perform various actions when the flush macro receives a trigger from the dbg macros. These actions include things like flushing the next op encountered for a particular thread or flushing the next op that is NTC op that is encountered on a particular slice. The kind of flush that the workaround is setup to perform is highly variable. #191,u,g,n,n,n,PM_LSU_FLUSH_LHL_SHL,The instruction was flushed because of a sequential load/store consistency. If a load or store hits on an older load that has either been snooped (for loads) or has stale data (for stores). ##000000C8B4 The instruction was flushed because of a sequential load/store consistency. If a load or store hits on an older load that has either been snooped (for loads) or has stale data (for stores). #192,u,g,n,n,n,PM_LSU_FLUSH_SAO,A load-hit-load condition with Strong Address Ordering will have address compare disabled and flush ##000000C0B8 A load-hit-load condition with Strong Address Ordering will have address compare disabled and flush #193,u,g,n,n,n,PM_LSU_FLUSH_LARX_STCX,A larx is flushed because an older larx has an LMQ reservation for the same thread. A stcx is flushed because an older stcx is in the LMQ. The flush happens when the older larx/stcx relaunches ##000000C8B8 A larx is flushed because an older larx has an LMQ reservation for the same thread. A stcx is flushed because an older stcx is in the LMQ. The flush happens when the older larx/stcx relaunches #194,u,g,n,n,n,PM_LSU_FLUSH_OTHER,Other LSU flushes including: Sync (sync ack from L2 caused search of LRQ for oldest snooped load, This will either signal a Precise Flush of the oldest snooped loa or a Flush Next PPC) ##000000C0BC Other LSU flushes including: Sync (sync ack from L2 caused search of LRQ for oldest snooped load, This will either signal a Precise Flush of the oldest snooped loa or a Flush Next PPC) #195,u,g,n,n,n,PM_STCX_SUCCESS_CMPL,Number of stcx instructions that completed successfully ##000000C8BC Number of stcx instructions that completed successfully #196,u,g,n,n,n,PM_LSU0_LDMX_FIN,New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): "The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region." This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56]). ##000000D088 New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): "The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region." This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56]). #197,u,g,n,n,n,PM_LSU1_LDMX_FIN,New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): "The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region." This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56]). ##000000D888 New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): "The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region." This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56]). #198,u,g,n,n,n,PM_LSU2_LDMX_FIN,New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): "The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region." This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56]). ##000000D08C New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): "The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region." This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56]). #199,u,g,n,n,n,PM_LSU3_LDMX_FIN,New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): "The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region." This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56]). ##000000D88C New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): "The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region." This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56]). #200,u,g,n,n,n,PM_LS0_DC_COLLISIONS,Read-write data cache collisions ##000000D090 Read-write data cache collisions #201,u,g,n,n,n,PM_LS1_DC_COLLISIONS,Read-write data cache collisions ##000000D890 Read-write data cache collisions #202,u,g,n,n,n,PM_LS2_DC_COLLISIONS,Read-write data cache collisions ##000000D094 Read-write data cache collisions #203,u,g,n,n,n,PM_LS3_DC_COLLISIONS,Read-write data cache collisions ##000000D894 Read-write data cache collisions #204,u,g,n,n,n,PM_LSU_FLUSH_ATOMIC,Quad-word loads (lq) are considered atomic because they always span at least 2 slices. If a snoop or store from another thread changes the data the load is accessing between the 2 or 3 pieces of the lq instruction, the lq will be flushed ##000000D198 Quad-word loads (lq) are considered atomic because they always span at least 2 slices. If a snoop or store from another thread changes the data the load is accessing between the 2 or 3 pieces of the lq instruction, the lq will be flushed #205,u,g,n,n,n,PM_LSU_FLUSH_EMSH,An ERAT miss was detected after a set-p hit. Erat tracker indicates fail due to tlbmiss and the instruction gets flushed because the instruction was working on the wrong address ##000000D998 An ERAT miss was detected after a set-p hit. Erat tracker indicates fail due to tlbmiss and the instruction gets flushed because the instruction was working on the wrong address #206,u,g,n,n,n,PM_LSU_FLUSH_RELAUNCH_MISS,If a load that has already returned data and has to relaunch for any reason then gets a miss (erat, setp, data cache), it will often be flushed at relaunch time because the data might be inconsistent ##000000D19C If a load that has already returned data and has to relaunch for any reason then gets a miss (erat, setp, data cache), it will often be flushed at relaunch time because the data might be inconsistent #207,u,g,n,n,n,PM_LSU_FLUSH_UE,Correctable ECC error on reload data, reported at critical data forward time ##000000D99C Correctable ECC error on reload data, reported at critical data forward time #208,u,g,n,n,n,PM_LSU_FLUSH_LHS,Effective Address alias flush : no EA match but Real Address match. If the data has not yet been returned for this load, the instruction will just be rejected, but if it has returned data, it will be flushed ##000000D1A0 Effective Address alias flush : no EA match but Real Address match. If the data has not yet been returned for this load, the instruction will just be rejected, but if it has returned data, it will be flushed #209,u,g,n,n,n,PM_LSU_FLUSH_LHL_SHL,The instruction was flushed because of a sequential load/store consistency. If a load or store hits on an older load that has either been snooped (for loads) or has stale data (for stores). ##000000D9A0 The instruction was flushed because of a sequential load/store consistency. If a load or store hits on an older load that has either been snooped (for loads) or has stale data (for stores). #210,u,g,n,n,n,PM_LSU_FLUSH_SAO,A load-hit-load condition with Strong Address Ordering will have address compare disabled and flush ##000000D1A4 A load-hit-load condition with Strong Address Ordering will have address compare disabled and flush #211,u,g,n,n,n,PM_LSU_FLUSH_LARX_STCX,A larx is flushed because an older larx has an LMQ reservation for the same thread. A stcx is flushed because an older stcx is in the LMQ. The flush happens when the older larx/stcx relaunches ##000000D9A4 A larx is flushed because an older larx has an LMQ reservation for the same thread. A stcx is flushed because an older stcx is in the LMQ. The flush happens when the older larx/stcx relaunches #212,u,g,n,n,n,PM_DSLB_MISS,Data SLB Miss - Total of all segment sizes ##000000D0A8 Data SLB Miss - Total of all segment sizes #213,u,g,n,n,n,PM_ISLB_MISS,Instruction SLB Miss - Total of all segment sizes ##000000D8A8 Instruction SLB Miss - Total of all segment sizes #214,u,g,n,n,n,PM_SRQ_SYNC_CYC,A sync is in the S2Q (edge detect to count) ##000000D0AC A sync is in the S2Q (edge detect to count) #215,u,g,n,n,n,PM_LWSYNC, ##000000D8AC #216,u,g,n,n,n,PM_HWSYNC, ##000000D0B0 #217,u,g,n,n,n,PM_PTESYNC, ##000000D8B0 #218,u,g,n,n,n,PM_LSU0_SRQ_S0_VALID_CYC,Slot 0 of SRQ valid ##000000D0B4 Slot 0 of SRQ valid #219,u,g,n,n,n,PM_LSU0_LRQ_S0_VALID_CYC,Slot 0 of LRQ valid ##000000D8B4 Slot 0 of LRQ valid #220,u,g,n,s,n,PM_LSU_LMQ_FULL_CYC,Counts the number of cycles the LMQ is full ##000000D0B8 Counts the number of cycles the LMQ is full #221,u,g,n,n,n,PM_LSU0_LMQ_S0_VALID,Slot 0 of LMQ valid ##000000D8B8 Slot 0 of LMQ valid #222,u,g,n,s,n,PM_LSU0_1_LRQF_FULL_CYC,Counts the number of cycles the LRQF is full. LRQF is the queue that holds loads between finish and completion. If it fills up, instructions stay in LRQ until completion, potentially backing up the LRQ ##000000D0BC Counts the number of cycles the LRQF is full. LRQF is the queue that holds loads between finish and completion. If it fills up, instructions stay in LRQ until completion, potentially backing up the LRQ #223,u,g,n,s,n,PM_LSU2_3_LRQF_FULL_CYC,Counts the number of cycles the LRQF is full. LRQF is the queue that holds loads between finish and completion. If it fills up, instructions stay in LRQ until completion, potentially backing up the LRQ ##000000D8BC Counts the number of cycles the LRQF is full. LRQF is the queue that holds loads between finish and completion. If it fills up, instructions stay in LRQ until completion, potentially backing up the LRQ #224,u,g,n,s,n,PM_S2Q_FULL,Cycles during which the S2Q is full ##000000E080 Cycles during which the S2Q is full #225,u,g,n,n,n,PM_L1_SW_PREF,Software L1 Prefetches, including SW Transient Prefetches ##000000E880 Software L1 Prefetches, including SW Transient Prefetches #226,u,g,n,n,n,PM_LS0_ERAT_MISS_PREF,LS0 Erat miss due to prefetch ##000000E084 LS0 Erat miss due to prefetch #227,u,g,n,n,n,PM_LS1_ERAT_MISS_PREF,LS1 Erat miss due to prefetch ##000000E884 LS1 Erat miss due to prefetch #228,u,g,n,n,n,PM_LS2_ERAT_MISS_PREF,LS0 Erat miss due to prefetch ##000000E088 LS0 Erat miss due to prefetch #229,u,g,n,n,n,PM_LS3_ERAT_MISS_PREF,LS1 Erat miss due to prefetch ##000000E888 LS1 Erat miss due to prefetch #230,u,g,n,n,n,PM_LSU0_ERAT_HIT,Primary ERAT hit. There is no secondary ERAT ##000000E08C Primary ERAT hit. There is no secondary ERAT #231,u,g,n,n,n,PM_LSU1_ERAT_HIT,Primary ERAT hit. There is no secondary ERAT ##000000E88C Primary ERAT hit. There is no secondary ERAT #232,u,g,n,n,n,PM_LSU2_ERAT_HIT,Primary ERAT hit. There is no secondary ERAT ##000000E090 Primary ERAT hit. There is no secondary ERAT #233,u,g,n,n,n,PM_LSU3_ERAT_HIT,Primary ERAT hit. There is no secondary ERAT ##000000E890 Primary ERAT hit. There is no secondary ERAT #234,u,g,n,n,n,PM_LSU0_TM_L1_HIT,Load tm hit in L1 ##000000E094 Load tm hit in L1 #235,u,g,n,n,n,PM_LSU1_TM_L1_HIT,Load tm hit in L1 ##000000E894 Load tm hit in L1 #236,u,g,n,n,n,PM_LSU2_TM_L1_HIT,Load tm hit in L1 ##000000E098 Load tm hit in L1 #237,u,g,n,n,n,PM_LSU3_TM_L1_HIT,Load tm hit in L1 ##000000E898 Load tm hit in L1 #238,u,g,n,n,n,PM_LSU0_TM_L1_MISS,Load tm L1 miss ##000000E09C Load tm L1 miss #239,u,g,n,n,n,PM_LSU1_TM_L1_MISS,Load tm L1 miss ##000000E89C Load tm L1 miss #240,u,g,n,n,n,PM_LSU2_TM_L1_MISS,Load tm L1 miss ##000000E0A0 Load tm L1 miss #241,u,g,n,n,n,PM_LSU3_TM_L1_MISS,Load tm L1 miss ##000000E8A0 Load tm L1 miss #242,u,g,n,n,n,PM_TMA_REQ_L2, addrs only req to L2 only on the first one,Indication that Load footprint is not expanding ##000000E0A4 addrs only req to L2 only on the first one,Indication that Load footprint is not expanding #243,u,g,n,n,n,PM_TM_FAIL_TLBIE,Transaction failed because there was a TLBIE hit in the bloom filter ##000000E0AC Transaction failed because there was a TLBIE hit in the bloom filter #244,u,g,n,n,n,PM_TM_FAIL_TX_CONFLICT,Transactional conflict from LSU, gets reported to TEXASR ##000000E8AC Transactional conflict from LSU, gets reported to TEXASR #245,u,g,n,n,n,PM_TM_FAIL_NON_TX_CONFLICT,Non transactional conflict from LSU, gets reported to TEXASR ##000000E0B0 Non transactional conflict from LSU, gets reported to TEXASR #246,u,g,n,n,n,PM_TEND_PEND_CYC,TEND latency per thread ##000000E8B0 TEND latency per thread #247,u,g,n,n,n,PM_LS0_TM_DISALLOW,A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it ##000000E0B4 A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it #248,u,g,n,n,n,PM_LS1_TM_DISALLOW,A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it ##000000E8B4 A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it #249,u,g,n,n,n,PM_LS2_TM_DISALLOW,A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it ##000000E0B8 A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it #250,u,g,n,n,n,PM_LS3_TM_DISALLOW,A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it ##000000E8B8 A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it #251,u,g,n,n,n,PM_LS0_PTE_TABLEWALK_CYC,Cycles when a tablewalk is pending on this thread on table 0 ##000000E0BC Cycles when a tablewalk is pending on this thread on table 0 #252,u,g,n,n,n,PM_LS1_PTE_TABLEWALK_CYC,Cycles when a tablewalk is pending on this thread on table 1 ##000000E8BC Cycles when a tablewalk is pending on this thread on table 1 #253,u,g,n,n,n,PM_LSU_STCX_FAIL, ##000000F080 #254,u,g,n,s,n,PM_SNOOP_TLBIE,TLBIE snoop ##000000F880 TLBIE snoop #255,u,g,n,n,n,PM_PTE_PREFETCH,PTE prefetches ##000000F084 PTE prefetches #256,u,g,n,n,n,PM_TABLEWALK_CYC_PREF,tablewalk qualified for pte prefetches ##000000F884 tablewalk qualified for pte prefetches #257,u,g,n,n,n,PM_LSU0_STORE_REJECT,All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met ##000000F088 All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met #258,u,g,n,n,n,PM_LSU1_STORE_REJECT,All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met ##000000F888 All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met #259,u,g,n,n,n,PM_LSU2_STORE_REJECT,All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met ##000000F08C All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met #260,u,g,n,n,n,PM_LSU3_STORE_REJECT,All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met ##000000F88C All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met #261,u,g,n,n,n,PM_LSU0_L1_CAM_CANCEL,ls0 l1 tm cam cancel ##000000F090 ls0 l1 tm cam cancel #262,u,g,n,n,n,PM_LSU1_L1_CAM_CANCEL,ls1 l1 tm cam cancel ##000000F890 ls1 l1 tm cam cancel #263,u,g,n,n,n,PM_LSU2_L1_CAM_CANCEL,ls2 l1 tm cam cancel ##000000F094 ls2 l1 tm cam cancel #264,u,g,n,n,n,PM_LSU3_L1_CAM_CANCEL,ls3 l1 tm cam cancel ##000000F894 ls3 l1 tm cam cancel #265,u,g,n,n,n,PM_XLATE_HPT_MODE,LSU reports every cycle the thread is in HPT translation mode (as opposed to radix mode) ##000000F098 LSU reports every cycle the thread is in HPT translation mode (as opposed to radix mode) #266,u,g,n,n,n,PM_XLATE_RADIX_MODE,LSU reports every cycle the thread is in radix translation mode (as opposed to HPT mode) ##000000F898 LSU reports every cycle the thread is in radix translation mode (as opposed to HPT mode) #267,u,g,n,n,n,PM_XLATE_MISS,The LSU requested a line from L2 for translation. It may be satisfied from any source beyond L2. Includes speculative instructions. Includes instruction, prefetch and demand ##000000F89C The LSU requested a line from L2 for translation. It may be satisfied from any source beyond L2. Includes speculative instructions. Includes instruction, prefetch and demand #268,u,g,n,n,n,PM_DATA_STORE,All ops that drain from s2q to L2 containing data ##000000F0A0 All ops that drain from s2q to L2 containing data #269,u,g,n,n,n,PM_NON_DATA_STORE,All ops that drain from s2q to L2 and contain no data ##000000F8A0 All ops that drain from s2q to L2 and contain no data #270,u,g,n,n,n,PM_DC_PREF_HW_ALLOC,Prefetch stream allocated by the hardware prefetch mechanism ##000000F0A4 Prefetch stream allocated by the hardware prefetch mechanism #271,u,g,n,n,n,PM_DC_PREF_SW_ALLOC,Prefetch stream allocated by software prefetching ##000000F8A4 Prefetch stream allocated by software prefetching #272,u,g,n,n,n,PM_DC_PREF_CONF,A demand load referenced a line in an active prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. Includes forwards and backwards streams ##000000F0A8 A demand load referenced a line in an active prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. Includes forwards and backwards streams #273,u,g,n,n,n,PM_DC_PREF_FUZZY_CONF,A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up) ##000000F8A8 A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up) #274,u,g,n,n,n,PM_DC_PREF_STRIDED_CONF,A demand load referenced a line in an active strided prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. ##000000F0AC A demand load referenced a line in an active strided prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. #275,u,g,n,n,n,PM_DC_DEALLOC_NO_CONF,A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up) ##000000F8AC A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up) #276,u,g,n,n,n,PM_L3_LD_PREF,L3 load prefetch, sourced from a hardware or software stream, was sent to the nest ##000000F0B0 L3 load prefetch, sourced from a hardware or software stream, was sent to the nest #277,u,g,n,n,n,PM_L3_SW_PREF,L3 load prefetch, sourced from a software prefetch stream, was sent to the nest ##000000F8B0 L3 load prefetch, sourced from a software prefetch stream, was sent to the nest #278,u,g,n,n,n,PM_DC_PREF_CONS_ALLOC,Prefetch stream allocated in the conservative phase by either the hardware prefetch mechanism or software prefetch. The sum of this pair subtracted from the total number of allocs will give the total allocs in normal phase ##000000F0B4 Prefetch stream allocated in the conservative phase by either the hardware prefetch mechanism or software prefetch. The sum of this pair subtracted from the total number of allocs will give the total allocs in normal phase #279,u,g,n,n,n,PM_DC_PREF_XCONS_ALLOC,Prefetch stream allocated in the Ultra conservative phase by either the hardware prefetch mechanism or software prefetch ##000000F8B4 Prefetch stream allocated in the Ultra conservative phase by either the hardware prefetch mechanism or software prefetch #280,u,g,n,n,n,PM_LS0_UNALIGNED_ST,Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty ##000000F0B8 Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty #281,u,g,n,n,n,PM_LS1_UNALIGNED_ST,Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty ##000000F8B8 Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty #282,u,g,n,n,n,PM_LS2_UNALIGNED_ST,Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty ##000000F0BC Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty #283,u,g,n,n,n,PM_LS3_UNALIGNED_ST,Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty ##000000F8BC Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty #284,u,g,n,n,n,PM_INST_FROM_L1,Instruction fetches from L1. L1 instruction hit ##0000004080 Instruction fetches from L1. L1 instruction hit #285,u,g,n,n,n,PM_BANK_CONFLICT,Read blocked due to interleave conflict. The ifar logic will detect an interleave conflict and kill the data that was read that cycle. ##0000004880 Read blocked due to interleave conflict. The ifar logic will detect an interleave conflict and kill the data that was read that cycle. #286,u,g,n,n,n,PM_EAT_FULL_CYC,Cycles No room in EAT ##0000004084 Cycles No room in EAT #287,u,g,n,n,n,PM_IBUF_FULL_CYC,Cycles No room in ibuff ##0000004884 Cycles No room in ibuff #288,u,g,n,n,n,PM_IC_DEMAND_REQ,Demand Instruction fetch request ##0000004088 Demand Instruction fetch request #289,u,g,n,n,n,PM_IC_PREF_REQ,Instruction prefetch requests ##0000004888 Instruction prefetch requests #290,u,g,n,n,n,PM_L1_DEMAND_WRITE,Instruction Demand sectors written into IL1 ##000000408C Instruction Demand sectors written into IL1 #291,u,g,n,n,n,PM_IC_PREF_WRITE,Instruction prefetch written into IL1 ##000000488C Instruction prefetch written into IL1 #292,u,g,n,n,n,PM_IC_PREF_CANCEL_PAGE,Prefetch Canceled due to page boundary ##0000004090 Prefetch Canceled due to page boundary #293,u,g,n,n,n,PM_IC_PREF_CANCEL_HIT,Prefetch Canceled due to icache hit ##0000004890 Prefetch Canceled due to icache hit #294,u,g,n,n,n,PM_IC_PREF_CANCEL_L2,L2 Squashed a demand or prefetch request ##0000004094 L2 Squashed a demand or prefetch request #295,u,g,n,n,n,PM_IC_RELOAD_PRIVATE,Reloading line was brought in private for a specific thread. Most lines are brought in shared for all eight threads. If RA does not match then invalidates and then brings it shared to other thread. In P7 line brought in private , then line was invalidat ##0000004894 Reloading line was brought in private for a specific thread. Most lines are brought in shared for all eight threads. If RA does not match then invalidates and then brings it shared to other thread. In P7 line brought in private , then line was invalidat #296,u,g,n,n,n,PM_IC_DEMAND_L2_BHT_REDIRECT, L2 I cache demand request due to BHT redirect, branch redirect ( 2 bubbles 3 cycles) ##0000004098 L2 I cache demand request due to BHT redirect, branch redirect ( 2 bubbles 3 cycles) #297,u,g,n,n,n,PM_IC_DEMAND_L2_BR_REDIRECT, L2 I cache demand request due to branch Mispredict ( 15 cycle path) ##0000004898 L2 I cache demand request due to branch Mispredict ( 15 cycle path) #298,u,g,n,n,n,PM_BR_PRED,Conditional Branch Executed in which the HW predicted the Direction or Target. Includes taken and not taken and is counted at execution time ##000000409C Conditional Branch Executed in which the HW predicted the Direction or Target. Includes taken and not taken and is counted at execution time #299,u,g,n,n,n,PM_BR_CORECT_PRED_TAKEN_CMPL,Conditional Branch Completed in which the HW correctly predicted the direction as taken. Counted at completion time ##000000489C Conditional Branch Completed in which the HW correctly predicted the direction as taken. Counted at completion time #300,u,g,n,n,n,PM_BR_UNCOND,Unconditional Branch Completed. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was covenrted to a Resolve. ##00000040A0 Unconditional Branch Completed. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was covenrted to a Resolve. #301,u,g,n,n,n,PM_BR_PRED_PCACHE,Conditional branch completed that used pattern cache prediction ##00000048A0 Conditional branch completed that used pattern cache prediction #302,u,g,n,n,n,PM_BR_PRED_CCACHE,Conditional Branch Completed that used the Count Cache for Target Prediction ##00000040A4 Conditional Branch Completed that used the Count Cache for Target Prediction #303,u,g,n,n,n,PM_STOP_FETCH_PENDING_CYC,Fetching is stopped due to an incoming instruction that will result in a flush ##00000048A4 Fetching is stopped due to an incoming instruction that will result in a flush #304,u,g,n,n,n,PM_BR_PRED_LSTACK,Conditional Branch Completed that used the Link Stack for Target Prediction ##00000040A8 Conditional Branch Completed that used the Link Stack for Target Prediction #305,u,g,n,n,n,PM_DECODE_FUSION_LD_ST_DISP,32-bit displacement D-form and 16-bit displacement X-form ##00000048A8 32-bit displacement D-form and 16-bit displacement X-form #306,u,g,n,n,n,PM_BR_MPRED_CCACHE,Conditional Branch Completed that was Mispredicted due to the Count Cache Target Prediction ##00000040AC Conditional Branch Completed that was Mispredicted due to the Count Cache Target Prediction #307,u,g,n,n,n,PM_BR_MPRED_LSTACK,Conditional Branch Completed that was Mispredicted due to the Link Stack Target Prediction ##00000048AC Conditional Branch Completed that was Mispredicted due to the Link Stack Target Prediction #308,u,g,n,n,n,PM_BR_PRED_TAKEN_CR,Conditional Branch that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and branches ##00000040B0 Conditional Branch that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and branches #309,u,g,n,n,n,PM_BR_MPRED_PCACHE,Conditional Branch Completed that was Mispredicted due to pattern cache prediction ##00000048B0 Conditional Branch Completed that was Mispredicted due to pattern cache prediction #310,u,g,n,n,n,PM_BR_PRED_TA,Conditional Branch Completed that had its target address predicted. Only XL-form branches set this event. This equal the sum of CCACHE, LSTACK, and PCACHE ##00000040B4 Conditional Branch Completed that had its target address predicted. Only XL-form branches set this event. This equal the sum of CCACHE, LSTACK, and PCACHE #311,u,g,n,n,n,PM_DECODE_FUSION_CONST_GEN,32-bit constant generation ##00000048B4 32-bit constant generation #312,u,g,n,n,n,PM_BR_MPRED_TAKEN_CR,A Conditional Branch that resolved to taken was mispredicted as not taken (due to the BHT Direction Prediction). ##00000040B8 A Conditional Branch that resolved to taken was mispredicted as not taken (due to the BHT Direction Prediction). #313,u,g,n,n,n,PM_BR_MPRED_TAKEN_TA,Conditional Branch Completed that was Mispredicted due to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that resolved Taken set this event. ##00000048B8 Conditional Branch Completed that was Mispredicted due to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that resolved Taken set this event. #314,u,g,n,n,n,PM_THRD_PRIO_0_1_CYC, Cycles thread running at priority level 0 or 1 ##00000040BC Cycles thread running at priority level 0 or 1 #315,u,g,n,n,n,PM_THRD_PRIO_2_3_CYC, Cycles thread running at priority level 2 or 3 ##00000048BC Cycles thread running at priority level 2 or 3 #316,u,g,n,n,n,PM_THRD_PRIO_4_5_CYC, Cycles thread running at priority level 4 or 5 ##0000005080 Cycles thread running at priority level 4 or 5 #317,u,g,n,n,n,PM_THRD_PRIO_6_7_CYC, Cycles thread running at priority level 6 or 7 ##0000005880 Cycles thread running at priority level 6 or 7 #318,u,g,n,n,n,PM_IC_INVALIDATE,Ic line invalidated ##0000005888 Ic line invalidated #319,u,g,n,n,n,PM_SHL_CREATED,Store-Hit-Load Table Entry Created ##000000508C Store-Hit-Load Table Entry Created #320,u,g,n,n,n,PM_SHL_ST_DEP_CREATED,Store-Hit-Load Table Read Hit with entry Enabled ##000000588C Store-Hit-Load Table Read Hit with entry Enabled #321,u,g,n,n,n,PM_IC_MISS_ICBI,threaded version, IC Misses where we got EA dir hit but no sector valids were on. ICBI took line out ##0000005094 threaded version, IC Misses where we got EA dir hit but no sector valids were on. ICBI took line out #322,u,g,n,n,n,PM_LINK_STACK_WRONG_ADD_PRED,Link stack predicts wrong address, because of link stack design limitation or software violating the coding conventions ##0000005098 Link stack predicts wrong address, because of link stack design limitation or software violating the coding conventions #323,u,g,n,n,n,PM_LINK_STACK_INVALID_PTR,It is most often caused by certain types of flush where the pointer is not available. Can result in the data in the link stack becoming unusable. ##0000005898 It is most often caused by certain types of flush where the pointer is not available. Can result in the data in the link stack becoming unusable. #324,u,g,n,n,n,PM_LINK_STACK_CORRECT,Link stack predicts right address ##00000058A0 Link stack predicts right address #325,u,g,n,n,n,PM_FLUSH_MPRED,Branch mispredict flushes. Includes target and address misprecition ##00000050A4 Branch mispredict flushes. Includes target and address misprecition #326,u,g,n,n,n,PM_FLUSH_LSU,LSU flushes. Includes all lsu flushes ##00000058A4 LSU flushes. Includes all lsu flushes #327,u,g,n,n,n,PM_EAT_FORCE_MISPRED,XL-form branch was mispredicted due to the predicted target address missing from EAT. The EAT forces a mispredict in this case since there is no predicated target to validate. This is a rare case that may occur when the EAT is full and a branch is issued ##00000050A8 XL-form branch was mispredicted due to the predicted target address missing from EAT. The EAT forces a mispredict in this case since there is no predicated target to validate. This is a rare case that may occur when the EAT is full and a branch is issued #328,u,g,n,n,n,PM_DECODE_HOLD_ICT_FULL,Counts the number of cycles in which the IFU was not able to decode and transmit one or more instructions because all itags were in use. This means the ICT is full for this thread ##00000058A8 Counts the number of cycles in which the IFU was not able to decode and transmit one or more instructions because all itags were in use. This means the ICT is full for this thread #329,u,g,n,n,n,PM_BTAC_BAD_RESULT,BTAC thinks branch will be taken but it is either predicted not-taken by the BHT, or the target address is wrong (less common). In both cases, a redirect will happen ##00000050B0 BTAC thinks branch will be taken but it is either predicted not-taken by the BHT, or the target address is wrong (less common). In both cases, a redirect will happen #330,u,g,n,n,n,PM_BTAC_GOOD_RESULT,BTAC predicts a taken branch and the BHT agrees, and the target address is correct ##00000058B0 BTAC predicts a taken branch and the BHT agrees, and the target address is correct #331,u,g,n,n,n,PM_TAGE_CORRECT_TAKEN_CMPL,The TAGE overrode BHT direction prediction and it was correct. Counted at completion for taken branches only ##00000050B4 The TAGE overrode BHT direction prediction and it was correct. Counted at completion for taken branches only #332,u,g,n,n,n,PM_TAGE_CORRECT,The TAGE overrode BHT direction prediction and it was correct. Includes taken and not taken and is counted at execution time ##00000058B4 The TAGE overrode BHT direction prediction and it was correct. Includes taken and not taken and is counted at execution time #333,u,g,n,n,n,PM_TAGE_OVERRIDE_WRONG,The TAGE overrode BHT direction prediction but it was incorrect. Counted at completion for taken branches only ##00000050B8 The TAGE overrode BHT direction prediction but it was incorrect. Counted at completion for taken branches only #334,u,g,n,n,n,PM_TAGE_OVERRIDE_WRONG_SPEC,The TAGE overrode BHT direction prediction and it was correct. Includes taken and not taken and is counted at execution time ##00000058B8 The TAGE overrode BHT direction prediction and it was correct. Includes taken and not taken and is counted at execution time #335,u,g,n,s,n,PM_L3_PF_ON_CHIP_CACHE,L3 PF from On chip cache ##00000360A0 L3 PF from On chip cache #336,u,g,n,s,n,PM_L3_PF_OFF_CHIP_CACHE,L3 PF from Off chip cache ##00000368A0 L3 PF from Off chip cache #337,u,g,n,s,n,PM_L3_L2_CO_HIT,L2 CO hits ##00000360A2 L2 CO hits #338,u,g,n,s,n,PM_L3_L2_CO_MISS,L2 CO miss ##00000368A2 L2 CO miss #339,u,g,n,n,n,PM_L3_CO_LCO,Total L3 COs occurred on LCO L3.1 (good cresp, may end up in mem on a retry) ##00000360A4 Total L3 COs occurred on LCO L3.1 (good cresp, may end up in mem on a retry) #340,u,g,n,n,n,PM_L3_CINJ,L3 castin of cache inject ##00000368A4 L3 castin of cache inject #341,u,g,n,n,n,PM_SNP_TM_HIT_M,TM snoop that is a store hits line in L3 in M or Mu state (exclusive modified) ##00000360A6 TM snoop that is a store hits line in L3 in M or Mu state (exclusive modified) #342,u,g,n,n,n,PM_SNP_TM_HIT_T,TM snoop that is a store hits line in L3 in T, Tn or Te state (shared modified) ##00000368A6 TM snoop that is a store hits line in L3 in T, Tn or Te state (shared modified) #343,u,g,n,n,n,PM_L3_CO,L3 castout occurring (does not include casthrough or log writes (cinj/dmaw)) ##00000360A8 L3 castout occurring (does not include casthrough or log writes (cinj/dmaw)) #344,u,g,n,n,n,PM_SN_INVL,Any port snooper detects a store to a line in the Sx state and invalidates the line. Up to 4 can happen in a cycle but we only count 1 ##00000368A8 Any port snooper detects a store to a line in the Sx state and invalidates the line. Up to 4 can happen in a cycle but we only count 1 #345,u,g,n,s,n,PM_L3_P0_CO_MEM,L3 CO to memory port 0 with or without data ##00000360AA L3 CO to memory port 0 with or without data #346,u,g,n,s,n,PM_L3_P1_CO_MEM,L3 CO to memory port 1 with or without data ##00000368AA L3 CO to memory port 1 with or without data #347,u,g,n,s,n,PM_L3_SN0_BUSY,Lifetime, sample of snooper machine 0 valid ##00000360AC Lifetime, sample of snooper machine 0 valid #348,u,g,n,s,n,PM_L3_CO0_BUSY,Lifetime, sample of CO machine 0 valid ##00000368AC Lifetime, sample of CO machine 0 valid #349,u,g,n,s,n,PM_L3_P0_CO_RTY,L3 CO received retry port 0 (memory only), every retry counted ##00000360AE L3 CO received retry port 0 (memory only), every retry counted #350,u,g,n,s,n,PM_L3_P1_CO_RTY,L3 CO received retry port 1 (memory only), every retry counted ##00000368AE L3 CO received retry port 1 (memory only), every retry counted #351,u,g,n,s,n,PM_L3_P0_SYS_PUMP,L3 PF sent with sys scope port 0, counts even retried requests ##00000360B0 L3 PF sent with sys scope port 0, counts even retried requests #352,u,g,n,s,n,PM_L3_P1_SYS_PUMP,L3 PF sent with sys scope port 1, counts even retried requests ##00000368B0 L3 PF sent with sys scope port 1, counts even retried requests #353,u,g,n,s,n,PM_L3_GRP_GUESS_WRONG_LOW,Prefetch scope predictor selected GS or NNS, but was wrong because scope was LNS ##00000360B2 Prefetch scope predictor selected GS or NNS, but was wrong because scope was LNS #354,u,g,n,s,n,PM_L3_GRP_GUESS_WRONG_HIGH,Prefetch scope predictor selected GS or NNS, but was wrong because scope was VGS or RNS ##00000368B2 Prefetch scope predictor selected GS or NNS, but was wrong because scope was VGS or RNS #355,u,g,n,s,n,PM_L3_PF0_BUSY,Lifetime, sample of PF machine 0 valid ##00000360B4 Lifetime, sample of PF machine 0 valid #356,u,g,n,s,n,PM_L3_RD0_BUSY,Lifetime, sample of RD machine 0 valid ##00000368B4 Lifetime, sample of RD machine 0 valid #357,u,g,n,n,n,PM_L2_INST, All successful I-side-instruction-fetch (e.g. i-demand, i-prefetch) dispatches for this thread ##0000036080 All successful I-side-instruction-fetch (e.g. i-demand, i-prefetch) dispatches for this thread #358,u,g,n,n,n,PM_L2_INST_MISS, All successful I-side-instruction-fetch (e.g. i-demand, i-prefetch) dispatches for this thread that were an L2 miss ##0000036880 All successful I-side-instruction-fetch (e.g. i-demand, i-prefetch) dispatches for this thread that were an L2 miss #359,u,g,n,n,n,PM_L2_LD_DISP, All successful D-side-Ld or I-side-instruction-fetch dispatches for this thread ##0000036082 All successful D-side-Ld or I-side-instruction-fetch dispatches for this thread #360,u,g,n,n,n,PM_L2_LD_HIT, All successful D-side-Ld or I-side-instruction-fetch dispatches for this thread that were L2 hits ##0000036882 All successful D-side-Ld or I-side-instruction-fetch dispatches for this thread that were L2 hits #361,u,g,n,n,n,PM_L2_RCST_DISP,All D-side store dispatch attempts for this thread ##0000036084 All D-side store dispatch attempts for this thread #362,u,g,n,n,n,PM_L2_RCST_DISP_FAIL_ADDR,All D-side store dispatch attempts for this thread that failed due to address collision with RC/CO/SN/SQ ##0000036884 All D-side store dispatch attempts for this thread that failed due to address collision with RC/CO/SN/SQ #363,u,g,n,s,n,PM_L2_RC_ST_DONE,Read-claim machine did store to line that was in Tx or Sx (Tagged or Shared state) ##0000036086 Read-claim machine did store to line that was in Tx or Sx (Tagged or Shared state) #364,u,g,n,s,n,PM_L2_SN_SX_I_DONE,Snoop dispatched and went from Sx to Ix ##0000036886 Snoop dispatched and went from Sx to Ix #365,u,g,n,s,n,PM_L2_SYS_GUESS_CORRECT,L2 guess system (VGS or RNS) and guess was correct (ie data beyond-group) ##0000036088 L2 guess system (VGS or RNS) and guess was correct (ie data beyond-group) #366,u,g,n,s,n,PM_L2_SYS_GUESS_WRONG,L2 guess system (VGS or RNS) and guess was not correct (ie data ^beyond-group) ##0000036888 L2 guess system (VGS or RNS) and guess was not correct (ie data ^beyond-group) #367,u,g,n,s,n,PM_L2_RTY_ST,RC retries on PB for any store from core (excludes DCBFs) ##000003608A RC retries on PB for any store from core (excludes DCBFs) #368,u,g,n,s,n,PM_L2_RTY_LD,RC retries on PB for any load from core (excludes DCBFs) ##000003688A RC retries on PB for any load from core (excludes DCBFs) #369,u,g,n,s,n,PM_CO0_BUSY,CO mach 0 Busy. Used by PMU to sample ave CO lifetime (mach0 used as sample point) ##000003608C CO mach 0 Busy. Used by PMU to sample ave CO lifetime (mach0 used as sample point) #370,u,g,n,s,n,PM_SN_USAGE,Continuous 16 cycle (2to1) window where this signals rotates thru sampling each SN machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running ##000003688C Continuous 16 cycle (2to1) window where this signals rotates thru sampling each SN machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running #371,u,g,n,s,n,PM_TM_ST_CONF,TM Store (fav or non-fav) ran into conflict (failed) ##000003608E TM Store (fav or non-fav) ran into conflict (failed) #372,u,g,n,s,n,PM_TM_ST_CAUSED_FAIL,TM Store (fav or non-fav) caused another thread to fail ##000003688E TM Store (fav or non-fav) caused another thread to fail #373,u,g,n,s,n,PM_DSIDE_L2MEMACC,Valid when first beat of data comes in for an D-side fetch where data came EXCLUSIVELY from memory (excluding hpcread64 accesses), i.e., total memory accesses by RCs ##0000036092 Valid when first beat of data comes in for an D-side fetch where data came EXCLUSIVELY from memory (excluding hpcread64 accesses), i.e., total memory accesses by RCs #374,u,g,n,s,n,PM_DSIDE_OTHER_64B_L2MEMACC,Valid when first beat of data comes in for an D-side fetch where data came EXCLUSIVELY from memory that was for hpc_read64, (RC had to fetch other 64B of a line from MC) i.e., number of times RC had to go to memory to get 'missing' 64B ##0000036892 Valid when first beat of data comes in for an D-side fetch where data came EXCLUSIVELY from memory that was for hpc_read64, (RC had to fetch other 64B of a line from MC) i.e., number of times RC had to go to memory to get 'missing' 64B #375,u,g,n,n,n,PM_L2_INST, All successful I-side-instruction-fetch (e.g. i-dem, i-pref) dispatches for this thread ##000003609E All successful I-side-instruction-fetch (e.g. i-dem, i-pref) dispatches for this thread #376,u,g,n,s,n,PM_L2_RTY_LD,RC retries on PB for any load from core (excludes DCBFs) ##000003689E RC retries on PB for any load from core (excludes DCBFs) $$$$$$$$ { counter 4} #0,u,g,n,n,n,PM_SUSPENDED,Counter OFF ##0000040000 Counter OFF #1,u,g,n,s,n,PM_CYC,Cycles ##000004001E Cycles #2,u,g,n,n,n,PM_INST_CMPL,PPC instructions completed ##0000040002 PPC instructions completed #3,u,g,n,n,n,PM_BR_2PATH,Branches that are not strongly biased ##0000040036 Branches that are not strongly biased #4,u,g,n,n,n,PM_LD_MISS_L1,Load Missed L1, counted at execution time (can be greater than loads finished). LMQ merges are not included in this count. i.e. if a load instruction misses on an address that is already allocated on the LMQ, this event will not increment for that load). Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load. ##00000400F0 Load Missed L1, counted at execution time (can be greater than loads finished). LMQ merges are not included in this count. i.e. if a load instruction misses on an address that is already allocated on the LMQ, this event will not increment for that load). Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load. #5,u,g,n,n,n,PM_FXU_FIN,The fixed point unit Unit finished an instruction. Instructions that finish may not necessary complete. ##0000040004 The fixed point unit Unit finished an instruction. Instructions that finish may not necessary complete. #6,u,g,n,n,n,PM_ISLB_MISS,Number of ISLB misses for this thread ##0000040006 Number of ISLB misses for this thread #7,u,g,n,s,n,PM_SRQ_EMPTY_CYC,Cycles in which the SRQ has at least one (out of four) empty slice ##0000040008 Cycles in which the SRQ has at least one (out of four) empty slice #8,u,g,n,s,n,PM_ISQ_36_44_ENTRIES,Cycles in which 36 or more Issue Queue entries are in use. This is a shared event, not per thread. There are 44 issue queue entries across 4 slices in the whole core ##000004000A Cycles in which 36 or more Issue Queue entries are in use. This is a shared event, not per thread. There are 44 issue queue entries across 4 slices in the whole core #9,u,g,n,s,n,PM_FREQ_UP,Power Management: Above Threshold A ##000004000C Power Management: Above Threshold A #10,u,g,n,n,n,PM_PMC3_OVERFLOW,Overflow from counter 3 ##0000040010 Overflow from counter 3 #11,u,g,n,n,n,PM_L1_ICACHE_RELOADED_ALL,Counts all Icache reloads includes demand, prefetch, prefetch turned into demand and demand turned into prefetch ##0000040012 Counts all Icache reloads includes demand, prefetch, prefetch turned into demand and demand turned into prefetch #12,u,g,n,n,n,PM_PROBE_NOP_DISP,ProbeNops dispatched ##0000040014 ProbeNops dispatched #13,u,g,n,n,m,PM_MRK_LARX_FIN,Larx finished ##0000040116 Larx finished #14,u,g,n,n,m,PM_MRK_DCACHE_RELOAD_INTV,Combined Intervention event ##0000040118 Combined Intervention event #15,u,g,n,n,n,PM_INST_IMC_MATCH_CMPL,IMC Match Count ##000004001C IMC Match Count #16,u,g,n,n,n,PM_CMPLU_STALL_STORE_PIPE_ARB,Finish stall because the NTF instruction was a store waiting for the next relaunch opportunity after an internal reject. This means the instruction is ready to relaunch and tried once but lost arbitration ##000004C010 Finish stall because the NTF instruction was a store waiting for the next relaunch opportunity after an internal reject. This means the instruction is ready to relaunch and tried once but lost arbitration #17,u,g,n,n,n,PM_CMPLU_STALL_ERAT_MISS,Finish stall because the NTF instruction was a load or store that suffered a translation miss ##000004C012 Finish stall because the NTF instruction was a load or store that suffered a translation miss #18,u,g,n,n,n,PM_CMPLU_STALL_LMQ_FULL,Finish stall because the NTF instruction was a load that missed in the L1 and the LMQ was unable to accept this load miss request because it was full ##000004C014 Finish stall because the NTF instruction was a load that missed in the L1 and the LMQ was unable to accept this load miss request because it was full #19,u,g,n,n,n,PM_CMPLU_STALL_DMISS_L2L3_CONFLICT,Completion stall due to cache miss that resolves in the L2 or L3 with a conflict ##000004C016 Completion stall due to cache miss that resolves in the L2 or L3 with a conflict #20,u,g,n,n,n,PM_CMPLU_STALL_DMISS_L3MISS,Completion stall due to cache miss resolving missed the L3 ##000004C01A Completion stall due to cache miss resolving missed the L3 #21,u,g,n,n,n,PM_CMPLU_STALL_ST_FWD,Completion stall due to store forward ##000004C01C Completion stall due to store forward #22,u,g,n,n,n,PM_CMPLU_STALL_CRYPTO,Finish stall because the NTF instruction was routed to the crypto execution pipe and was waiting to finish ##000004C01E Finish stall because the NTF instruction was routed to the crypto execution pipe and was waiting to finish #23,u,g,n,n,n,PM_PMC1_SAVED,PMC1 Rewind Value saved ##000004D010 PMC1 Rewind Value saved #24,u,g,n,n,n,PM_PMC3_SAVED,PMC3 Rewind Value saved ##000004D012 PMC3 Rewind Value saved #25,u,g,n,n,n,PM_CMPLU_STALL_LOAD_FINISH,Finish stall because the NTF instruction was a load instruction with all its dependencies satisfied just going through the LSU pipe to finish ##000004D014 Finish stall because the NTF instruction was a load instruction with all its dependencies satisfied just going through the LSU pipe to finish #26,u,g,n,n,n,PM_CMPLU_STALL_FXLONG,Completion stall due to a long latency scalar fixed point instruction (division, square root) ##000004D016 Completion stall due to a long latency scalar fixed point instruction (division, square root) #27,u,g,n,n,n,PM_CMPLU_STALL_BRU,Completion stall due to a Branch Unit ##000004D018 Completion stall due to a Branch Unit #28,u,g,n,n,n,PM_CMPLU_STALL_EIEIO,Finish stall because the NTF instruction is an EIEIO waiting for response from L2 ##000004D01A Finish stall because the NTF instruction is an EIEIO waiting for response from L2 #29,u,g,n,n,n,PM_ICT_NOSLOT_DISP_HELD_SYNC,Dispatch held due to a synchronizing instruction at dispatch ##000004D01C Dispatch held due to a synchronizing instruction at dispatch #30,u,g,n,n,n,PM_ICT_NOSLOT_BR_MPRED,Ict empty for this thread due to branch mispred ##000004D01E Ict empty for this thread due to branch mispred #31,u,g,n,n,n,PM_ICT_NOSLOT_IC_L3MISS,Ict empty for this thread due to icache misses that were sourced from beyond the local L3. The source could be local/remote/distant memory or another core's cache ##000004E010 Ict empty for this thread due to icache misses that were sourced from beyond the local L3. The source could be local/remote/distant memory or another core's cache #32,u,g,n,n,n,PM_CMPLU_STALL_MTFPSCR,Completion stall because the ISU is updating the register and notifying the Effective Address Table (EAT) ##000004E012 Completion stall because the ISU is updating the register and notifying the Effective Address Table (EAT) #33,u,g,n,n,n,PM_CMPLU_STALL_LSAQ_ARB,Finish stall because the NTF instruction was a load or store that was held in LSAQ because an older instruction from SRQ or LRQ won arbitration to the LSU pipe when this instruction tried to launch ##000004E016 Finish stall because the NTF instruction was a load or store that was held in LSAQ because an older instruction from SRQ or LRQ won arbitration to the LSU pipe when this instruction tried to launch #34,u,g,n,n,n,PM_CMPLU_STALL_NTC_DISP_FIN,Finish stall because the NTF instruction was one that must finish at dispatch. ##000004E018 Finish stall because the NTF instruction was one that must finish at dispatch. #35,u,g,n,n,n,PM_ICT_NOSLOT_DISP_HELD,Cycles in which the NTC instruction is held at dispatch for any reason ##000004E01A Cycles in which the NTC instruction is held at dispatch for any reason #36,u,g,n,n,m,PM_MRK_DATA_FROM_DMEM_CYC,Duration in cycles to reload from another chip's memory on the same Node or Group (Distant) due to a marked load ##000004E11E Duration in cycles to reload from another chip's memory on the same Node or Group (Distant) due to a marked load #37,u,g,n,n,m,PM_MRK_DATA_FROM_L2_MEPF,The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load ##000004C120 The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load #38,u,g,n,n,n,PM_DARQ1_0_3_ENTRIES,Cycles in which 3 or fewer DARQ1 entries (out of 12) are in use ##000004C122 Cycles in which 3 or fewer DARQ1 entries (out of 12) are in use #39,u,g,n,n,m,PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC,Duration in cycles to reload from local core's L3 without conflict due to a marked load ##000004C124 Duration in cycles to reload from local core's L3 without conflict due to a marked load #40,u,g,n,n,m,PM_MRK_DATA_FROM_RL2L3_SHR_CYC,Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load ##000004C12A Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load #41,u,g,n,n,m,PM_MRK_DATA_FROM_L31_SHR,The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to a marked load ##000004D124 The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to a marked load #42,u,g,n,n,m,PM_MRK_DATA_FROM_LMEM_CYC,Duration in cycles to reload from the local chip's Memory due to a marked load ##000004D128 Duration in cycles to reload from the local chip's Memory due to a marked load #43,u,g,n,n,m,PM_MRK_DATA_FROM_RL4_CYC,Duration in cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load ##000004D12A Duration in cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load #44,u,g,n,n,n,PM_PMC1_REWIND, ##000004D02C #45,u,g,n,n,m,PM_MRK_DATA_FROM_DL2L3_MOD_CYC,Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load ##000004D12E Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load #46,u,g,n,n,m,PM_MRK_LSU_FIN,lsu marked instr PPC finish ##0000040132 lsu marked instr PPC finish #47,u,g,n,n,m,PM_MRK_INST_TIMEO,marked Instruction finish timeout (instruction lost) ##0000040134 marked Instruction finish timeout (instruction lost) #48,u,g,n,n,m,PM_MRK_IC_MISS,Marked instruction experienced I cache miss ##000004013A Marked instruction experienced I cache miss #49,u,g,n,n,n,PM_LD_CMPL,count of Loads completed ##000004003E count of Loads completed #50,u,g,n,n,n,PM_DATA_FROM_L2_DISP_CONFLICT_OTHER,The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a demand load ##000004C040 The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a demand load #51,u,g,n,n,n,PM_DATA_FROM_L3,The processor's data cache was reloaded from local core's L3 due to a demand load ##000004C042 The processor's data cache was reloaded from local core's L3 due to a demand load #52,u,g,n,n,n,PM_DATA_FROM_L31_ECO_MOD,The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a demand load ##000004C044 The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a demand load #53,u,g,n,n,n,PM_DATA_FROM_L21_MOD,The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a demand load ##000004C046 The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a demand load #54,u,g,n,n,n,PM_DATA_FROM_DL2L3_MOD,The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load ##000004C048 The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load #55,u,g,n,n,n,PM_DATA_FROM_OFF_CHIP_CACHE,The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a demand load ##000004C04A The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a demand load #56,u,g,n,n,n,PM_DATA_FROM_DMEM,The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a demand load ##000004C04C The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a demand load #57,u,g,n,n,n,PM_DATA_FROM_L3MISS_MOD,The processor's data cache was reloaded from a location other than the local core's L3 due to a demand load ##000004C04E The processor's data cache was reloaded from a location other than the local core's L3 due to a demand load #58,u,g,n,n,n,PM_INST_FROM_L2_DISP_CONFLICT_OTHER,The processor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to an instruction fetch (not prefetch) ##0000044040 The processor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to an instruction fetch (not prefetch) #59,u,g,n,n,n,PM_INST_FROM_L3,The processor's Instruction cache was reloaded from local core's L3 due to an instruction fetch (not prefetch) ##0000044042 The processor's Instruction cache was reloaded from local core's L3 due to an instruction fetch (not prefetch) #60,u,g,n,n,n,PM_INST_FROM_L31_ECO_MOD,The processor's Instruction cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to an instruction fetch (not prefetch) ##0000044044 The processor's Instruction cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to an instruction fetch (not prefetch) #61,u,g,n,n,n,PM_INST_FROM_L21_MOD,The processor's Instruction cache was reloaded with Modified (M) data from another core's L2 on the same chip due to an instruction fetch (not prefetch) ##0000044046 The processor's Instruction cache was reloaded with Modified (M) data from another core's L2 on the same chip due to an instruction fetch (not prefetch) #62,u,g,n,n,n,PM_INST_FROM_DL2L3_MOD,The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction fetch (not prefetch) ##0000044048 The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction fetch (not prefetch) #63,u,g,n,n,n,PM_INST_FROM_OFF_CHIP_CACHE,The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to an instruction fetch (not prefetch) ##000004404A The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to an instruction fetch (not prefetch) #64,u,g,n,n,n,PM_INST_FROM_DMEM,The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Distant) due to an instruction fetch (not prefetch) ##000004404C The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Distant) due to an instruction fetch (not prefetch) #65,u,g,n,n,n,PM_INST_FROM_L3MISS_MOD,The processor's Instruction cache was reloaded from a location other than the local core's L3 due to a instruction fetch ##000004404E The processor's Instruction cache was reloaded from a location other than the local core's L3 due to a instruction fetch #66,u,g,n,n,m,PM_MRK_DATA_FROM_ON_CHIP_CACHE,The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a marked load ##000004D140 The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a marked load #67,u,g,n,n,m,PM_MRK_DATA_FROM_L3,The processor's data cache was reloaded from local core's L3 due to a marked load ##000004D142 The processor's data cache was reloaded from local core's L3 due to a marked load #68,u,g,n,n,m,PM_MRK_DATA_FROM_L31_ECO_MOD,The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a marked load ##000004D144 The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a marked load #69,u,g,n,n,m,PM_MRK_DATA_FROM_L21_MOD,The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a marked load ##000004D146 The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a marked load #70,u,g,n,n,n,PM_DARQ0_0_3_ENTRIES,Cycles in which 3 or less DARQ entries (out of 12) are in use ##000004D04A Cycles in which 3 or less DARQ entries (out of 12) are in use #71,u,g,n,s,n,PM_DFU_BUSY,Cycles in which all 4 Decimal Floating Point units are busy. The DFU is running at capacity ##000004D04C Cycles in which all 4 Decimal Floating Point units are busy. The DFU is running at capacity #72,u,g,n,n,n,PM_VSU_FSQRT_FDIV,four flops operation (fdiv,fsqrt) Scalar Instructions only ##000004D04E four flops operation (fdiv,fsqrt) Scalar Instructions only #73,u,g,n,n,n,PM_IPTEG_FROM_L3,A Page Table Entry was loaded into the TLB from local core's L3 due to a instruction side request ##0000045042 A Page Table Entry was loaded into the TLB from local core's L3 due to a instruction side request #74,u,g,n,n,n,PM_IPTEG_FROM_L31_ECO_MOD,A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a instruction side request ##0000045044 A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a instruction side request #75,u,g,n,n,n,PM_IPTEG_FROM_L21_MOD,A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a instruction side request ##0000045046 A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a instruction side request #76,u,g,n,n,n,PM_IPTEG_FROM_DL2L3_MOD,A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request ##0000045048 A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request #77,u,g,n,n,n,PM_IPTEG_FROM_OFF_CHIP_CACHE,A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a instruction side request ##000004504A A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a instruction side request #78,u,g,n,n,n,PM_IPTEG_FROM_DMEM,A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a instruction side request ##000004504C A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a instruction side request #79,u,g,n,n,n,PM_IPTEG_FROM_L3MISS,A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a instruction side request ##000004504E A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a instruction side request #80,u,g,n,n,n,PM_DPTEG_FROM_L3,A Page Table Entry was loaded into the TLB from local core's L3 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000004E042 A Page Table Entry was loaded into the TLB from local core's L3 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #81,u,g,n,n,n,PM_DPTEG_FROM_L31_ECO_MOD,A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000004E044 A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #82,u,g,n,n,n,PM_DPTEG_FROM_L21_MOD,A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000004E046 A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #83,u,g,n,n,n,PM_DPTEG_FROM_DL2L3_MOD,A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000004E048 A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #84,u,g,n,n,n,PM_DPTEG_FROM_OFF_CHIP_CACHE,A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000004E04A A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #85,u,g,n,n,n,PM_DPTEG_FROM_DMEM,A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000004E04C A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #86,u,g,n,n,n,PM_DPTEG_FROM_L3MISS,A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000004E04E A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #87,u,g,n,n,m,PM_MRK_DPTEG_FROM_L3,A Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000004F142 A Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #88,u,g,n,n,m,PM_MRK_DPTEG_FROM_L31_ECO_MOD,A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000004F144 A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #89,u,g,n,n,m,PM_MRK_DPTEG_FROM_L21_MOD,A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000004F146 A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #90,u,g,n,n,m,PM_MRK_DPTEG_FROM_DL2L3_MOD,A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000004F148 A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #91,u,g,n,n,m,PM_MRK_DPTEG_FROM_OFF_CHIP_CACHE,A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000004F14A A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #92,u,g,n,n,m,PM_MRK_DPTEG_FROM_DMEM,A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000004F14C A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #93,u,g,n,n,m,PM_MRK_DPTEG_FROM_L3MISS,A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included ##000004F14E A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included #94,u,g,n,n,n,PM_SYS_PUMP_MPRED_RTY,Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) ##0000040050 Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) #95,u,g,n,n,n,PM_PUMP_MPRED,Pump misprediction. Counts across all types of pumps for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) ##0000040052 Pump misprediction. Counts across all types of pumps for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) #96,u,g,n,n,m,PM_MRK_FAB_RSP_BKILL,Marked store had to do a bkill ##0000040154 Marked store had to do a bkill #97,u,g,n,s,n,PM_MEM_LOC_THRESH_LSU_HIGH,Local memory above threshold for LSU medium ##0000040056 Local memory above threshold for LSU medium #98,u,g,n,n,m,PM_MRK_FAB_RSP_RD_RTY,Sampled L2 reads retry count ##000004015E Sampled L2 reads retry count #99,u,g,n,n,n,PM_DATA_SYS_PUMP_MPRED_RTY,Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for a demand load ##000004C050 Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for a demand load #100,u,g,n,n,n,PM_DATA_PUMP_MPRED,Pump misprediction. Counts across all types of pumps for a demand load ##000004C052 Pump misprediction. Counts across all types of pumps for a demand load #101,u,g,n,n,n,PM_DERAT_MISS_16G_1G,Data ERAT Miss (Data TLB Access) page size 16G (hpt mode) or 1G (radix mode) ##000004C054 Data ERAT Miss (Data TLB Access) page size 16G (hpt mode) or 1G (radix mode) #102,u,g,n,n,n,PM_MEM_CO,Memory castouts from this thread ##000004C058 Memory castouts from this thread #103,u,g,n,n,m,PM_MRK_DERAT_MISS_16G_1G,Marked Data ERAT Miss (Data TLB Access) page size 16G (hpt mode) and 1G (radix mode) ##000004C15C Marked Data ERAT Miss (Data TLB Access) page size 16G (hpt mode) and 1G (radix mode) #104,u,g,n,n,n,PM_INST_SYS_PUMP_MPRED_RTY,Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for an instruction fetch ##0000044050 Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for an instruction fetch #105,u,g,n,n,n,PM_INST_PUMP_MPRED,Pump misprediction. Counts across all types of pumps for an instruction fetch ##0000044052 Pump misprediction. Counts across all types of pumps for an instruction fetch #106,u,g,n,n,n,PM_VECTOR_LD_CMPL,Number of vector load instructions completed ##0000044054 Number of vector load instructions completed #107,u,g,n,n,n,PM_VECTOR_ST_CMPL,Number of vector store instructions completed ##0000044056 Number of vector store instructions completed #108,u,g,n,n,n,PM_CMPLU_STALL_VDP,Finish stall because the NTF instruction was a vector instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Not qualified multicycle. Qualified by vector ##000004405C Finish stall because the NTF instruction was a vector instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Not qualified multicycle. Qualified by vector #109,u,g,n,s,n,PM_DARQ_STORE_REJECT,The DARQ attempted to transmit a store into an LSAQ or SRQ entry but It was rejected. Divide by PM_DARQ_STORE_XMIT to get reject ratio ##000004405E The DARQ attempted to transmit a store into an LSAQ or SRQ entry but It was rejected. Divide by PM_DARQ_STORE_XMIT to get reject ratio #110,u,g,n,n,n,PM_VSU_NON_FLOP_CMPL,Non FLOP operation completed ##000004D050 Non FLOP operation completed #111,u,g,n,n,n,PM_2FLOP_CMPL,DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg  ##000004D052 DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg  #112,u,g,n,n,n,PM_8FLOP_CMPL,8 FLOP instruction completed ##000004D054 8 FLOP instruction completed #113,u,g,n,n,n,PM_NON_FMA_FLOP_CMPL,Non FMA instruction completed ##000004D056 Non FMA instruction completed #114,u,g,n,n,n,PM_VECTOR_FLOP_CMPL,Vector FP instruction completed ##000004D058 Vector FP instruction completed #115,u,g,n,n,n,PM_NON_MATH_FLOP_CMPL,Non FLOP operation completed ##000004D05A Non FLOP operation completed #116,u,g,n,n,n,PM_DP_QP_FLOP_CMPL,Double-Precion or Quad-Precision instruction completed ##000004D05C Double-Precion or Quad-Precision instruction completed #117,u,g,n,n,n,PM_BR_CMPL,Any Branch instruction completed ##000004D05E Any Branch instruction completed #118,u,g,n,n,n,PM_1FLOP_CMPL,one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation completed ##0000045050 one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation completed #119,u,g,n,n,n,PM_4FLOP_CMPL,4 FLOP instruction completed ##0000045052 4 FLOP instruction completed #120,u,g,n,n,n,PM_FMA_CMPL,two flops operation completed (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only.  ##0000045054 two flops operation completed (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only.  #121,u,g,n,n,n,PM_SCALAR_FLOP_CMPL,Scalar flop operation completed ##0000045056 Scalar flop operation completed #122,u,g,n,n,n,PM_IC_MISS_CMPL,Non-speculative icache miss, counted at completion ##0000045058 Non-speculative icache miss, counted at completion #123,u,g,n,n,n,PM_SP_FLOP_CMPL,SP instruction completed ##000004505A SP instruction completed #124,u,g,n,n,n,PM_MATH_FLOP_CMPL,Math flop instruction completed ##000004505C Math flop instruction completed #125,u,g,n,n,n,PM_FLOP_CMPL,Floating Point Operation Finished ##000004505E Floating Point Operation Finished #126,u,g,n,n,n,PM_LSU_REJECT_LHS,LSU Reject due to LHS (up to 4 per cycle) ##000004E05C LSU Reject due to LHS (up to 4 per cycle) #127,u,g,n,n,n,PM_TM_OUTER_TBEGIN_DISP,Number of outer tbegin instructions dispatched. The dispatch unit determines whether the tbegin instruction is outer or nested. This is a speculative count, which includes flushed instructions ##000004E05E Number of outer tbegin instructions dispatched. The dispatch unit determines whether the tbegin instruction is outer or nested. This is a speculative count, which includes flushed instructions #128,u,g,n,n,m,PM_MRK_FAB_RSP_RWITM_CYC,cycles L2 RC took for a rwitm ##000004F150 cycles L2 RC took for a rwitm #129,u,g,n,n,n,PM_RADIX_PWC_MISS,A radix translation attempt missed in the TLB and all levels of page walk cache. ##000004F054 A radix translation attempt missed in the TLB and all levels of page walk cache. #130,u,g,n,n,n,PM_RADIX_PWC_L1_PDE_FROM_L3MISS,A Page Directory Entry was reloaded to a level 1 page walk cache from beyond the core's L3 data cache. The source could be local/remote/distant memory or another core's cache ##000004F056 A Page Directory Entry was reloaded to a level 1 page walk cache from beyond the core's L3 data cache. The source could be local/remote/distant memory or another core's cache #131,u,g,n,n,n,PM_RADIX_PWC_L2_PTE_FROM_L3,A Page Table Entry was reloaded to a level 2 page walk cache from the core's L3 data cache. This implies that level 3 and level 4 PWC accesses were not necessary for this translation ##000004F058 A Page Table Entry was reloaded to a level 2 page walk cache from the core's L3 data cache. This implies that level 3 and level 4 PWC accesses were not necessary for this translation #132,u,g,n,n,n,PM_RADIX_PWC_L4_PTE_FROM_L3,A Page Table Entry was reloaded to a level 4 page walk cache from the core's L3 data cache. This is the deepest level of PWC possible for a translation ##000004F05A A Page Table Entry was reloaded to a level 4 page walk cache from the core's L3 data cache. This is the deepest level of PWC possible for a translation #133,u,g,n,n,n,PM_RADIX_PWC_L2_PTE_FROM_L3MISS,A Page Table Entry was reloaded to a level 2 page walk cache from beyond the core's L3 data cache. This implies that level 3 and level 4 PWC accesses were not necessary for this translation. The source could be local/remote/distant memory or another core's cache ##000004F05C A Page Table Entry was reloaded to a level 2 page walk cache from beyond the core's L3 data cache. This implies that level 3 and level 4 PWC accesses were not necessary for this translation. The source could be local/remote/distant memory or another core's cache #134,u,g,n,n,n,PM_RADIX_PWC_L3_PTE_FROM_L3MISS,A Page Table Entry was reloaded to a level 3 page walk cache from beyond the core's L3 data cache. This implies that a level 4 PWC access was not necessary for this translation. The source could be local/remote/distant memory or another core's cache ##000004F05E A Page Table Entry was reloaded to a level 3 page walk cache from beyond the core's L3 data cache. This implies that a level 4 PWC access was not necessary for this translation. The source could be local/remote/distant memory or another core's cache #135,u,g,n,n,n,PM_DUMMY1_REMOVE_ME,Space holder for L2_PC_PM_MK_LDST_SCOPE_PRED_STATUS ##0000040062 Space holder for L2_PC_PM_MK_LDST_SCOPE_PRED_STATUS #136,u,g,n,n,n,PM_DUMMY2_REMOVE_ME,Space holder for LS_PC_RELOAD_RA ##0000040064 Space holder for LS_PC_RELOAD_RA #137,u,g,n,n,n,PM_IERAT_RELOAD_16M,IERAT Reloaded (Miss) for a 16M page ##000004006A IERAT Reloaded (Miss) for a 16M page #138,u,g,t,n,n,PM_THRESH_NOT_MET,Threshold counter did not meet threshold ##000004016E Threshold counter did not meet threshold #139,u,g,n,n,m,PM_MRK_INST_CMPL,marked instruction completed ##00000401E0 marked instruction completed #140,u,g,n,n,m,PM_MRK_DTLB_MISS,Marked dtlb miss ##00000401E4 Marked dtlb miss #141,u,g,n,n,m,PM_MRK_INST_FROM_L3MISS,Marked instruction was reloaded from a location beyond the local chiplet ##00000401E6 Marked instruction was reloaded from a location beyond the local chiplet #142,u,g,n,n,m,PM_MRK_DATA_FROM_L2MISS,The processor's data cache was reloaded from a location other than the local core's L2 due to a marked load ##00000401E8 The processor's data cache was reloaded from a location other than the local core's L2 due to a marked load #143,u,g,t,n,n,PM_THRESH_EXC_128,Threshold counter exceeded a value of 128 ##00000401EA Threshold counter exceeded a value of 128 #144,u,g,t,n,n,PM_THRESH_EXC_2048,Threshold counter exceeded a value of 2048 ##00000401EC Threshold counter exceeded a value of 2048 #145,u,g,n,n,n,PM_1PLUS_PPC_DISP,Cycles at least one Instr Dispatched ##00000400F2 Cycles at least one Instr Dispatched #146,u,g,n,n,n,PM_RUN_PURR,Run_PURR ##00000400F4 Run_PURR #147,u,g,n,n,n,PM_BR_MPRED_CMPL,Number of Branch Mispredicts ##00000400F6 Number of Branch Mispredicts #148,u,g,n,n,n,PM_FLUSH,Flush (any type) ##00000400F8 Flush (any type) #149,u,g,n,n,n,PM_RUN_INST_CMPL,Run_Instructions ##00000400FA Run_Instructions #150,u,g,n,n,n,PM_ITLB_MISS,ITLB Reloaded. Counts 1 per ITLB miss for HPT but multiple for radix depending on number of levels traveresed ##00000400FC ITLB Reloaded. Counts 1 per ITLB miss for HPT but multiple for radix depending on number of levels traveresed #151,u,g,n,n,n,PM_DATA_FROM_MEMORY,The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a demand load ##00000400FE The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a demand load #152,u,g,n,n,n,PM_EE_OFF_EXT_INT,CyclesMSR[EE] is off and external interrupts are active ##0000002080 CyclesMSR[EE] is off and external interrupts are active #153,u,g,n,n,n,PM_FLUSH_DISP,Dispatch flush ##0000002880 Dispatch flush #154,u,g,n,n,n,PM_FLUSH_HB_RESTORE_CYC,Cycles in which no new instructions can be dispatched to the ICT after a flush. History buffer recovery ##0000002084 Cycles in which no new instructions can be dispatched to the ICT after a flush. History buffer recovery #155,u,g,n,n,n,PM_ISYNC,Isync completion count per thread ##0000002884 Isync completion count per thread #156,u,g,n,n,n,PM_FLUSH_DISP_SB,Dispatch Flush: Scoreboard ##0000002088 Dispatch Flush: Scoreboard #157,u,g,n,n,n,PM_FLUSH_DISP_TLBIE,Dispatch Flush: TLBIE ##0000002888 Dispatch Flush: TLBIE #158,u,g,n,n,n,PM_CLB_HELD,CLB (control logic block - indicates quadword fetch block) Hold: Any Reason ##000000208C CLB (control logic block - indicates quadword fetch block) Hold: Any Reason #159,u,g,n,n,n,PM_DISP_CLB_HELD_BAL,Dispatch/CLB Hold: Balance Flush ##000000288C Dispatch/CLB Hold: Balance Flush #160,u,g,n,n,n,PM_DISP_CLB_HELD_SB,Dispatch/CLB Hold: Scoreboard ##0000002090 Dispatch/CLB Hold: Scoreboard #161,u,g,n,n,n,PM_DISP_CLB_HELD_TLBIE,Dispatch Hold: Due to TLBIE ##0000002890 Dispatch Hold: Due to TLBIE #162,u,g,n,n,n,PM_TM_OUTER_TBEGIN,Completion time outer tbegin ##0000002094 Completion time outer tbegin #163,u,g,n,n,n,PM_TM_OUTER_TEND,Completion time outer tend ##0000002894 Completion time outer tend #164,u,g,n,n,n,PM_TM_NESTED_TEND,Completion time nested tend ##0000002098 Completion time nested tend #165,u,g,n,n,n,PM_TM_TABORT_TRECLAIM,Completion time tabortnoncd, tabortcd, treclaim ##0000002898 Completion time tabortnoncd, tabortcd, treclaim #166,u,g,n,n,n,PM_TM_FAV_TBEGIN,Dispatch time Favored tbegin ##000000209C Dispatch time Favored tbegin #167,u,g,n,n,n,PM_TM_NON_FAV_TBEGIN,Dispatch time non favored tbegin ##000000289C Dispatch time non favored tbegin #168,u,g,n,n,n,PM_TM_NESTED_TBEGIN,Completion Tm nested tbegin ##00000020A0 Completion Tm nested tbegin #169,u,g,n,n,n,PM_TM_TSUSPEND,TM suspend instruction completed ##00000028A0 TM suspend instruction completed #170,u,g,n,n,n,PM_TM_TRESUME,TM resume instruction completed ##00000020A4 TM resume instruction completed #171,u,g,n,n,n,PM_MRK_TEND_FAIL,Nested or not nested tend failed for a marked tend instruction ##00000028A4 Nested or not nested tend failed for a marked tend instruction #172,u,g,n,n,n,PM_TM_FAIL_FOOTPRINT_OVERFLOW,TM aborted because the tracking limit for transactional storage accesses was exceeded.. Asynchronous ##00000020A8 TM aborted because the tracking limit for transactional storage accesses was exceeded.. Asynchronous #173,u,g,n,n,n,PM_TM_FAIL_CONF_NON_TM,TM aborted because a conflict occurred with a non-transactional access by another processor ##00000028A8 TM aborted because a conflict occurred with a non-transactional access by another processor #174,u,g,n,n,n,PM_TM_FAIL_CONF_TM,TM aborted because a conflict occurred with another transaction. ##00000020AC TM aborted because a conflict occurred with another transaction. #175,u,g,n,n,n,PM_TM_FAIL_SELF,TM aborted because a self-induced conflict occurred in Suspended state, due to one of the following: a store to a storage location that was previously accessed transactionally ##00000028AC TM aborted because a self-induced conflict occurred in Suspended state, due to one of the following: a store to a storage location that was previously accessed transactionally #176,u,g,n,n,n,PM_LSU_FLUSH_NEXT,LSU flush next reported at flush time. Sometimes these also come with an exception ##00000020B0 LSU flush next reported at flush time. Sometimes these also come with an exception #177,u,g,n,n,n,PM_DISP_HELD_TBEGIN,This outer tbegin transaction cannot be dispatched until the previous tend instruction completes ##00000028B0 This outer tbegin transaction cannot be dispatched until the previous tend instruction completes #178,u,g,n,n,n,PM_ISU0_ISS_HOLD_ALL,All ISU rejects ##0000003080 All ISU rejects #179,u,g,n,n,n,PM_ISU2_ISS_HOLD_ALL,All ISU rejects ##0000003880 All ISU rejects #180,u,g,n,n,n,PM_ISU1_ISS_HOLD_ALL,All ISU rejects ##0000003084 All ISU rejects #181,u,g,n,n,n,PM_ISU3_ISS_HOLD_ALL,All ISU rejects ##0000003884 All ISU rejects #182,u,g,n,n,n,PM_LS0_LD_VECTOR_FIN,LS0 finished load vector op ##000000C080 LS0 finished load vector op #183,u,g,n,n,n,PM_LS1_LD_VECTOR_FIN,LS1 finished load vector op ##000000C880 LS1 finished load vector op #184,u,g,n,n,n,PM_LS2_LD_VECTOR_FIN,LS2 finished load vector op ##000000C084 LS2 finished load vector op #185,u,g,n,n,n,PM_LS3_LD_VECTOR_FIN,LS3 finished load vector op ##000000C884 LS3 finished load vector op #186,u,g,n,n,n,PM_LSU_DTLB_MISS_4K,Data TLB Miss page size 4K ##000000C088 Data TLB Miss page size 4K #187,u,g,n,n,n,PM_LSU_DTLB_MISS_64K,Data TLB Miss page size 64K ##000000C888 Data TLB Miss page size 64K #188,u,g,n,n,n,PM_LSU_DTLB_MISS_16M_2M,Data TLB Miss page size 16M (HPT) or 2M (Radix) ##000000C08C Data TLB Miss page size 16M (HPT) or 2M (Radix) #189,u,g,n,n,n,PM_LSU_DTLB_MISS_16G_1G,Data TLB Miss page size 16G (HPT) or 1G (Radix) ##000000C88C Data TLB Miss page size 16G (HPT) or 1G (Radix) #190,u,g,n,n,n,PM_LSU_STCX,STCX sent to nest, i.e. total ##000000C090 STCX sent to nest, i.e. total #191,u,g,n,n,n,PM_LSU_NCST,Asserts when a i=1 store op is sent to the nest. No record of issue pipe (LS0/LS1) is maintained so this is for both pipes. Probably don't need separate LS0 and LS1 ##000000C890 Asserts when a i=1 store op is sent to the nest. No record of issue pipe (LS0/LS1) is maintained so this is for both pipes. Probably don't need separate LS0 and LS1 #192,u,g,n,n,n,PM_LS0_UNALIGNED_LD,Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty ##000000C094 Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty #193,u,g,n,n,n,PM_LS1_UNALIGNED_LD,Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty ##000000C894 Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty #194,u,g,n,n,n,PM_LS2_UNALIGNED_LD,Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty ##000000C098 Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty #195,u,g,n,n,n,PM_LS3_UNALIGNED_LD,Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty ##000000C898 Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty #196,u,g,n,n,n,PM_LS0_LAUNCH_HELD_PREF,Number of times a load or store instruction was unable to launch/relaunch because a high priority prefetch used that relaunch cycle ##000000C09C Number of times a load or store instruction was unable to launch/relaunch because a high priority prefetch used that relaunch cycle #197,u,g,n,n,n,PM_LS1_LAUNCH_HELD_PREF,Number of times a load or store instruction was unable to launch/relaunch because a high priority prefetch used that relaunch cycle ##000000C89C Number of times a load or store instruction was unable to launch/relaunch because a high priority prefetch used that relaunch cycle #198,u,g,n,n,n,PM_LSU0_FALSE_LHS,False LHS match detected ##000000C0A0 False LHS match detected #199,u,g,n,n,n,PM_LSU1_FALSE_LHS,False LHS match detected ##000000C8A0 False LHS match detected #200,u,g,n,n,n,PM_LSU2_FALSE_LHS,False LHS match detected ##000000C0A4 False LHS match detected #201,u,g,n,n,n,PM_LSU3_FALSE_LHS,False LHS match detected ##000000C8A4 False LHS match detected #202,u,g,n,n,n,PM_LSU_FLUSH_CI,Load was not issued to LSU as a cache inhibited (non-cacheable) load but it was later determined to be cache inhibited ##000000C0A8 Load was not issued to LSU as a cache inhibited (non-cacheable) load but it was later determined to be cache inhibited #203,u,g,n,n,n,PM_LSU_FLUSH_ATOMIC,Quad-word loads (lq) are considered atomic because they always span at least 2 slices. If a snoop or store from another thread changes the data the load is accessing between the 2 or 3 pieces of the lq instruction, the lq will be flushed ##000000C8A8 Quad-word loads (lq) are considered atomic because they always span at least 2 slices. If a snoop or store from another thread changes the data the load is accessing between the 2 or 3 pieces of the lq instruction, the lq will be flushed #204,u,g,n,n,n,PM_LSU_FLUSH_EMSH,An ERAT miss was detected after a set-p hit. Erat tracker indicates fail due to tlbmiss and the instruction gets flushed because the instruction was working on the wrong address ##000000C0AC An ERAT miss was detected after a set-p hit. Erat tracker indicates fail due to tlbmiss and the instruction gets flushed because the instruction was working on the wrong address #205,u,g,n,n,n,PM_LSU_FLUSH_RELAUNCH_MISS,If a load that has already returned data and has to relaunch for any reason then gets a miss (erat, setp, data cache), it will often be flushed at relaunch time because the data might be inconsistent ##000000C8AC If a load that has already returned data and has to relaunch for any reason then gets a miss (erat, setp, data cache), it will often be flushed at relaunch time because the data might be inconsistent #206,u,g,n,n,n,PM_LSU_FLUSH_UE,Correctable ECC error on reload data, reported at critical data forward time ##000000C0B0 Correctable ECC error on reload data, reported at critical data forward time #207,u,g,n,n,n,PM_LSU_FLUSH_LHS,Effective Address alias flush : no EA match but Real Address match. If the data has not yet been returned for this load, the instruction will just be rejected, but if it has returned data, it will be flushed ##000000C8B0 Effective Address alias flush : no EA match but Real Address match. If the data has not yet been returned for this load, the instruction will just be rejected, but if it has returned data, it will be flushed #208,u,g,n,n,n,PM_LSU_FLUSH_WRK_ARND,LSU workaround flush. These flushes are setup with programmable scan only latches to perform various actions when the flush macro receives a trigger from the dbg macros. These actions include things like flushing the next op encountered for a particular thread or flushing the next op that is NTC op that is encountered on a particular slice. The kind of flush that the workaround is setup to perform is highly variable. ##000000C0B4 LSU workaround flush. These flushes are setup with programmable scan only latches to perform various actions when the flush macro receives a trigger from the dbg macros. These actions include things like flushing the next op encountered for a particular thread or flushing the next op that is NTC op that is encountered on a particular slice. The kind of flush that the workaround is setup to perform is highly variable. #209,u,g,n,n,n,PM_LSU_FLUSH_LHL_SHL,The instruction was flushed because of a sequential load/store consistency. If a load or store hits on an older load that has either been snooped (for loads) or has stale data (for stores). ##000000C8B4 The instruction was flushed because of a sequential load/store consistency. If a load or store hits on an older load that has either been snooped (for loads) or has stale data (for stores). #210,u,g,n,n,n,PM_LSU_FLUSH_SAO,A load-hit-load condition with Strong Address Ordering will have address compare disabled and flush ##000000C0B8 A load-hit-load condition with Strong Address Ordering will have address compare disabled and flush #211,u,g,n,n,n,PM_LSU_FLUSH_LARX_STCX,A larx is flushed because an older larx has an LMQ reservation for the same thread. A stcx is flushed because an older stcx is in the LMQ. The flush happens when the older larx/stcx relaunches ##000000C8B8 A larx is flushed because an older larx has an LMQ reservation for the same thread. A stcx is flushed because an older stcx is in the LMQ. The flush happens when the older larx/stcx relaunches #212,u,g,n,n,n,PM_LSU_FLUSH_OTHER,Other LSU flushes including: Sync (sync ack from L2 caused search of LRQ for oldest snooped load, This will either signal a Precise Flush of the oldest snooped loa or a Flush Next PPC) ##000000C0BC Other LSU flushes including: Sync (sync ack from L2 caused search of LRQ for oldest snooped load, This will either signal a Precise Flush of the oldest snooped loa or a Flush Next PPC) #213,u,g,n,n,n,PM_STCX_SUCCESS_CMPL,Number of stcx instructions that completed successfully ##000000C8BC Number of stcx instructions that completed successfully #214,u,g,n,n,n,PM_LSU0_LDMX_FIN,New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): "The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region." This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56]). ##000000D088 New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): "The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region." This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56]). #215,u,g,n,n,n,PM_LSU1_LDMX_FIN,New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): "The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region." This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56]). ##000000D888 New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): "The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region." This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56]). #216,u,g,n,n,n,PM_LSU2_LDMX_FIN,New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): "The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region." This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56]). ##000000D08C New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): "The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region." This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56]). #217,u,g,n,n,n,PM_LSU3_LDMX_FIN,New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): "The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region." This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56]). ##000000D88C New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): "The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region." This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56]). #218,u,g,n,n,n,PM_LS0_DC_COLLISIONS,Read-write data cache collisions ##000000D090 Read-write data cache collisions #219,u,g,n,n,n,PM_LS1_DC_COLLISIONS,Read-write data cache collisions ##000000D890 Read-write data cache collisions #220,u,g,n,n,n,PM_LS2_DC_COLLISIONS,Read-write data cache collisions ##000000D094 Read-write data cache collisions #221,u,g,n,n,n,PM_LS3_DC_COLLISIONS,Read-write data cache collisions ##000000D894 Read-write data cache collisions #222,u,g,n,n,n,PM_LSU_FLUSH_ATOMIC,Quad-word loads (lq) are considered atomic because they always span at least 2 slices. If a snoop or store from another thread changes the data the load is accessing between the 2 or 3 pieces of the lq instruction, the lq will be flushed ##000000D198 Quad-word loads (lq) are considered atomic because they always span at least 2 slices. If a snoop or store from another thread changes the data the load is accessing between the 2 or 3 pieces of the lq instruction, the lq will be flushed #223,u,g,n,n,n,PM_LSU_FLUSH_EMSH,An ERAT miss was detected after a set-p hit. Erat tracker indicates fail due to tlbmiss and the instruction gets flushed because the instruction was working on the wrong address ##000000D998 An ERAT miss was detected after a set-p hit. Erat tracker indicates fail due to tlbmiss and the instruction gets flushed because the instruction was working on the wrong address #224,u,g,n,n,n,PM_LSU_FLUSH_RELAUNCH_MISS,If a load that has already returned data and has to relaunch for any reason then gets a miss (erat, setp, data cache), it will often be flushed at relaunch time because the data might be inconsistent ##000000D19C If a load that has already returned data and has to relaunch for any reason then gets a miss (erat, setp, data cache), it will often be flushed at relaunch time because the data might be inconsistent #225,u,g,n,n,n,PM_LSU_FLUSH_UE,Correctable ECC error on reload data, reported at critical data forward time ##000000D99C Correctable ECC error on reload data, reported at critical data forward time #226,u,g,n,n,n,PM_LSU_FLUSH_LHS,Effective Address alias flush : no EA match but Real Address match. If the data has not yet been returned for this load, the instruction will just be rejected, but if it has returned data, it will be flushed ##000000D1A0 Effective Address alias flush : no EA match but Real Address match. If the data has not yet been returned for this load, the instruction will just be rejected, but if it has returned data, it will be flushed #227,u,g,n,n,n,PM_LSU_FLUSH_LHL_SHL,The instruction was flushed because of a sequential load/store consistency. If a load or store hits on an older load that has either been snooped (for loads) or has stale data (for stores). ##000000D9A0 The instruction was flushed because of a sequential load/store consistency. If a load or store hits on an older load that has either been snooped (for loads) or has stale data (for stores). #228,u,g,n,n,n,PM_LSU_FLUSH_SAO,A load-hit-load condition with Strong Address Ordering will have address compare disabled and flush ##000000D1A4 A load-hit-load condition with Strong Address Ordering will have address compare disabled and flush #229,u,g,n,n,n,PM_LSU_FLUSH_LARX_STCX,A larx is flushed because an older larx has an LMQ reservation for the same thread. A stcx is flushed because an older stcx is in the LMQ. The flush happens when the older larx/stcx relaunches ##000000D9A4 A larx is flushed because an older larx has an LMQ reservation for the same thread. A stcx is flushed because an older stcx is in the LMQ. The flush happens when the older larx/stcx relaunches #230,u,g,n,n,n,PM_DSLB_MISS,Data SLB Miss - Total of all segment sizes ##000000D0A8 Data SLB Miss - Total of all segment sizes #231,u,g,n,n,n,PM_ISLB_MISS,Instruction SLB Miss - Total of all segment sizes ##000000D8A8 Instruction SLB Miss - Total of all segment sizes #232,u,g,n,n,n,PM_SRQ_SYNC_CYC,A sync is in the S2Q (edge detect to count) ##000000D0AC A sync is in the S2Q (edge detect to count) #233,u,g,n,n,n,PM_LWSYNC, ##000000D8AC #234,u,g,n,n,n,PM_HWSYNC, ##000000D0B0 #235,u,g,n,n,n,PM_PTESYNC, ##000000D8B0 #236,u,g,n,n,n,PM_LSU0_SRQ_S0_VALID_CYC,Slot 0 of SRQ valid ##000000D0B4 Slot 0 of SRQ valid #237,u,g,n,n,n,PM_LSU0_LRQ_S0_VALID_CYC,Slot 0 of LRQ valid ##000000D8B4 Slot 0 of LRQ valid #238,u,g,n,s,n,PM_LSU_LMQ_FULL_CYC,Counts the number of cycles the LMQ is full ##000000D0B8 Counts the number of cycles the LMQ is full #239,u,g,n,n,n,PM_LSU0_LMQ_S0_VALID,Slot 0 of LMQ valid ##000000D8B8 Slot 0 of LMQ valid #240,u,g,n,s,n,PM_LSU0_1_LRQF_FULL_CYC,Counts the number of cycles the LRQF is full. LRQF is the queue that holds loads between finish and completion. If it fills up, instructions stay in LRQ until completion, potentially backing up the LRQ ##000000D0BC Counts the number of cycles the LRQF is full. LRQF is the queue that holds loads between finish and completion. If it fills up, instructions stay in LRQ until completion, potentially backing up the LRQ #241,u,g,n,s,n,PM_LSU2_3_LRQF_FULL_CYC,Counts the number of cycles the LRQF is full. LRQF is the queue that holds loads between finish and completion. If it fills up, instructions stay in LRQ until completion, potentially backing up the LRQ ##000000D8BC Counts the number of cycles the LRQF is full. LRQF is the queue that holds loads between finish and completion. If it fills up, instructions stay in LRQ until completion, potentially backing up the LRQ #242,u,g,n,s,n,PM_S2Q_FULL,Cycles during which the S2Q is full ##000000E080 Cycles during which the S2Q is full #243,u,g,n,n,n,PM_L1_SW_PREF,Software L1 Prefetches, including SW Transient Prefetches ##000000E880 Software L1 Prefetches, including SW Transient Prefetches #244,u,g,n,n,n,PM_LS0_ERAT_MISS_PREF,LS0 Erat miss due to prefetch ##000000E084 LS0 Erat miss due to prefetch #245,u,g,n,n,n,PM_LS1_ERAT_MISS_PREF,LS1 Erat miss due to prefetch ##000000E884 LS1 Erat miss due to prefetch #246,u,g,n,n,n,PM_LS2_ERAT_MISS_PREF,LS0 Erat miss due to prefetch ##000000E088 LS0 Erat miss due to prefetch #247,u,g,n,n,n,PM_LS3_ERAT_MISS_PREF,LS1 Erat miss due to prefetch ##000000E888 LS1 Erat miss due to prefetch #248,u,g,n,n,n,PM_LSU0_ERAT_HIT,Primary ERAT hit. There is no secondary ERAT ##000000E08C Primary ERAT hit. There is no secondary ERAT #249,u,g,n,n,n,PM_LSU1_ERAT_HIT,Primary ERAT hit. There is no secondary ERAT ##000000E88C Primary ERAT hit. There is no secondary ERAT #250,u,g,n,n,n,PM_LSU2_ERAT_HIT,Primary ERAT hit. There is no secondary ERAT ##000000E090 Primary ERAT hit. There is no secondary ERAT #251,u,g,n,n,n,PM_LSU3_ERAT_HIT,Primary ERAT hit. There is no secondary ERAT ##000000E890 Primary ERAT hit. There is no secondary ERAT #252,u,g,n,n,n,PM_LSU0_TM_L1_HIT,Load tm hit in L1 ##000000E094 Load tm hit in L1 #253,u,g,n,n,n,PM_LSU1_TM_L1_HIT,Load tm hit in L1 ##000000E894 Load tm hit in L1 #254,u,g,n,n,n,PM_LSU2_TM_L1_HIT,Load tm hit in L1 ##000000E098 Load tm hit in L1 #255,u,g,n,n,n,PM_LSU3_TM_L1_HIT,Load tm hit in L1 ##000000E898 Load tm hit in L1 #256,u,g,n,n,n,PM_LSU0_TM_L1_MISS,Load tm L1 miss ##000000E09C Load tm L1 miss #257,u,g,n,n,n,PM_LSU1_TM_L1_MISS,Load tm L1 miss ##000000E89C Load tm L1 miss #258,u,g,n,n,n,PM_LSU2_TM_L1_MISS,Load tm L1 miss ##000000E0A0 Load tm L1 miss #259,u,g,n,n,n,PM_LSU3_TM_L1_MISS,Load tm L1 miss ##000000E8A0 Load tm L1 miss #260,u,g,n,n,n,PM_TMA_REQ_L2, addrs only req to L2 only on the first one,Indication that Load footprint is not expanding ##000000E0A4 addrs only req to L2 only on the first one,Indication that Load footprint is not expanding #261,u,g,n,n,n,PM_TM_FAIL_TLBIE,Transaction failed because there was a TLBIE hit in the bloom filter ##000000E0AC Transaction failed because there was a TLBIE hit in the bloom filter #262,u,g,n,n,n,PM_TM_FAIL_TX_CONFLICT,Transactional conflict from LSU, gets reported to TEXASR ##000000E8AC Transactional conflict from LSU, gets reported to TEXASR #263,u,g,n,n,n,PM_TM_FAIL_NON_TX_CONFLICT,Non transactional conflict from LSU, gets reported to TEXASR ##000000E0B0 Non transactional conflict from LSU, gets reported to TEXASR #264,u,g,n,n,n,PM_TEND_PEND_CYC,TEND latency per thread ##000000E8B0 TEND latency per thread #265,u,g,n,n,n,PM_LS0_TM_DISALLOW,A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it ##000000E0B4 A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it #266,u,g,n,n,n,PM_LS1_TM_DISALLOW,A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it ##000000E8B4 A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it #267,u,g,n,n,n,PM_LS2_TM_DISALLOW,A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it ##000000E0B8 A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it #268,u,g,n,n,n,PM_LS3_TM_DISALLOW,A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it ##000000E8B8 A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it #269,u,g,n,n,n,PM_LS0_PTE_TABLEWALK_CYC,Cycles when a tablewalk is pending on this thread on table 0 ##000000E0BC Cycles when a tablewalk is pending on this thread on table 0 #270,u,g,n,n,n,PM_LS1_PTE_TABLEWALK_CYC,Cycles when a tablewalk is pending on this thread on table 1 ##000000E8BC Cycles when a tablewalk is pending on this thread on table 1 #271,u,g,n,n,n,PM_LSU_STCX_FAIL, ##000000F080 #272,u,g,n,s,n,PM_SNOOP_TLBIE,TLBIE snoop ##000000F880 TLBIE snoop #273,u,g,n,n,n,PM_PTE_PREFETCH,PTE prefetches ##000000F084 PTE prefetches #274,u,g,n,n,n,PM_TABLEWALK_CYC_PREF,tablewalk qualified for pte prefetches ##000000F884 tablewalk qualified for pte prefetches #275,u,g,n,n,n,PM_LSU0_STORE_REJECT,All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met ##000000F088 All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met #276,u,g,n,n,n,PM_LSU1_STORE_REJECT,All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met ##000000F888 All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met #277,u,g,n,n,n,PM_LSU2_STORE_REJECT,All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met ##000000F08C All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met #278,u,g,n,n,n,PM_LSU3_STORE_REJECT,All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met ##000000F88C All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met #279,u,g,n,n,n,PM_LSU0_L1_CAM_CANCEL,ls0 l1 tm cam cancel ##000000F090 ls0 l1 tm cam cancel #280,u,g,n,n,n,PM_LSU1_L1_CAM_CANCEL,ls1 l1 tm cam cancel ##000000F890 ls1 l1 tm cam cancel #281,u,g,n,n,n,PM_LSU2_L1_CAM_CANCEL,ls2 l1 tm cam cancel ##000000F094 ls2 l1 tm cam cancel #282,u,g,n,n,n,PM_LSU3_L1_CAM_CANCEL,ls3 l1 tm cam cancel ##000000F894 ls3 l1 tm cam cancel #283,u,g,n,n,n,PM_XLATE_HPT_MODE,LSU reports every cycle the thread is in HPT translation mode (as opposed to radix mode) ##000000F098 LSU reports every cycle the thread is in HPT translation mode (as opposed to radix mode) #284,u,g,n,n,n,PM_XLATE_RADIX_MODE,LSU reports every cycle the thread is in radix translation mode (as opposed to HPT mode) ##000000F898 LSU reports every cycle the thread is in radix translation mode (as opposed to HPT mode) #285,u,g,n,n,n,PM_XLATE_MISS,The LSU requested a line from L2 for translation. It may be satisfied from any source beyond L2. Includes speculative instructions. Includes instruction, prefetch and demand ##000000F89C The LSU requested a line from L2 for translation. It may be satisfied from any source beyond L2. Includes speculative instructions. Includes instruction, prefetch and demand #286,u,g,n,n,n,PM_DATA_STORE,All ops that drain from s2q to L2 containing data ##000000F0A0 All ops that drain from s2q to L2 containing data #287,u,g,n,n,n,PM_NON_DATA_STORE,All ops that drain from s2q to L2 and contain no data ##000000F8A0 All ops that drain from s2q to L2 and contain no data #288,u,g,n,n,n,PM_DC_PREF_HW_ALLOC,Prefetch stream allocated by the hardware prefetch mechanism ##000000F0A4 Prefetch stream allocated by the hardware prefetch mechanism #289,u,g,n,n,n,PM_DC_PREF_SW_ALLOC,Prefetch stream allocated by software prefetching ##000000F8A4 Prefetch stream allocated by software prefetching #290,u,g,n,n,n,PM_DC_PREF_CONF,A demand load referenced a line in an active prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. Includes forwards and backwards streams ##000000F0A8 A demand load referenced a line in an active prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. Includes forwards and backwards streams #291,u,g,n,n,n,PM_DC_PREF_FUZZY_CONF,A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up) ##000000F8A8 A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up) #292,u,g,n,n,n,PM_DC_PREF_STRIDED_CONF,A demand load referenced a line in an active strided prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. ##000000F0AC A demand load referenced a line in an active strided prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. #293,u,g,n,n,n,PM_DC_DEALLOC_NO_CONF,A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up) ##000000F8AC A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up) #294,u,g,n,n,n,PM_L3_LD_PREF,L3 load prefetch, sourced from a hardware or software stream, was sent to the nest ##000000F0B0 L3 load prefetch, sourced from a hardware or software stream, was sent to the nest #295,u,g,n,n,n,PM_L3_SW_PREF,L3 load prefetch, sourced from a software prefetch stream, was sent to the nest ##000000F8B0 L3 load prefetch, sourced from a software prefetch stream, was sent to the nest #296,u,g,n,n,n,PM_DC_PREF_CONS_ALLOC,Prefetch stream allocated in the conservative phase by either the hardware prefetch mechanism or software prefetch. The sum of this pair subtracted from the total number of allocs will give the total allocs in normal phase ##000000F0B4 Prefetch stream allocated in the conservative phase by either the hardware prefetch mechanism or software prefetch. The sum of this pair subtracted from the total number of allocs will give the total allocs in normal phase #297,u,g,n,n,n,PM_DC_PREF_XCONS_ALLOC,Prefetch stream allocated in the Ultra conservative phase by either the hardware prefetch mechanism or software prefetch ##000000F8B4 Prefetch stream allocated in the Ultra conservative phase by either the hardware prefetch mechanism or software prefetch #298,u,g,n,n,n,PM_LS0_UNALIGNED_ST,Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty ##000000F0B8 Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty #299,u,g,n,n,n,PM_LS1_UNALIGNED_ST,Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty ##000000F8B8 Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty #300,u,g,n,n,n,PM_LS2_UNALIGNED_ST,Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty ##000000F0BC Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty #301,u,g,n,n,n,PM_LS3_UNALIGNED_ST,Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty ##000000F8BC Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty #302,u,g,n,n,n,PM_INST_FROM_L1,Instruction fetches from L1. L1 instruction hit ##0000004080 Instruction fetches from L1. L1 instruction hit #303,u,g,n,n,n,PM_BANK_CONFLICT,Read blocked due to interleave conflict. The ifar logic will detect an interleave conflict and kill the data that was read that cycle. ##0000004880 Read blocked due to interleave conflict. The ifar logic will detect an interleave conflict and kill the data that was read that cycle. #304,u,g,n,n,n,PM_EAT_FULL_CYC,Cycles No room in EAT ##0000004084 Cycles No room in EAT #305,u,g,n,n,n,PM_IBUF_FULL_CYC,Cycles No room in ibuff ##0000004884 Cycles No room in ibuff #306,u,g,n,n,n,PM_IC_DEMAND_REQ,Demand Instruction fetch request ##0000004088 Demand Instruction fetch request #307,u,g,n,n,n,PM_IC_PREF_REQ,Instruction prefetch requests ##0000004888 Instruction prefetch requests #308,u,g,n,n,n,PM_L1_DEMAND_WRITE,Instruction Demand sectors written into IL1 ##000000408C Instruction Demand sectors written into IL1 #309,u,g,n,n,n,PM_IC_PREF_WRITE,Instruction prefetch written into IL1 ##000000488C Instruction prefetch written into IL1 #310,u,g,n,n,n,PM_IC_PREF_CANCEL_PAGE,Prefetch Canceled due to page boundary ##0000004090 Prefetch Canceled due to page boundary #311,u,g,n,n,n,PM_IC_PREF_CANCEL_HIT,Prefetch Canceled due to icache hit ##0000004890 Prefetch Canceled due to icache hit #312,u,g,n,n,n,PM_IC_PREF_CANCEL_L2,L2 Squashed a demand or prefetch request ##0000004094 L2 Squashed a demand or prefetch request #313,u,g,n,n,n,PM_IC_RELOAD_PRIVATE,Reloading line was brought in private for a specific thread. Most lines are brought in shared for all eight threads. If RA does not match then invalidates and then brings it shared to other thread. In P7 line brought in private , then line was invalidat ##0000004894 Reloading line was brought in private for a specific thread. Most lines are brought in shared for all eight threads. If RA does not match then invalidates and then brings it shared to other thread. In P7 line brought in private , then line was invalidat #314,u,g,n,n,n,PM_IC_DEMAND_L2_BHT_REDIRECT, L2 I cache demand request due to BHT redirect, branch redirect ( 2 bubbles 3 cycles) ##0000004098 L2 I cache demand request due to BHT redirect, branch redirect ( 2 bubbles 3 cycles) #315,u,g,n,n,n,PM_IC_DEMAND_L2_BR_REDIRECT, L2 I cache demand request due to branch Mispredict ( 15 cycle path) ##0000004898 L2 I cache demand request due to branch Mispredict ( 15 cycle path) #316,u,g,n,n,n,PM_BR_PRED,Conditional Branch Executed in which the HW predicted the Direction or Target. Includes taken and not taken and is counted at execution time ##000000409C Conditional Branch Executed in which the HW predicted the Direction or Target. Includes taken and not taken and is counted at execution time #317,u,g,n,n,n,PM_BR_CORECT_PRED_TAKEN_CMPL,Conditional Branch Completed in which the HW correctly predicted the direction as taken. Counted at completion time ##000000489C Conditional Branch Completed in which the HW correctly predicted the direction as taken. Counted at completion time #318,u,g,n,n,n,PM_BR_UNCOND,Unconditional Branch Completed. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was covenrted to a Resolve. ##00000040A0 Unconditional Branch Completed. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was covenrted to a Resolve. #319,u,g,n,n,n,PM_BR_PRED_PCACHE,Conditional branch completed that used pattern cache prediction ##00000048A0 Conditional branch completed that used pattern cache prediction #320,u,g,n,n,n,PM_BR_PRED_CCACHE,Conditional Branch Completed that used the Count Cache for Target Prediction ##00000040A4 Conditional Branch Completed that used the Count Cache for Target Prediction #321,u,g,n,n,n,PM_STOP_FETCH_PENDING_CYC,Fetching is stopped due to an incoming instruction that will result in a flush ##00000048A4 Fetching is stopped due to an incoming instruction that will result in a flush #322,u,g,n,n,n,PM_BR_PRED_LSTACK,Conditional Branch Completed that used the Link Stack for Target Prediction ##00000040A8 Conditional Branch Completed that used the Link Stack for Target Prediction #323,u,g,n,n,n,PM_DECODE_FUSION_LD_ST_DISP,32-bit displacement D-form and 16-bit displacement X-form ##00000048A8 32-bit displacement D-form and 16-bit displacement X-form #324,u,g,n,n,n,PM_BR_MPRED_CCACHE,Conditional Branch Completed that was Mispredicted due to the Count Cache Target Prediction ##00000040AC Conditional Branch Completed that was Mispredicted due to the Count Cache Target Prediction #325,u,g,n,n,n,PM_BR_MPRED_LSTACK,Conditional Branch Completed that was Mispredicted due to the Link Stack Target Prediction ##00000048AC Conditional Branch Completed that was Mispredicted due to the Link Stack Target Prediction #326,u,g,n,n,n,PM_BR_PRED_TAKEN_CR,Conditional Branch that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and branches ##00000040B0 Conditional Branch that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and branches #327,u,g,n,n,n,PM_BR_MPRED_PCACHE,Conditional Branch Completed that was Mispredicted due to pattern cache prediction ##00000048B0 Conditional Branch Completed that was Mispredicted due to pattern cache prediction #328,u,g,n,n,n,PM_BR_PRED_TA,Conditional Branch Completed that had its target address predicted. Only XL-form branches set this event. This equal the sum of CCACHE, LSTACK, and PCACHE ##00000040B4 Conditional Branch Completed that had its target address predicted. Only XL-form branches set this event. This equal the sum of CCACHE, LSTACK, and PCACHE #329,u,g,n,n,n,PM_DECODE_FUSION_CONST_GEN,32-bit constant generation ##00000048B4 32-bit constant generation #330,u,g,n,n,n,PM_BR_MPRED_TAKEN_CR,A Conditional Branch that resolved to taken was mispredicted as not taken (due to the BHT Direction Prediction). ##00000040B8 A Conditional Branch that resolved to taken was mispredicted as not taken (due to the BHT Direction Prediction). #331,u,g,n,n,n,PM_BR_MPRED_TAKEN_TA,Conditional Branch Completed that was Mispredicted due to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that resolved Taken set this event. ##00000048B8 Conditional Branch Completed that was Mispredicted due to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that resolved Taken set this event. #332,u,g,n,n,n,PM_THRD_PRIO_0_1_CYC, Cycles thread running at priority level 0 or 1 ##00000040BC Cycles thread running at priority level 0 or 1 #333,u,g,n,n,n,PM_THRD_PRIO_2_3_CYC, Cycles thread running at priority level 2 or 3 ##00000048BC Cycles thread running at priority level 2 or 3 #334,u,g,n,n,n,PM_THRD_PRIO_4_5_CYC, Cycles thread running at priority level 4 or 5 ##0000005080 Cycles thread running at priority level 4 or 5 #335,u,g,n,n,n,PM_THRD_PRIO_6_7_CYC, Cycles thread running at priority level 6 or 7 ##0000005880 Cycles thread running at priority level 6 or 7 #336,u,g,n,n,n,PM_IC_INVALIDATE,Ic line invalidated ##0000005888 Ic line invalidated #337,u,g,n,n,n,PM_SHL_CREATED,Store-Hit-Load Table Entry Created ##000000508C Store-Hit-Load Table Entry Created #338,u,g,n,n,n,PM_SHL_ST_DEP_CREATED,Store-Hit-Load Table Read Hit with entry Enabled ##000000588C Store-Hit-Load Table Read Hit with entry Enabled #339,u,g,n,n,n,PM_IC_MISS_ICBI,threaded version, IC Misses where we got EA dir hit but no sector valids were on. ICBI took line out ##0000005094 threaded version, IC Misses where we got EA dir hit but no sector valids were on. ICBI took line out #340,u,g,n,n,n,PM_LINK_STACK_WRONG_ADD_PRED,Link stack predicts wrong address, because of link stack design limitation or software violating the coding conventions ##0000005098 Link stack predicts wrong address, because of link stack design limitation or software violating the coding conventions #341,u,g,n,n,n,PM_LINK_STACK_INVALID_PTR,It is most often caused by certain types of flush where the pointer is not available. Can result in the data in the link stack becoming unusable. ##0000005898 It is most often caused by certain types of flush where the pointer is not available. Can result in the data in the link stack becoming unusable. #342,u,g,n,n,n,PM_LINK_STACK_CORRECT,Link stack predicts right address ##00000058A0 Link stack predicts right address #343,u,g,n,n,n,PM_FLUSH_MPRED,Branch mispredict flushes. Includes target and address misprecition ##00000050A4 Branch mispredict flushes. Includes target and address misprecition #344,u,g,n,n,n,PM_FLUSH_LSU,LSU flushes. Includes all lsu flushes ##00000058A4 LSU flushes. Includes all lsu flushes #345,u,g,n,n,n,PM_EAT_FORCE_MISPRED,XL-form branch was mispredicted due to the predicted target address missing from EAT. The EAT forces a mispredict in this case since there is no predicated target to validate. This is a rare case that may occur when the EAT is full and a branch is issued ##00000050A8 XL-form branch was mispredicted due to the predicted target address missing from EAT. The EAT forces a mispredict in this case since there is no predicated target to validate. This is a rare case that may occur when the EAT is full and a branch is issued #346,u,g,n,n,n,PM_DECODE_HOLD_ICT_FULL,Counts the number of cycles in which the IFU was not able to decode and transmit one or more instructions because all itags were in use. This means the ICT is full for this thread ##00000058A8 Counts the number of cycles in which the IFU was not able to decode and transmit one or more instructions because all itags were in use. This means the ICT is full for this thread #347,u,g,n,n,n,PM_BTAC_BAD_RESULT,BTAC thinks branch will be taken but it is either predicted not-taken by the BHT, or the target address is wrong (less common). In both cases, a redirect will happen ##00000050B0 BTAC thinks branch will be taken but it is either predicted not-taken by the BHT, or the target address is wrong (less common). In both cases, a redirect will happen #348,u,g,n,n,n,PM_BTAC_GOOD_RESULT,BTAC predicts a taken branch and the BHT agrees, and the target address is correct ##00000058B0 BTAC predicts a taken branch and the BHT agrees, and the target address is correct #349,u,g,n,n,n,PM_TAGE_CORRECT_TAKEN_CMPL,The TAGE overrode BHT direction prediction and it was correct. Counted at completion for taken branches only ##00000050B4 The TAGE overrode BHT direction prediction and it was correct. Counted at completion for taken branches only #350,u,g,n,n,n,PM_TAGE_CORRECT,The TAGE overrode BHT direction prediction and it was correct. Includes taken and not taken and is counted at execution time ##00000058B4 The TAGE overrode BHT direction prediction and it was correct. Includes taken and not taken and is counted at execution time #351,u,g,n,n,n,PM_TAGE_OVERRIDE_WRONG,The TAGE overrode BHT direction prediction but it was incorrect. Counted at completion for taken branches only ##00000050B8 The TAGE overrode BHT direction prediction but it was incorrect. Counted at completion for taken branches only #352,u,g,n,n,n,PM_TAGE_OVERRIDE_WRONG_SPEC,The TAGE overrode BHT direction prediction and it was correct. Includes taken and not taken and is counted at execution time ##00000058B8 The TAGE overrode BHT direction prediction and it was correct. Includes taken and not taken and is counted at execution time #353,u,g,n,s,n,PM_L3_PF_ON_CHIP_MEM,L3 PF from On chip memory ##00000460A0 L3 PF from On chip memory #354,u,g,n,s,n,PM_L3_PF_OFF_CHIP_MEM,L3 PF from Off chip memory ##00000468A0 L3 PF from Off chip memory #355,u,g,n,s,n,PM_L3_LAT_CI_HIT,L3 Lateral Castins Hit ##00000460A2 L3 Lateral Castins Hit #356,u,g,n,s,n,PM_L3_LAT_CI_MISS,L3 Lateral Castins Miss ##00000468A2 L3 Lateral Castins Miss #357,u,g,n,n,n,PM_L3_TRANS_PF,L3 Transient prefetch received from L2 ##00000468A4 L3 Transient prefetch received from L2 #358,u,g,n,n,n,PM_RD_FORMING_SC,Doesn't occur ##00000460A6 Doesn't occur #359,u,g,n,n,n,PM_RD_CLEARING_SC,Core TM load hits line in L3 in TM_SC state and causes it to be invalidated ##00000468A6 Core TM load hits line in L3 in TM_SC state and causes it to be invalidated #360,u,g,n,n,n,PM_SN_HIT,Any port snooper hit L3. Up to 4 can happen in a cycle but we only count 1 ##00000460A8 Any port snooper hit L3. Up to 4 can happen in a cycle but we only count 1 #361,u,g,n,n,n,PM_SN_MISS,Any port snooper L3 miss or collision. Up to 4 can happen in a cycle but we only count 1 ##00000468A8 Any port snooper L3 miss or collision. Up to 4 can happen in a cycle but we only count 1 #362,u,g,n,s,n,PM_L3_P0_CO_L31,L3 CO to L3.1 (LCO) port 0 with or without data ##00000460AA L3 CO to L3.1 (LCO) port 0 with or without data #363,u,g,n,s,n,PM_L3_P1_CO_L31,L3 CO to L3.1 (LCO) port 1 with or without data ##00000468AA L3 CO to L3.1 (LCO) port 1 with or without data #364,u,g,n,s,n,PM_L3_SN0_BUSY,Lifetime, sample of snooper machine 0 valid ##00000460AC Lifetime, sample of snooper machine 0 valid #365,u,g,n,s,n,PM_L3_CO0_BUSY,Lifetime, sample of CO machine 0 valid ##00000468AC Lifetime, sample of CO machine 0 valid #366,u,g,n,n,n,PM_L3_P2_CO_RTY,L3 CO received retry port 2 (memory only), every retry counted ##00000460AE L3 CO received retry port 2 (memory only), every retry counted #367,u,g,n,n,n,PM_L3_P3_CO_RTY,L3 CO received retry port 3 (memory only), every retry counted ##00000468AE L3 CO received retry port 3 (memory only), every retry counted #368,u,g,n,s,n,PM_L3_SYS_GUESS_WRONG,Prefetch scope predictor selected VGS or RNS, but was wrong ##00000460B2 Prefetch scope predictor selected VGS or RNS, but was wrong #369,u,g,n,s,n,PM_L3_PF0_BUSY,Lifetime, sample of PF machine 0 valid ##00000460B4 Lifetime, sample of PF machine 0 valid #370,u,g,n,s,n,PM_L3_RD0_BUSY,Lifetime, sample of RD machine 0 valid ##00000468B4 Lifetime, sample of RD machine 0 valid #371,u,g,n,n,n,PM_L2_DISP_ALL_L2MISS, All successful D-side-Ld/St or I-side-instruction-fetch dispatches for this thread that were an L2 miss ##0000046080 All successful D-side-Ld/St or I-side-instruction-fetch dispatches for this thread that were an L2 miss #372,u,g,n,n,n,PM_ISIDE_MRU_TOUCH,I-side L2 MRU touch sent to L2 for this thread I-side L2 MRU touch commands sent to the L2 for this thread ##0000046880 I-side L2 MRU touch sent to L2 for this thread I-side L2 MRU touch commands sent to the L2 for this thread #373,u,g,n,n,n,PM_L2_ST_DISP,All successful D-side store dispatches for this thread ##0000046082 All successful D-side store dispatches for this thread #374,u,g,n,n,n,PM_L2_ST_HIT,All successful D-side store dispatches for this thread that were L2 hits ##0000046882 All successful D-side store dispatches for this thread that were L2 hits #375,u,g,n,n,n,PM_L2_RCST_DISP_FAIL_OTHER,All D-side store dispatch attempts for this thread that failed due to reason other than address collision ##0000046084 All D-side store dispatch attempts for this thread that failed due to reason other than address collision #376,u,g,n,s,n,PM_L2_SN_M_RD_DONE,Snoop dispatched for a read and was M (true M) ##0000046086 Snoop dispatched for a read and was M (true M) #377,u,g,n,s,n,PM_L2_SN_M_WR_DONE, Snoop dispatched for a store and was M (true M) ##0000046886 Snoop dispatched for a store and was M (true M) #378,u,g,n,s,n,PM_L2_CHIP_PUMP,RC requests that were local (aka chip) pump attempts ##0000046088 RC requests that were local (aka chip) pump attempts #379,u,g,n,s,n,PM_L2_GROUP_PUMP,RC requests that were on group (aka nodel) pump attempts ##0000046888 RC requests that were on group (aka nodel) pump attempts #380,u,g,n,s,n,PM_L2_SYS_PUMP,RC requests that were system pump attempts ##000004688A RC requests that were system pump attempts #381,u,g,n,s,n,PM_CO0_BUSY,CO mach 0 Busy. Used by PMU to sample ave CO lifetime (mach0 used as sample point) ##000004608C CO mach 0 Busy. Used by PMU to sample ave CO lifetime (mach0 used as sample point) #382,u,g,n,s,n,PM_TM_CAP_OVERFLOW,TM Footprint Capacity Overflow ##000004608E TM Footprint Capacity Overflow #383,u,g,n,n,n,PM_L2_INST_MISS, All successful I-side-instruction-fetch (e.g. i-dem, i-pref) dispatches for this thread that were an L2 miss ##000004609E All successful I-side-instruction-fetch (e.g. i-dem, i-pref) dispatches for this thread that were an L2 miss #384,u,g,n,s,n,PM_L2_RTY_ST,RC retries on PB for any store from core (excludes DCBFs) ##000004689E RC retries on PB for any store from core (excludes DCBFs) $$$$$$$$ { counter 5} #0,u,g,n,n,n,PM_RUN_INST_CMPL,Run_Instructions ##0000000 Number of run instructions completed $$$$$$$$ { counter 6} #0,u,g,n,n,n,PM_RUN_CYC,Run_cycles ##0000000 Processor cycle gated by the run latch