{ IBM_PROLOG_BEGIN_TAG { This is an automatically generated prolog. { { bos720 src/bos/usr/sbin/perf/pmapi/events/POWER8.evs 1.7 { { Licensed Materials - Property of IBM { { Restricted Materials of IBM { { COPYRIGHT International Business Machines Corp. 2013,2014 { All Rights Reserved { { US Government Users Restricted Rights - Use, duplication or { disclosure restricted by GSA ADP Schedule Contract with IBM Corp. { { IBM_PROLOG_END_TAG 506,495,487,499,1,1 { counter 1 } #0,u,g,n,s,n,PM_1LPAR_CYC,Number of cycles in single lpar mode. All threads in the core are assigned to the same lpar ##000001F05E Number of cycles in single lpar mode. #1,v,g,n,n,n,PM_1PLUS_PPC_CMPL,1 or more ppc insts finished ##00000100F2 1 or more ppc insts finished (completed). #2,u,g,n,n,n,PM_ALL_CHIP_PUMP_CPRED,Initial and Final Pump Scope was chip pump (prediction=correct) for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate) ##0000610050 Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for all data types ( demand load,data,inst prefetch,inst fetch,xlate (I or d) #3,u,g,n,n,n,PM_ALL_GRP_PUMP_MPRED_RTY,Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate) ##0000610052 Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) #4,u,g,n,n,n,PM_ALL_PUMP_CPRED,Pump prediction correct. Counts across all types of pumps for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate) ##0000610054 Pump prediction correct. Counts across all types of pumpsfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) #5,v,g,n,n,n,PM_ANY_THRD_RUN_CYC,One of threads in run_cycles ##00000100FA Any thread in run_cycles (was one thread in run_cycles). #6,u,g,n,n,n,PM_BANK_CONFLICT,Read blocked due to interleave conflict. The ifar logic will detect an interleave conflict and kill the data that was read that cycle. ##0000004082 Read blocked due to interleave conflict. The ifar logic will detect an interleave conflict and kill the data that was read that cycle. #7,v,g,n,n,n,PM_BR_BC_8,Pairable BC+8 branch that has not been converted to a Resolve Finished in the BRU pipeline ##0000005086 Pairable BC+8 branch that has not been converted to a Resolve Finished in the BRU pipeline #8,v,g,n,n,n,PM_BR_BC_8_CONV,Pairable BC+8 branch that was converted to a Resolve Finished in the BRU pipeline. ##0000005084 Pairable BC+8 branch that was converted to a Resolve Finished in the BRU pipeline. #9,v,g,n,n,n,PM_BR_MPRED_CCACHE,Conditional Branch Completed that was Mispredicted due to the Count Cache Target Prediction ##00000040AC Conditional Branch Completed that was Mispredicted due to the Count Cache Target Prediction #10,v,g,n,n,n,PM_BR_MPRED_CR,Conditional Branch Completed that was Mispredicted due to the BHT Direction Prediction (taken/not taken). ##00000040B8 Conditional Branch Completed that was Mispredicted due to the BHT Direction Prediction (taken/not taken). #11,u,g,n,n,n,PM_BR_MPRED_LSTACK,Conditional Branch Completed that was Mispredicted due to the Link Stack Target Prediction ##00000040AE Conditional Branch Completed that was Mispredicted due to the Link Stack Target Prediction #12,u,g,n,n,n,PM_BR_MPRED_TA,Conditional Branch Completed that was Mispredicted due to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that resolved Taken set this event. ##00000040BA Conditional Branch Completed that was Mispredicted due to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that resolved Taken set this event. #13,v,g,n,n,m,PM_BR_MRK_2PATH,marked two path branch ##0000010138 marked two path branch. #14,v,g,n,n,n,PM_BR_PRED_BR0,Conditional Branch Completed on BR0 (1st branch in group) in which the HW predicted the Direction or Target ##000000409C Conditional Branch Completed on BR0 (1st branch in group) in which the HW predicted the Direction or Target #15,v,g,n,n,n,PM_BR_PRED_BR1,Conditional Branch Completed on BR1 (2nd branch in group) in which the HW predicted the Direction or Target. Note: BR1 can only be used in Single Thread Mode. In all of the SMT modes, only one branch can complete, thus BR1 is unused. ##000000409E Conditional Branch Completed on BR1 (2nd branch in group) in which the HW predicted the Direction or Target. Note: BR1 can only be used in Single Thread Mode. In all of the SMT modes, only one branch can complete, thus BR1 is unused. #16,u,g,n,n,n,PM_BR_PRED_BR_CMPL,Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred(0) OR if_pc_br0_br_pred(1). ##000000489C IFU #17,v,g,n,n,n,PM_BR_PRED_CCACHE_BR0,Conditional Branch Completed on BR0 that used the Count Cache for Target Prediction ##00000040A4 Conditional Branch Completed on BR0 that used the Count Cache for Target Prediction #18,v,g,n,n,n,PM_BR_PRED_CCACHE_BR1,Conditional Branch Completed on BR1 that used the Count Cache for Target Prediction ##00000040A6 Conditional Branch Completed on BR1 that used the Count Cache for Target Prediction #19,u,g,n,n,n,PM_BR_PRED_CCACHE_CMPL,Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred(0) AND if_pc_br0_pred_type. ##00000048A4 IFU #20,v,g,n,n,n,PM_BR_PRED_CR_BR0,Conditional Branch Completed on BR0 that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and branches ##00000040B0 Conditional Branch Completed on BR0 that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and bra #21,v,g,n,n,n,PM_BR_PRED_CR_BR1,Conditional Branch Completed on BR1 that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and branches ##00000040B2 Conditional Branch Completed on BR1 that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and bra #22,u,g,n,n,n,PM_BR_PRED_CR_CMPL,Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred(1)='1'. ##00000048B0 IFU #23,u,g,n,n,n,PM_BR_PRED_LSTACK_BR0,Conditional Branch Completed on BR0 that used the Link Stack for Target Prediction ##00000040A8 Conditional Branch Completed on BR0 that used the Link Stack for Target Prediction #24,u,g,n,n,n,PM_BR_PRED_LSTACK_BR1,Conditional Branch Completed on BR1 that used the Link Stack for Target Prediction ##00000040AA Conditional Branch Completed on BR1 that used the Link Stack for Target Prediction #25,u,g,n,n,n,PM_BR_PRED_LSTACK_CMPL,Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred(0) AND (not if_pc_br0_pred_type). ##00000048A8 IFU #26,u,g,n,n,n,PM_BR_PRED_TA_BR0,Conditional Branch Completed on BR0 that had its target address predicted. Only XL-form branches set this event. ##00000040B4 Conditional Branch Completed on BR0 that had its target address predicted. Only XL-form branches set this event. #27,u,g,n,n,n,PM_BR_PRED_TA_BR1,Conditional Branch Completed on BR1 that had its target address predicted. Only XL-form branches set this event. ##00000040B6 Conditional Branch Completed on BR1 that had its target address predicted. Only XL-form branches set this event. #28,u,g,n,n,n,PM_BR_PRED_TA_CMPL,Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred(0)='1'. ##00000048B4 IFU #29,v,g,n,n,n,PM_BRU_FIN,Branch Instruction Finished ##0000010068 Branch Instruction Finished . #30,v,g,n,n,n,PM_BR_UNCOND_BR0,Unconditional Branch Completed on BR0. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was coverted to a Resolve. ##00000040A0 Unconditional Branch Completed on BR0. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was coverted to a Resolve. #31,v,g,n,n,n,PM_BR_UNCOND_BR1,Unconditional Branch Completed on BR1. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was coverted to a Resolve. ##00000040A2 Unconditional Branch Completed on BR1. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was coverted to a Resolve. #32,u,g,n,n,n,PM_BR_UNCOND_CMPL,Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred=00 AND if_pc_br0_completed. ##00000048A0 IFU #33,v,g,n,s,n,PM_CASTOUT_ISSUED,Castouts issued ##0000003094 Castouts issued #34,v,g,n,s,n,PM_CASTOUT_ISSUED_GPR,Castouts issued GPR ##0000003096 Castouts issued GPR #35,u,g,n,n,n,PM_CHIP_PUMP_CPRED,Initial and Final Pump Scope was chip pump (prediction=correct) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) ##0000010050 Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for all data types ( demand load,data,inst prefetch,inst fetch,xlate (I or d). #36,u,g,n,n,n,PM_CLB_HELD,CLB Hold: Any Reason ##0000002090 CLB Hold: Any Reason #37,v,g,n,n,n,PM_CMPLU_STALL,Completion stall ##000001E054 Completion stall. #38,v,g,n,n,n,PM_CMPLU_STALL_LWSYNC,completion stall due to isync/lwsync ##0000010036 completion stall due to isync/lwsync. #39,u,g,n,n,n,PM_CMPLU_STALL_THRD,Completion Stalled due to thread conflict. Group ready to complete but it was another thread's turn ##000001001C Completion stall due to thread conflict. #40,u,g,n,n,n,PM_CO0_ALLOC,CO mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point) ##0000016083 0.0 #41,v,g,n,s,n,PM_CO0_BUSY,CO mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point) ##0000016082 CO mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point) #42,u,g,n,s,n,PM_CO_DISP_FAIL,CO dispatch failed due to all CO machines being busy ##0000517082 CO dispatch failed due to all CO machines being busy #43,v,g,n,n,n,PM_CYC,Cycles ##000001001E Cycles . #44,u,g,n,n,n,PM_DATA_ALL_CHIP_PUMP_CPRED,Initial and Final Pump Scope was chip pump (prediction=correct) for either demand loads or data prefetch ##000061C050 Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for a demand load #45,u,g,n,n,n,PM_DATA_ALL_FROM_L2,The processor's data cache was reloaded from local core's L2 due to either demand loads or data prefetch ##000061C042 The processor's data cache was reloaded from local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 #46,u,g,n,n,n,PM_DATA_ALL_FROM_L2MISS_MOD,The processor's data cache was reloaded from a localtion other than the local core's L2 due to either demand loads or data prefetch ##000061C04E The processor's data cache was reloaded from a localtion other than the local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 #47,u,g,n,n,n,PM_DATA_ALL_FROM_L2_NO_CONFLICT,The processor's data cache was reloaded from local core's L2 without conflict due to either demand loads or data prefetch ##000061C040 The processor's data cache was reloaded from local core's L2 without conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 #48,u,g,n,n,n,PM_DATA_ALL_FROM_L31_SHR,The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to either demand loads or data prefetch ##000061C046 The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 #49,u,g,n,n,n,PM_DATA_ALL_FROM_L3_NO_CONFLICT,The processor's data cache was reloaded from local core's L3 without conflict due to either demand loads or data prefetch ##000061C044 The processor's data cache was reloaded from local core's L3 without conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 #50,u,g,n,n,n,PM_DATA_ALL_FROM_LL4,The processor's data cache was reloaded from the local chip's L4 cache due to either demand loads or data prefetch ##000061C04C The processor's data cache was reloaded from the local chip's L4 cache due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 #51,u,g,n,n,n,PM_DATA_ALL_FROM_ON_CHIP_CACHE,The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to either demand loads or data prefetch ##000061C048 The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 #52,u,g,n,n,n,PM_DATA_ALL_FROM_RL2L3_SHR,The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either demand loads or data prefetch ##000061C04A The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 #53,u,g,n,n,n,PM_DATA_ALL_GRP_PUMP_MPRED_RTY,Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for either demand loads or data prefetch ##000061C052 Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor a demand load #54,u,g,n,n,n,PM_DATA_ALL_PUMP_CPRED,Pump prediction correct. Counts across all types of pumps for either demand loads or data prefetch ##000061C054 Pump prediction correct. Counts across all types of pumps for a demand load #55,u,g,n,n,n,PM_DATA_CHIP_PUMP_CPRED,Initial and Final Pump Scope was chip pump (prediction=correct) for a demand load ##000001C050 Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for a demand load. #56,v,g,n,n,n,PM_DATA_FROM_L2,The processor's data cache was reloaded from local core's L2 due to a demand load ##000001C042 The processor's data cache was reloaded from local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. #57,v,g,n,n,n,PM_DATA_FROM_L2MISS_MOD,The processor's data cache was reloaded from a localtion other than the local core's L2 due to a demand load ##000001C04E The processor's data cache was reloaded from a localtion other than the local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. #58,v,g,n,n,n,PM_DATA_FROM_L2_NO_CONFLICT,The processor's data cache was reloaded from local core's L2 without conflict due to a demand load ##000001C040 The processor's data cache was reloaded from local core's L2 without conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 . #59,v,g,n,n,n,PM_DATA_FROM_L31_SHR,The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to a demand load ##000001C046 The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. #60,v,g,n,n,n,PM_DATA_FROM_L3_NO_CONFLICT,The processor's data cache was reloaded from local core's L3 without conflict due to a demand load ##000001C044 The processor's data cache was reloaded from local core's L3 without conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. #61,v,g,n,n,n,PM_DATA_FROM_LL4,The processor's data cache was reloaded from the local chip's L4 cache due to a demand load ##000001C04C The processor's data cache was reloaded from the local chip's L4 cache due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. #62,v,g,n,n,n,PM_DATA_FROM_ON_CHIP_CACHE,The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a demand load ##000001C048 The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. #63,v,g,n,n,n,PM_DATA_FROM_RL2L3_SHR,The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load ##000001C04A The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. #64,u,g,n,n,n,PM_DATA_GRP_PUMP_MPRED_RTY,Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a demand load ##000001C052 Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor a demand load. #65,u,g,n,n,n,PM_DATA_PUMP_CPRED,Pump prediction correct. Counts across all types of pumps for a demand load ##000001C054 Pump prediction correct. Counts across all types of pumps for a demand load. #66,u,g,n,n,n,PM_DC_COLLISIONS,DATA Cache collisions ##000000E0BC DATA Cache collisions42 #67,v,g,n,n,n,PM_DC_PREF_STREAM_ALLOC,Stream marked valid. The stream could have been allocated through the hardware prefetch mechanism or through software. This is combined ls0 and ls1 ##000001E050 Stream marked valid. The stream could have been allocated through the hardware prefetch mechanism or through software. This is combined ls0 and ls1. #68,u,g,n,n,n,PM_DERAT_MISS_4K,Data ERAT Miss (Data TLB Access) page size 4K ##000001C056 Data ERAT Miss (Data TLB Access) page size 4K. #69,u,g,n,n,n,PM_DFU,Finish DFU (all finish) ##000000B0BA Finish DFU (all finish) #70,u,g,n,n,n,PM_DFU_DCFFIX,Convert from fixed opcode finish (dcffix,dcffixq) ##000000B0BE Convert from fixed opcode finish (dcffix,dcffixq) #71,u,g,n,n,n,PM_DFU_DENBCD,BCD->DPD opcode finish (denbcd, denbcdq) ##000000B0BC BCD->DPD opcode finish (denbcd, denbcdq) #72,u,g,n,n,n,PM_DFU_MC,Finish DFU multicycle ##000000B0B8 Finish DFU multicycle #73,u,g,n,n,n,PM_DISP_CLB_HELD_BAL,Dispatch/CLB Hold: Balance ##0000002092 Dispatch/CLB Hold: Balance #74,u,g,n,n,n,PM_DISP_CLB_HELD_RES,Dispatch/CLB Hold: Resource ##0000002094 Dispatch/CLB Hold: Resource #75,u,g,n,n,n,PM_DISP_CLB_HELD_SB,Dispatch/CLB Hold: Scoreboard ##00000020A8 Dispatch/CLB Hold: Scoreboard #76,u,g,n,n,n,PM_DISP_CLB_HELD_SYNC,Dispatch/CLB Hold: Sync type instruction ##0000002098 Dispatch/CLB Hold: Sync type instruction #77,v,g,n,n,n,PM_DISP_CLB_HELD_TLBIE,Dispatch Hold: Due to TLBIE ##0000002096 Dispatch Hold: Due to TLBIE #78,v,g,n,n,n,PM_DISP_HELD,Dispatch Held ##0000010006 Dispatch Held. #79,v,g,n,n,n,PM_DISP_HELD_MAP_FULL,Dispatch for this thread was held because the Mappers were full ##000001002A Dispatch held due to Mapper full. #80,u,g,n,n,n,PM_DISP_HOLD_GCT_FULL,Dispatch Hold Due to no space in the GCT ##00000030A6 Dispatch Hold Due to no space in the GCT #81,u,g,n,n,n,PM_DPTEG_FROM_L2,A Page Table Entry was loaded into the TLB from local core's L2 due to a data side request ##000001E042 A Page Table Entry was loaded into the TLB from local core's L2 due to a data side request. #82,u,g,n,n,n,PM_DPTEG_FROM_L2MISS,A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a data side request ##000001E04E A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a data side request. #83,u,g,n,n,n,PM_DPTEG_FROM_L2_NO_CONFLICT,A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a data side request ##000001E040 A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a data side request. #84,u,g,n,n,n,PM_DPTEG_FROM_L31_SHR,A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a data side request ##000001E046 A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a data side request. #85,u,g,n,n,n,PM_DPTEG_FROM_L3_NO_CONFLICT,A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a data side request ##000001E044 A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a data side request. #86,u,g,n,n,n,PM_DPTEG_FROM_LL4,A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a data side request ##000001E04C A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a data side request. #87,u,g,n,n,n,PM_DPTEG_FROM_ON_CHIP_CACHE,A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a data side request ##000001E048 A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a data side request. #88,u,g,n,n,n,PM_DPTEG_FROM_RL2L3_SHR,A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request ##000001E04A A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request. #89,v,g,n,n,n,PM_DSLB_MISS,Data SLB Miss - Total of all segment sizes ##000000D094 Data SLB Miss - Total of all segment sizesData SLB misses #90,u,g,n,n,n,PM_DTLB_MISS_16G,Data TLB Miss page size 16G ##000001C058 Data TLB Miss page size 16G. #91,u,g,n,n,n,PM_EAT_FORCE_MISPRED,XL-form branch was mispredicted due to the predicted target address missing from EAT. The EAT forces a mispredict in this case since there is no predicated target to validate. This is a rare case that may occur when the EAT is full and a branch is issue ##00000050A8 XL-form branch was mispredicted due to the predicted target address missing from EAT. The EAT forces a mispredict in this case since there is no predicated target to validate. This is a rare case that may occur when the EAT is full and a branch is #92,u,g,n,n,n,PM_EAT_FULL_CYC,Cycles No room in EAT ##0000004084 Cycles No room in EATSet on bank conflict and case where no ibuffers available. #93,u,g,n,n,n,PM_EE_OFF_EXT_INT,Ee off and external interrupt ##0000002080 Ee off and external interrupt #94,u,g,n,n,n,PM_FAV_TBEGIN,Dispatch time Favored tbegin ##00000020B4 Dispatch time Favored tbegin #95,v,g,n,n,n,PM_FLOP,Floating Point Operation Finished ##00000100F4 Floating Point Operations Finished. #96,u,g,n,n,n,PM_FLOP_SUM_SCALAR,flops summary scalar instructions ##000000A0AE flops summary scalar instructions #97,u,g,n,n,n,PM_FLOP_SUM_VEC,flops summary vector instructions ##000000A0AC flops summary vector instructions #98,u,g,n,n,n,PM_FLUSH_BR_MPRED,Flush caused by branch mispredict ##0000002084 Flush caused by branch mispredict #99,u,g,n,n,n,PM_FLUSH_DISP,Dispatch flush ##0000002082 Dispatch flush #100,u,g,n,n,n,PM_FLUSH_DISP_SB,Dispatch Flush: Scoreboard ##000000208C Dispatch Flush: Scoreboard #101,u,g,n,n,n,PM_FLUSH_DISP_SYNC,Dispatch Flush: Sync ##0000002088 Dispatch Flush: Sync #102,u,g,n,n,n,PM_FLUSH_DISP_TLBIE,Dispatch Flush: TLBIE ##000000208A Dispatch Flush: TLBIE #103,u,g,n,n,n,PM_FLUSH_LSU,Flush initiated by LSU ##000000208E Flush initiated by LSU #104,u,g,n,n,n,PM_FLUSH_PARTIAL,Partial flush ##0000002086 Partial flush #105,u,g,n,n,n,PM_FPU0_FCONV,Convert instruction executed ##000000A0B0 Convert instruction executed #106,u,g,n,n,n,PM_FPU0_FEST,Estimate instruction executed ##000000A0B8 Estimate instruction executed #107,u,g,n,n,n,PM_FPU0_FRSP,Round to single precision instruction executed ##000000A0B4 Round to single precision instruction executed #108,u,g,n,n,n,PM_FPU1_FCONV,Convert instruction executed ##000000A0B2 Convert instruction executed #109,u,g,n,n,n,PM_FPU1_FEST,Estimate instruction executed ##000000A0BA Estimate instruction executed #110,u,g,n,n,n,PM_FPU1_FRSP,Round to single precision instruction executed ##000000A0B6 Round to single precision instruction executed #111,u,g,n,n,n,PM_FUSION_TOC_GRP0_1,One pair of instructions fused with TOC in Group0 ##00000050B0 One pair of instructions fused with TOC in Group0 #112,u,g,n,n,n,PM_FUSION_TOC_GRP0_2,Two pairs of instructions fused with TOCin Group0 ##00000050AE Two pairs of instructions fused with TOCin Group0 #113,u,g,n,n,n,PM_FUSION_TOC_GRP0_3,Three pairs of instructions fused with TOC in Group0 ##00000050AC Three pairs of instructions fused with TOC in Group0 #114,u,g,n,n,n,PM_FUSION_TOC_GRP1_1,One pair of instructions fused with TOX in Group1 ##00000050B2 One pair of instructions fused with TOX in Group1 #115,u,g,n,n,n,PM_FUSION_VSX_GRP0_1,One pair of instructions fused with VSX in Group0 ##00000050B8 One pair of instructions fused with VSX in Group0 #116,u,g,n,n,n,PM_FUSION_VSX_GRP0_2,Two pairs of instructions fused with VSX in Group0 ##00000050B6 Two pairs of instructions fused with VSX in Group0 #117,u,g,n,n,n,PM_FUSION_VSX_GRP0_3,Three pairs of instructions fused with VSX in Group0 ##00000050B4 Three pairs of instructions fused with VSX in Group0 #118,u,g,n,n,n,PM_FUSION_VSX_GRP1_1,One pair of instructions fused with VSX in Group1 ##00000050BA One pair of instructions fused with VSX in Group1 #119,v,g,n,n,n,PM_FXU0_FIN,The fixed point unit Unit 0 finished an instruction. Instructions that finish may not necessary complete. ##0000010004 FXU0 Finished. #120,v,g,n,n,n,PM_FXU_IDLE,fxu0 idle and fxu1 idle ##000001000E fxu0 idle and fxu1 idle. #121,v,g,n,n,n,PM_GCT_MERGE,Group dispatched on a merged GCT empty. GCT entries can be merged only within the same thread ##00000030A4 Group dispatched on a merged GCT empty. GCT entries can be merged only within the same thread #122,v,g,n,n,n,PM_GCT_NOSLOT_CYC,No itags assigned ##00000100F8 Pipeline empty (No itags assigned , no GCT slots used). #123,u,g,n,n,n,PM_GCT_UTIL_11_14_ENTRIES,GCT Utilization 11-14 entries ##00000020A2 GCT Utilization 11-14 entries #124,u,g,n,n,n,PM_GCT_UTIL_1_2_ENTRIES,GCT Utilization 1-2 entries ##000000209C GCT Utilization 1-2 entries #125,u,g,n,n,n,PM_GCT_UTIL_15_17_ENTRIES,GCT Utilization 15-17 entries ##00000020A4 GCT Utilization 15-17 entries #126,v,g,n,n,n,PM_GCT_UTIL_18_ENTRIES,GCT Utilization 18+ entries ##00000020A6 GCT Utilization 18+ entries #127,u,g,n,n,n,PM_GCT_UTIL_3_6_ENTRIES,GCT Utilization 3-6 entries ##000000209E GCT Utilization 3-6 entries #128,u,g,n,n,n,PM_GCT_UTIL_7_10_ENTRIES,GCT Utilization 7-10 entries ##00000020A0 GCT Utilization 7-10 entries #129,v,g,n,n,n,PM_GRP_BR_MPRED_NONSPEC,Group experienced non-speculative branch redirect ##000001000A Group experienced Non-speculative br mispredicct. #130,v,g,n,n,n,PM_GRP_IC_MISS_NONSPEC,Group experienced non-speculative I cache miss ##000001000C Group experi enced Non-specu lative I cache miss. #131,v,g,n,n,m,PM_GRP_MRK,Instruction Marked ##0000010130 Instruction marked in idu. #132,u,g,n,n,n,PM_GRP_NON_FULL_GROUP,GROUPs where we did not have 6 non branch instructions in the group(ST mode), in SMT mode 3 non branches ##000000509C GROUPs where we did not have 6 non branch instructions in the group(ST mode), in SMT mode 3 non branches #133,u,g,n,n,n,PM_GRP_PUMP_MPRED_RTY,Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) ##0000010052 Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate). #134,u,g,n,n,n,PM_GRP_TERM_2ND_BRANCH,There were enough instructions in the Ibuffer, but 2nd branch ends group ##00000050A4 There were enough instructions in the Ibuffer, but 2nd branch ends group #135,u,g,n,n,n,PM_GRP_TERM_FPU_AFTER_BR,There were enough instructions in the Ibuffer, but FPU OP IN same group after a branch terminates a group, cant do partial flushes ##00000050A6 There were enough instructions in the Ibuffer, but FPU OP IN same group after a branch terminates a group, cant do partial flushes #136,u,g,n,n,n,PM_GRP_TERM_NOINST,Do not fill every slot in the group, Not enough instructions in the Ibuffer. This includes cases where the group started with enough instructions, but some got knocked out by a cache miss or branch redirect (which would also empty the Ibuffer). ##000000509E Do not fill every slot in the group, Not enough instructions in the Ibuffer. This includes cases where the group started with enough instructions, but some got knocked out by a cache miss or branch redirect (which would also empty the Ibuffer). #137,u,g,n,n,n,PM_GRP_TERM_OTHER,There were enough instructions in the Ibuffer, but the group terminated early for some other reason, most likely due to a First or Last. ##00000050A0 There were enough instructions in the Ibuffer, but the group terminated early for some other reason, most likely due to a First or Last. #138,u,g,n,n,n,PM_GRP_TERM_SLOT_LIMIT,There were enough instructions in the Ibuffer, but 3 src RA/RB/RC , 2 way crack caused a group termination ##00000050A2 There were enough instructions in the Ibuffer, but 3 src RA/RB/RC , 2 way crack caused a group termination #139,u,g,n,n,n,PM_IBUF_FULL_CYC,Cycles No room in ibuff ##0000004086 Cycles No room in ibufffully qualified tranfer (if5 valid). #140,v,g,n,n,n,PM_IC_DEMAND_CYC,Cycles when a demand ifetch was pending ##0000010018 Demand ifetch pending. #141,u,g,n,n,n,PM_IC_DEMAND_L2_BHT_REDIRECT, L2 I cache demand request due to BHT redirect, branch redirect ( 2 bubbles 3 cycles) ##0000004098 L2 I cache demand request due to BHT redirect, branch redirect ( 2 bubbles 3 cycles) #142,u,g,n,n,n,PM_IC_DEMAND_L2_BR_REDIRECT, L2 I cache demand request due to branch Mispredict ( 15 cycle path) ##000000409A L2 I cache demand request due to branch Mispredict ( 15 cycle path) #143,u,g,n,n,n,PM_IC_DEMAND_REQ,Demand Instruction fetch request ##0000004088 Demand Instruction fetch request #144,u,g,n,n,n,PM_IC_INVALIDATE,Ic line invalidated ##000000508A Ic line invalidated #145,u,g,n,n,n,PM_IC_PREF_CANCEL_HIT,Prefetch Canceled due to icache hit ##0000004092 Prefetch Canceled due to icache hit #146,u,g,n,n,n,PM_IC_PREF_CANCEL_L2,L2 Squashed request ##0000004094 L2 Squashed request #147,u,g,n,n,n,PM_IC_PREF_CANCEL_PAGE,Prefetch Canceled due to page boundary ##0000004090 Prefetch Canceled due to page boundary #148,u,g,n,n,n,PM_IC_PREF_REQ,Instruction prefetch requests ##000000408A Instruction prefetch requests #149,v,g,n,n,n,PM_IC_PREF_WRITE,Instruction prefetch written into IL1 ##000000408E Instruction prefetch written into IL1 #150,u,g,n,n,n,PM_IC_RELOAD_PRIVATE,Reloading line was brought in private for a specific thread. Most lines are brought in shared for all eight thrreads. If RA does not match then invalidates and then brings it shared to other thread. In P7 line brought in private , then line was invalidat ##0000004096 Reloading line was brought in private for a specific thread. Most lines are brought in shared for all eight thrreads. If RA does not match then invalidates and then brings it shared to other thread. In P7 line brought in private , then line was inv #151,u,g,n,n,n,PM_IERAT_RELOAD,Number of I-ERAT reloads ##00000100F6 IERAT Reloaded (Miss). #152,u,g,n,n,n,PM_IFU_L2_TOUCH,L2 touch to update MRU on a line ##0000005088 L2 touch to update MRU on a line #153,u,g,n,n,n,PM_INST_ALL_CHIP_PUMP_CPRED,Initial and Final Pump Scope was chip pump (prediction=correct) for instruction fetches and prefetches ##0000514050 Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for an instruction fetch #154,u,g,n,n,n,PM_INST_ALL_FROM_L2,The processor's Instruction cache was reloaded from local core's L2 due to instruction fetches and prefetches ##0000514042 The processor's Instruction cache was reloaded from local core's L2 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 #155,u,g,n,n,n,PM_INST_ALL_FROM_L2MISS,The processor's Instruction cache was reloaded from a localtion other than the local core's L2 due to instruction fetches and prefetches ##000051404E The processor's Instruction cache was reloaded from a localtion other than the local core's L2 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 #156,u,g,n,n,n,PM_INST_ALL_FROM_L2_NO_CONFLICT,The processor's Instruction cache was reloaded from local core's L2 without conflict due to instruction fetches and prefetches ##0000514040 The processor's Instruction cache was reloaded from local core's L2 without conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 #157,u,g,n,n,n,PM_INST_ALL_FROM_L31_SHR,The processor's Instruction cache was reloaded with Shared (S) data from another core's L3 on the same chip due to instruction fetches and prefetches ##0000514046 The processor's Instruction cache was reloaded with Shared (S) data from another core's L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 #158,u,g,n,n,n,PM_INST_ALL_FROM_L3_NO_CONFLICT,The processor's Instruction cache was reloaded from local core's L3 without conflict due to instruction fetches and prefetches ##0000514044 The processor's Instruction cache was reloaded from local core's L3 without conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 #159,u,g,n,n,n,PM_INST_ALL_FROM_LL4,The processor's Instruction cache was reloaded from the local chip's L4 cache due to instruction fetches and prefetches ##000051404C The processor's Instruction cache was reloaded from the local chip's L4 cache due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 #160,u,g,n,n,n,PM_INST_ALL_FROM_ON_CHIP_CACHE,The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to instruction fetches and prefetches ##0000514048 The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 #161,u,g,n,n,n,PM_INST_ALL_FROM_RL2L3_SHR,The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to instruction fetches and prefetches ##000051404A The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 #162,u,g,n,n,n,PM_INST_ALL_GRP_PUMP_MPRED_RTY,Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for instruction fetches and prefetches ##0000514052 Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor an instruction fetch #163,u,g,n,n,n,PM_INST_ALL_PUMP_CPRED,Pump prediction correct. Counts across all types of pumps for instruction fetches and prefetches ##0000514054 Pump prediction correct. Counts across all types of pumpsfor an instruction fetch #164,u,g,n,n,n,PM_INST_CHIP_PUMP_CPRED,Initial and Final Pump Scope was chip pump (prediction=correct) for an instruction fetch ##0000014050 Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for an instruction fetch. #165,v,g,n,n,n,PM_INST_CMPL,Number of PowerPC Instructions that completed. ##0000010002 PPC Instructions Finished (completed). #166,u,g,n,n,n,PM_INST_FROM_L1,Instruction fetches from L1 ##0000004080 Instruction fetches from L1 #167,v,g,n,n,n,PM_INST_FROM_L2,The processor's Instruction cache was reloaded from local core's L2 due to an instruction fetch (not prefetch) ##0000014042 The processor's Instruction cache was reloaded from local core's L2 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . #168,v,g,n,n,n,PM_INST_FROM_L2MISS,The processor's Instruction cache was reloaded from a localtion other than the local core's L2 due to an instruction fetch (not prefetch) ##000001404E The processor's Instruction cache was reloaded from a localtion other than the local core's L2 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . #169,v,g,n,n,n,PM_INST_FROM_L2_NO_CONFLICT,The processor's Instruction cache was reloaded from local core's L2 without conflict due to an instruction fetch (not prefetch) ##0000014040 The processor's Instruction cache was reloaded from local core's L2 without conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . #170,v,g,n,n,n,PM_INST_FROM_L31_SHR,The processor's Instruction cache was reloaded with Shared (S) data from another core's L3 on the same chip due to an instruction fetch (not prefetch) ##0000014046 The processor's Instruction cache was reloaded with Shared (S) data from another core's L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . #171,v,g,n,n,n,PM_INST_FROM_L3_NO_CONFLICT,The processor's Instruction cache was reloaded from local core's L3 without conflict due to an instruction fetch (not prefetch) ##0000014044 The processor's Instruction cache was reloaded from local core's L3 without conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . #172,v,g,n,n,n,PM_INST_FROM_LL4,The processor's Instruction cache was reloaded from the local chip's L4 cache due to an instruction fetch (not prefetch) ##000001404C The processor's Instruction cache was reloaded from the local chip's L4 cache due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . #173,v,g,n,n,n,PM_INST_FROM_ON_CHIP_CACHE,The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to an instruction fetch (not prefetch) ##0000014048 The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . #174,v,g,n,n,n,PM_INST_FROM_RL2L3_SHR,The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch) ##000001404A The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . #175,u,g,n,n,n,PM_INST_GRP_PUMP_MPRED_RTY,Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for an instruction fetch ##0000014052 Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor an instruction fetch. #176,v,g,n,n,n,PM_INST_IMC_MATCH_CMPL,IMC Match Count ( Not architected in P8) ##000001003A IMC Match Count. #177,u,g,n,n,n,PM_INST_PUMP_CPRED,Pump prediction correct. Counts across all types of pumps for an instruction fetch ##0000014054 Pump prediction correct. Counts across all types of pumpsfor an instruction fetch. #178,u,g,n,n,n,PM_IOPS_CMPL,Internal Operations completed ##0000010014 IOPS Completed. #179,u,g,n,n,n,PM_IPTEG_FROM_L2,A Page Table Entry was loaded into the TLB from local core's L2 due to a instruction side request ##0000015042 A Page Table Entry was loaded into the TLB from local core's L2 due to a instruction side request. #180,u,g,n,n,n,PM_IPTEG_FROM_L2MISS,A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a instruction side request ##000001504E A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a instruction side request. #181,u,g,n,n,n,PM_IPTEG_FROM_L2_NO_CONFLICT,A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a instruction side request ##0000015040 A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a instruction side request. #182,u,g,n,n,n,PM_IPTEG_FROM_L31_SHR,A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a instruction side request ##0000015046 A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a instruction side request. #183,u,g,n,n,n,PM_IPTEG_FROM_L3_NO_CONFLICT,A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a instruction side request ##0000015044 A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a instruction side request. #184,u,g,n,n,n,PM_IPTEG_FROM_LL4,A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a instruction side request ##000001504C A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a instruction side request. #185,u,g,n,n,n,PM_IPTEG_FROM_ON_CHIP_CACHE,A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a instruction side request ##0000015048 A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a instruction side request. #186,u,g,n,n,n,PM_IPTEG_FROM_RL2L3_SHR,A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request ##000001504A A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request. #187,u,g,n,n,n,PM_ISIDE_DISP,All i-side dispatch attempts ##0000617082 All i-side dispatch attempts #188,v,g,n,n,n,PM_ISLB_MISS,I SLB Miss. ##000000D096 I SLB Miss. #189,u,g,n,s,n,PM_ISU_REF_FX0,FX0 ISU reject ##00000030AC FX0 ISU reject #190,u,g,n,s,n,PM_ISU_REF_FX1,FX1 ISU reject ##00000030AE FX1 ISU reject #191,u,g,n,n,n,PM_ISU_REF_FXU,FXU ISU reject from either pipe ##00000038AC ISU #192,u,g,n,s,n,PM_ISU_REF_LS0,LS0 ISU reject ##00000030B0 LS0 ISU reject #193,u,g,n,s,n,PM_ISU_REF_LS1,LS1 ISU reject ##00000030B2 LS1 ISU reject #194,u,g,n,s,n,PM_ISU_REF_LS2,LS2 ISU reject ##00000030B4 LS2 ISU reject #195,u,g,n,s,n,PM_ISU_REF_LS3,LS3 ISU reject ##00000030B6 LS3 ISU reject #196,u,g,n,s,n,PM_ISU_REJECT_RES_NA,ISU reject due to resource not available ##00000030A2 ISU reject due to resource not available #197,v,g,n,s,n,PM_ISU_REJECTS_ALL,All isu rejects could be more than 1 per cycle ##000000309C All isu rejects could be more than 1 per cycle #198,v,g,n,s,n,PM_ISU_REJECT_SAR_BYPASS,Reject because of SAR bypass ##000000309E Reject because of SAR bypass #199,u,g,n,s,n,PM_ISU_REJECT_SRC_NA,ISU reject due to source not available ##00000030A0 ISU reject due to source not available #200,u,g,n,s,n,PM_ISU_REJ_VS0,VS0 ISU reject ##00000030A8 VS0 ISU reject #201,u,g,n,s,n,PM_ISU_REJ_VS1,VS1 ISU reject ##00000030AA VS1 ISU reject #202,u,g,n,n,n,PM_ISU_REJ_VSU,VSU ISU reject from either pipe ##00000038A8 ISU #203,u,g,n,n,n,PM_ISYNC,Isync count per thread ##00000030B8 Isync count per thread #204,v,g,n,n,n,PM_L1_DCACHE_RELOADED_ALL,L1 data cache reloaded for demand or prefetch ##000001002C L1 data cache reloaded for demand or prefetch . #205,v,g,n,n,n,PM_L1_DEMAND_WRITE,Instruction Demand sectors wriittent into IL1 ##000000408C Instruction Demand sectors wriittent into IL1 #206,u,g,n,n,m,PM_L1MISS_LAT_EXC_256,L1 misses that took longer than 256 cyles to resolve (miss to reload) ##67200101E8 Reload latency exceeded 256 cyc #207,u,g,n,s,n,PM_L2_CASTOUT_MOD,L2 Castouts - Modified (M, Mu, Me) ##0000417080 L2 Castouts - Modified (M, Mu, Me) #208,u,g,n,s,n,PM_L2_CASTOUT_SHR,L2 Castouts - Shared (T, Te, Si, S) ##0000417082 L2 Castouts - Shared (T, Te, Si, S) #209,v,g,n,n,n,PM_L2_LD,All successful D-side Load dispatches for this thread ##0000416080 All successful D-side Load dispatches for this thread #210,u,g,n,s,n,PM_L2_LOC_GUESS_CORRECT,L2 guess loc and guess was correct (ie data local) ##0000616080 L2 guess loc and guess was correct (ie data local) #211,u,g,n,s,n,PM_L2_LOC_GUESS_WRONG,L2 guess loc and guess was not correct (ie data not on chip) ##0000616082 L2 guess loc and guess was not correct (ie data not on chip) #212,v,g,n,n,n,PM_L2_RCLD_DISP, L2 RC load dispatch attempt ##0000516080 L2 RC load dispatch attempt #213,u,g,n,n,n,PM_L2_RCLD_DISP_FAIL_ADDR, L2 RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ ##0000516082 L2 RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ #214,v,g,n,n,n,PM_L2_ST,All successful D-side store dispatches for this thread ##0000017080 All successful D-side store dispatches for this thread #215,v,g,n,n,n,PM_L2_ST_MISS,All successful D-side store dispatches for this thread that were L2 Miss ##0000017082 All successful D-side store dispatches for this thread that were L2 Miss #216,c,g,n,s,n,PM_L2_SYS_PUMP,RC requests that were system pump attempts ##0000617080 RC requests that were system pump attempts #217,v,g,n,n,n,PM_L2_TM_REQ_ABORT,TM abort ##000001E05E TM abort. #218,u,g,n,s,n,PM_L3_CI_USAGE,rotating sample of 16 CI or CO actives ##0000819082 rotating sample of 16 CI or CO actives #219,v,g,n,s,n,PM_L3_CO_MEPF,L3 CO of line in Mep state ( includes casthrough) ##0000018082 L3 CO of line in Mep state ( includes casthrough) #220,u,g,n,s,n,PM_L3_GRP_GUESS_CORRECT,Initial scope=group and data from same group (near) (pred successful) ##0000B19082 Initial scope=group and data from same group (near) (pred successful) #221,v,g,n,s,n,PM_L3_HIT,L3 Hits ##0000218080 L3 Hits #222,v,g,n,n,n,PM_L3_LD_PREF,L3 Load Prefetches ##000001E052 L3 Load Prefetches. #223,u,g,n,s,n,PM_L3_LOC_GUESS_CORRECT,initial scope=node/chip and data from local node (local) (pred successful) ##0000B19080 initial scope=node/chip and data from local node (local) (pred successful) #224,v,g,n,s,n,PM_L3_MISS,L3 Misses ##0000218082 L3 Misses #225,u,g,n,s,n,PM_L3_P0_LCO_NO_DATA,dataless l3 lco sent port 0 ##0000518080 dataless l3 lco sent port 0 #226,u,g,n,s,n,PM_L3_P0_NODE_PUMP,L3 pf sent with nodal scope port 0 ##0000A19080 L3 pf sent with nodal scope port 0 #227,u,g,n,s,n,PM_L3_P0_PF_RTY,L3 PF received retry port 0 ##0000919080 L3 PF received retry port 0 #228,u,g,n,s,n,PM_L3_P0_SN_INV,Port0 snooper detects someone doing a store to a line thats Sx ##0000118080 Port0 snooper detects someone doing a store to a line thats Sx #229,u,g,n,s,n,PM_L3_P1_LCO_NO_DATA,dataless l3 lco sent port 1 ##0000518082 dataless l3 lco sent port 1 #230,u,g,n,s,n,PM_L3_P1_NODE_PUMP,L3 pf sent with nodal scope port 1 ##0000A19082 L3 pf sent with nodal scope port 1 #231,u,g,n,s,n,PM_L3_P1_PF_RTY,L3 PF received retry port 1 ##0000919082 L3 PF received retry port 1 #232,u,g,n,s,n,PM_L3_P1_SN_INV,Port1 snooper detects someone doing a store to a line thats Sx ##0000118082 Port1 snooper detects someone doing a store to a line thats Sx #233,v,g,n,s,n,PM_L3_PF_MISS_L3,L3 Prefetch missed in L3 ##0000018080 L3 Prefetch missed in L3 #234,u,g,n,s,n,PM_L3_SN_USAGE,rotating sample of 8 snoop valids ##0000819080 rotating sample of 8 snoop valids #235,u,g,n,n,n,PM_L3_WI0_ALLOC,lifetime, sample of Write Inject machine 0 valid ##0000018081 0.0 #236,u,g,n,s,n,PM_L3_WI0_BUSY,lifetime, sample of Write Inject machine 0 valid ##0000418080 lifetime, sample of Write Inject machine 0 valid #237,u,g,n,s,n,PM_L3_WI_USAGE,rotating sample of 8 WI actives ##0000418082 rotating sample of 8 WI actives #238,v,g,n,n,n,PM_LD_CMPL,count of Loads completed ##000001002E count of Loads completed. #239,v,g,n,n,n,PM_LD_L3MISS_PEND_CYC,Cycles L3 miss was pending for this thread ##0000010062 Cycles L3 miss was pending for this thread. #240,v,g,n,n,n,PM_LD_REF_L1,All L1 D cache load references counted at finish, gated by reject ##00000100EE Load Ref count combined for all units. #241,v,g,n,n,n,PM_LD_REF_L1_LSU0, LS0 L1 D cache load references counted at finish, gated by reject ##000000C080 LS0 L1 D cache load references counted at finish, gated by rejectLSU0 L1 D cache load references #242,v,g,n,n,n,PM_LD_REF_L1_LSU1, LS1 L1 D cache load references counted at finish, gated by reject ##000000C082 LS1 L1 D cache load references counted at finish, gated by rejectLSU1 L1 D cache load references #243,v,g,n,n,n,PM_LD_REF_L1_LSU2, LS2 L1 D cache load references counted at finish, gated by reject ##000000C094 LS2 L1 D cache load references counted at finish, gated by reject42 #244,v,g,n,n,n,PM_LD_REF_L1_LSU3, LS3 L1 D cache load references counted at finish, gated by reject ##000000C096 LS3 L1 D cache load references counted at finish, gated by reject42 #245,u,g,n,n,n,PM_LINK_STACK_INVALID_PTR,A flush were LS ptr is invalid, results in a pop , A lot of interrupts between push and pops ##000000509A A flush were LS ptr is invalid, results in a pop , A lot of interrupts between push and pops #246,u,g,n,n,n,PM_LINK_STACK_WRONG_ADD_PRED,Link stack predicts wrong address, because of link stack design limitation. ##0000005098 Link stack predicts wrong address, because of link stack design limitation. #247,u,g,n,n,n,PM_LS0_ERAT_MISS_PREF,LS0 Erat miss due to prefetch ##000000E080 LS0 Erat miss due to prefetch42 #248,v,g,n,n,n,PM_LS0_L1_PREF, LS0 L1 cache data prefetches ##000000D0B8 LS0 L1 cache data prefetches42 #249,v,g,n,n,n,PM_LS0_L1_SW_PREF,Software L1 Prefetches, including SW Transient Prefetches ##000000C098 Software L1 Prefetches, including SW Transient Prefetches42 #250,u,g,n,n,n,PM_LS1_ERAT_MISS_PREF,LS1 Erat miss due to prefetch ##000000E082 LS1 Erat miss due to prefetch42 #251,v,g,n,n,n,PM_LS1_L1_PREF, LS1 L1 cache data prefetches ##000000D0BA LS1 L1 cache data prefetches42 #252,v,g,n,n,n,PM_LS1_L1_SW_PREF,Software L1 Prefetches, including SW Transient Prefetches ##000000C09A Software L1 Prefetches, including SW Transient Prefetches42 #253,u,g,n,n,n,PM_LSU0_FLUSH_LRQ,LS0 Flush: LRQ ##000000C0B0 LS0 Flush: LRQLSU0 LRQ flushes #254,u,g,n,n,n,PM_LSU0_FLUSH_SRQ,LS0 Flush: SRQ ##000000C0B8 LS0 Flush: SRQLSU0 SRQ lhs flushes #255,u,g,n,n,n,PM_LSU0_FLUSH_ULD,LS0 Flush: Unaligned Load ##000000C0A4 LS0 Flush: Unaligned LoadLSU0 unaligned load flushes #256,u,g,n,n,n,PM_LSU0_FLUSH_UST,LS0 Flush: Unaligned Store ##000000C0AC LS0 Flush: Unaligned StoreLSU0 unaligned store flushes #257,u,g,n,n,n,PM_LSU0_L1_CAM_CANCEL,ls0 l1 tm cam cancel ##000000F088 ls0 l1 tm cam cancel42 #258,v,g,n,n,n,PM_LSU0_LARX_FIN,Larx finished in LSU pipe0 ##000001E056 . #259,v,g,n,n,n,PM_LSU0_LMQ_LHR_MERGE,LS0 Load Merged with another cacheline request ##000000D08C LS0 Load Merged with another cacheline request42 #260,u,g,n,n,n,PM_LSU0_NCLD,LS0 Non-cachable Loads counted at finish ##000000C08C LS0 Non-cachable Loads counted at finishLSU0 non-cacheable loads #261,u,g,n,n,n,PM_LSU0_PRIMARY_ERAT_HIT,Primary ERAT hit ##000000E090 Primary ERAT hit42 #262,v,g,n,n,n,PM_LSU0_REJECT,LSU0 reject ##000001E05A LSU0 reject . #263,u,g,n,n,n,PM_LSU0_SRQ_STFWD,LS0 SRQ forwarded data to a load ##000000C09C LS0 SRQ forwarded data to a loadLSU0 SRQ store forwarded #264,v,g,n,n,n,PM_LSU0_STORE_REJECT,ls0 store reject ##000000F084 ls0 store reject42 #265,u,g,n,n,n,PM_LSU0_TMA_REQ_L2, addrs only req to L2 only on the first one,Indication that Load footprint is not expanding ##000000E0A8 addrs only req to L2 only on the first one,Indication that Load footprint is not expanding42 #266,u,g,n,n,n,PM_LSU0_TM_L1_HIT,Load tm hit in L1 ##000000E098 Load tm hit in L142 #267,u,g,n,n,n,PM_LSU0_TM_L1_MISS,Load tm L1 miss ##000000E0A0 Load tm L1 miss42 #268,u,g,n,n,n,PM_LSU1_FLUSH_LRQ,LS1 Flush: LRQ ##000000C0B2 LS1 Flush: LRQLSU1 LRQ flushes #269,u,g,n,n,n,PM_LSU1_FLUSH_SRQ,LS1 Flush: SRQ ##000000C0BA LS1 Flush: SRQLSU1 SRQ lhs flushes #270,u,g,n,n,n,PM_LSU1_FLUSH_ULD,LS 1 Flush: Unaligned Load ##000000C0A6 LS 1 Flush: Unaligned LoadLSU1 unaligned load flushes #271,u,g,n,n,n,PM_LSU1_FLUSH_UST,LS1 Flush: Unaligned Store ##000000C0AE LS1 Flush: Unaligned StoreLSU1 unaligned store flushes #272,u,g,n,n,n,PM_LSU1_L1_CAM_CANCEL,ls1 l1 tm cam cancel ##000000F08A ls1 l1 tm cam cancel42 #273,v,g,n,n,n,PM_LSU1_LMQ_LHR_MERGE,LS1 Load Merge with another cacheline request ##000000D08E LS1 Load Merge with another cacheline request42 #274,u,g,n,n,n,PM_LSU1_NCLD,LS1 Non-cachable Loads counted at finish ##000000C08E LS1 Non-cachable Loads counted at finishLSU1 non-cacheable loads #275,u,g,n,n,n,PM_LSU1_PRIMARY_ERAT_HIT,Primary ERAT hit ##000000E092 Primary ERAT hit42 #276,u,g,n,n,n,PM_LSU1_SRQ_STFWD,LS1 SRQ forwarded data to a load ##000000C09E LS1 SRQ forwarded data to a loadLSU1 SRQ store forwarded #277,v,g,n,n,n,PM_LSU1_STORE_REJECT,ls1 store reject ##000000F086 ls1 store reject42 #278,u,g,n,n,n,PM_LSU1_TMA_REQ_L2, addrs only req to L2 only on the first one,Indication that Load footprint is not expanding ##000000E0AA addrs only req to L2 only on the first one,Indication that Load footprint is not expanding42 #279,u,g,n,n,n,PM_LSU1_TM_L1_HIT,Load tm hit in L1 ##000000E09A Load tm hit in L142 #280,u,g,n,n,n,PM_LSU1_TM_L1_MISS,Load tm L1 miss ##000000E0A2 Load tm L1 miss42 #281,u,g,n,n,n,PM_LSU2_FLUSH_LRQ,LS02Flush: LRQ ##000000C0B4 LS02Flush: LRQ42 #282,u,g,n,n,n,PM_LSU2_FLUSH_SRQ,LS2 Flush: SRQ ##000000C0BC LS2 Flush: SRQ42 #283,u,g,n,n,n,PM_LSU2_FLUSH_ULD,LS3 Flush: Unaligned Load ##000000C0A8 LS3 Flush: Unaligned Load42 #284,u,g,n,n,n,PM_LSU2_L1_CAM_CANCEL,ls2 l1 tm cam cancel ##000000F08C ls2 l1 tm cam cancel42 #285,u,g,n,n,n,PM_LSU2_LDF,LS2 Scalar Loads ##000000C084 LS2 Scalar Loads42 #286,u,g,n,n,n,PM_LSU2_LDX,LS0 Vector Loads ##000000C088 LS0 Vector Loads42 #287,v,g,n,n,n,PM_LSU2_LMQ_LHR_MERGE,LS0 Load Merged with another cacheline request ##000000D090 LS0 Load Merged with another cacheline request42 #288,u,g,n,n,n,PM_LSU2_PRIMARY_ERAT_HIT,Primary ERAT hit ##000000E094 Primary ERAT hit42 #289,u,g,n,n,n,PM_LSU2_SRQ_STFWD,LS2 SRQ forwarded data to a load ##000000C0A0 LS2 SRQ forwarded data to a load42 #290,u,g,n,n,n,PM_LSU2_TMA_REQ_L2, addrs only req to L2 only on the first one,Indication that Load footprint is not expanding ##000000E0AC addrs only req to L2 only on the first one,Indication that Load footprint is not expanding42 #291,u,g,n,n,n,PM_LSU2_TM_L1_HIT,Load tm hit in L1 ##000000E09C Load tm hit in L142 #292,u,g,n,n,n,PM_LSU2_TM_L1_MISS,Load tm L1 miss ##000000E0A4 Load tm L1 miss42 #293,u,g,n,n,n,PM_LSU3_FLUSH_LRQ,LS3 Flush: LRQ ##000000C0B6 LS3 Flush: LRQ42 #294,u,g,n,n,n,PM_LSU3_FLUSH_SRQ,LS13 Flush: SRQ ##000000C0BE LS13 Flush: SRQ42 #295,u,g,n,n,n,PM_LSU3_FLUSH_ULD,LS 14Flush: Unaligned Load ##000000C0AA LS 14Flush: Unaligned Load42 #296,u,g,n,n,n,PM_LSU3_L1_CAM_CANCEL,ls3 l1 tm cam cancel ##000000F08E ls3 l1 tm cam cancel42 #297,u,g,n,n,n,PM_LSU3_LDF,LS3 Scalar Loads ##000000C086 LS3 Scalar Loads 42 #298,u,g,n,n,n,PM_LSU3_LDX,LS1 Vector Loads ##000000C08A LS1 Vector Loads42 #299,v,g,n,n,n,PM_LSU3_LMQ_LHR_MERGE,LS1 Load Merge with another cacheline request ##000000D092 LS1 Load Merge with another cacheline request42 #300,u,g,n,n,n,PM_LSU3_PRIMARY_ERAT_HIT,Primary ERAT hit ##000000E096 Primary ERAT hit42 #301,u,g,n,n,n,PM_LSU3_SRQ_STFWD,LS3 SRQ forwarded data to a load ##000000C0A2 LS3 SRQ forwarded data to a load42 #302,u,g,n,n,n,PM_LSU3_TMA_REQ_L2, addrs only req to L2 only on the first one,Indication that Load footprint is not expanding ##000000E0AE addrs only req to L2 only on the first one,Indication that Load footprint is not expanding42 #303,u,g,n,n,n,PM_LSU3_TM_L1_HIT,Load tm hit in L1 ##000000E09E Load tm hit in L142 #304,u,g,n,n,n,PM_LSU3_TM_L1_MISS,Load tm L1 miss ##000000E0A6 Load tm L1 miss42 #305,u,g,n,n,n,PM_LSU_ERAT_MISS_PREF,Erat miss due to prefetch, on either pipe ##000000E880 LSU #306,u,g,n,n,n,PM_LSU_FLUSH_UST,Unaligned Store Flush on either pipe ##000000C8AC LSU #307,u,g,n,n,n,PM_LSU_FOUR_TABLEWALK_CYC,Cycles when four tablewalks pending on this thread ##000000D0A4 Cycles when four tablewalks pending on this thread42 #308,v,g,n,n,n,PM_LSU_FX_FIN,LSU Finished a FX operation (up to 2 per cycle ##0000010066 LSU Finished a FX operation (up to 2 per cycle. #309,u,g,n,n,n,PM_LSU_L1_PREF,hw initiated , include sw streaming forms as well , include sw streams as a separate event ##000000D8B8 LSU #310,u,g,n,n,n,PM_LSU_L1_SW_PREF,Software L1 Prefetches, including SW Transient Prefetches, on both pipes ##000000C898 LSU #311,u,g,n,n,n,PM_LSU_LDF,FPU loads only on LS2/LS3 ie LU0/LU1 ##000000C884 LSU #312,u,g,n,n,n,PM_LSU_LDX,Vector loads can issue only on LS2/LS3 ##000000C888 LSU #313,v,g,n,n,n,PM_LSU_LMQ_FULL_CYC,LMQ full ##000000D0A2 LMQ fullCycles LMQ full, #314,u,g,n,n,n,PM_LSU_LMQ_S0_ALLOC,Per thread - use edge detect to count allocates On a per thread basis, level signal indicating Slot 0 is valid. By instrumenting a single slot we can calculate service time for that slot. Previous machines required a separate signal indicating the slot was allocated. Because any signal can be routed to any counter in P8, we can count level in one PMC and edge detect in another PMC using the same signal ##000000D0A1 0.0 #315,v,g,n,n,n,PM_LSU_LMQ_S0_VALID,Slot 0 of LMQ valid ##000000D0A0 Slot 0 of LMQ validLMQ slot 0 valid #316,u,g,n,n,n,PM_LSU_LRQ_S0_ALLOC,Per thread - use edge detect to count allocates On a per thread basis, level signal indicating Slot 0 is valid. By instrumenting a single slot we can calculate service time for that slot. Previous machines required a separate signal indicating the slot was allocated. Because any signal can be routed to any counter in P8, we can count level in one PMC and edge detect in another PMC using the same signal ##000000D09F 0.0 #317,v,g,n,n,n,PM_LSU_LRQ_S0_VALID,Slot 0 of LRQ valid ##000000D09E Slot 0 of LRQ validLRQ slot 0 valid #318,u,g,n,n,n,PM_LSU_LRQ_S43_ALLOC,LRQ slot 43 was released ##000000F091 0.0 #319,u,g,n,n,n,PM_LSU_LRQ_S43_VALID,LRQ slot 43 was busy ##000000F090 LRQ slot 43 was busy42 #320,u,g,n,n,n,PM_LSU_NCLD,count at finish so can return only on ls0 or ls1 ##000000C88C LSU #321,u,g,n,n,n,PM_LSU_NCST,Non-cachable Stores sent to nest ##000000C092 Non-cachable Stores sent to nest42 #322,v,g,n,n,n,PM_LSU_REJECT,LSU Reject (up to 4 per cycle) ##0000010064 LSU Reject (up to 4 per cycle). #323,v,g,n,n,n,PM_LSU_REJECT_LMQ_FULL,LSU reject due to LMQ full ( 4 per cycle) ##000001E05C LSU reject due to LMQ full ( 4 per cycle). #324,u,g,n,n,n,PM_LSU_SET_MPRED,Line already in cache at reload time ##000000D082 Line already in cache at reload time42 #325,u,g,n,n,n,PM_LSU_SRQ_FULL_CYC,Storage Queue is full and is blocking dispatch ##000001001A SRQ is Full. #326,u,g,n,n,n,PM_LSU_SRQ_S0_ALLOC,Per thread - use edge detect to count allocates On a per thread basis, level signal indicating Slot 0 is valid. By instrumenting a single slot we can calculate service time for that slot. Previous machines required a separate signal indicating the slot was allocated. Because any signal can be routed to any counter in P8, we can count level in one PMC and edge detect in another PMC using the same signal ##000000D09D 0.0 #327,v,g,n,n,n,PM_LSU_SRQ_S0_VALID,Slot 0 of SRQ valid ##000000D09C Slot 0 of SRQ validSRQ slot 0 valid #328,u,g,n,n,n,PM_LSU_SRQ_S39_ALLOC,SRQ slot 39 was released ##000000F093 0.0 #329,u,g,n,n,n,PM_LSU_SRQ_S39_VALID,SRQ slot 39 was busy ##000000F092 SRQ slot 39 was busy42 #330,u,g,n,n,n,PM_LSU_SRQ_SYNC,A sync in the SRQ ended ##000000D09B 0.0 #331,u,g,n,n,n,PM_LSU_SRQ_SYNC_CYC,A sync is in the SRQ (edge detect to count) ##000000D09A A sync is in the SRQ (edge detect to count)SRQ sync duration #332,u,g,n,n,n,PM_LSU_STORE_REJECT,Store reject on either pipe ##000000F084 LSU #333,u,g,n,n,n,PM_LSU_TWO_TABLEWALK_CYC,Cycles when two tablewalks pending on this thread ##000000D0A6 Cycles when two tablewalks pending on this thread42 #334,u,g,n,n,n,PM_LWSYNC,threaded version, IC Misses where we got EA dir hit but no sector valids were on. ICBI took line out ##0000005094 threaded version, IC Misses where we got EA dir hit but no sector valids were on. ICBI took line out #335,u,g,n,n,n,PM_LWSYNC_HELD,LWSYNC held at dispatch ##000000209A LWSYNC held at dispatch #336,u,g,n,n,n,PM_MEM_LOC_THRESH_IFU,Local Memory above threshold for IFU speculation control ##0000010058 Local Memory above threshold for IFU speculation control. #337,u,g,n,n,n,PM_MEM_LOC_THRESH_LSU_MED,Local memory above theshold for data prefetch ##000001C05E Local memory above theshold for data prefetch. #338,u,g,n,s,n,PM_MEM_READ,Reads from Memory from this lpar (includes demand data/inst/xlate). Includes L4 ##0000010056 Reads from Memory from this lpar (includes data/inst/xlate/l1prefetch/inst prefetch). #339,v,g,n,n,m,PM_MRK_BR_CMPL,Branch Instruction completed ##000001016E Branch Instruction completed. #340,v,g,n,n,m,PM_MRK_BR_TAKEN_CMPL,Marked Branch Taken completed ##00000101E2 Marked Branch Taken. #341,v,g,n,n,m,PM_MRK_DATA_FROM_L2,The processor's data cache was reloaded from local core's L2 due to a marked load ##000001D142 The processor's data cache was reloaded from local core's L2 due to a marked load. #342,v,g,n,n,m,PM_MRK_DATA_FROM_L2MISS,Data cache reload L2 miss ##000001D14E Data cache reload L2 miss. #343,v,g,n,n,m,PM_MRK_DATA_FROM_L2_NO_CONFLICT,The processor's data cache was reloaded from local core's L2 without conflict due to a marked load ##000001D140 The processor's data cache was reloaded from local core's L2 without conflict due to a marked load. #344,v,g,n,n,m,PM_MRK_DATA_FROM_L31_SHR,The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to a marked load ##000001D146 The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to a marked load. #345,v,g,n,n,m,PM_MRK_DATA_FROM_L3_NO_CONFLICT,The processor's data cache was reloaded from local core's L3 without conflict due to a marked load ##000001D144 The processor's data cache was reloaded from local core's L3 without conflict due to a marked load. #346,v,g,n,n,m,PM_MRK_DATA_FROM_LL4,The processor's data cache was reloaded from the local chip's L4 cache due to a marked load ##000001D14C The processor's data cache was reloaded from the local chip's L4 cache due to a marked load. #347,v,g,n,n,m,PM_MRK_DATA_FROM_ON_CHIP_CACHE,The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a marked load ##000001D148 The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a marked load. #348,v,g,n,n,m,PM_MRK_DATA_FROM_RL2L3_SHR,The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load ##000001D14A The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load. #349,v,g,n,n,m,PM_MRK_DERAT_MISS_4K,Marked Data ERAT Miss (Data TLB Access) page size 4K ##000001D156 Marked Data ERAT Miss (Data TLB Access) page size 4K. #350,u,g,n,n,m,PM_MRK_DPTEG_FROM_L2,A Page Table Entry was loaded into the TLB from local core's L2 due to a marked data side request ##000001F142 A Page Table Entry was loaded into the TLB from local core's L2 due to a marked data side request. #351,u,g,n,n,m,PM_MRK_DPTEG_FROM_L2MISS,A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a marked data side request ##000001F14E A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a marked data side request. #352,u,g,n,n,m,PM_MRK_DPTEG_FROM_L2_NO_CONFLICT,A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a marked data side request ##000001F140 A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a marked data side request. #353,u,g,n,n,m,PM_MRK_DPTEG_FROM_L31_SHR,A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a marked data side request ##000001F146 A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a marked data side request. #354,u,g,n,n,m,PM_MRK_DPTEG_FROM_L3_NO_CONFLICT,A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a marked data side request ##000001F144 A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a marked data side request. #355,u,g,n,n,m,PM_MRK_DPTEG_FROM_LL4,A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a marked data side request ##000001F14C A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a marked data side request. #356,u,g,n,n,m,PM_MRK_DPTEG_FROM_ON_CHIP_CACHE,A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a marked data side request ##000001F148 A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a marked data side request. #357,u,g,n,n,m,PM_MRK_DPTEG_FROM_RL2L3_SHR,A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request ##000001F14A A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request. #358,u,g,n,n,m,PM_MRK_DTLB_MISS_16G,Marked Data TLB Miss page size 16G ##000001D158 Marked Data TLB Miss page size 16G. #359,u,g,n,n,m,PM_MRK_FAB_RSP_RD_T_INTV,Sampled Read got a T intervention ##000001015E Sampled Read got a T intervention. #360,v,g,n,n,m,PM_MRK_FIN_STALL_CYC,Marked instruction Finish Stall cycles (marked finish after NTC) (use edge detect to count ) ##000001013C Marked instruction Finish Stall cycles (marked finish after NTC) (use edge detect to count #). #361,v,g,n,n,m,PM_MRK_INST_DISP,The thread has dispatched a randomly sampled marked instruction ##00000101E0 Marked Instruction dispatched. #362,v,g,n,n,m,PM_MRK_INST_ISSUED,Marked instruction issued ##0000010132 Marked instruction issued. #363,v,g,n,n,m,PM_MRK_L1_ICACHE_MISS,sampled Instruction suffered an icache Miss ##00000101E4 Marked L1 Icache Miss. #364,v,g,n,n,m,PM_MRK_L1_RELOAD_VALID,Marked demand reload ##00000101EA Marked demand reload. #365,u,g,n,n,m,PM_MRK_LD_MISS_EXPOSED,Marked Load exposed Miss (exposed period ended) ##000001013F Marked Load exposed Miss (use edge detect to count #) #366,v,g,n,n,m,PM_MRK_LD_MISS_EXPOSED_CYC,Marked Load exposed Miss cycles ##000001013E Marked Load exposed Miss (use edge detect to count #). #367,u,g,n,n,m,PM_MRK_LSU_FLUSH,Flush: (marked) : All Cases ##000000D180 Flush: (marked) : All Cases42 #368,u,g,n,n,m,PM_MRK_LSU_FLUSH_LRQ,Flush: (marked) LRQ ##000000D188 Flush: (marked) LRQMarked LRQ flushes #369,u,g,n,n,m,PM_MRK_LSU_FLUSH_SRQ,Flush: (marked) SRQ ##000000D18A Flush: (marked) SRQMarked SRQ lhs flushes #370,u,g,n,n,m,PM_MRK_LSU_FLUSH_ULD,Flush: (marked) Unaligned Load ##000000D184 Flush: (marked) Unaligned LoadMarked unaligned load flushes #371,u,g,n,n,m,PM_MRK_LSU_FLUSH_UST,Flush: (marked) Unaligned Store ##000000D186 Flush: (marked) Unaligned StoreMarked unaligned store flushes #372,u,g,n,n,m,PM_MRK_RUN_CYC,Marked run cycles ##000001D15E Marked run cycles. #373,u,g,n,n,m,PM_MRK_SRC_PREF_TRACK_EFF,Marked src pref track was effective ##000001D15A Marked src pref track was effective. #374,u,g,n,n,m,PM_MRK_SRC_PREF_TRACK_MOD_L2,Marked src Prefetch Tracked was moderate (source L2) ##000001D15C Marked src Prefetch Tracked was moderate (source L2). #375,v,g,n,n,m,PM_MRK_ST_CMPL,marked store completed and sent to nest ##0000010134 Marked store completed. #376,u,g,n,n,m,PM_MRK_ST_L2DISP_TO_CMPL_CYC,cycles from L2 rc disp to l2 rc completion ##000001F150 cycles from L2 rc disp to l2 rc completion. #377,u,g,n,n,m,PM_MRK_TGT_PREF_TRACK_EFF,Marked target pref track was effective ##000001C15A Marked target pref track was effective. #378,u,g,n,n,m,PM_MRK_TGT_PREF_TRACK_MOD_L2,Marked target Prefetch Tracked was moderate (source L2) ##000001C15C Marked target Prefetch Tracked was moderate (source L2). #379,v,g,n,n,n,PM_NESTED_TEND,Completion time nested tend ##00000020B0 Completion time nested tend #380,u,g,n,n,n,PM_NON_FAV_TBEGIN,Dispatch time non favored tbegin ##00000020B6 Dispatch time non favored tbegin #381,v,g,n,n,n,PM_OUTER_TBEGIN,Completion time outer tbegin ##00000020AC Completion time outer tbegin #382,v,g,n,n,n,PM_OUTER_TEND,Completion time outer tend ##00000020AE Completion time outer tend #383,v,g,n,n,n,PM_PMC2_SAVED,PMC2 Rewind Value saved ##0000010022 PMC2 Rewind Value saved (matched condition). #384,v,g,n,n,n,PM_PMC4_OVERFLOW,Overflow from counter 4 ##0000010010 Overflow from counter 4. #385,v,g,n,n,n,PM_PMC4_REWIND,PMC4 Rewind Event ##0000010020 PMC4 Rewind Event (did not match condition). #386,v,g,n,n,n,PM_PMC5_OVERFLOW,Overflow from counter 5 ##0000010024 Overflow from counter 5. #387,u,g,n,n,n,PM_PREF_TRACK_EFF,Prefetch Tracked was effective ##000001005A Prefetch Tracked was effective. #388,u,g,n,n,n,PM_PREF_TRACK_MOD_L2,Prefetch Tracked was moderate (source L2) ##000001005C Prefetch Tracked was moderate (source L2). #389,u,g,n,n,n,PM_PTE_PREFETCH,PTE prefetches ##000000E084 PTE prefetches42 #390,u,g,n,n,n,PM_PUMP_CPRED,Pump prediction correct. Counts across all types of pumps for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) ##0000010054 Pump prediction correct. Counts across all types of pumpsfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate). #391,u,g,n,n,n,PM_RC0_ALLOC,RC mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point) ##0000016081 0.0 #392,v,g,n,s,n,PM_RC0_BUSY,RC mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point) ##0000016080 RC mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point) #393,u,g,n,n,m,PM_RC_LIFETIME_EXC_256,Number of times the RC machine for a sampled instruction was active for more than 256 cycles ##DE200101E8 Threshold counter exceed a count of 256 #394,u,g,n,n,n,PM_RUN_CYC_SMT2_SPLIT_MODE,Cycles run latch is set and core is in SMT2-split mode ##000001006A Cycles run latch is set and core is in SMT2-split mode. #395,v,g,n,n,n,PM_RUN_CYC_ST_MODE,Cycles run latch is set and core is in ST mode ##000001006C Cycles run latch is set and core is in ST mode. #396,v,g,n,n,n,PM_RUN_SPURR,Run SPURR ##0000010008 Run SPURR. #397,u,g,n,n,n,PM_SEC_ERAT_HIT,secondary ERAT Hit ##000000F082 secondary ERAT Hit42 #398,u,g,n,n,n,PM_SHL_CREATED,Store-Hit-Load Table Entry Created ##000000508C Store-Hit-Load Table Entry Created #399,u,g,n,n,n,PM_SHL_ST_CONVERT,Store-Hit-Load Table Read Hit with entry Enabled ##000000508E Store-Hit-Load Table Read Hit with entry Enabled #400,u,g,n,n,n,PM_SHL_ST_DISABLE,Store-Hit-Load Table Read Hit with entry Disabled (entry was disabled due to the entry shown to not prevent the flush) ##0000005090 Store-Hit-Load Table Read Hit with entry Disabled (entry was disabled due to the entry shown to not prevent the flush) #401,v,g,n,s,n,PM_SNOOP_TLBIE,TLBIE snoop ##000000D0B2 TLBIE snoopSnoop TLBIE #402,v,g,n,n,n,PM_STALL_END_GCT_EMPTY,Count ended because GCT went empty ##0000010028 Count ended because GCT went empty. #403,u,g,n,s,n,PM_ST_CAUSED_FAIL,Non TM St caused any thread to fail ##0000717080 Non TM St caused any thread to fail #404,v,g,n,n,n,PM_STCX_FAIL,stcx failed ##000001E058 stcx failed . #405,v,g,n,n,n,PM_STCX_LSU,STCX executed reported at sent to nest ##000000C090 STCX executed reported at sent to nest42 #406,v,g,n,n,n,PM_SUSPENDED,Counter OFF ##0000010000 Counter OFF. #407,u,g,n,s,n,PM_SWAP_CANCEL,SWAP cancel , rtag not available ##0000003090 SWAP cancel , rtag not available #408,u,g,n,s,n,PM_SWAP_CANCEL_GPR,SWAP cancel , rtag not available for gpr ##0000003092 SWAP cancel , rtag not available for gpr #409,v,g,n,s,n,PM_SWAP_COMPLETE,swap cast in completed ##000000308C swap cast in completed #410,v,g,n,s,n,PM_SWAP_COMPLETE_GPR,swap cast in completed fpr gpr ##000000308E swap cast in completed fpr gpr #411,u,g,n,n,m,PM_SYNC_MRK_BR_LINK,Marked Branch and link branch that can cause a synchronous interrupt ##0000015152 Marked Branch and link branch that can cause a synchronous interrupt. #412,u,g,n,n,m,PM_SYNC_MRK_BR_MPRED,Marked Branch mispredict that can cause a synchronous interrupt ##000001515C Marked Branch mispredict that can cause a synchronous interrupt. #413,u,g,n,n,m,PM_SYNC_MRK_FX_DIVIDE,Marked fixed point divide that can cause a synchronous interrupt ##0000015156 Marked fixed point divide that can cause a synchronous interrupt. #414,u,g,n,n,m,PM_SYNC_MRK_L2HIT,Marked L2 Hits that can throw a synchronous interrupt ##0000015158 Marked L2 Hits that can throw a synchronous interrupt. #415,u,g,n,n,m,PM_SYNC_MRK_L2MISS,Marked L2 Miss that can throw a synchronous interrupt ##000001515A Marked L2 Miss that can throw a synchronous interrupt. #416,u,g,n,n,m,PM_SYNC_MRK_L3MISS,Marked L3 misses that can throw a synchronous interrupt ##0000015154 Marked L3 misses that can throw a synchronous interrupt. #417,u,g,n,n,m,PM_SYNC_MRK_PROBE_NOP,Marked probeNops which can cause synchronous interrupts ##0000015150 Marked probeNops which can cause synchronous interrupts. #418,v,g,n,n,n,PM_TABLEWALK_CYC,Cycles when a tablewalk (I or D) is active ##0000010026 Tablewalk Active. #419,u,g,n,n,n,PM_TABLEWALK_CYC_PREF,tablewalk qualified for pte prefetches ##000000E086 tablewalk qualified for pte prefetches42 #420,u,g,n,n,n,PM_TABORT_TRECLAIM,Completion time tabortnoncd, tabortcd, treclaim ##00000020B2 Completion time tabortnoncd, tabortcd, treclaim #421,u,g,n,n,n,PM_TEND_PEND_CYC,TEND latency per thread ##000000E0BA TEND latency per thread42 #422,u,g,n,s,n,PM_THRD_GRP_CMPL_BOTH_CYC,Cycles group completed on both completion slots by any thread ##0000010012 Two threads finished same cycle (gated by run latch). #423,u,g,n,n,n,PM_THRD_PRIO_0_1_CYC, Cycles thread running at priority level 0 or 1 ##00000040BC Cycles thread running at priority level 0 or 1 #424,u,g,n,n,n,PM_THRD_PRIO_2_3_CYC, Cycles thread running at priority level 2 or 3 ##00000040BE Cycles thread running at priority level 2 or 3 #425,u,g,n,n,n,PM_THRD_PRIO_4_5_CYC, Cycles thread running at priority level 4 or 5 ##0000005080 Cycles thread running at priority level 4 or 5 #426,u,g,n,n,n,PM_THRD_PRIO_6_7_CYC, Cycles thread running at priority level 6 or 7 ##0000005082 Cycles thread running at priority level 6 or 7 #427,u,g,n,n,n,PM_THRD_REBAL_CYC,cycles rebalance was active ##0000003098 cycles rebalance was active #428,v,g,t,n,m,PM_THRESH_EXC_256,Threshold counter exceed a count of 256 ##00000101E8 Threshold counter exceed a count of 256. #429,v,g,t,n,m,PM_THRESH_EXC_4096,Threshold counter exceed a count of 4096 ##00000101E6 Threshold counter exceed a count of 4096. #430,v,g,t,n,m,PM_THRESH_MET,threshold exceeded ##00000101EC threshold exceeded. #431,v,g,n,n,n,PM_TM_BEGIN_ALL,Tm any tbegin ##00000020B8 Tm any tbegin #432,u,g,n,s,n,PM_TM_CAM_OVERFLOW,l3 tm cam overflow during L2 co of SC ##0000318082 l3 tm cam overflow during L2 co of SC #433,v,g,n,n,n,PM_TM_END_ALL,Tm any tend ##00000020BA Tm any tend #434,u,g,n,n,n,PM_TM_FAIL_CONF_NON_TM,TEXAS fail reason @ completion ##0000003086 TEXAS fail reason @ completion #435,u,g,n,n,n,PM_TM_FAIL_CON_TM,TEXAS fail reason @ completion ##0000003088 TEXAS fail reason @ completion #436,u,g,n,n,n,PM_TM_FAIL_DISALLOW,TM fail disallow ##000000E0B2 TM fail disallow42 #437,u,g,n,n,n,PM_TM_FAIL_FOOTPRINT_OVERFLOW,TEXAS fail reason @ completion ##0000003084 TEXAS fail reason @ completion #438,u,g,n,n,n,PM_TM_FAIL_NON_TX_CONFLICT,Non transactional conflict from LSU whtver gets repoted to texas ##000000E0B8 Non transactional conflict from LSU whtver gets repoted to texas42 #439,u,g,n,n,n,PM_TM_FAIL_SELF,TEXAS fail reason @ completion ##000000308A TEXAS fail reason @ completion #440,u,g,n,n,n,PM_TM_FAIL_TLBIE,TLBIE hit bloom filter ##000000E0B4 TLBIE hit bloom filter42 #441,u,g,n,n,n,PM_TM_FAIL_TX_CONFLICT,Transactional conflict from LSU, whatever gets reported to texas ##000000E0B6 Transactional conflict from LSU, whatever gets reported to texas 42 #442,u,g,n,s,n,PM_TM_LD_CAUSED_FAIL,Non TM Ld caused any thread to fail ##0000717082 Non TM Ld caused any thread to fail #443,u,g,n,s,n,PM_TM_SC_CO,l3 castout tm Sc line ##0000318080 l3 castout tm Sc line #444,v,g,n,n,n,PM_TM_TBEGIN,Tm nested tbegin ##00000020BC Tm nested tbegin #445,u,g,n,n,n,PM_TM_TRANS_RUN_CYC,run cycles in transactional state ##0000010060 run cycles in transactional state. #446,u,g,n,n,n,PM_TM_TRESUME,Tm resume ##0000003080 Tm resume #447,u,g,n,n,n,PM_TM_TSUSPEND,Tm suspend ##00000020BE Tm suspend #448,u,g,n,n,n,PM_UP_PREF_L3,Micropartition prefetch ##000000E08C Micropartition prefetch42 #449,u,g,n,n,n,PM_UP_PREF_POINTER,Micrpartition pointer prefetches ##000000E08E Micrpartition pointer prefetches42 #450,u,g,n,n,n,PM_VSU0_16FLOP,Sixteen flops operation (SP vector versions of fdiv,fsqrt) ##000000A0A4 Sixteen flops operation (SP vector versions of fdiv,fsqrt) #451,v,g,n,n,n,PM_VSU0_1FLOP,one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished ##000000A080 one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finishedDecode into 1,2,4 FLOP according to instr IOP, multiplied by #vector elements according to route( eg x1, x2, x4) Only if instr sends finish to ISU #452,u,g,n,n,n,PM_VSU0_2FLOP,two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) ##000000A098 two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) #453,u,g,n,n,n,PM_VSU0_4FLOP,four flops operation (scalar fdiv, fsqrt, DP vector version of fmadd, fnmadd, fmsub, fnmsub, SP vector versions of single flop instructions) ##000000A09C four flops operation (scalar fdiv, fsqrt, DP vector version of fmadd, fnmadd, fmsub, fnmsub, SP vector versions of single flop instructions) #454,u,g,n,n,n,PM_VSU0_8FLOP,eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) ##000000A0A0 eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) #455,u,g,n,n,n,PM_VSU0_COMPLEX_ISSUED,Complex VMX instruction issued ##000000B0A4 Complex VMX instruction issued #456,u,g,n,n,n,PM_VSU0_CY_ISSUED,Cryptographic instruction RFC02196 Issued ##000000B0B4 Cryptographic instruction RFC02196 Issued #457,u,g,n,n,n,PM_VSU0_DD_ISSUED,64BIT Decimal Issued ##000000B0A8 64BIT Decimal Issued #458,u,g,n,n,n,PM_VSU0_DP_2FLOP,DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg ##000000A08C DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg #459,u,g,n,n,n,PM_VSU0_DP_FMA,DP vector version of fmadd,fnmadd,fmsub,fnmsub ##000000A090 DP vector version of fmadd,fnmadd,fmsub,fnmsub #460,u,g,n,n,n,PM_VSU0_DP_FSQRT_FDIV,DP vector versions of fdiv,fsqrt ##000000A094 DP vector versions of fdiv,fsqrt #461,u,g,n,n,n,PM_VSU0_DQ_ISSUED,128BIT Decimal Issued ##000000B0AC 128BIT Decimal Issued #462,u,g,n,n,n,PM_VSU0_EX_ISSUED,Direct move 32/64b VRFtoGPR RFC02206 Issued ##000000B0B0 Direct move 32/64b VRFtoGPR RFC02206 Issued #463,u,g,n,n,n,PM_VSU0_FIN,VSU0 Finished an instruction ##000000A0BC VSU0 Finished an instruction #464,u,g,n,n,n,PM_VSU0_FMA,two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only! ##000000A084 two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only! #465,u,g,n,n,n,PM_VSU0_FPSCR,Move to/from FPSCR type instruction issued on Pipe 0 ##000000B098 Move to/from FPSCR type instruction issued on Pipe 0 #466,u,g,n,n,n,PM_VSU0_FSQRT_FDIV,four flops operation (fdiv,fsqrt) Scalar Instructions only! ##000000A088 four flops operation (fdiv,fsqrt) Scalar Instructions only! #467,u,g,n,n,n,PM_VSU0_PERMUTE_ISSUED,Permute VMX Instruction Issued ##000000B090 Permute VMX Instruction Issued #468,u,g,n,n,n,PM_VSU0_SCALAR_DP_ISSUED,Double Precision scalar instruction issued on Pipe0 ##000000B088 Double Precision scalar instruction issued on Pipe0 #469,u,g,n,n,n,PM_VSU0_SIMPLE_ISSUED,Simple VMX instruction issued ##000000B094 Simple VMX instruction issued #470,u,g,n,n,n,PM_VSU0_SINGLE,FPU single precision ##000000A0A8 FPU single precision #471,u,g,n,n,n,PM_VSU0_SQ,Store Vector Issued ##000000B09C Store Vector Issued #472,u,g,n,n,n,PM_VSU0_STF,FPU store (SP or DP) issued on Pipe0 ##000000B08C FPU store (SP or DP) issued on Pipe0 #473,u,g,n,n,n,PM_VSU0_VECTOR_DP_ISSUED,Double Precision vector instruction issued on Pipe0 ##000000B080 Double Precision vector instruction issued on Pipe0 #474,u,g,n,n,n,PM_VSU0_VECTOR_SP_ISSUED,Single Precision vector instruction issued (executed) ##000000B084 Single Precision vector instruction issued (executed) #475,u,g,n,n,n,PM_VSU1_16FLOP,Sixteen flops operation (SP vector versions of fdiv,fsqrt) ##000000A0A6 Sixteen flops operation (SP vector versions of fdiv,fsqrt) #476,v,g,n,n,n,PM_VSU1_1FLOP,one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished ##000000A082 one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished #477,u,g,n,n,n,PM_VSU1_2FLOP,two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) ##000000A09A two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) #478,u,g,n,n,n,PM_VSU1_4FLOP,four flops operation (scalar fdiv, fsqrt, DP vector version of fmadd, fnmadd, fmsub, fnmsub, SP vector versions of single flop instructions) ##000000A09E four flops operation (scalar fdiv, fsqrt, DP vector version of fmadd, fnmadd, fmsub, fnmsub, SP vector versions of single flop instructions) #479,u,g,n,n,n,PM_VSU1_8FLOP,eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) ##000000A0A2 eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) #480,u,g,n,n,n,PM_VSU1_COMPLEX_ISSUED,Complex VMX instruction issued ##000000B0A6 Complex VMX instruction issued #481,u,g,n,n,n,PM_VSU1_CY_ISSUED,Cryptographic instruction RFC02196 Issued ##000000B0B6 Cryptographic instruction RFC02196 Issued #482,u,g,n,n,n,PM_VSU1_DD_ISSUED,64BIT Decimal Issued ##000000B0AA 64BIT Decimal Issued #483,u,g,n,n,n,PM_VSU1_DP_2FLOP,DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg ##000000A08E DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg #484,u,g,n,n,n,PM_VSU1_DP_FMA,DP vector version of fmadd,fnmadd,fmsub,fnmsub ##000000A092 DP vector version of fmadd,fnmadd,fmsub,fnmsub #485,u,g,n,n,n,PM_VSU1_DP_FSQRT_FDIV,DP vector versions of fdiv,fsqrt ##000000A096 DP vector versions of fdiv,fsqrt #486,u,g,n,n,n,PM_VSU1_DQ_ISSUED,128BIT Decimal Issued ##000000B0AE 128BIT Decimal Issued #487,u,g,n,n,n,PM_VSU1_EX_ISSUED,Direct move 32/64b VRFtoGPR RFC02206 Issued ##000000B0B2 Direct move 32/64b VRFtoGPR RFC02206 Issued #488,u,g,n,n,n,PM_VSU1_FIN,VSU1 Finished an instruction ##000000A0BE VSU1 Finished an instruction #489,u,g,n,n,n,PM_VSU1_FMA,two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only! ##000000A086 two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only! #490,u,g,n,n,n,PM_VSU1_FPSCR,Move to/from FPSCR type instruction issued on Pipe 0 ##000000B09A Move to/from FPSCR type instruction issued on Pipe 0 #491,u,g,n,n,n,PM_VSU1_FSQRT_FDIV,four flops operation (fdiv,fsqrt) Scalar Instructions only! ##000000A08A four flops operation (fdiv,fsqrt) Scalar Instructions only! #492,u,g,n,n,n,PM_VSU1_PERMUTE_ISSUED,Permute VMX Instruction Issued ##000000B092 Permute VMX Instruction Issued #493,u,g,n,n,n,PM_VSU1_SCALAR_DP_ISSUED,Double Precision scalar instruction issued on Pipe1 ##000000B08A Double Precision scalar instruction issued on Pipe1 #494,u,g,n,n,n,PM_VSU1_SIMPLE_ISSUED,Simple VMX instruction issued ##000000B096 Simple VMX instruction issued #495,u,g,n,n,n,PM_VSU1_SINGLE,FPU single precision ##000000A0AA FPU single precision #496,u,g,n,n,n,PM_VSU1_SQ,Store Vector Issued ##000000B09E Store Vector Issued #497,u,g,n,n,n,PM_VSU1_STF,FPU store (SP or DP) issued on Pipe1 ##000000B08E FPU store (SP or DP) issued on Pipe1 #498,u,g,n,n,n,PM_VSU1_VECTOR_DP_ISSUED,Double Precision vector instruction issued on Pipe1 ##000000B082 Double Precision vector instruction issued on Pipe1 #499,u,g,n,n,n,PM_VSU1_VECTOR_SP_ISSUED,Single Precision vector instruction issued (executed) ##000000B086 Single Precision vector instruction issued (executed) #500,v,g,n,n,n,PM_VSU_1FLOP,one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished ##000000A880 one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished #501,v,g,n,n,n,PM_VSU_2FLOP,two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) ##000000A898 two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) #502,v,g,n,n,n,PM_VSU_4FLOP,four flops operation (scalar fdiv, fsqrt, DP vector version of fmadd, fnmadd, fmsub, fnmsub, SP vector versions of single flop instructions) ##000000A89C four flops operation (scalar fdiv, fsqrt, DP vector version of fmadd, fnmadd, fmsub, fnmsub, SP vector versions of single flop instructions) #503,v,g,n,n,n,PM_VSU_8FLOP,eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) ##000000A8A0 eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) #504,v,g,n,n,n,PM_VSU_FMA,two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only ##000000A884 two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only #505,v,g,n,n,n,PM_VSU_FSQRT_FDIV,four flops operation (fdiv,fsqrt) Scalar Instructions only ##000000A888 four flops operation (fdiv,fsqrt) Scalar Instructions only $$$$$$$$ { counter 2 } #0,u,g,n,s,n,PM_2LPAR_CYC,Cycles in 2-lpar mode. Threads 0-3 belong to Lpar0 and threads 4-7 belong to Lpar1 ##000002006E Number of cycles in 2 lpar mode. #1,u,g,n,n,n,PM_ALL_GRP_PUMP_CPRED,Initial and Final Pump Scope and data sourced across this scope was group pump for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate) ##0000520050 Initial and Final Pump Scope and data sourced across this scope was group pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) #2,u,g,n,n,n,PM_ALL_GRP_PUMP_MPRED,Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate) ##0000620052 Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro #3,v,g,n,n,n,PM_BACK_BR_CMPL,Branch instruction completed with a target address less than current instruction address ##000002505E Branch instruction completed with a target address less than current instruction address. #4,u,g,n,n,n,PM_BANK_CONFLICT,Read blocked due to interleave conflict. The ifar logic will detect an interleave conflict and kill the data that was read that cycle. ##0000004082 Read blocked due to interleave conflict. The ifar logic will detect an interleave conflict and kill the data that was read that cycle. #5,v,g,n,n,n,PM_BR_2PATH,two path branch ##0000020036 two path branch. #6,v,g,n,n,n,PM_BR_BC_8,Pairable BC+8 branch that has not been converted to a Resolve Finished in the BRU pipeline ##0000005086 Pairable BC+8 branch that has not been converted to a Resolve Finished in the BRU pipeline #7,v,g,n,n,n,PM_BR_BC_8_CONV,Pairable BC+8 branch that was converted to a Resolve Finished in the BRU pipeline. ##0000005084 Pairable BC+8 branch that was converted to a Resolve Finished in the BRU pipeline. #8,v,g,n,n,n,PM_BR_MPRED_CCACHE,Conditional Branch Completed that was Mispredicted due to the Count Cache Target Prediction ##00000040AC Conditional Branch Completed that was Mispredicted due to the Count Cache Target Prediction #9,v,g,n,n,n,PM_BR_MPRED_CR,Conditional Branch Completed that was Mispredicted due to the BHT Direction Prediction (taken/not taken). ##00000040B8 Conditional Branch Completed that was Mispredicted due to the BHT Direction Prediction (taken/not taken). #10,u,g,n,n,n,PM_BR_MPRED_LSTACK,Conditional Branch Completed that was Mispredicted due to the Link Stack Target Prediction ##00000040AE Conditional Branch Completed that was Mispredicted due to the Link Stack Target Prediction #11,u,g,n,n,n,PM_BR_MPRED_TA,Conditional Branch Completed that was Mispredicted due to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that resolved Taken set this event. ##00000040BA Conditional Branch Completed that was Mispredicted due to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that resolved Taken set this event. #12,v,g,n,n,n,PM_BR_PRED_BR0,Conditional Branch Completed on BR0 (1st branch in group) in which the HW predicted the Direction or Target ##000000409C Conditional Branch Completed on BR0 (1st branch in group) in which the HW predicted the Direction or Target #13,v,g,n,n,n,PM_BR_PRED_BR1,Conditional Branch Completed on BR1 (2nd branch in group) in which the HW predicted the Direction or Target. Note: BR1 can only be used in Single Thread Mode. In all of the SMT modes, only one branch can complete, thus BR1 is unused. ##000000409E Conditional Branch Completed on BR1 (2nd branch in group) in which the HW predicted the Direction or Target. Note: BR1 can only be used in Single Thread Mode. In all of the SMT modes, only one branch can complete, thus BR1 is unused. #14,u,g,n,n,n,PM_BR_PRED_BR_CMPL,Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred(0) OR if_pc_br0_br_pred(1). ##000000489C IFU #15,v,g,n,n,n,PM_BR_PRED_CCACHE_BR0,Conditional Branch Completed on BR0 that used the Count Cache for Target Prediction ##00000040A4 Conditional Branch Completed on BR0 that used the Count Cache for Target Prediction #16,v,g,n,n,n,PM_BR_PRED_CCACHE_BR1,Conditional Branch Completed on BR1 that used the Count Cache for Target Prediction ##00000040A6 Conditional Branch Completed on BR1 that used the Count Cache for Target Prediction #17,u,g,n,n,n,PM_BR_PRED_CCACHE_CMPL,Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred(0) AND if_pc_br0_pred_type. ##00000048A4 IFU #18,v,g,n,n,n,PM_BR_PRED_CR_BR0,Conditional Branch Completed on BR0 that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and branches ##00000040B0 Conditional Branch Completed on BR0 that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and bra #19,v,g,n,n,n,PM_BR_PRED_CR_BR1,Conditional Branch Completed on BR1 that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and branches ##00000040B2 Conditional Branch Completed on BR1 that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and bra #20,u,g,n,n,n,PM_BR_PRED_CR_CMPL,Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred(1)='1'. ##00000048B0 IFU #21,u,g,n,n,n,PM_BR_PRED_LSTACK_BR0,Conditional Branch Completed on BR0 that used the Link Stack for Target Prediction ##00000040A8 Conditional Branch Completed on BR0 that used the Link Stack for Target Prediction #22,u,g,n,n,n,PM_BR_PRED_LSTACK_BR1,Conditional Branch Completed on BR1 that used the Link Stack for Target Prediction ##00000040AA Conditional Branch Completed on BR1 that used the Link Stack for Target Prediction #23,u,g,n,n,n,PM_BR_PRED_LSTACK_CMPL,Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred(0) AND (not if_pc_br0_pred_type). ##00000048A8 IFU #24,u,g,n,n,n,PM_BR_PRED_TA_BR0,Conditional Branch Completed on BR0 that had its target address predicted. Only XL-form branches set this event. ##00000040B4 Conditional Branch Completed on BR0 that had its target address predicted. Only XL-form branches set this event. #25,u,g,n,n,n,PM_BR_PRED_TA_BR1,Conditional Branch Completed on BR1 that had its target address predicted. Only XL-form branches set this event. ##00000040B6 Conditional Branch Completed on BR1 that had its target address predicted. Only XL-form branches set this event. #26,u,g,n,n,n,PM_BR_PRED_TA_CMPL,Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred(0)='1'. ##00000048B4 IFU #27,u,g,n,n,n,PM_BR_TAKEN_CMPL,New event for Branch Taken ##00000200FA Branch Taken. #28,v,g,n,n,n,PM_BR_UNCOND_BR0,Unconditional Branch Completed on BR0. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was coverted to a Resolve. ##00000040A0 Unconditional Branch Completed on BR0. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was coverted to a Resolve. #29,v,g,n,n,n,PM_BR_UNCOND_BR1,Unconditional Branch Completed on BR1. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was coverted to a Resolve. ##00000040A2 Unconditional Branch Completed on BR1. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was coverted to a Resolve. #30,u,g,n,n,n,PM_BR_UNCOND_CMPL,Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred=00 AND if_pc_br0_completed. ##00000048A0 IFU #31,v,g,n,s,n,PM_CASTOUT_ISSUED,Castouts issued ##0000003094 Castouts issued #32,v,g,n,s,n,PM_CASTOUT_ISSUED_GPR,Castouts issued GPR ##0000003096 Castouts issued GPR #33,u,g,n,n,n,PM_CLB_HELD,CLB Hold: Any Reason ##0000002090 CLB Hold: Any Reason #34,v,g,n,n,n,PM_CMPLU_STALL_BRU_CRU,Completion stall due to IFU ##000002D018 Completion stall due to IFU. #35,v,g,n,n,n,PM_CMPLU_STALL_DCACHE_MISS,Completion stall by Dcache miss ##000002C012 Completion stall by Dcache miss. #36,v,g,n,n,n,PM_CMPLU_STALL_DMISS_L21_L31,Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3) ##000002C018 Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3). #37,v,g,n,n,n,PM_CMPLU_STALL_DMISS_L2L3,Completion stall by Dcache miss which resolved in L2/L3 ##000002C016 Completion stall by Dcache miss which resolved in L2/L3. #38,v,g,n,n,n,PM_CMPLU_STALL_DMISS_REMOTE,Completion stall by Dcache miss which resolved from remote chip (cache or memory) ##000002C01C Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3). #39,v,g,n,n,n,PM_CMPLU_STALL_FXU,Completion stall due to FXU ##000002D016 Completion stall due to FXU. #40,v,g,n,n,n,PM_CMPLU_STALL_LSU,Completion stall by LSU instruction ##000002C010 Completion stall by LSU instruction. #41,v,g,n,n,n,PM_CMPLU_STALL_NO_NTF,Completion stall due to nop ##000002E01C Completion stall due to nop. #42,v,g,n,n,n,PM_CMPLU_STALL_NTCG_FLUSH,Completion stall due to ntcg flush ##000002E01E Completion stall due to reject (load hit store). #43,v,g,n,n,n,PM_CMPLU_STALL_REJECT_LHS,Completion stall due to reject (load hit store) ##000002C01A Completion stall due to reject (load hit store). #44,v,g,n,n,n,PM_CMPLU_STALL_SCALAR_LONG,Completion stall due to VSU scalar long latency instruction ##000002D010 Completion stall due to VSU scalar long latency instruction. #45,v,g,n,n,n,PM_CMPLU_STALL_STORE,Completion stall by stores this includes store agen finishes in pipe LS0/LS1 and store data finishes in LS2/LS3 ##000002C014 Completion stall by stores. #46,v,g,n,n,n,PM_CMPLU_STALL_VECTOR,Completion stall due to VSU vector instruction ##000002D014 Completion stall due to VSU vector instruction. #47,v,g,n,n,n,PM_CMPLU_STALL_VSU,Completion stall due to VSU instruction ##000002D012 Completion stall due to VSU instruction. #48,u,g,n,s,n,PM_CO_TM_SC_FOOTPRINT,L2 did a cleanifdirty CO to the L3 (ie created an SC line in the L3) ##0000527084 L2 did a cleanifdirty CO to the L3 (ie created an SC line in the L3) #49,v,g,n,n,n,PM_CYC,Cycles ##000002001E Cycles . #50,u,g,n,n,n,PM_DATA_ALL_FROM_L2_MEPF,The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to either demand loads or data prefetch ##000062C040 The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 #51,u,g,n,n,n,PM_DATA_ALL_FROM_L31_MOD,The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to either demand loads or data prefetch ##000062C044 The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 #52,u,g,n,n,n,PM_DATA_ALL_FROM_L3_MEPF,The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to either demand loads or data prefetch ##000062C042 The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 #53,u,g,n,n,n,PM_DATA_ALL_FROM_LMEM,The processor's data cache was reloaded from the local chip's Memory due to either demand loads or data prefetch ##000062C048 The processor's data cache was reloaded from the local chip's Memory due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 #54,u,g,n,n,n,PM_DATA_ALL_FROM_MEMORY,The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to either demand loads or data prefetch ##000062C04C The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 #55,u,g,n,n,n,PM_DATA_ALL_FROM_RL2L3_MOD,The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either demand loads or data prefetch ##000062C046 The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 #56,u,g,n,n,n,PM_DATA_ALL_FROM_RL4,The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to either demand loads or data prefetch ##000062C04A The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 #57,u,g,n,n,n,PM_DATA_ALL_GRP_PUMP_CPRED,Initial and Final Pump Scope was group pump (prediction=correct) for either demand loads or data prefetch ##000062C050 Initial and Final Pump Scope and data sourced across this scope was group pump for a demand load #58,u,g,n,n,n,PM_DATA_ALL_GRP_PUMP_MPRED,Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for either demand loads or data prefetch ##000062C052 Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro #59,v,g,n,n,n,PM_DATA_FROM_L2_MEPF,The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to a demand load ##000002C040 The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. #60,u,g,n,n,n,PM_DATA_FROM_L2MISS,Demand LD - L2 Miss (not L2 hit) ##00000200FE Demand LD - L2 Miss (not L2 hit). #61,v,g,n,n,n,PM_DATA_FROM_L31_MOD,The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to a demand load ##000002C044 The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. #62,v,g,n,n,n,PM_DATA_FROM_L3_MEPF,The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to a demand load ##000002C042 The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. #63,v,g,n,n,n,PM_DATA_FROM_LMEM,The processor's data cache was reloaded from the local chip's Memory due to a demand load ##000002C048 The processor's data cache was reloaded from the local chip's Memory due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. #64,v,g,n,n,n,PM_DATA_FROM_MEMORY,The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a demand load ##000002C04C The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. #65,v,g,n,n,n,PM_DATA_FROM_RL2L3_MOD,The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load ##000002C046 The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. #66,v,g,n,n,n,PM_DATA_FROM_RL4,The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a demand load ##000002C04A The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. #67,u,g,n,n,n,PM_DATA_GRP_PUMP_CPRED,Initial and Final Pump Scope was group pump (prediction=correct) for a demand load ##000002C050 Initial and Final Pump Scope and data sourced across this scope was group pump for a demand load. #68,u,g,n,n,n,PM_DATA_GRP_PUMP_MPRED,Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for a demand load ##000002C052 Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro #69,u,g,n,n,n,PM_DC_COLLISIONS,DATA Cache collisions ##000000E0BC DATA Cache collisions42 #70,u,g,n,n,n,PM_DC_PREF_STREAM_CONF,A demand load referenced a line in an active prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. Combine up + down ##000002E050 A demand load referenced a line in an active prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. Combine up + down. #71,u,g,n,n,n,PM_DERAT_MISS_64K,Data ERAT Miss (Data TLB Access) page size 64K ##000002C054 Data ERAT Miss (Data TLB Access) page size 64K. #72,u,g,n,n,n,PM_DFU,Finish DFU (all finish) ##000000B0BA Finish DFU (all finish) #73,u,g,n,n,n,PM_DFU_DCFFIX,Convert from fixed opcode finish (dcffix,dcffixq) ##000000B0BE Convert from fixed opcode finish (dcffix,dcffixq) #74,u,g,n,n,n,PM_DFU_DENBCD,BCD->DPD opcode finish (denbcd, denbcdq) ##000000B0BC BCD->DPD opcode finish (denbcd, denbcdq) #75,u,g,n,n,n,PM_DFU_MC,Finish DFU multicycle ##000000B0B8 Finish DFU multicycle #76,u,g,n,n,n,PM_DISP_CLB_HELD_BAL,Dispatch/CLB Hold: Balance ##0000002092 Dispatch/CLB Hold: Balance #77,u,g,n,n,n,PM_DISP_CLB_HELD_RES,Dispatch/CLB Hold: Resource ##0000002094 Dispatch/CLB Hold: Resource #78,u,g,n,n,n,PM_DISP_CLB_HELD_SB,Dispatch/CLB Hold: Scoreboard ##00000020A8 Dispatch/CLB Hold: Scoreboard #79,u,g,n,n,n,PM_DISP_CLB_HELD_SYNC,Dispatch/CLB Hold: Sync type instruction ##0000002098 Dispatch/CLB Hold: Sync type instruction #80,v,g,n,n,n,PM_DISP_CLB_HELD_TLBIE,Dispatch Hold: Due to TLBIE ##0000002096 Dispatch Hold: Due to TLBIE #81,u,g,n,n,n,PM_DISP_HELD_IQ_FULL,Dispatch held due to Issue q full ##0000020006 Dispatch held due to Issue q full. #82,u,g,n,n,n,PM_DISP_HOLD_GCT_FULL,Dispatch Hold Due to no space in the GCT ##00000030A6 Dispatch Hold Due to no space in the GCT #83,u,g,n,n,n,PM_DPTEG_FROM_L2_MEPF,A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a data side request ##000002E040 A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a data side request. #84,u,g,n,n,n,PM_DPTEG_FROM_L31_MOD,A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a data side request ##000002E044 A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a data side request. #85,u,g,n,n,n,PM_DPTEG_FROM_L3_MEPF,A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a data side request ##000002E042 A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a data side request. #86,u,g,n,n,n,PM_DPTEG_FROM_LMEM,A Page Table Entry was loaded into the TLB from the local chip's Memory due to a data side request ##000002E048 A Page Table Entry was loaded into the TLB from the local chip's Memory due to a data side request. #87,u,g,n,n,n,PM_DPTEG_FROM_MEMORY,A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a data side request ##000002E04C A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a data side request. #88,u,g,n,n,n,PM_DPTEG_FROM_RL2L3_MOD,A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request ##000002E046 A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request. #89,u,g,n,n,n,PM_DPTEG_FROM_RL4,A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a data side request ##000002E04A A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a data side request. #90,v,g,n,n,n,PM_DSLB_MISS,Data SLB Miss - Total of all segment sizes ##000000D094 Data SLB Miss - Total of all segment sizesData SLB misses #91,u,g,n,n,n,PM_DTLB_MISS_4K,Data TLB Miss page size 4k ##000002C056 Data TLB Miss page size 4k. #92,u,g,n,n,n,PM_EAT_FORCE_MISPRED,XL-form branch was mispredicted due to the predicted target address missing from EAT. The EAT forces a mispredict in this case since there is no predicated target to validate. This is a rare case that may occur when the EAT is full and a branch is issue ##00000050A8 XL-form branch was mispredicted due to the predicted target address missing from EAT. The EAT forces a mispredict in this case since there is no predicated target to validate. This is a rare case that may occur when the EAT is full and a branch is #93,u,g,n,n,n,PM_EAT_FULL_CYC,Cycles No room in EAT ##0000004084 Cycles No room in EATSet on bank conflict and case where no ibuffers available. #94,u,g,n,n,n,PM_EE_OFF_EXT_INT,Ee off and external interrupt ##0000002080 Ee off and external interrupt #95,u,g,n,s,n,PM_EXT_INT,external interrupt ##00000200F8 external interrupt. #96,u,g,n,n,n,PM_FAV_TBEGIN,Dispatch time Favored tbegin ##00000020B4 Dispatch time Favored tbegin #97,u,g,n,n,n,PM_FLOP_SUM_SCALAR,flops summary scalar instructions ##000000A0AE flops summary scalar instructions #98,u,g,n,n,n,PM_FLOP_SUM_VEC,flops summary vector instructions ##000000A0AC flops summary vector instructions #99,u,g,n,n,n,PM_FLUSH_BR_MPRED,Flush caused by branch mispredict ##0000002084 Flush caused by branch mispredict #100,u,g,n,n,n,PM_FLUSH_DISP,Dispatch flush ##0000002082 Dispatch flush #101,u,g,n,n,n,PM_FLUSH_DISP_SB,Dispatch Flush: Scoreboard ##000000208C Dispatch Flush: Scoreboard #102,u,g,n,n,n,PM_FLUSH_DISP_SYNC,Dispatch Flush: Sync ##0000002088 Dispatch Flush: Sync #103,u,g,n,n,n,PM_FLUSH_DISP_TLBIE,Dispatch Flush: TLBIE ##000000208A Dispatch Flush: TLBIE #104,u,g,n,n,n,PM_FLUSH_LSU,Flush initiated by LSU ##000000208E Flush initiated by LSU #105,u,g,n,n,n,PM_FLUSH_PARTIAL,Partial flush ##0000002086 Partial flush #106,u,g,n,n,n,PM_FPU0_FCONV,Convert instruction executed ##000000A0B0 Convert instruction executed #107,u,g,n,n,n,PM_FPU0_FEST,Estimate instruction executed ##000000A0B8 Estimate instruction executed #108,u,g,n,n,n,PM_FPU0_FRSP,Round to single precision instruction executed ##000000A0B4 Round to single precision instruction executed #109,u,g,n,n,n,PM_FPU1_FCONV,Convert instruction executed ##000000A0B2 Convert instruction executed #110,u,g,n,n,n,PM_FPU1_FEST,Estimate instruction executed ##000000A0BA Estimate instruction executed #111,u,g,n,n,n,PM_FPU1_FRSP,Round to single precision instruction executed ##000000A0B6 Round to single precision instruction executed #112,u,g,n,n,n,PM_FUSION_TOC_GRP0_1,One pair of instructions fused with TOC in Group0 ##00000050B0 One pair of instructions fused with TOC in Group0 #113,u,g,n,n,n,PM_FUSION_TOC_GRP0_2,Two pairs of instructions fused with TOCin Group0 ##00000050AE Two pairs of instructions fused with TOCin Group0 #114,u,g,n,n,n,PM_FUSION_TOC_GRP0_3,Three pairs of instructions fused with TOC in Group0 ##00000050AC Three pairs of instructions fused with TOC in Group0 #115,u,g,n,n,n,PM_FUSION_TOC_GRP1_1,One pair of instructions fused with TOX in Group1 ##00000050B2 One pair of instructions fused with TOX in Group1 #116,u,g,n,n,n,PM_FUSION_VSX_GRP0_1,One pair of instructions fused with VSX in Group0 ##00000050B8 One pair of instructions fused with VSX in Group0 #117,u,g,n,n,n,PM_FUSION_VSX_GRP0_2,Two pairs of instructions fused with VSX in Group0 ##00000050B6 Two pairs of instructions fused with VSX in Group0 #118,u,g,n,n,n,PM_FUSION_VSX_GRP0_3,Three pairs of instructions fused with VSX in Group0 ##00000050B4 Three pairs of instructions fused with VSX in Group0 #119,u,g,n,n,n,PM_FUSION_VSX_GRP1_1,One pair of instructions fused with VSX in Group1 ##00000050BA One pair of instructions fused with VSX in Group1 #120,v,g,n,n,n,PM_FXU_BUSY,fxu0 busy and fxu1 busy. ##000002000E fxu0 busy and fxu1 busy.. #121,v,g,n,s,n,PM_GCT_EMPTY_CYC,No itags assigned either thread (GCT Empty) ##0000020008 No itags assigned either thread (GCT Empty). #122,v,g,n,n,n,PM_GCT_MERGE,Group dispatched on a merged GCT empty. GCT entries can be merged only within the same thread ##00000030A4 Group dispatched on a merged GCT empty. GCT entries can be merged only within the same thread #123,v,g,n,n,n,PM_GCT_NOSLOT_DISP_HELD_ISSQ,Gct empty for this thread due to dispatch hold on this thread due to Issue q full ##000002D01E Gct empty for this thread due to dispatch hold on this thread due to Issue q full. #124,v,g,n,n,n,PM_GCT_NOSLOT_DISP_HELD_OTHER,Gct empty for this thread due to dispatch hold on this thread due to sync ##000002E010 Gct empty for this thread due to dispatch hold on this thread due to sync. #125,v,g,n,n,n,PM_GCT_NOSLOT_DISP_HELD_SRQ,Gct empty for this thread due to dispatch hold on this thread due to SRQ full ##000002D01C Gct empty for this thread due to dispatch hold on this thread due to SRQ full. #126,v,g,n,n,n,PM_GCT_NOSLOT_IC_MISS,Gct empty for this thread due to Icache Miss ##000002D01A Gct empty for this thread due to Icache Miss. #127,u,g,n,n,n,PM_GCT_UTIL_11_14_ENTRIES,GCT Utilization 11-14 entries ##00000020A2 GCT Utilization 11-14 entries #128,u,g,n,n,n,PM_GCT_UTIL_1_2_ENTRIES,GCT Utilization 1-2 entries ##000000209C GCT Utilization 1-2 entries #129,u,g,n,n,n,PM_GCT_UTIL_15_17_ENTRIES,GCT Utilization 15-17 entries ##00000020A4 GCT Utilization 15-17 entries #130,v,g,n,n,n,PM_GCT_UTIL_18_ENTRIES,GCT Utilization 18+ entries ##00000020A6 GCT Utilization 18+ entries #131,u,g,n,n,n,PM_GCT_UTIL_3_6_ENTRIES,GCT Utilization 3-6 entries ##000000209E GCT Utilization 3-6 entries #132,u,g,n,n,n,PM_GCT_UTIL_7_10_ENTRIES,GCT Utilization 7-10 entries ##00000020A0 GCT Utilization 7-10 entries #133,u,g,n,n,n,PM_GRP_NON_FULL_GROUP,GROUPs where we did not have 6 non branch instructions in the group(ST mode), in SMT mode 3 non branches ##000000509C GROUPs where we did not have 6 non branch instructions in the group(ST mode), in SMT mode 3 non branches #134,u,g,n,n,n,PM_GRP_PUMP_CPRED,Initial and Final Pump Scope and data sourced across this scope was group pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) ##0000020050 Initial and Final Pump Scope and data sourced across this scope was group pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate). #135,u,g,n,n,n,PM_GRP_PUMP_MPRED,Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) ##0000020052 Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro #136,u,g,n,n,n,PM_GRP_TERM_2ND_BRANCH,There were enough instructions in the Ibuffer, but 2nd branch ends group ##00000050A4 There were enough instructions in the Ibuffer, but 2nd branch ends group #137,u,g,n,n,n,PM_GRP_TERM_FPU_AFTER_BR,There were enough instructions in the Ibuffer, but FPU OP IN same group after a branch terminates a group, cant do partial flushes ##00000050A6 There were enough instructions in the Ibuffer, but FPU OP IN same group after a branch terminates a group, cant do partial flushes #138,u,g,n,n,n,PM_GRP_TERM_NOINST,Do not fill every slot in the group, Not enough instructions in the Ibuffer. This includes cases where the group started with enough instructions, but some got knocked out by a cache miss or branch redirect (which would also empty the Ibuffer). ##000000509E Do not fill every slot in the group, Not enough instructions in the Ibuffer. This includes cases where the group started with enough instructions, but some got knocked out by a cache miss or branch redirect (which would also empty the Ibuffer). #139,u,g,n,n,n,PM_GRP_TERM_OTHER,There were enough instructions in the Ibuffer, but the group terminated early for some other reason, most likely due to a First or Last. ##00000050A0 There were enough instructions in the Ibuffer, but the group terminated early for some other reason, most likely due to a First or Last. #140,u,g,n,n,n,PM_GRP_TERM_SLOT_LIMIT,There were enough instructions in the Ibuffer, but 3 src RA/RB/RC , 2 way crack caused a group termination ##00000050A2 There were enough instructions in the Ibuffer, but 3 src RA/RB/RC , 2 way crack caused a group termination #141,v,g,n,n,n,PM_HV_CYC,Cycles in which msr_hv is high. Note that this event does not take msr_pr into consideration ##000002000A cycles in hypervisor mode . #142,u,g,n,n,n,PM_IBUF_FULL_CYC,Cycles No room in ibuff ##0000004086 Cycles No room in ibufffully qualified tranfer (if5 valid). #143,u,g,n,n,n,PM_IC_DEMAND_L2_BHT_REDIRECT, L2 I cache demand request due to BHT redirect, branch redirect ( 2 bubbles 3 cycles) ##0000004098 L2 I cache demand request due to BHT redirect, branch redirect ( 2 bubbles 3 cycles) #144,u,g,n,n,n,PM_IC_DEMAND_L2_BR_REDIRECT, L2 I cache demand request due to branch Mispredict ( 15 cycle path) ##000000409A L2 I cache demand request due to branch Mispredict ( 15 cycle path) #145,u,g,n,n,n,PM_IC_DEMAND_REQ,Demand Instruction fetch request ##0000004088 Demand Instruction fetch request #146,u,g,n,n,n,PM_IC_INVALIDATE,Ic line invalidated ##000000508A Ic line invalidated #147,u,g,n,n,n,PM_IC_PREF_CANCEL_HIT,Prefetch Canceled due to icache hit ##0000004092 Prefetch Canceled due to icache hit #148,u,g,n,n,n,PM_IC_PREF_CANCEL_L2,L2 Squashed request ##0000004094 L2 Squashed request #149,u,g,n,n,n,PM_IC_PREF_CANCEL_PAGE,Prefetch Canceled due to page boundary ##0000004090 Prefetch Canceled due to page boundary #150,u,g,n,n,n,PM_IC_PREF_REQ,Instruction prefetch requests ##000000408A Instruction prefetch requests #151,v,g,n,n,n,PM_IC_PREF_WRITE,Instruction prefetch written into IL1 ##000000408E Instruction prefetch written into IL1 #152,u,g,n,n,n,PM_IC_RELOAD_PRIVATE,Reloading line was brought in private for a specific thread. Most lines are brought in shared for all eight thrreads. If RA does not match then invalidates and then brings it shared to other thread. In P7 line brought in private , then line was invalidat ##0000004096 Reloading line was brought in private for a specific thread. Most lines are brought in shared for all eight thrreads. If RA does not match then invalidates and then brings it shared to other thread. In P7 line brought in private , then line was inv #153,u,g,n,n,n,PM_IERAT_RELOAD_4K,IERAT Miss (Not implemented as DI on POWER6) ##0000020064 IERAT Reloaded (Miss) for a 4k page. #154,u,g,n,n,n,PM_IFU_L2_TOUCH,L2 touch to update MRU on a line ##0000005088 L2 touch to update MRU on a line #155,u,g,n,n,n,PM_INST_ALL_FROM_L2_MEPF,The processor's Instruction cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to instruction fetches and prefetches ##0000524040 The processor's Instruction cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 #156,u,g,n,n,n,PM_INST_ALL_FROM_L31_MOD,The processor's Instruction cache was reloaded with Modified (M) data from another core's L3 on the same chip due to instruction fetches and prefetches ##0000524044 The processor's Instruction cache was reloaded with Modified (M) data from another core's L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 #157,u,g,n,n,n,PM_INST_ALL_FROM_L3_MEPF,The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to instruction fetches and prefetches ##0000524042 The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 #158,u,g,n,n,n,PM_INST_ALL_FROM_LMEM,The processor's Instruction cache was reloaded from the local chip's Memory due to instruction fetches and prefetches ##0000524048 The processor's Instruction cache was reloaded from the local chip's Memory due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 #159,u,g,n,n,n,PM_INST_ALL_FROM_MEMORY,The processor's Instruction cache was reloaded from a memory location including L4 from local remote or distant due to instruction fetches and prefetches ##000052404C The processor's Instruction cache was reloaded from a memory location including L4 from local remote or distant due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 #160,u,g,n,n,n,PM_INST_ALL_FROM_RL2L3_MOD,The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to instruction fetches and prefetches ##0000524046 The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 #161,u,g,n,n,n,PM_INST_ALL_FROM_RL4,The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to instruction fetches and prefetches ##000052404A The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 #162,u,g,n,n,n,PM_INST_ALL_GRP_PUMP_CPRED,Initial and Final Pump Scope was group pump (prediction=correct) for instruction fetches and prefetches ##0000524050 Initial and Final Pump Scope and data sourced across this scope was group pump for an instruction fetch #163,u,g,n,n,n,PM_INST_ALL_GRP_PUMP_MPRED,Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for instruction fetches and prefetches ##0000524052 Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro #164,v,g,n,n,n,PM_INST_CMPL,Number of PowerPC Instructions that completed. ##0000020002 PPC Instructions Finished (completed). #165,u,g,n,n,n,PM_INST_DISP, PPC Dispatched ##00000200F2 PPC Dispatched. #166,u,g,n,n,n,PM_INST_FROM_L1,Instruction fetches from L1 ##0000004080 Instruction fetches from L1 #167,v,g,n,n,n,PM_INST_FROM_L2_MEPF,The processor's Instruction cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to an instruction fetch (not prefetch) ##0000024040 The processor's Instruction cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . #168,u,g,n,n,n,PM_INST_FROM_L31_MOD,The processor's Instruction cache was reloaded with Modified (M) data from another core's L3 on the same chip due to an instruction fetch (not prefetch) ##0000024044 The processor's Instruction cache was reloaded with Modified (M) data from another core's L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . #169,u,g,n,n,n,PM_INST_FROM_L3_MEPF,The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to an instruction fetch (not prefetch) ##0000024042 The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . #170,u,g,n,n,n,PM_INST_FROM_LMEM,The processor's Instruction cache was reloaded from the local chip's Memory due to an instruction fetch (not prefetch) ##0000024048 The processor's Instruction cache was reloaded from the local chip's Memory due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . #171,u,g,n,n,n,PM_INST_FROM_MEMORY,The processor's Instruction cache was reloaded from a memory location including L4 from local remote or distant due to an instruction fetch (not prefetch) ##000002404C The processor's Instruction cache was reloaded from a memory location including L4 from local remote or distant due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . #172,u,g,n,n,n,PM_INST_FROM_RL2L3_MOD,The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch) ##0000024046 The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . #173,u,g,n,n,n,PM_INST_FROM_RL4,The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to an instruction fetch (not prefetch) ##000002404A The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . #174,u,g,n,n,n,PM_INST_GRP_PUMP_CPRED,Initial and Final Pump Scope was group pump (prediction=correct) for an instruction fetch ##0000024050 Initial and Final Pump Scope and data sourced across this scope was group pump for an instruction fetch. #175,u,g,n,n,n,PM_INST_GRP_PUMP_MPRED,Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for an instruction fetch ##0000024052 Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro #176,u,g,n,n,n,PM_IPTEG_FROM_L2_MEPF,A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a instruction side request ##0000025040 A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a instruction side request. #177,u,g,n,n,n,PM_IPTEG_FROM_L31_MOD,A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a instruction side request ##0000025044 A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a instruction side request. #178,u,g,n,n,n,PM_IPTEG_FROM_L3_MEPF,A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a instruction side request ##0000025042 A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a instruction side request. #179,u,g,n,n,n,PM_IPTEG_FROM_LMEM,A Page Table Entry was loaded into the TLB from the local chip's Memory due to a instruction side request ##0000025048 A Page Table Entry was loaded into the TLB from the local chip's Memory due to a instruction side request. #180,u,g,n,n,n,PM_IPTEG_FROM_MEMORY,A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a instruction side request ##000002504C A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a instruction side request. #181,u,g,n,n,n,PM_IPTEG_FROM_RL2L3_MOD,A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request ##0000025046 A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request. #182,u,g,n,n,n,PM_IPTEG_FROM_RL4,A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction side request ##000002504A A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction side request. #183,u,g,n,n,n,PM_ISIDE_DISP_FAIL,All i-side dispatch attempts that failed due to a addr collision with another machine ##0000627084 All i-side dispatch attempts that failed due to a addr collision with another machine #184,u,g,n,n,n,PM_ISIDE_DISP_FAIL_OTHER,All i-side dispatch attempts that failed due to a reason other than addrs collision ##0000627086 All i-side dispatch attempts that failed due to a reason other than addrs collision #185,v,g,n,n,n,PM_ISLB_MISS,I SLB Miss. ##000000D096 I SLB Miss. #186,u,g,n,s,n,PM_ISU_REF_FX0,FX0 ISU reject ##00000030AC FX0 ISU reject #187,u,g,n,s,n,PM_ISU_REF_FX1,FX1 ISU reject ##00000030AE FX1 ISU reject #188,u,g,n,n,n,PM_ISU_REF_FXU,FXU ISU reject from either pipe ##00000038AC ISU #189,u,g,n,s,n,PM_ISU_REF_LS0,LS0 ISU reject ##00000030B0 LS0 ISU reject #190,u,g,n,s,n,PM_ISU_REF_LS1,LS1 ISU reject ##00000030B2 LS1 ISU reject #191,u,g,n,s,n,PM_ISU_REF_LS2,LS2 ISU reject ##00000030B4 LS2 ISU reject #192,u,g,n,s,n,PM_ISU_REF_LS3,LS3 ISU reject ##00000030B6 LS3 ISU reject #193,u,g,n,s,n,PM_ISU_REJECT_RES_NA,ISU reject due to resource not available ##00000030A2 ISU reject due to resource not available #194,v,g,n,s,n,PM_ISU_REJECTS_ALL,All isu rejects could be more than 1 per cycle ##000000309C All isu rejects could be more than 1 per cycle #195,v,g,n,s,n,PM_ISU_REJECT_SAR_BYPASS,Reject because of SAR bypass ##000000309E Reject because of SAR bypass #196,u,g,n,s,n,PM_ISU_REJECT_SRC_NA,ISU reject due to source not available ##00000030A0 ISU reject due to source not available #197,u,g,n,s,n,PM_ISU_REJ_VS0,VS0 ISU reject ##00000030A8 VS0 ISU reject #198,u,g,n,s,n,PM_ISU_REJ_VS1,VS1 ISU reject ##00000030AA VS1 ISU reject #199,u,g,n,n,n,PM_ISU_REJ_VSU,VSU ISU reject from either pipe ##00000038A8 ISU #200,u,g,n,n,n,PM_ISYNC,Isync count per thread ##00000030B8 Isync count per thread #201,v,g,n,n,n,PM_L1_DEMAND_WRITE,Instruction Demand sectors wriittent into IL1 ##000000408C Instruction Demand sectors wriittent into IL1 #202,u,g,n,n,n,PM_L1_ICACHE_MISS,Demand iCache Miss ##00000200FD Demand iCache Miss. #203,u,g,n,n,m,PM_L1MISS_LAT_EXC_32,L1 misses that took longer than 32 cyles to resolve (miss to reload) ##67200201E6 Reload latency exceeded 32 cyc #204,u,g,n,s,n,PM_L1PF_L2MEMACC,valid when first beat of data comes in for an L1pref where data came from mem(or L4) ##0000026086 valid when first beat of data comes in for an L1pref where data came from mem(or L4) #205,c,g,n,s,n,PM_L2_CHIP_PUMP,RC requests that were local on chip pump attempts ##0000027084 RC requests that were local on chip pump attempts #206,u,g,n,s,n,PM_L2_DC_INV,Dcache invalidates from L2 ##0000427086 Dcache invalidates from L2 #207,c,g,n,s,n,PM_L2_GROUP_PUMP,RC requests that were on Node Pump attempts ##0000027086 RC requests that were on Node Pump attempts #208,u,g,n,s,n,PM_L2_GRP_GUESS_CORRECT,L2 guess grp and guess was correct (data intra-6chip AND ^on-chip) ##0000626084 L2 guess grp and guess was correct (data intra-6chip AND ^on-chip) #209,u,g,n,s,n,PM_L2_GRP_GUESS_WRONG,L2 guess grp and guess was not correct (ie data on-chip OR beyond-6chip) ##0000626086 L2 guess grp and guess was not correct (ie data on-chip OR beyond-6chip) #210,u,g,n,s,n,PM_L2_IC_INV,Icache Invalidates from L2 ##0000427084 Icache Invalidates from L2 #211,v,g,n,n,n,PM_L2_LD_MISS,All successful D-Side Load dispatches that were an L2miss for this thread ##0000426084 All successful D-Side Load dispatches that were an L2miss for this thread #212,u,g,n,n,n,PM_L2_RCLD_DISP_FAIL_OTHER, L2 RC load dispatch attempt failed due to other reasons ##0000526084 L2 RC load dispatch attempt failed due to other reasons #213,v,g,n,n,n,PM_L2_ST_MISS,All successful D-side store dispatches for this thread that were L2 Miss ##0000426086 All successful D-side store dispatches for this thread that were L2 Miss #214,u,g,n,s,n,PM_L3_CI_HIT,L3 Castins Hit (total count ##0000128084 L3 Castins Hit (total count #215,u,g,n,s,n,PM_L3_CI_MISS,L3 castins miss (total count ##0000128086 L3 castins miss (total count #216,u,g,n,s,n,PM_L3_CO_L31,L3 CO to L3.1 OR of port 0 and 1 ( lossy) ##0000028086 L3 CO to L3.1 OR of port 0 and 1 ( lossy) #217,u,g,n,s,n,PM_L3_CO_MEM,L3 CO to memory OR of port 0 and 1 ( lossy) ##0000028084 L3 CO to memory OR of port 0 and 1 ( lossy) #218,v,g,n,s,n,PM_L3_LD_HIT,L3 demand LD Hits ##0000228084 L3 demand LD Hits #219,v,g,n,s,n,PM_L3_LD_MISS,L3 demand LD Miss ##0000228086 L3 demand LD Miss #220,u,g,n,s,n,PM_L3_LOC_GUESS_WRONG,Initial scope=node but data from out side local node (near or far or rem). Prediction too Low ##0000B29086 Initial scope=node but data from out side local node (near or far or rem). Prediction too Low #221,u,g,n,s,n,PM_L3_P0_CO_RTY,L3 CO received retry port 0 ##0000929084 L3 CO received retry port 0 #222,u,g,n,s,n,PM_L3_P0_GRP_PUMP,L3 pf sent with grp scope port 0 ##0000A29084 L3 pf sent with grp scope port 0 #223,u,g,n,s,n,PM_L3_P0_LCO_DATA,lco sent with data port 0 ##0000528084 lco sent with data port 0 #224,u,g,n,s,n,PM_L3_P1_CO_RTY,L3 CO received retry port 1 ##0000929086 L3 CO received retry port 1 #225,u,g,n,s,n,PM_L3_P1_GRP_PUMP,L3 pf sent with grp scope port 1 ##0000A29086 L3 pf sent with grp scope port 1 #226,u,g,n,s,n,PM_L3_P1_LCO_DATA,lco sent with data port 1 ##0000528086 lco sent with data port 1 #227,v,g,n,s,n,PM_L3_PF_HIT_L3,l3 pf hit in l3 ##0000428084 l3 pf hit in l3 #228,v,g,n,s,n,PM_L3_PF_USAGE,rotating sample of 32 PF actives ##0000829084 rotating sample of 32 PF actives #229,v,g,n,s,n,PM_L3_RD_USAGE,rotating sample of 16 RD actives ##0000829086 rotating sample of 16 RD actives #230,u,g,n,n,n,PM_L3_ST_PREF,L3 store Prefetches ##000002E052 L3 store Prefetches. #231,u,g,n,s,n,PM_L3_SYS_GUESS_CORRECT,Initial scope=system and data from outside group (far or rem)(pred successful) ##0000B29084 Initial scope=system and data from outside group (far or rem)(pred successful) #232,v,g,n,n,n,PM_LD_REF_L1_LSU0, LS0 L1 D cache load references counted at finish, gated by reject ##000000C080 LS0 L1 D cache load references counted at finish, gated by rejectLSU0 L1 D cache load references #233,v,g,n,n,n,PM_LD_REF_L1_LSU1, LS1 L1 D cache load references counted at finish, gated by reject ##000000C082 LS1 L1 D cache load references counted at finish, gated by rejectLSU1 L1 D cache load references #234,v,g,n,n,n,PM_LD_REF_L1_LSU2, LS2 L1 D cache load references counted at finish, gated by reject ##000000C094 LS2 L1 D cache load references counted at finish, gated by reject42 #235,v,g,n,n,n,PM_LD_REF_L1_LSU3, LS3 L1 D cache load references counted at finish, gated by reject ##000000C096 LS3 L1 D cache load references counted at finish, gated by reject42 #236,u,g,n,n,n,PM_LINK_STACK_INVALID_PTR,A flush were LS ptr is invalid, results in a pop , A lot of interrupts between push and pops ##000000509A A flush were LS ptr is invalid, results in a pop , A lot of interrupts between push and pops #237,u,g,n,n,n,PM_LINK_STACK_WRONG_ADD_PRED,Link stack predicts wrong address, because of link stack design limitation. ##0000005098 Link stack predicts wrong address, because of link stack design limitation. #238,u,g,n,n,n,PM_LS0_ERAT_MISS_PREF,LS0 Erat miss due to prefetch ##000000E080 LS0 Erat miss due to prefetch42 #239,v,g,n,n,n,PM_LS0_L1_PREF, LS0 L1 cache data prefetches ##000000D0B8 LS0 L1 cache data prefetches42 #240,v,g,n,n,n,PM_LS0_L1_SW_PREF,Software L1 Prefetches, including SW Transient Prefetches ##000000C098 Software L1 Prefetches, including SW Transient Prefetches42 #241,u,g,n,n,n,PM_LS1_ERAT_MISS_PREF,LS1 Erat miss due to prefetch ##000000E082 LS1 Erat miss due to prefetch42 #242,v,g,n,n,n,PM_LS1_L1_PREF, LS1 L1 cache data prefetches ##000000D0BA LS1 L1 cache data prefetches42 #243,v,g,n,n,n,PM_LS1_L1_SW_PREF,Software L1 Prefetches, including SW Transient Prefetches ##000000C09A Software L1 Prefetches, including SW Transient Prefetches42 #244,u,g,n,n,n,PM_LSU0_FLUSH_LRQ,LS0 Flush: LRQ ##000000C0B0 LS0 Flush: LRQLSU0 LRQ flushes #245,u,g,n,n,n,PM_LSU0_FLUSH_SRQ,LS0 Flush: SRQ ##000000C0B8 LS0 Flush: SRQLSU0 SRQ lhs flushes #246,u,g,n,n,n,PM_LSU0_FLUSH_ULD,LS0 Flush: Unaligned Load ##000000C0A4 LS0 Flush: Unaligned LoadLSU0 unaligned load flushes #247,u,g,n,n,n,PM_LSU0_FLUSH_UST,LS0 Flush: Unaligned Store ##000000C0AC LS0 Flush: Unaligned StoreLSU0 unaligned store flushes #248,u,g,n,n,n,PM_LSU0_L1_CAM_CANCEL,ls0 l1 tm cam cancel ##000000F088 ls0 l1 tm cam cancel42 #249,v,g,n,n,n,PM_LSU0_LMQ_LHR_MERGE,LS0 Load Merged with another cacheline request ##000000D08C LS0 Load Merged with another cacheline request42 #250,u,g,n,n,n,PM_LSU0_NCLD,LS0 Non-cachable Loads counted at finish ##000000C08C LS0 Non-cachable Loads counted at finishLSU0 non-cacheable loads #251,u,g,n,n,n,PM_LSU0_PRIMARY_ERAT_HIT,Primary ERAT hit ##000000E090 Primary ERAT hit42 #252,u,g,n,n,n,PM_LSU0_SRQ_STFWD,LS0 SRQ forwarded data to a load ##000000C09C LS0 SRQ forwarded data to a loadLSU0 SRQ store forwarded #253,v,g,n,n,n,PM_LSU0_STORE_REJECT,ls0 store reject ##000000F084 ls0 store reject42 #254,u,g,n,n,n,PM_LSU0_TMA_REQ_L2, addrs only req to L2 only on the first one,Indication that Load footprint is not expanding ##000000E0A8 addrs only req to L2 only on the first one,Indication that Load footprint is not expanding42 #255,u,g,n,n,n,PM_LSU0_TM_L1_HIT,Load tm hit in L1 ##000000E098 Load tm hit in L142 #256,u,g,n,n,n,PM_LSU0_TM_L1_MISS,Load tm L1 miss ##000000E0A0 Load tm L1 miss42 #257,u,g,n,n,n,PM_LSU1_FLUSH_LRQ,LS1 Flush: LRQ ##000000C0B2 LS1 Flush: LRQLSU1 LRQ flushes #258,u,g,n,n,n,PM_LSU1_FLUSH_SRQ,LS1 Flush: SRQ ##000000C0BA LS1 Flush: SRQLSU1 SRQ lhs flushes #259,u,g,n,n,n,PM_LSU1_FLUSH_ULD,LS 1 Flush: Unaligned Load ##000000C0A6 LS 1 Flush: Unaligned LoadLSU1 unaligned load flushes #260,u,g,n,n,n,PM_LSU1_FLUSH_UST,LS1 Flush: Unaligned Store ##000000C0AE LS1 Flush: Unaligned StoreLSU1 unaligned store flushes #261,u,g,n,n,n,PM_LSU1_L1_CAM_CANCEL,ls1 l1 tm cam cancel ##000000F08A ls1 l1 tm cam cancel42 #262,u,g,n,n,n,PM_LSU1_LARX_FIN,Larx finished in LSU pipe1 ##000002E056 Larx finished in LSU pipe1. #263,v,g,n,n,n,PM_LSU1_LMQ_LHR_MERGE,LS1 Load Merge with another cacheline request ##000000D08E LS1 Load Merge with another cacheline request42 #264,u,g,n,n,n,PM_LSU1_NCLD,LS1 Non-cachable Loads counted at finish ##000000C08E LS1 Non-cachable Loads counted at finishLSU1 non-cacheable loads #265,u,g,n,n,n,PM_LSU1_PRIMARY_ERAT_HIT,Primary ERAT hit ##000000E092 Primary ERAT hit42 #266,u,g,n,n,n,PM_LSU1_REJECT,LSU1 reject ##000002E05A LSU1 reject . #267,u,g,n,n,n,PM_LSU1_SRQ_STFWD,LS1 SRQ forwarded data to a load ##000000C09E LS1 SRQ forwarded data to a loadLSU1 SRQ store forwarded #268,v,g,n,n,n,PM_LSU1_STORE_REJECT,ls1 store reject ##000000F086 ls1 store reject42 #269,u,g,n,n,n,PM_LSU1_TMA_REQ_L2, addrs only req to L2 only on the first one,Indication that Load footprint is not expanding ##000000E0AA addrs only req to L2 only on the first one,Indication that Load footprint is not expanding42 #270,u,g,n,n,n,PM_LSU1_TM_L1_HIT,Load tm hit in L1 ##000000E09A Load tm hit in L142 #271,u,g,n,n,n,PM_LSU1_TM_L1_MISS,Load tm L1 miss ##000000E0A2 Load tm L1 miss42 #272,u,g,n,n,n,PM_LSU2_FLUSH_LRQ,LS02Flush: LRQ ##000000C0B4 LS02Flush: LRQ42 #273,u,g,n,n,n,PM_LSU2_FLUSH_SRQ,LS2 Flush: SRQ ##000000C0BC LS2 Flush: SRQ42 #274,u,g,n,n,n,PM_LSU2_FLUSH_ULD,LS3 Flush: Unaligned Load ##000000C0A8 LS3 Flush: Unaligned Load42 #275,u,g,n,n,n,PM_LSU2_L1_CAM_CANCEL,ls2 l1 tm cam cancel ##000000F08C ls2 l1 tm cam cancel42 #276,u,g,n,n,n,PM_LSU2_LDF,LS2 Scalar Loads ##000000C084 LS2 Scalar Loads42 #277,u,g,n,n,n,PM_LSU2_LDX,LS0 Vector Loads ##000000C088 LS0 Vector Loads42 #278,v,g,n,n,n,PM_LSU2_LMQ_LHR_MERGE,LS0 Load Merged with another cacheline request ##000000D090 LS0 Load Merged with another cacheline request42 #279,u,g,n,n,n,PM_LSU2_PRIMARY_ERAT_HIT,Primary ERAT hit ##000000E094 Primary ERAT hit42 #280,u,g,n,n,n,PM_LSU2_SRQ_STFWD,LS2 SRQ forwarded data to a load ##000000C0A0 LS2 SRQ forwarded data to a load42 #281,u,g,n,n,n,PM_LSU2_TMA_REQ_L2, addrs only req to L2 only on the first one,Indication that Load footprint is not expanding ##000000E0AC addrs only req to L2 only on the first one,Indication that Load footprint is not expanding42 #282,u,g,n,n,n,PM_LSU2_TM_L1_HIT,Load tm hit in L1 ##000000E09C Load tm hit in L142 #283,u,g,n,n,n,PM_LSU2_TM_L1_MISS,Load tm L1 miss ##000000E0A4 Load tm L1 miss42 #284,u,g,n,n,n,PM_LSU3_FLUSH_LRQ,LS3 Flush: LRQ ##000000C0B6 LS3 Flush: LRQ42 #285,u,g,n,n,n,PM_LSU3_FLUSH_SRQ,LS13 Flush: SRQ ##000000C0BE LS13 Flush: SRQ42 #286,u,g,n,n,n,PM_LSU3_FLUSH_ULD,LS 14Flush: Unaligned Load ##000000C0AA LS 14Flush: Unaligned Load42 #287,u,g,n,n,n,PM_LSU3_L1_CAM_CANCEL,ls3 l1 tm cam cancel ##000000F08E ls3 l1 tm cam cancel42 #288,u,g,n,n,n,PM_LSU3_LDF,LS3 Scalar Loads ##000000C086 LS3 Scalar Loads 42 #289,u,g,n,n,n,PM_LSU3_LDX,LS1 Vector Loads ##000000C08A LS1 Vector Loads42 #290,v,g,n,n,n,PM_LSU3_LMQ_LHR_MERGE,LS1 Load Merge with another cacheline request ##000000D092 LS1 Load Merge with another cacheline request42 #291,u,g,n,n,n,PM_LSU3_PRIMARY_ERAT_HIT,Primary ERAT hit ##000000E096 Primary ERAT hit42 #292,u,g,n,n,n,PM_LSU3_SRQ_STFWD,LS3 SRQ forwarded data to a load ##000000C0A2 LS3 SRQ forwarded data to a load42 #293,u,g,n,n,n,PM_LSU3_TMA_REQ_L2, addrs only req to L2 only on the first one,Indication that Load footprint is not expanding ##000000E0AE addrs only req to L2 only on the first one,Indication that Load footprint is not expanding42 #294,u,g,n,n,n,PM_LSU3_TM_L1_HIT,Load tm hit in L1 ##000000E09E Load tm hit in L142 #295,u,g,n,n,n,PM_LSU3_TM_L1_MISS,Load tm L1 miss ##000000E0A6 Load tm L1 miss42 #296,u,g,n,n,n,PM_LSU_DERAT_MISS,DERAT Reloaded due to a DERAT miss ##00000200F6 DERAT Reloaded (Miss). #297,u,g,n,n,n,PM_LSU_ERAT_MISS_PREF,Erat miss due to prefetch, on either pipe ##000000E880 LSU #298,u,g,n,n,n,PM_LSU_FLUSH_UST,Unaligned Store Flush on either pipe ##000000C8AC LSU #299,u,g,n,n,n,PM_LSU_FOUR_TABLEWALK_CYC,Cycles when four tablewalks pending on this thread ##000000D0A4 Cycles when four tablewalks pending on this thread42 #300,u,g,n,n,n,PM_LSU_L1_PREF,hw initiated , include sw streaming forms as well , include sw streams as a separate event ##000000D8B8 LSU #301,u,g,n,n,n,PM_LSU_L1_SW_PREF,Software L1 Prefetches, including SW Transient Prefetches, on both pipes ##000000C898 LSU #302,u,g,n,n,n,PM_LSU_LDF,FPU loads only on LS2/LS3 ie LU0/LU1 ##000000C884 LSU #303,u,g,n,n,n,PM_LSU_LDX,Vector loads can issue only on LS2/LS3 ##000000C888 LSU #304,v,g,n,n,n,PM_LSU_LMQ_FULL_CYC,LMQ full ##000000D0A2 LMQ fullCycles LMQ full, #305,u,g,n,n,n,PM_LSU_LMQ_S0_ALLOC,Per thread - use edge detect to count allocates On a per thread basis, level signal indicating Slot 0 is valid. By instrumenting a single slot we can calculate service time for that slot. Previous machines required a separate signal indicating the slot was allocated. Because any signal can be routed to any counter in P8, we can count level in one PMC and edge detect in another PMC using the same signal ##000000D0A1 0.0 #306,v,g,n,n,n,PM_LSU_LMQ_S0_VALID,Slot 0 of LMQ valid ##000000D0A0 Slot 0 of LMQ validLMQ slot 0 valid #307,v,g,n,n,n,PM_LSU_LMQ_SRQ_EMPTY_CYC,LSU empty (lmq and srq empty) ##000002003E LSU empty (lmq and srq empty). #308,u,g,n,n,n,PM_LSU_LRQ_S0_ALLOC,Per thread - use edge detect to count allocates On a per thread basis, level signal indicating Slot 0 is valid. By instrumenting a single slot we can calculate service time for that slot. Previous machines required a separate signal indicating the slot was allocated. Because any signal can be routed to any counter in P8, we can count level in one PMC and edge detect in another PMC using the same signal ##000000D09F 0.0 #309,v,g,n,n,n,PM_LSU_LRQ_S0_VALID,Slot 0 of LRQ valid ##000000D09E Slot 0 of LRQ validLRQ slot 0 valid #310,u,g,n,n,n,PM_LSU_LRQ_S43_ALLOC,LRQ slot 43 was released ##000000F091 0.0 #311,u,g,n,n,n,PM_LSU_LRQ_S43_VALID,LRQ slot 43 was busy ##000000F090 LRQ slot 43 was busy42 #312,u,g,n,n,n,PM_LSU_NCLD,count at finish so can return only on ls0 or ls1 ##000000C88C LSU #313,u,g,n,n,n,PM_LSU_NCST,Non-cachable Stores sent to nest ##000000C092 Non-cachable Stores sent to nest42 #314,u,g,n,n,n,PM_LSU_REJECT_ERAT_MISS,LSU Reject due to ERAT (up to 4 per cycles) ##000002E05C LSU Reject due to ERAT (up to 4 per cycles). #315,u,g,n,n,n,PM_LSU_SET_MPRED,Line already in cache at reload time ##000000D082 Line already in cache at reload time42 #316,u,g,n,n,n,PM_LSU_SRQ_S0_ALLOC,Per thread - use edge detect to count allocates On a per thread basis, level signal indicating Slot 0 is valid. By instrumenting a single slot we can calculate service time for that slot. Previous machines required a separate signal indicating the slot was allocated. Because any signal can be routed to any counter in P8, we can count level in one PMC and edge detect in another PMC using the same signal ##000000D09D 0.0 #317,v,g,n,n,n,PM_LSU_SRQ_S0_VALID,Slot 0 of SRQ valid ##000000D09C Slot 0 of SRQ validSRQ slot 0 valid #318,u,g,n,n,n,PM_LSU_SRQ_S39_ALLOC,SRQ slot 39 was released ##000000F093 0.0 #319,u,g,n,n,n,PM_LSU_SRQ_S39_VALID,SRQ slot 39 was busy ##000000F092 SRQ slot 39 was busy42 #320,u,g,n,n,n,PM_LSU_SRQ_SYNC,A sync in the SRQ ended ##000000D09B 0.0 #321,u,g,n,n,n,PM_LSU_SRQ_SYNC_CYC,A sync is in the SRQ (edge detect to count) ##000000D09A A sync is in the SRQ (edge detect to count)SRQ sync duration #322,u,g,n,n,n,PM_LSU_STORE_REJECT,Store reject on either pipe ##000000F084 LSU #323,u,g,n,n,n,PM_LSU_TWO_TABLEWALK_CYC,Cycles when two tablewalks pending on this thread ##000000D0A6 Cycles when two tablewalks pending on this thread42 #324,u,g,n,n,n,PM_LWSYNC,threaded version, IC Misses where we got EA dir hit but no sector valids were on. ICBI took line out ##0000005094 threaded version, IC Misses where we got EA dir hit but no sector valids were on. ICBI took line out #325,u,g,n,n,n,PM_LWSYNC_HELD,LWSYNC held at dispatch ##000000209A LWSYNC held at dispatch #326,u,g,n,s,n,PM_MEM_PREF,Memory prefetch for this lpar. Includes L4 ##000002C058 Memory prefetch for this lpar. #327,v,g,n,n,m,PM_MRK_BRU_FIN,bru marked instr finish ##000002013A bru marked instr finish. #328,v,g,n,n,m,PM_MRK_DATA_FROM_DL2L3_MOD_CYC,Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load ##000002D128 Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load. #329,v,g,n,n,m,PM_MRK_DATA_FROM_DL2L3_SHR_CYC,Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load ##000002C128 Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load. #330,v,g,n,n,m,PM_MRK_DATA_FROM_DL4_CYC,Duration in cycles to reload from another chip's L4 on a different Node or Group (Distant) due to a marked load ##000002C12C Duration in cycles to reload from another chip's L4 on a different Node or Group (Distant) due to a marked load. #331,v,g,n,n,m,PM_MRK_DATA_FROM_DMEM_CYC,Duration in cycles to reload from another chip's memory on the same Node or Group (Distant) due to a marked load ##000002D12C Duration in cycles to reload from another chip's memory on the same Node or Group (Distant) due to a marked load. #332,v,g,n,n,m,PM_MRK_DATA_FROM_L21_MOD_CYC,Duration in cycles to reload with Modified (M) data from another core's L2 on the same chip due to a marked load ##000002D126 Duration in cycles to reload with Modified (M) data from another core's L2 on the same chip due to a marked load. #333,v,g,n,n,m,PM_MRK_DATA_FROM_L21_SHR_CYC,Duration in cycles to reload with Shared (S) data from another core's L2 on the same chip due to a marked load ##000002C126 Duration in cycles to reload with Shared (S) data from another core's L2 on the same chip due to a marked load. #334,v,g,n,n,m,PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC,Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load ##000002C120 Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load. #335,v,g,n,n,m,PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER_CYC,Duration in cycles to reload from local core's L2 with dispatch conflict due to a marked load ##000002D120 Duration in cycles to reload from local core's L2 with dispatch conflict due to a marked load. #336,v,g,n,n,m,PM_MRK_DATA_FROM_L2_MEPF,The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load ##000002D140 The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load. #337,v,g,n,n,m,PM_MRK_DATA_FROM_L31_ECO_MOD_CYC,Duration in cycles to reload with Modified (M) data from another core's ECO L3 on the same chip due to a marked load ##000002D124 Duration in cycles to reload with Modified (M) data from another core's ECO L3 on the same chip due to a marked load. #338,v,g,n,n,m,PM_MRK_DATA_FROM_L31_ECO_SHR_CYC,Duration in cycles to reload with Shared (S) data from another core's ECO L3 on the same chip due to a marked load ##000002C124 Duration in cycles to reload with Shared (S) data from another core's ECO L3 on the same chip due to a marked load. #339,v,g,n,n,m,PM_MRK_DATA_FROM_L31_MOD,The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to a marked load ##000002D144 The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to a marked load. #340,v,g,n,n,m,PM_MRK_DATA_FROM_L3_CYC,Duration in cycles to reload from local core's L3 due to a marked load ##000002D122 Duration in cycles to reload from local core's L3 due to a marked load. #341,v,g,n,n,m,PM_MRK_DATA_FROM_L3_DISP_CONFLICT_CYC,Duration in cycles to reload from local core's L3 with dispatch conflict due to a marked load ##000002C122 Duration in cycles to reload from local core's L3 with dispatch conflict due to a marked load. #342,v,g,n,n,m,PM_MRK_DATA_FROM_L3_MEPF,The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load ##000002D142 The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load. #343,v,g,n,n,m,PM_MRK_DATA_FROM_L3MISS,The processor's data cache was reloaded from a localtion other than the local core's L3 due to a marked load ##00000201E4 The processor's data cache was reloaded from a localtion other than the local core's L3 due to a marked load. #344,v,g,n,n,m,PM_MRK_DATA_FROM_L3MISS_CYC,Duration in cycles to reload from a localtion other than the local core's L3 due to a marked load ##000002D12E Duration in cycles to reload from a localtion other than the local core's L3 due to a marked load. #345,v,g,n,n,m,PM_MRK_DATA_FROM_LMEM,The processor's data cache was reloaded from the local chip's Memory due to a marked load ##000002D148 The processor's data cache was reloaded from the local chip's Memory due to a marked load. #346,u,g,n,n,m,PM_MRK_DATA_FROM_MEM,The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked load ##00000201E0 The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked load. #347,v,g,n,n,m,PM_MRK_DATA_FROM_MEMORY,The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked load ##000002D14C The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked load. #348,v,g,n,n,m,PM_MRK_DATA_FROM_OFF_CHIP_CACHE_CYC,Duration in cycles to reload either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load ##000002D12A Duration in cycles to reload either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load. #349,v,g,n,n,m,PM_MRK_DATA_FROM_RL2L3_MOD,The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load ##000002D146 The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load. #350,v,g,n,n,m,PM_MRK_DATA_FROM_RL4,The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a marked load ##000002D14A The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a marked load. #351,v,g,n,n,m,PM_MRK_DATA_FROM_RMEM_CYC,Duration in cycles to reload from another chip's memory on the same Node or Group ( Remote) due to a marked load ##000002C12A Duration in cycles to reload from another chip's memory on the same Node or Group ( Remote) due to a marked load. #352,v,g,n,n,m,PM_MRK_DERAT_MISS_64K,Marked Data ERAT Miss (Data TLB Access) page size 64K ##000002D154 Marked Data ERAT Miss (Data TLB Access) page size 64K. #353,v,g,n,n,m,PM_MRK_DFU_FIN,Decimal Unit marked Instruction Finish ##0000020132 Decimal Unit marked Instruction Finish. #354,u,g,n,n,m,PM_MRK_DPTEG_FROM_L2_MEPF,A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data side request ##000002F140 A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data side request. #355,u,g,n,n,m,PM_MRK_DPTEG_FROM_L31_MOD,A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a marked data side request ##000002F144 A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a marked data side request. #356,u,g,n,n,m,PM_MRK_DPTEG_FROM_L3_MEPF,A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked data side request ##000002F142 A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked data side request. #357,u,g,n,n,m,PM_MRK_DPTEG_FROM_LMEM,A Page Table Entry was loaded into the TLB from the local chip's Memory due to a marked data side request ##000002F148 A Page Table Entry was loaded into the TLB from the local chip's Memory due to a marked data side request. #358,u,g,n,n,m,PM_MRK_DPTEG_FROM_MEMORY,A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a marked data side request ##000002F14C A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a marked data side request. #359,u,g,n,n,m,PM_MRK_DPTEG_FROM_RL2L3_MOD,A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request ##000002F146 A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request. #360,u,g,n,n,m,PM_MRK_DPTEG_FROM_RL4,A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a marked data side request ##000002F14A A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a marked data side request. #361,u,g,n,n,m,PM_MRK_DTLB_MISS_4K,Marked Data TLB Miss page size 4k ##000002D156 Marked Data TLB Miss page size 4k. #362,u,g,n,n,m,PM_MRK_FAB_RSP_BKILL_CYC,cycles L2 RC took for a bkill ##000002F150 cycles L2 RC took for a bkill. #363,u,g,n,n,m,PM_MRK_FAB_RSP_DCLAIM_CYC,cycles L2 RC took for a dclaim ##000002F152 cycles L2 RC took for a dclaim. #364,u,g,n,n,m,PM_MRK_FAB_RSP_RWITM_RTY,Sampled store did a rwitm and got a rty ##000002015E Sampled store did a rwitm and got a rty. #365,u,g,n,n,m,PM_MRK_FILT_MATCH,Marked filter Match ##000002013C Marked filter Match. #366,v,g,n,n,m,PM_MRK_FXU_FIN,fxu marked instr finish ##0000020134 fxu marked instr finish. #367,v,g,n,n,m,PM_MRK_INST_DECODED,marked instruction decoded ##0000020130 marked instruction decoded. Name from ISU? #368,v,g,n,n,m,PM_MRK_L2_RC_DISP,Marked Instruction RC dispatched in L2 ##0000020114 Marked Instruction RC dispatched in L2. #369,u,g,n,n,m,PM_MRK_LD_MISS_L1,Marked DL1 Demand Miss counted at exec time ##00000201E2 Marked DL1 Demand Miss counted at exec time. #370,u,g,n,n,m,PM_MRK_LSU_FLUSH,Flush: (marked) : All Cases ##000000D180 Flush: (marked) : All Cases42 #371,u,g,n,n,m,PM_MRK_LSU_FLUSH_LRQ,Flush: (marked) LRQ ##000000D188 Flush: (marked) LRQMarked LRQ flushes #372,u,g,n,n,m,PM_MRK_LSU_FLUSH_SRQ,Flush: (marked) SRQ ##000000D18A Flush: (marked) SRQMarked SRQ lhs flushes #373,u,g,n,n,m,PM_MRK_LSU_FLUSH_ULD,Flush: (marked) Unaligned Load ##000000D184 Flush: (marked) Unaligned LoadMarked unaligned load flushes #374,u,g,n,n,m,PM_MRK_LSU_FLUSH_UST,Flush: (marked) Unaligned Store ##000000D186 Flush: (marked) Unaligned StoreMarked unaligned store flushes #375,v,g,n,n,m,PM_MRK_NTF_FIN,Marked next to finish instruction finished ##0000020112 Marked next to finish instruction finished. #376,v,g,n,n,m,PM_MRK_ST_NEST,Marked store sent to nest ##0000020138 Marked store sent to nest. #377,v,g,n,n,n,PM_NESTED_TEND,Completion time nested tend ##00000020B0 Completion time nested tend #378,u,g,n,n,n,PM_NON_FAV_TBEGIN,Dispatch time non favored tbegin ##00000020B6 Dispatch time non favored tbegin #379,u,g,n,s,n,PM_NON_TM_RST_SC,non tm snp rst tm sc ##0000328084 non tm snp rst tm sc #380,v,g,n,n,n,PM_NTCG_ALL_FIN,Cycles after all instructions have finished to group completed ##000002001A Ccycles after all instructions have finished to group completed. #381,v,g,n,n,n,PM_OUTER_TBEGIN,Completion time outer tbegin ##00000020AC Completion time outer tbegin #382,v,g,n,n,n,PM_OUTER_TEND,Completion time outer tend ##00000020AE Completion time outer tend #383,v,g,n,n,n,PM_PMC1_OVERFLOW,Overflow from counter 1 ##0000020010 Overflow from counter 1. #384,u,g,n,n,n,PM_PREF_TRACKED,Total number of Prefetch Operations that were tracked ##000002005A Total number of Prefetch Operations that were tracked. #385,u,g,n,n,n,PM_PTE_PREFETCH,PTE prefetches ##000000E084 PTE prefetches42 #386,u,g,n,n,m,PM_RC_LIFETIME_EXC_32,Number of times the RC machine for a sampled instruction was active for more than 32 cycles ##DE200201E6 Reload latency exceeded 32 cyc #387,v,g,n,s,n,PM_RD_HIT_PF,rd machine hit l3 pf machine ##0000428086 rd machine hit l3 pf machine #388,u,g,n,s,n,PM_REAL_SRQ_FULL,Out of real srq entries ##0000020004 Out of real srq entries. #389,u,g,n,n,n,PM_RUN_CYC,Run_cycles ##00000200F4 Run_cycles. #390,u,g,n,n,n,PM_RUN_CYC_SMT2_SHRD_MODE,cycles this threads run latch is set and the core is in SMT2 shared mode ##000002006A Cycles run latch is set and core is in SMT2-shared mode. #391,u,g,n,n,n,PM_RUN_CYC_SMT4_MODE,cycles this threads run latch is set and the core is in SMT4 mode ##000002006C Cycles run latch is set and core is in SMT4 mode. #392,u,g,n,n,n,PM_SEC_ERAT_HIT,secondary ERAT Hit ##000000F082 secondary ERAT Hit42 #393,u,g,n,n,n,PM_SHL_CREATED,Store-Hit-Load Table Entry Created ##000000508C Store-Hit-Load Table Entry Created #394,u,g,n,n,n,PM_SHL_ST_CONVERT,Store-Hit-Load Table Read Hit with entry Enabled ##000000508E Store-Hit-Load Table Read Hit with entry Enabled #395,u,g,n,n,n,PM_SHL_ST_DISABLE,Store-Hit-Load Table Read Hit with entry Disabled (entry was disabled due to the entry shown to not prevent the flush) ##0000005090 Store-Hit-Load Table Read Hit with entry Disabled (entry was disabled due to the entry shown to not prevent the flush) #396,u,g,n,n,n,PM_SN0_ALLOC,SN mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point) ##0000026085 0.0 #397,v,g,n,s,n,PM_SN0_BUSY,SN mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point) ##0000026084 SN mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point) #398,v,g,n,s,n,PM_SNOOP_TLBIE,TLBIE snoop ##000000D0B2 TLBIE snoopSnoop TLBIE #399,v,g,n,n,n,PM_ST_CMPL,Store completion count ##0000020016 Store completion count. #400,v,g,n,n,n,PM_STCX_LSU,STCX executed reported at sent to nest ##000000C090 STCX executed reported at sent to nest42 #401,u,g,n,n,n,PM_ST_FIN,Store Instructions Finished ##00000200F0 Store Instructions Finished (store sent to nest). #402,u,g,n,n,n,PM_ST_FWD,Store forwards that finished ##0000020018 Store forwards that finished. #403,v,g,n,n,n,PM_SUSPENDED,Counter OFF ##0000020000 Counter OFF. #404,u,g,n,s,n,PM_SWAP_CANCEL,SWAP cancel , rtag not available ##0000003090 SWAP cancel , rtag not available #405,u,g,n,s,n,PM_SWAP_CANCEL_GPR,SWAP cancel , rtag not available for gpr ##0000003092 SWAP cancel , rtag not available for gpr #406,v,g,n,s,n,PM_SWAP_COMPLETE,swap cast in completed ##000000308C swap cast in completed #407,v,g,n,s,n,PM_SWAP_COMPLETE_GPR,swap cast in completed fpr gpr ##000000308E swap cast in completed fpr gpr #408,u,g,n,n,n,PM_TABLEWALK_CYC_PREF,tablewalk qualified for pte prefetches ##000000E086 tablewalk qualified for pte prefetches42 #409,u,g,n,n,n,PM_TABORT_TRECLAIM,Completion time tabortnoncd, tabortcd, treclaim ##00000020B2 Completion time tabortnoncd, tabortcd, treclaim #410,u,g,n,n,n,PM_TEND_PEND_CYC,TEND latency per thread ##000000E0BA TEND latency per thread42 #411,v,g,n,s,n,PM_THRD_ALL_RUN_CYC,All Threads in Run_cycles (was both threads in run_cycles) ##000002000C All Threads in Run_cycles (was both threads in run_cycles). #412,u,g,n,n,n,PM_THRD_PRIO_0_1_CYC, Cycles thread running at priority level 0 or 1 ##00000040BC Cycles thread running at priority level 0 or 1 #413,u,g,n,n,n,PM_THRD_PRIO_2_3_CYC, Cycles thread running at priority level 2 or 3 ##00000040BE Cycles thread running at priority level 2 or 3 #414,u,g,n,n,n,PM_THRD_PRIO_4_5_CYC, Cycles thread running at priority level 4 or 5 ##0000005080 Cycles thread running at priority level 4 or 5 #415,u,g,n,n,n,PM_THRD_PRIO_6_7_CYC, Cycles thread running at priority level 6 or 7 ##0000005082 Cycles thread running at priority level 6 or 7 #416,u,g,n,n,n,PM_THRD_REBAL_CYC,cycles rebalance was active ##0000003098 cycles rebalance was active #417,u,g,t,n,m,PM_THRESH_EXC_32,Threshold counter exceeded a value of 32 ##00000201E6 Threshold counter exceeded a value of 32. #418,u,g,t,n,m,PM_THRESH_EXC_512,Threshold counter exceeded a value of 512 ##00000201E8 Threshold counter exceeded a value of 512. #419,u,g,n,n,n,PM_TLB_MISS,TLB Miss (I + D) ##0000020066 TLB Miss (I + D). #420,v,g,n,n,n,PM_TM_BEGIN_ALL,Tm any tbegin ##00000020B8 Tm any tbegin #421,v,g,n,n,n,PM_TM_END_ALL,Tm any tend ##00000020BA Tm any tend #422,u,g,n,n,n,PM_TM_FAIL_CONF_NON_TM,TEXAS fail reason @ completion ##0000003086 TEXAS fail reason @ completion #423,u,g,n,n,n,PM_TM_FAIL_CON_TM,TEXAS fail reason @ completion ##0000003088 TEXAS fail reason @ completion #424,u,g,n,n,n,PM_TM_FAIL_DISALLOW,TM fail disallow ##000000E0B2 TM fail disallow42 #425,u,g,n,n,n,PM_TM_FAIL_FOOTPRINT_OVERFLOW,TEXAS fail reason @ completion ##0000003084 TEXAS fail reason @ completion #426,u,g,n,n,n,PM_TM_FAIL_NON_TX_CONFLICT,Non transactional conflict from LSU whtver gets repoted to texas ##000000E0B8 Non transactional conflict from LSU whtver gets repoted to texas42 #427,u,g,n,n,n,PM_TM_FAIL_SELF,TEXAS fail reason @ completion ##000000308A TEXAS fail reason @ completion #428,u,g,n,n,n,PM_TM_FAIL_TLBIE,TLBIE hit bloom filter ##000000E0B4 TLBIE hit bloom filter42 #429,u,g,n,n,n,PM_TM_FAIL_TX_CONFLICT,Transactional conflict from LSU, whatever gets reported to texas ##000000E0B6 Transactional conflict from LSU, whatever gets reported to texas 42 #430,u,g,n,s,n,PM_TM_FAV_CAUSED_FAIL,TM Load (fav) caused another thread to fail ##0000727086 TM Load (fav) caused another thread to fail #431,u,g,n,s,n,PM_TM_LD_CONF,TM Load (fav or non-fav) ran into conflict (failed) ##0000727084 TM Load (fav or non-fav) ran into conflict (failed) #432,u,g,n,s,n,PM_TM_RST_SC,tm snp rst tm sc ##0000328086 tm snp rst tm sc #433,v,g,n,n,n,PM_TM_TBEGIN,Tm nested tbegin ##00000020BC Tm nested tbegin #434,u,g,n,n,n,PM_TM_TRESUME,Tm resume ##0000003080 Tm resume #435,u,g,n,n,n,PM_TM_TSUSPEND,Tm suspend ##00000020BE Tm suspend #436,u,g,n,n,n,PM_TM_TX_PASS_RUN_CYC,cycles spent in successful transactions ##000002E012 run cycles spent in successful transactions. #437,u,g,n,n,n,PM_UP_PREF_L3,Micropartition prefetch ##000000E08C Micropartition prefetch42 #438,u,g,n,n,n,PM_UP_PREF_POINTER,Micrpartition pointer prefetches ##000000E08E Micrpartition pointer prefetches42 #439,u,g,n,n,n,PM_VSU0_16FLOP,Sixteen flops operation (SP vector versions of fdiv,fsqrt) ##000000A0A4 Sixteen flops operation (SP vector versions of fdiv,fsqrt) #440,v,g,n,n,n,PM_VSU0_1FLOP,one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished ##000000A080 one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finishedDecode into 1,2,4 FLOP according to instr IOP, multiplied by #vector elements according to route( eg x1, x2, x4) Only if instr sends finish to ISU #441,u,g,n,n,n,PM_VSU0_2FLOP,two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) ##000000A098 two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) #442,u,g,n,n,n,PM_VSU0_4FLOP,four flops operation (scalar fdiv, fsqrt, DP vector version of fmadd, fnmadd, fmsub, fnmsub, SP vector versions of single flop instructions) ##000000A09C four flops operation (scalar fdiv, fsqrt, DP vector version of fmadd, fnmadd, fmsub, fnmsub, SP vector versions of single flop instructions) #443,u,g,n,n,n,PM_VSU0_8FLOP,eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) ##000000A0A0 eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) #444,u,g,n,n,n,PM_VSU0_COMPLEX_ISSUED,Complex VMX instruction issued ##000000B0A4 Complex VMX instruction issued #445,u,g,n,n,n,PM_VSU0_CY_ISSUED,Cryptographic instruction RFC02196 Issued ##000000B0B4 Cryptographic instruction RFC02196 Issued #446,u,g,n,n,n,PM_VSU0_DD_ISSUED,64BIT Decimal Issued ##000000B0A8 64BIT Decimal Issued #447,u,g,n,n,n,PM_VSU0_DP_2FLOP,DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg ##000000A08C DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg #448,u,g,n,n,n,PM_VSU0_DP_FMA,DP vector version of fmadd,fnmadd,fmsub,fnmsub ##000000A090 DP vector version of fmadd,fnmadd,fmsub,fnmsub #449,u,g,n,n,n,PM_VSU0_DP_FSQRT_FDIV,DP vector versions of fdiv,fsqrt ##000000A094 DP vector versions of fdiv,fsqrt #450,u,g,n,n,n,PM_VSU0_DQ_ISSUED,128BIT Decimal Issued ##000000B0AC 128BIT Decimal Issued #451,u,g,n,n,n,PM_VSU0_EX_ISSUED,Direct move 32/64b VRFtoGPR RFC02206 Issued ##000000B0B0 Direct move 32/64b VRFtoGPR RFC02206 Issued #452,u,g,n,n,n,PM_VSU0_FIN,VSU0 Finished an instruction ##000000A0BC VSU0 Finished an instruction #453,u,g,n,n,n,PM_VSU0_FMA,two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only! ##000000A084 two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only! #454,u,g,n,n,n,PM_VSU0_FPSCR,Move to/from FPSCR type instruction issued on Pipe 0 ##000000B098 Move to/from FPSCR type instruction issued on Pipe 0 #455,u,g,n,n,n,PM_VSU0_FSQRT_FDIV,four flops operation (fdiv,fsqrt) Scalar Instructions only! ##000000A088 four flops operation (fdiv,fsqrt) Scalar Instructions only! #456,u,g,n,n,n,PM_VSU0_PERMUTE_ISSUED,Permute VMX Instruction Issued ##000000B090 Permute VMX Instruction Issued #457,u,g,n,n,n,PM_VSU0_SCALAR_DP_ISSUED,Double Precision scalar instruction issued on Pipe0 ##000000B088 Double Precision scalar instruction issued on Pipe0 #458,u,g,n,n,n,PM_VSU0_SIMPLE_ISSUED,Simple VMX instruction issued ##000000B094 Simple VMX instruction issued #459,u,g,n,n,n,PM_VSU0_SINGLE,FPU single precision ##000000A0A8 FPU single precision #460,u,g,n,n,n,PM_VSU0_SQ,Store Vector Issued ##000000B09C Store Vector Issued #461,u,g,n,n,n,PM_VSU0_STF,FPU store (SP or DP) issued on Pipe0 ##000000B08C FPU store (SP or DP) issued on Pipe0 #462,u,g,n,n,n,PM_VSU0_VECTOR_DP_ISSUED,Double Precision vector instruction issued on Pipe0 ##000000B080 Double Precision vector instruction issued on Pipe0 #463,u,g,n,n,n,PM_VSU0_VECTOR_SP_ISSUED,Single Precision vector instruction issued (executed) ##000000B084 Single Precision vector instruction issued (executed) #464,u,g,n,n,n,PM_VSU1_16FLOP,Sixteen flops operation (SP vector versions of fdiv,fsqrt) ##000000A0A6 Sixteen flops operation (SP vector versions of fdiv,fsqrt) #465,v,g,n,n,n,PM_VSU1_1FLOP,one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished ##000000A082 one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished #466,u,g,n,n,n,PM_VSU1_2FLOP,two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) ##000000A09A two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) #467,u,g,n,n,n,PM_VSU1_4FLOP,four flops operation (scalar fdiv, fsqrt, DP vector version of fmadd, fnmadd, fmsub, fnmsub, SP vector versions of single flop instructions) ##000000A09E four flops operation (scalar fdiv, fsqrt, DP vector version of fmadd, fnmadd, fmsub, fnmsub, SP vector versions of single flop instructions) #468,u,g,n,n,n,PM_VSU1_8FLOP,eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) ##000000A0A2 eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) #469,u,g,n,n,n,PM_VSU1_COMPLEX_ISSUED,Complex VMX instruction issued ##000000B0A6 Complex VMX instruction issued #470,u,g,n,n,n,PM_VSU1_CY_ISSUED,Cryptographic instruction RFC02196 Issued ##000000B0B6 Cryptographic instruction RFC02196 Issued #471,u,g,n,n,n,PM_VSU1_DD_ISSUED,64BIT Decimal Issued ##000000B0AA 64BIT Decimal Issued #472,u,g,n,n,n,PM_VSU1_DP_2FLOP,DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg ##000000A08E DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg #473,u,g,n,n,n,PM_VSU1_DP_FMA,DP vector version of fmadd,fnmadd,fmsub,fnmsub ##000000A092 DP vector version of fmadd,fnmadd,fmsub,fnmsub #474,u,g,n,n,n,PM_VSU1_DP_FSQRT_FDIV,DP vector versions of fdiv,fsqrt ##000000A096 DP vector versions of fdiv,fsqrt #475,u,g,n,n,n,PM_VSU1_DQ_ISSUED,128BIT Decimal Issued ##000000B0AE 128BIT Decimal Issued #476,u,g,n,n,n,PM_VSU1_EX_ISSUED,Direct move 32/64b VRFtoGPR RFC02206 Issued ##000000B0B2 Direct move 32/64b VRFtoGPR RFC02206 Issued #477,u,g,n,n,n,PM_VSU1_FIN,VSU1 Finished an instruction ##000000A0BE VSU1 Finished an instruction #478,u,g,n,n,n,PM_VSU1_FMA,two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only! ##000000A086 two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only! #479,u,g,n,n,n,PM_VSU1_FPSCR,Move to/from FPSCR type instruction issued on Pipe 0 ##000000B09A Move to/from FPSCR type instruction issued on Pipe 0 #480,u,g,n,n,n,PM_VSU1_FSQRT_FDIV,four flops operation (fdiv,fsqrt) Scalar Instructions only! ##000000A08A four flops operation (fdiv,fsqrt) Scalar Instructions only! #481,u,g,n,n,n,PM_VSU1_PERMUTE_ISSUED,Permute VMX Instruction Issued ##000000B092 Permute VMX Instruction Issued #482,u,g,n,n,n,PM_VSU1_SCALAR_DP_ISSUED,Double Precision scalar instruction issued on Pipe1 ##000000B08A Double Precision scalar instruction issued on Pipe1 #483,u,g,n,n,n,PM_VSU1_SIMPLE_ISSUED,Simple VMX instruction issued ##000000B096 Simple VMX instruction issued #484,u,g,n,n,n,PM_VSU1_SINGLE,FPU single precision ##000000A0AA FPU single precision #485,u,g,n,n,n,PM_VSU1_SQ,Store Vector Issued ##000000B09E Store Vector Issued #486,u,g,n,n,n,PM_VSU1_STF,FPU store (SP or DP) issued on Pipe1 ##000000B08E FPU store (SP or DP) issued on Pipe1 #487,u,g,n,n,n,PM_VSU1_VECTOR_DP_ISSUED,Double Precision vector instruction issued on Pipe1 ##000000B082 Double Precision vector instruction issued on Pipe1 #488,u,g,n,n,n,PM_VSU1_VECTOR_SP_ISSUED,Single Precision vector instruction issued (executed) ##000000B086 Single Precision vector instruction issued (executed) #489,v,g,n,n,n,PM_VSU_1FLOP,one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished ##000000A880 one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished #490,v,g,n,n,n,PM_VSU_2FLOP,two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) ##000000A898 two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) #491,v,g,n,n,n,PM_VSU_4FLOP,four flops operation (scalar fdiv, fsqrt, DP vector version of fmadd, fnmadd, fmsub, fnmsub, SP vector versions of single flop instructions) ##000000A89C four flops operation (scalar fdiv, fsqrt, DP vector version of fmadd, fnmadd, fmsub, fnmsub, SP vector versions of single flop instructions) #492,v,g,n,n,n,PM_VSU_8FLOP,eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) ##000000A8A0 eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) #493,v,g,n,n,n,PM_VSU_FMA,two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only ##000000A884 two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only #494,v,g,n,n,n,PM_VSU_FSQRT_FDIV,four flops operation (fdiv,fsqrt) Scalar Instructions only ##000000A888 four flops operation (fdiv,fsqrt) Scalar Instructions only $$$$$$$$ { counter 3 } #0,u,g,n,n,n,PM_ALL_SYS_PUMP_CPRED,Initial and Final Pump Scope was system pump for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate) ##0000630050 Initial and Final Pump Scope and data sourced across this scope was system pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) #1,u,g,n,n,n,PM_ALL_SYS_PUMP_MPRED,Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate) ##0000630052 Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or #2,u,g,n,n,n,PM_BANK_CONFLICT,Read blocked due to interleave conflict. The ifar logic will detect an interleave conflict and kill the data that was read that cycle. ##0000004082 Read blocked due to interleave conflict. The ifar logic will detect an interleave conflict and kill the data that was read that cycle. #3,v,g,n,n,n,PM_BR_BC_8,Pairable BC+8 branch that has not been converted to a Resolve Finished in the BRU pipeline ##0000005086 Pairable BC+8 branch that has not been converted to a Resolve Finished in the BRU pipeline #4,v,g,n,n,n,PM_BR_BC_8_CONV,Pairable BC+8 branch that was converted to a Resolve Finished in the BRU pipeline. ##0000005084 Pairable BC+8 branch that was converted to a Resolve Finished in the BRU pipeline. #5,v,g,n,n,n,PM_BR_MPRED_CCACHE,Conditional Branch Completed that was Mispredicted due to the Count Cache Target Prediction ##00000040AC Conditional Branch Completed that was Mispredicted due to the Count Cache Target Prediction #6,v,g,n,n,n,PM_BR_MPRED_CR,Conditional Branch Completed that was Mispredicted due to the BHT Direction Prediction (taken/not taken). ##00000040B8 Conditional Branch Completed that was Mispredicted due to the BHT Direction Prediction (taken/not taken). #7,u,g,n,n,n,PM_BR_MPRED_LSTACK,Conditional Branch Completed that was Mispredicted due to the Link Stack Target Prediction ##00000040AE Conditional Branch Completed that was Mispredicted due to the Link Stack Target Prediction #8,u,g,n,n,n,PM_BR_MPRED_TA,Conditional Branch Completed that was Mispredicted due to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that resolved Taken set this event. ##00000040BA Conditional Branch Completed that was Mispredicted due to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that resolved Taken set this event. #9,v,g,n,n,n,PM_BR_PRED_BR0,Conditional Branch Completed on BR0 (1st branch in group) in which the HW predicted the Direction or Target ##000000409C Conditional Branch Completed on BR0 (1st branch in group) in which the HW predicted the Direction or Target #10,v,g,n,n,n,PM_BR_PRED_BR1,Conditional Branch Completed on BR1 (2nd branch in group) in which the HW predicted the Direction or Target. Note: BR1 can only be used in Single Thread Mode. In all of the SMT modes, only one branch can complete, thus BR1 is unused. ##000000409E Conditional Branch Completed on BR1 (2nd branch in group) in which the HW predicted the Direction or Target. Note: BR1 can only be used in Single Thread Mode. In all of the SMT modes, only one branch can complete, thus BR1 is unused. #11,u,g,n,n,n,PM_BR_PRED_BR_CMPL,Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred(0) OR if_pc_br0_br_pred(1). ##000000489C IFU #12,v,g,n,n,n,PM_BR_PRED_CCACHE_BR0,Conditional Branch Completed on BR0 that used the Count Cache for Target Prediction ##00000040A4 Conditional Branch Completed on BR0 that used the Count Cache for Target Prediction #13,v,g,n,n,n,PM_BR_PRED_CCACHE_BR1,Conditional Branch Completed on BR1 that used the Count Cache for Target Prediction ##00000040A6 Conditional Branch Completed on BR1 that used the Count Cache for Target Prediction #14,u,g,n,n,n,PM_BR_PRED_CCACHE_CMPL,Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred(0) AND if_pc_br0_pred_type. ##00000048A4 IFU #15,v,g,n,n,n,PM_BR_PRED_CR_BR0,Conditional Branch Completed on BR0 that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and branches ##00000040B0 Conditional Branch Completed on BR0 that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and bra #16,v,g,n,n,n,PM_BR_PRED_CR_BR1,Conditional Branch Completed on BR1 that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and branches ##00000040B2 Conditional Branch Completed on BR1 that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and bra #17,u,g,n,n,n,PM_BR_PRED_CR_CMPL,Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred(1)='1'. ##00000048B0 IFU #18,u,g,n,n,n,PM_BR_PRED_LSTACK_BR0,Conditional Branch Completed on BR0 that used the Link Stack for Target Prediction ##00000040A8 Conditional Branch Completed on BR0 that used the Link Stack for Target Prediction #19,u,g,n,n,n,PM_BR_PRED_LSTACK_BR1,Conditional Branch Completed on BR1 that used the Link Stack for Target Prediction ##00000040AA Conditional Branch Completed on BR1 that used the Link Stack for Target Prediction #20,u,g,n,n,n,PM_BR_PRED_LSTACK_CMPL,Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred(0) AND (not if_pc_br0_pred_type). ##00000048A8 IFU #21,u,g,n,n,n,PM_BR_PRED_TA_BR0,Conditional Branch Completed on BR0 that had its target address predicted. Only XL-form branches set this event. ##00000040B4 Conditional Branch Completed on BR0 that had its target address predicted. Only XL-form branches set this event. #22,u,g,n,n,n,PM_BR_PRED_TA_BR1,Conditional Branch Completed on BR1 that had its target address predicted. Only XL-form branches set this event. ##00000040B6 Conditional Branch Completed on BR1 that had its target address predicted. Only XL-form branches set this event. #23,u,g,n,n,n,PM_BR_PRED_TA_CMPL,Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred(0)='1'. ##00000048B4 IFU #24,v,g,n,n,n,PM_BR_UNCOND_BR0,Unconditional Branch Completed on BR0. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was coverted to a Resolve. ##00000040A0 Unconditional Branch Completed on BR0. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was coverted to a Resolve. #25,v,g,n,n,n,PM_BR_UNCOND_BR1,Unconditional Branch Completed on BR1. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was coverted to a Resolve. ##00000040A2 Unconditional Branch Completed on BR1. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was coverted to a Resolve. #26,u,g,n,n,n,PM_BR_UNCOND_CMPL,Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred=00 AND if_pc_br0_completed. ##00000048A0 IFU #27,v,g,n,s,n,PM_CASTOUT_ISSUED,Castouts issued ##0000003094 Castouts issued #28,v,g,n,s,n,PM_CASTOUT_ISSUED_GPR,Castouts issued GPR ##0000003096 Castouts issued GPR #29,u,g,n,n,n,PM_CLB_HELD,CLB Hold: Any Reason ##0000002090 CLB Hold: Any Reason #30,v,g,n,n,n,PM_CMPLU_STALL_COQ_FULL,Completion stall due to CO q full ##0000030026 Completion stall due to CO q full. #31,v,g,n,n,n,PM_CMPLU_STALL_FLUSH,completion stall due to flush by own thread ##0000030038 completion stall due to flush by own thread. #32,v,g,n,n,n,PM_CMPLU_STALL_HWSYNC,completion stall due to hwsync ##0000030036 completion stall due to hwsync. #33,v,g,n,n,n,PM_CMPLU_STALL_MEM_ECC_DELAY,Completion stall due to mem ECC delay ##0000030028 Completion stall due to mem ECC delay. #34,u,g,n,n,n,PM_CMPLU_STALL_OTHER_CMPL,Instructions core completed while this tread was stalled ##0000030006 Instructions core completed while this thread was stalled. #35,v,g,n,s,n,PM_CO_USAGE,Continuous 16 cycle(2to1) window where this signals rotates thru sampling each L2 CO machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running ##000003608A Continuous 16 cycle(2to1) window where this signals rotates thru sampling each L2 CO machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running #36,v,g,n,n,n,PM_CYC,Cycles ##000003001E Cycles . #37,u,g,n,n,n,PM_DATA_ALL_FROM_DL2L3_SHR,The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either demand loads or data prefetch ##000063C048 The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 #38,u,g,n,n,n,PM_DATA_ALL_FROM_DL4,The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to either demand loads or data prefetch ##000063C04C The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 #39,u,g,n,n,n,PM_DATA_ALL_FROM_L21_SHR,The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to either demand loads or data prefetch ##000063C046 The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 #40,u,g,n,n,n,PM_DATA_ALL_FROM_L2_DISP_CONFLICT_LDHITST,The processor's data cache was reloaded from local core's L2 with load hit store conflict due to either demand loads or data prefetch ##000063C040 The processor's data cache was reloaded from local core's L2 with load hit store conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 #41,u,g,n,n,n,PM_DATA_ALL_FROM_L31_ECO_SHR,The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to either demand loads or data prefetch ##000063C044 The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 #42,u,g,n,n,n,PM_DATA_ALL_FROM_L3_DISP_CONFLICT,The processor's data cache was reloaded from local core's L3 with dispatch conflict due to either demand loads or data prefetch ##000063C042 The processor's data cache was reloaded from local core's L3 with dispatch conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 #43,u,g,n,n,n,PM_DATA_ALL_FROM_RMEM,The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to either demand loads or data prefetch ##000063C04A The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 #44,u,g,n,n,n,PM_DATA_ALL_SYS_PUMP_CPRED,Initial and Final Pump Scope was system pump (prediction=correct) for either demand loads or data prefetch ##000063C050 Initial and Final Pump Scope and data sourced across this scope was system pump for a demand load #45,u,g,n,n,n,PM_DATA_ALL_SYS_PUMP_MPRED,Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for either demand loads or data prefetch ##000063C052 Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or #46,v,g,n,n,n,PM_DATA_FROM_DL2L3_SHR,The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load ##000003C048 The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. #47,v,g,n,n,n,PM_DATA_FROM_DL4,The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a demand load ##000003C04C The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. #48,v,g,n,n,n,PM_DATA_FROM_L21_SHR,The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a demand load ##000003C046 The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. #49,v,g,n,n,n,PM_DATA_FROM_L2_DISP_CONFLICT_LDHITST,The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a demand load ##000003C040 The processor's data cache was reloaded from local core's L2 with load hit store conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. #50,v,g,n,n,n,PM_DATA_FROM_L31_ECO_SHR,The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a demand load ##000003C044 The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. #51,v,g,n,n,n,PM_DATA_FROM_L3_DISP_CONFLICT,The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a demand load ##000003C042 The processor's data cache was reloaded from local core's L3 with dispatch conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. #52,v,g,n,n,n,PM_DATA_FROM_L3MISS,Demand LD - L3 Miss (not L2 hit and not L3 hit) ##00000300FE Demand LD - L3 Miss (not L2 hit and not L3 hit). #53,v,g,n,n,n,PM_DATA_FROM_RMEM,The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a demand load ##000003C04A The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. #54,u,g,n,n,n,PM_DATA_SYS_PUMP_CPRED,Initial and Final Pump Scope was system pump (prediction=correct) for a demand load ##000003C050 Initial and Final Pump Scope and data sourced across this scope was system pump for a demand load. #55,u,g,n,n,n,PM_DATA_SYS_PUMP_MPRED,Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for a demand load ##000003C052 Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or #56,u,g,n,n,n,PM_DATA_TABLEWALK_CYC,Tablwalk Cycles (could be 1 or 2 active) ##000003001A Data Tablewalk Active. #57,u,g,n,n,n,PM_DC_COLLISIONS,DATA Cache collisions ##000000E0BC DATA Cache collisions42 #58,u,g,n,n,n,PM_DC_PREF_STREAM_STRIDED_CONF,A demand load referenced a line in an active strided prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. ##000003E050 A demand load referenced a line in an active strided prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.. #59,u,g,n,n,n,PM_DERAT_MISS_16M,Data ERAT Miss (Data TLB Access) page size 16M ##000003C054 Data ERAT Miss (Data TLB Access) page size 16M. #60,u,g,n,n,n,PM_DFU,Finish DFU (all finish) ##000000B0BA Finish DFU (all finish) #61,u,g,n,n,n,PM_DFU_DCFFIX,Convert from fixed opcode finish (dcffix,dcffixq) ##000000B0BE Convert from fixed opcode finish (dcffix,dcffixq) #62,u,g,n,n,n,PM_DFU_DENBCD,BCD->DPD opcode finish (denbcd, denbcdq) ##000000B0BC BCD->DPD opcode finish (denbcd, denbcdq) #63,u,g,n,n,n,PM_DFU_MC,Finish DFU multicycle ##000000B0B8 Finish DFU multicycle #64,u,g,n,n,n,PM_DISP_CLB_HELD_BAL,Dispatch/CLB Hold: Balance ##0000002092 Dispatch/CLB Hold: Balance #65,u,g,n,n,n,PM_DISP_CLB_HELD_RES,Dispatch/CLB Hold: Resource ##0000002094 Dispatch/CLB Hold: Resource #66,u,g,n,n,n,PM_DISP_CLB_HELD_SB,Dispatch/CLB Hold: Scoreboard ##00000020A8 Dispatch/CLB Hold: Scoreboard #67,u,g,n,n,n,PM_DISP_CLB_HELD_SYNC,Dispatch/CLB Hold: Sync type instruction ##0000002098 Dispatch/CLB Hold: Sync type instruction #68,v,g,n,n,n,PM_DISP_CLB_HELD_TLBIE,Dispatch Hold: Due to TLBIE ##0000002096 Dispatch Hold: Due to TLBIE #69,u,g,n,n,n,PM_DISP_HELD_SRQ_FULL,Dispatch held due SRQ no room ##0000030018 Dispatch held due SRQ no room. #70,u,g,n,n,n,PM_DISP_HOLD_GCT_FULL,Dispatch Hold Due to no space in the GCT ##00000030A6 Dispatch Hold Due to no space in the GCT #71,u,g,n,n,n,PM_DISP_WT,Dispatched Starved ##0000030008 Dispatched Starved (not held, nothing to dispatch). #72,u,g,n,n,n,PM_DPTEG_FROM_DL2L3_SHR,A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request ##000003E048 A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request. #73,u,g,n,n,n,PM_DPTEG_FROM_DL4,A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a data side request ##000003E04C A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a data side request. #74,u,g,n,n,n,PM_DPTEG_FROM_L21_SHR,A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a data side request ##000003E046 A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a data side request. #75,u,g,n,n,n,PM_DPTEG_FROM_L2_DISP_CONFLICT_LDHITST,A Page Table Entry was loaded into the TLB from local core's L2 with load hit store conflict due to a data side request ##000003E040 A Page Table Entry was loaded into the TLB from local core's L2 with load hit store conflict due to a data side request. #76,u,g,n,n,n,PM_DPTEG_FROM_L31_ECO_SHR,A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a data side request ##000003E044 A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a data side request. #77,u,g,n,n,n,PM_DPTEG_FROM_L3_DISP_CONFLICT,A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a data side request ##000003E042 A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a data side request. #78,u,g,n,n,n,PM_DPTEG_FROM_RMEM,A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a data side request ##000003E04A A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a data side request. #79,v,g,n,n,n,PM_DSLB_MISS,Data SLB Miss - Total of all segment sizes ##000000D094 Data SLB Miss - Total of all segment sizesData SLB misses #80,v,g,n,n,n,PM_DTLB_MISS,Data PTEG reload ##00000300FC Data PTEG Reloaded (DTLB Miss). #81,u,g,n,n,n,PM_DTLB_MISS_64K,Data TLB Miss page size 64K ##000003C056 Data TLB Miss page size 64K. #82,u,g,n,n,n,PM_EAT_FORCE_MISPRED,XL-form branch was mispredicted due to the predicted target address missing from EAT. The EAT forces a mispredict in this case since there is no predicated target to validate. This is a rare case that may occur when the EAT is full and a branch is issue ##00000050A8 XL-form branch was mispredicted due to the predicted target address missing from EAT. The EAT forces a mispredict in this case since there is no predicated target to validate. This is a rare case that may occur when the EAT is full and a branch is #83,u,g,n,n,n,PM_EAT_FULL_CYC,Cycles No room in EAT ##0000004084 Cycles No room in EATSet on bank conflict and case where no ibuffers available. #84,u,g,n,n,n,PM_EE_OFF_EXT_INT,Ee off and external interrupt ##0000002080 Ee off and external interrupt #85,u,g,n,n,n,PM_FAV_TBEGIN,Dispatch time Favored tbegin ##00000020B4 Dispatch time Favored tbegin #86,u,g,n,n,n,PM_FLOP_SUM_SCALAR,flops summary scalar instructions ##000000A0AE flops summary scalar instructions #87,u,g,n,n,n,PM_FLOP_SUM_VEC,flops summary vector instructions ##000000A0AC flops summary vector instructions #88,u,g,n,n,n,PM_FLUSH_BR_MPRED,Flush caused by branch mispredict ##0000002084 Flush caused by branch mispredict #89,u,g,n,n,n,PM_FLUSH_COMPLETION,Completion Flush ##0000030012 Completion Flush. #90,u,g,n,n,n,PM_FLUSH_DISP,Dispatch flush ##0000002082 Dispatch flush #91,u,g,n,n,n,PM_FLUSH_DISP_SB,Dispatch Flush: Scoreboard ##000000208C Dispatch Flush: Scoreboard #92,u,g,n,n,n,PM_FLUSH_DISP_SYNC,Dispatch Flush: Sync ##0000002088 Dispatch Flush: Sync #93,u,g,n,n,n,PM_FLUSH_DISP_TLBIE,Dispatch Flush: TLBIE ##000000208A Dispatch Flush: TLBIE #94,u,g,n,n,n,PM_FLUSH_LSU,Flush initiated by LSU ##000000208E Flush initiated by LSU #95,u,g,n,n,n,PM_FLUSH_PARTIAL,Partial flush ##0000002086 Partial flush #96,u,g,n,n,n,PM_FPU0_FCONV,Convert instruction executed ##000000A0B0 Convert instruction executed #97,u,g,n,n,n,PM_FPU0_FEST,Estimate instruction executed ##000000A0B8 Estimate instruction executed #98,u,g,n,n,n,PM_FPU0_FRSP,Round to single precision instruction executed ##000000A0B4 Round to single precision instruction executed #99,u,g,n,n,n,PM_FPU1_FCONV,Convert instruction executed ##000000A0B2 Convert instruction executed #100,u,g,n,n,n,PM_FPU1_FEST,Estimate instruction executed ##000000A0BA Estimate instruction executed #101,u,g,n,n,n,PM_FPU1_FRSP,Round to single precision instruction executed ##000000A0B6 Round to single precision instruction executed #102,u,g,n,s,n,PM_FREQ_DOWN,Power Management: Below Threshold B ##000003000C Frequency is being slewed down due to Power Management. #103,u,g,n,n,n,PM_FUSION_TOC_GRP0_1,One pair of instructions fused with TOC in Group0 ##00000050B0 One pair of instructions fused with TOC in Group0 #104,u,g,n,n,n,PM_FUSION_TOC_GRP0_2,Two pairs of instructions fused with TOCin Group0 ##00000050AE Two pairs of instructions fused with TOCin Group0 #105,u,g,n,n,n,PM_FUSION_TOC_GRP0_3,Three pairs of instructions fused with TOC in Group0 ##00000050AC Three pairs of instructions fused with TOC in Group0 #106,u,g,n,n,n,PM_FUSION_TOC_GRP1_1,One pair of instructions fused with TOX in Group1 ##00000050B2 One pair of instructions fused with TOX in Group1 #107,u,g,n,n,n,PM_FUSION_VSX_GRP0_1,One pair of instructions fused with VSX in Group0 ##00000050B8 One pair of instructions fused with VSX in Group0 #108,u,g,n,n,n,PM_FUSION_VSX_GRP0_2,Two pairs of instructions fused with VSX in Group0 ##00000050B6 Two pairs of instructions fused with VSX in Group0 #109,u,g,n,n,n,PM_FUSION_VSX_GRP0_3,Three pairs of instructions fused with VSX in Group0 ##00000050B4 Three pairs of instructions fused with VSX in Group0 #110,u,g,n,n,n,PM_FUSION_VSX_GRP1_1,One pair of instructions fused with VSX in Group1 ##00000050BA One pair of instructions fused with VSX in Group1 #111,u,g,n,n,n,PM_FXU0_BUSY_FXU1_IDLE,fxu0 busy and fxu1 idle ##000003000E fxu0 busy and fxu1 idle. #112,v,g,n,n,n,PM_GCT_MERGE,Group dispatched on a merged GCT empty. GCT entries can be merged only within the same thread ##00000030A4 Group dispatched on a merged GCT empty. GCT entries can be merged only within the same thread #113,u,g,n,n,n,PM_GCT_UTIL_11_14_ENTRIES,GCT Utilization 11-14 entries ##00000020A2 GCT Utilization 11-14 entries #114,u,g,n,n,n,PM_GCT_UTIL_1_2_ENTRIES,GCT Utilization 1-2 entries ##000000209C GCT Utilization 1-2 entries #115,u,g,n,n,n,PM_GCT_UTIL_15_17_ENTRIES,GCT Utilization 15-17 entries ##00000020A4 GCT Utilization 15-17 entries #116,v,g,n,n,n,PM_GCT_UTIL_18_ENTRIES,GCT Utilization 18+ entries ##00000020A6 GCT Utilization 18+ entries #117,u,g,n,n,n,PM_GCT_UTIL_3_6_ENTRIES,GCT Utilization 3-6 entries ##000000209E GCT Utilization 3-6 entries #118,u,g,n,n,n,PM_GCT_UTIL_7_10_ENTRIES,GCT Utilization 7-10 entries ##00000020A0 GCT Utilization 7-10 entries #119,u,g,n,n,n,PM_GRP_CMPL,group completed ##0000030004 group completed. #120,u,g,n,n,n,PM_GRP_DISP,group dispatch ##000003000A dispatch_success (Group Dispatched). #121,u,g,n,n,n,PM_GRP_NON_FULL_GROUP,GROUPs where we did not have 6 non branch instructions in the group(ST mode), in SMT mode 3 non branches ##000000509C GROUPs where we did not have 6 non branch instructions in the group(ST mode), in SMT mode 3 non branches #122,u,g,n,n,n,PM_GRP_TERM_2ND_BRANCH,There were enough instructions in the Ibuffer, but 2nd branch ends group ##00000050A4 There were enough instructions in the Ibuffer, but 2nd branch ends group #123,u,g,n,n,n,PM_GRP_TERM_FPU_AFTER_BR,There were enough instructions in the Ibuffer, but FPU OP IN same group after a branch terminates a group, cant do partial flushes ##00000050A6 There were enough instructions in the Ibuffer, but FPU OP IN same group after a branch terminates a group, cant do partial flushes #124,u,g,n,n,n,PM_GRP_TERM_NOINST,Do not fill every slot in the group, Not enough instructions in the Ibuffer. This includes cases where the group started with enough instructions, but some got knocked out by a cache miss or branch redirect (which would also empty the Ibuffer). ##000000509E Do not fill every slot in the group, Not enough instructions in the Ibuffer. This includes cases where the group started with enough instructions, but some got knocked out by a cache miss or branch redirect (which would also empty the Ibuffer). #125,u,g,n,n,n,PM_GRP_TERM_OTHER,There were enough instructions in the Ibuffer, but the group terminated early for some other reason, most likely due to a First or Last. ##00000050A0 There were enough instructions in the Ibuffer, but the group terminated early for some other reason, most likely due to a First or Last. #126,u,g,n,n,n,PM_GRP_TERM_SLOT_LIMIT,There were enough instructions in the Ibuffer, but 3 src RA/RB/RC , 2 way crack caused a group termination ##00000050A2 There were enough instructions in the Ibuffer, but 3 src RA/RB/RC , 2 way crack caused a group termination #127,u,g,n,n,n,PM_IBUF_FULL_CYC,Cycles No room in ibuff ##0000004086 Cycles No room in ibufffully qualified tranfer (if5 valid). #128,u,g,n,n,n,PM_IC_DEMAND_L2_BHT_REDIRECT, L2 I cache demand request due to BHT redirect, branch redirect ( 2 bubbles 3 cycles) ##0000004098 L2 I cache demand request due to BHT redirect, branch redirect ( 2 bubbles 3 cycles) #129,u,g,n,n,n,PM_IC_DEMAND_L2_BR_REDIRECT, L2 I cache demand request due to branch Mispredict ( 15 cycle path) ##000000409A L2 I cache demand request due to branch Mispredict ( 15 cycle path) #130,u,g,n,n,n,PM_IC_DEMAND_REQ,Demand Instruction fetch request ##0000004088 Demand Instruction fetch request #131,u,g,n,n,n,PM_IC_INVALIDATE,Ic line invalidated ##000000508A Ic line invalidated #132,u,g,n,n,n,PM_IC_PREF_CANCEL_HIT,Prefetch Canceled due to icache hit ##0000004092 Prefetch Canceled due to icache hit #133,u,g,n,n,n,PM_IC_PREF_CANCEL_L2,L2 Squashed request ##0000004094 L2 Squashed request #134,u,g,n,n,n,PM_IC_PREF_CANCEL_PAGE,Prefetch Canceled due to page boundary ##0000004090 Prefetch Canceled due to page boundary #135,u,g,n,n,n,PM_IC_PREF_REQ,Instruction prefetch requests ##000000408A Instruction prefetch requests #136,v,g,n,n,n,PM_IC_PREF_WRITE,Instruction prefetch written into IL1 ##000000408E Instruction prefetch written into IL1 #137,u,g,n,n,n,PM_IC_RELOAD_PRIVATE,Reloading line was brought in private for a specific thread. Most lines are brought in shared for all eight thrreads. If RA does not match then invalidates and then brings it shared to other thread. In P7 line brought in private , then line was invalidat ##0000004096 Reloading line was brought in private for a specific thread. Most lines are brought in shared for all eight thrreads. If RA does not match then invalidates and then brings it shared to other thread. In P7 line brought in private , then line was inv #138,v,g,n,n,n,PM_IERAT_RELOAD_64K,IERAT Reloaded (Miss) for a 64k page ##000003006A IERAT Reloaded (Miss) for a 64k page. #139,u,g,n,s,n,PM_IFETCH_THROTTLE,Cycles in which Instruction fetch throttle was active ##000003405E Cycles instruction fecth was throttled in IFU. #140,u,g,n,n,n,PM_IFU_L2_TOUCH,L2 touch to update MRU on a line ##0000005088 L2 touch to update MRU on a line #141,u,g,n,n,n,PM_INST_ALL_FROM_DL2L3_SHR,The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to instruction fetches and prefetches ##0000534048 The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 #142,u,g,n,n,n,PM_INST_ALL_FROM_DL4,The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to instruction fetches and prefetches ##000053404C The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 #143,u,g,n,n,n,PM_INST_ALL_FROM_L21_SHR,The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due to instruction fetches and prefetches ##0000534046 The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 #144,u,g,n,n,n,PM_INST_ALL_FROM_L2_DISP_CONFLICT_LDHITST,The processor's Instruction cache was reloaded from local core's L2 with load hit store conflict due to instruction fetches and prefetches ##0000534040 The processor's Instruction cache was reloaded from local core's L2 with load hit store conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 #145,u,g,n,n,n,PM_INST_ALL_FROM_L31_ECO_SHR,The processor's Instruction cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to instruction fetches and prefetches ##0000534044 The processor's Instruction cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 #146,u,g,n,n,n,PM_INST_ALL_FROM_L3_DISP_CONFLICT,The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to instruction fetches and prefetches ##0000534042 The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 #147,u,g,n,n,n,PM_INST_ALL_FROM_RMEM,The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to instruction fetches and prefetches ##000053404A The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 #148,u,g,n,n,n,PM_INST_ALL_SYS_PUMP_CPRED,Initial and Final Pump Scope was system pump (prediction=correct) for instruction fetches and prefetches ##0000534050 Initial and Final Pump Scope and data sourced across this scope was system pump for an instruction fetch #149,u,g,n,n,n,PM_INST_ALL_SYS_PUMP_MPRED,Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for instruction fetches and prefetches ##0000534052 Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or #150,v,g,n,n,n,PM_INST_CMPL,Number of PowerPC Instructions that completed. ##0000030002 PPC Instructions Finished (completed). #151,u,g,n,n,n,PM_INST_DISP, PPC Dispatched ##00000300F2 PPC Dispatched. #152,u,g,n,n,n,PM_INST_FROM_DL2L3_SHR,The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction fetch (not prefetch) ##0000034048 The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . #153,u,g,n,n,n,PM_INST_FROM_DL4,The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to an instruction fetch (not prefetch) ##000003404C The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . #154,u,g,n,n,n,PM_INST_FROM_L1,Instruction fetches from L1 ##0000004080 Instruction fetches from L1 #155,u,g,n,n,n,PM_INST_FROM_L21_SHR,The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due to an instruction fetch (not prefetch) ##0000034046 The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . #156,u,g,n,n,n,PM_INST_FROM_L2_DISP_CONFLICT_LDHITST,The processor's Instruction cache was reloaded from local core's L2 with load hit store conflict due to an instruction fetch (not prefetch) ##0000034040 The processor's Instruction cache was reloaded from local core's L2 with load hit store conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . #157,u,g,n,n,n,PM_INST_FROM_L31_ECO_SHR,The processor's Instruction cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to an instruction fetch (not prefetch) ##0000034044 The processor's Instruction cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . #158,u,g,n,n,n,PM_INST_FROM_L3_DISP_CONFLICT,The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to an instruction fetch (not prefetch) ##0000034042 The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . #159,v,g,n,n,n,PM_INST_FROM_L3MISS,Marked instruction was reloaded from a location beyond the local chiplet ##00000300FA Inst from L3 miss. #160,u,g,n,n,n,PM_INST_FROM_RMEM,The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to an instruction fetch (not prefetch) ##000003404A The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . #161,u,g,n,n,n,PM_INST_IMC_MATCH_DISP,Matched Instructions Dispatched ##0000030016 IMC Matches dispatched. #162,u,g,n,n,n,PM_INST_SYS_PUMP_CPRED,Initial and Final Pump Scope was system pump (prediction=correct) for an instruction fetch ##0000034050 Initial and Final Pump Scope and data sourced across this scope was system pump for an instruction fetch. #163,u,g,n,n,n,PM_INST_SYS_PUMP_MPRED,Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for an instruction fetch ##0000034052 Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or #164,u,g,n,n,n,PM_IOPS_DISP,Internal Operations dispatched ##0000030014 IOPS dispatched. #165,u,g,n,n,n,PM_IPTEG_FROM_DL2L3_SHR,A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request ##0000035048 A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request. #166,u,g,n,n,n,PM_IPTEG_FROM_DL4,A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a instruction side request ##000003504C A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a instruction side request. #167,u,g,n,n,n,PM_IPTEG_FROM_L21_SHR,A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a instruction side request ##0000035046 A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a instruction side request. #168,u,g,n,n,n,PM_IPTEG_FROM_L2_DISP_CONFLICT_LDHITST,A Page Table Entry was loaded into the TLB from local core's L2 with load hit store conflict due to a instruction side request ##0000035040 A Page Table Entry was loaded into the TLB from local core's L2 with load hit store conflict due to a instruction side request. #169,u,g,n,n,n,PM_IPTEG_FROM_L31_ECO_SHR,A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a instruction side request ##0000035044 A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a instruction side request. #170,u,g,n,n,n,PM_IPTEG_FROM_L3_DISP_CONFLICT,A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a instruction side request ##0000035042 A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a instruction side request. #171,u,g,n,n,n,PM_IPTEG_FROM_RMEM,A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a instruction side request ##000003504A A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a instruction side request. #172,v,g,n,n,n,PM_ISLB_MISS,I SLB Miss. ##000000D096 I SLB Miss. #173,u,g,n,s,n,PM_ISU_REF_FX0,FX0 ISU reject ##00000030AC FX0 ISU reject #174,u,g,n,s,n,PM_ISU_REF_FX1,FX1 ISU reject ##00000030AE FX1 ISU reject #175,u,g,n,n,n,PM_ISU_REF_FXU,FXU ISU reject from either pipe ##00000038AC ISU #176,u,g,n,s,n,PM_ISU_REF_LS0,LS0 ISU reject ##00000030B0 LS0 ISU reject #177,u,g,n,s,n,PM_ISU_REF_LS1,LS1 ISU reject ##00000030B2 LS1 ISU reject #178,u,g,n,s,n,PM_ISU_REF_LS2,LS2 ISU reject ##00000030B4 LS2 ISU reject #179,u,g,n,s,n,PM_ISU_REF_LS3,LS3 ISU reject ##00000030B6 LS3 ISU reject #180,u,g,n,s,n,PM_ISU_REJECT_RES_NA,ISU reject due to resource not available ##00000030A2 ISU reject due to resource not available #181,v,g,n,s,n,PM_ISU_REJECTS_ALL,All isu rejects could be more than 1 per cycle ##000000309C All isu rejects could be more than 1 per cycle #182,v,g,n,s,n,PM_ISU_REJECT_SAR_BYPASS,Reject because of SAR bypass ##000000309E Reject because of SAR bypass #183,u,g,n,s,n,PM_ISU_REJECT_SRC_NA,ISU reject due to source not available ##00000030A0 ISU reject due to source not available #184,u,g,n,s,n,PM_ISU_REJ_VS0,VS0 ISU reject ##00000030A8 VS0 ISU reject #185,u,g,n,s,n,PM_ISU_REJ_VS1,VS1 ISU reject ##00000030AA VS1 ISU reject #186,u,g,n,n,n,PM_ISU_REJ_VSU,VSU ISU reject from either pipe ##00000038A8 ISU #187,u,g,n,n,n,PM_ISYNC,Isync count per thread ##00000030B8 Isync count per thread #188,v,g,n,n,n,PM_L1_DCACHE_RELOAD_VALID,DL1 reloaded due to Demand Load ##00000300F6 DL1 reloaded due to Demand Load . #189,v,g,n,n,n,PM_L1_DEMAND_WRITE,Instruction Demand sectors wriittent into IL1 ##000000408C Instruction Demand sectors wriittent into IL1 #190,v,g,n,n,n,PM_L1_ICACHE_RELOADED_PREF,Counts all Icache prefetch reloads ( includes demand turned into prefetch) ##0000030068 Counts all Icache prefetch reloads ( includes demand turned into prefetch). #191,u,g,n,n,m,PM_L1MISS_LAT_EXC_1024,L1 misses that took longer than 1024 cyles to resolve (miss to reload) ##67200301EA Reload latency exceeded 1024 cyc #192,v,g,n,n,n,PM_L2_INST,All successful I-side dispatches for this thread (excludes i_l2mru_tch reqs) ##0000436088 All successful I-side dispatches for this thread (excludes i_l2mru_tch reqs) #193,v,g,n,n,n,PM_L2_INST_MISS,All successful i-side dispatches that were an L2miss for this thread (excludes i_l2mru_tch reqs) ##000043608A All successful i-side dispatches that were an L2miss for this thread (excludes i_l2mru_tch reqs) #194,v,g,n,n,n,PM_L2_LD_DISP,All successful load dispatches ##0000437088 All successful load dispatches #195,v,g,n,n,n,PM_L2_LD_HIT,All successful load dispatches that were L2 hits ##000043708A All successful load dispatches that were L2 hits #196,u,g,n,n,n,PM_L2_RCST_DISP, L2 RC store dispatch attempt ##0000536088 L2 RC store dispatch attempt #197,u,g,n,n,n,PM_L2_RCST_DISP_FAIL_ADDR, L2 RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ ##000053608A L2 RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ #198,v,g,n,s,n,PM_L2_RC_ST_DONE,RC did st to line that was Tx or Sx ##0000537088 RC did st to line that was Tx or Sx #199,u,g,n,s,n,PM_L2_RTY_LD,RC retries on PB for any load from core ##000063708A RC retries on PB for any load from core #200,u,g,n,s,n,PM_L2_RTY_ST,RC retries on PB for any store from core ##000003708A RC retries on PB for any store from core #201,u,g,n,s,n,PM_L2_SN_SX_I_DONE,SNP dispatched and went from Sx or Tx to Ix ##000053708A SNP dispatched and went from Sx or Tx to Ix #202,u,g,n,s,n,PM_L2_SYS_GUESS_CORRECT,L2 guess sys and guess was correct (ie data beyond-6chip) ##0000636088 L2 guess sys and guess was correct (ie data beyond-6chip) #203,u,g,n,s,n,PM_L2_SYS_GUESS_WRONG,L2 guess sys and guess was not correct (ie data ^beyond-6chip) ##000063608A L2 guess sys and guess was not correct (ie data ^beyond-6chip) #204,c,g,n,s,n,PM_L2_SYS_PUMP,RC requests that were system pump attempts ##0000037088 RC requests that were system pump attempts #205,u,g,n,n,n,PM_L2_TM_ST_ABORT_SISTER,TM marked store abort ##000003E05C TM marked store abort. #206,u,g,n,s,n,PM_L3_CINJ,l3 ci of cache inject ##000023808A l3 ci of cache inject #207,v,g,n,s,n,PM_L3_CO,l3 castout occuring ( does not include casthrough or log writes (cinj/dmaw) ##0000438088 l3 castout occuring ( does not include casthrough or log writes (cinj/dmaw) #208,u,g,n,n,n,PM_L3_CO0_ALLOC,lifetime, sample of CO machine 0 valid ##000083908B 0.0 #209,v,g,n,s,n,PM_L3_CO0_BUSY,lifetime, sample of CO machine 0 valid ##000083908A lifetime, sample of CO machine 0 valid #210,u,g,n,s,n,PM_L3_CO_LCO,Total L3 castouts occurred on LCO ##0000238088 Total L3 castouts occurred on LCO #211,v,g,n,s,n,PM_L3_CO_MEPF,L3 CO of line in Mep state ( includes casthrough ##000003E05E L3 CO of line in Mep state ( includes casthrough #212,u,g,n,s,n,PM_L3_GRP_GUESS_WRONG_HIGH,Initial scope=group but data from local node. Predition too high ##0000B3908A Initial scope=group but data from local node. Predition too high #213,u,g,n,s,n,PM_L3_GRP_GUESS_WRONG_LOW,Initial scope=group but data from outside group (far or rem). Prediction too Low ##0000B39088 Initial scope=group but data from outside group (far or rem). Prediction too Low #214,u,g,n,s,n,PM_L3_L2_CO_HIT,L2 castout hits ##0000138088 L2 castout hits #215,u,g,n,s,n,PM_L3_L2_CO_MISS,L2 castout miss ##000013808A L2 castout miss #216,v,g,n,s,n,PM_L3_P0_CO_MEM,l3 CO to memory port 0 ##0000538088 l3 CO to memory port 0 #217,u,g,n,s,n,PM_L3_P0_SN_HIT,L3 snoop hit port 0 ##0000939088 L3 snoop hit port 0 #218,u,g,n,s,n,PM_L3_P0_SYS_PUMP,L3 pf sent with sys scope port 0 ##0000A39088 L3 pf sent with sys scope port 0 #219,v,g,n,s,n,PM_L3_P1_CO_MEM,l3 CO to memory port 1 ##000053808A l3 CO to memory port 1 #220,u,g,n,s,n,PM_L3_P1_SN_HIT,L3 snoop hit port 1 ##000093908A L3 snoop hit port 1 #221,u,g,n,s,n,PM_L3_P1_SYS_PUMP,L3 pf sent with sys scope port 1 ##0000A3908A L3 pf sent with sys scope port 1 #222,u,g,n,s,n,PM_L3_PF_OFF_CHIP_CACHE,L3 Prefetch from Off chip cache ##000003808A L3 Prefetch from Off chip cache #223,u,g,n,s,n,PM_L3_PF_ON_CHIP_CACHE,L3 Prefetch from On chip cache ##0000038088 L3 Prefetch from On chip cache #224,u,g,n,n,n,PM_L3_SN0_ALLOC,lifetime, sample of snooper machine 0 valid ##0000839089 0.0 #225,u,g,n,s,n,PM_L3_SN0_BUSY,lifetime, sample of snooper machine 0 valid ##0000839088 lifetime, sample of snooper machine 0 valid #226,u,g,n,n,n,PM_L3_SW_PREF,Data stream touchto L3 ##000003E052 Data stream touchto L3. #227,u,g,n,n,n,PM_LARX_FIN,Larx finished ##000003C058 Larx finished . #228,v,g,n,n,n,PM_LD_MISS_L1,Load Missed L1 ##000003E054 Load Missed L1. #229,v,g,n,n,n,PM_LD_REF_L1_LSU0, LS0 L1 D cache load references counted at finish, gated by reject ##000000C080 LS0 L1 D cache load references counted at finish, gated by rejectLSU0 L1 D cache load references #230,v,g,n,n,n,PM_LD_REF_L1_LSU1, LS1 L1 D cache load references counted at finish, gated by reject ##000000C082 LS1 L1 D cache load references counted at finish, gated by rejectLSU1 L1 D cache load references #231,v,g,n,n,n,PM_LD_REF_L1_LSU2, LS2 L1 D cache load references counted at finish, gated by reject ##000000C094 LS2 L1 D cache load references counted at finish, gated by reject42 #232,v,g,n,n,n,PM_LD_REF_L1_LSU3, LS3 L1 D cache load references counted at finish, gated by reject ##000000C096 LS3 L1 D cache load references counted at finish, gated by reject42 #233,u,g,n,n,n,PM_LINK_STACK_INVALID_PTR,A flush were LS ptr is invalid, results in a pop , A lot of interrupts between push and pops ##000000509A A flush were LS ptr is invalid, results in a pop , A lot of interrupts between push and pops #234,u,g,n,n,n,PM_LINK_STACK_WRONG_ADD_PRED,Link stack predicts wrong address, because of link stack design limitation. ##0000005098 Link stack predicts wrong address, because of link stack design limitation. #235,u,g,n,n,n,PM_LS0_ERAT_MISS_PREF,LS0 Erat miss due to prefetch ##000000E080 LS0 Erat miss due to prefetch42 #236,v,g,n,n,n,PM_LS0_L1_PREF, LS0 L1 cache data prefetches ##000000D0B8 LS0 L1 cache data prefetches42 #237,v,g,n,n,n,PM_LS0_L1_SW_PREF,Software L1 Prefetches, including SW Transient Prefetches ##000000C098 Software L1 Prefetches, including SW Transient Prefetches42 #238,u,g,n,n,n,PM_LS1_ERAT_MISS_PREF,LS1 Erat miss due to prefetch ##000000E082 LS1 Erat miss due to prefetch42 #239,v,g,n,n,n,PM_LS1_L1_PREF, LS1 L1 cache data prefetches ##000000D0BA LS1 L1 cache data prefetches42 #240,v,g,n,n,n,PM_LS1_L1_SW_PREF,Software L1 Prefetches, including SW Transient Prefetches ##000000C09A Software L1 Prefetches, including SW Transient Prefetches42 #241,u,g,n,n,n,PM_LSU0_FLUSH_LRQ,LS0 Flush: LRQ ##000000C0B0 LS0 Flush: LRQLSU0 LRQ flushes #242,u,g,n,n,n,PM_LSU0_FLUSH_SRQ,LS0 Flush: SRQ ##000000C0B8 LS0 Flush: SRQLSU0 SRQ lhs flushes #243,u,g,n,n,n,PM_LSU0_FLUSH_ULD,LS0 Flush: Unaligned Load ##000000C0A4 LS0 Flush: Unaligned LoadLSU0 unaligned load flushes #244,u,g,n,n,n,PM_LSU0_FLUSH_UST,LS0 Flush: Unaligned Store ##000000C0AC LS0 Flush: Unaligned StoreLSU0 unaligned store flushes #245,u,g,n,n,n,PM_LSU0_L1_CAM_CANCEL,ls0 l1 tm cam cancel ##000000F088 ls0 l1 tm cam cancel42 #246,v,g,n,n,n,PM_LSU0_LMQ_LHR_MERGE,LS0 Load Merged with another cacheline request ##000000D08C LS0 Load Merged with another cacheline request42 #247,u,g,n,n,n,PM_LSU0_NCLD,LS0 Non-cachable Loads counted at finish ##000000C08C LS0 Non-cachable Loads counted at finishLSU0 non-cacheable loads #248,u,g,n,n,n,PM_LSU0_PRIMARY_ERAT_HIT,Primary ERAT hit ##000000E090 Primary ERAT hit42 #249,u,g,n,n,n,PM_LSU0_SRQ_STFWD,LS0 SRQ forwarded data to a load ##000000C09C LS0 SRQ forwarded data to a loadLSU0 SRQ store forwarded #250,v,g,n,n,n,PM_LSU0_STORE_REJECT,ls0 store reject ##000000F084 ls0 store reject42 #251,u,g,n,n,n,PM_LSU0_TMA_REQ_L2, addrs only req to L2 only on the first one,Indication that Load footprint is not expanding ##000000E0A8 addrs only req to L2 only on the first one,Indication that Load footprint is not expanding42 #252,u,g,n,n,n,PM_LSU0_TM_L1_HIT,Load tm hit in L1 ##000000E098 Load tm hit in L142 #253,u,g,n,n,n,PM_LSU0_TM_L1_MISS,Load tm L1 miss ##000000E0A0 Load tm L1 miss42 #254,u,g,n,n,n,PM_LSU1_FLUSH_LRQ,LS1 Flush: LRQ ##000000C0B2 LS1 Flush: LRQLSU1 LRQ flushes #255,u,g,n,n,n,PM_LSU1_FLUSH_SRQ,LS1 Flush: SRQ ##000000C0BA LS1 Flush: SRQLSU1 SRQ lhs flushes #256,u,g,n,n,n,PM_LSU1_FLUSH_ULD,LS 1 Flush: Unaligned Load ##000000C0A6 LS 1 Flush: Unaligned LoadLSU1 unaligned load flushes #257,u,g,n,n,n,PM_LSU1_FLUSH_UST,LS1 Flush: Unaligned Store ##000000C0AE LS1 Flush: Unaligned StoreLSU1 unaligned store flushes #258,u,g,n,n,n,PM_LSU1_L1_CAM_CANCEL,ls1 l1 tm cam cancel ##000000F08A ls1 l1 tm cam cancel42 #259,v,g,n,n,n,PM_LSU1_LMQ_LHR_MERGE,LS1 Load Merge with another cacheline request ##000000D08E LS1 Load Merge with another cacheline request42 #260,u,g,n,n,n,PM_LSU1_NCLD,LS1 Non-cachable Loads counted at finish ##000000C08E LS1 Non-cachable Loads counted at finishLSU1 non-cacheable loads #261,u,g,n,n,n,PM_LSU1_PRIMARY_ERAT_HIT,Primary ERAT hit ##000000E092 Primary ERAT hit42 #262,u,g,n,n,n,PM_LSU1_SRQ_STFWD,LS1 SRQ forwarded data to a load ##000000C09E LS1 SRQ forwarded data to a loadLSU1 SRQ store forwarded #263,v,g,n,n,n,PM_LSU1_STORE_REJECT,ls1 store reject ##000000F086 ls1 store reject42 #264,u,g,n,n,n,PM_LSU1_TMA_REQ_L2, addrs only req to L2 only on the first one,Indication that Load footprint is not expanding ##000000E0AA addrs only req to L2 only on the first one,Indication that Load footprint is not expanding42 #265,u,g,n,n,n,PM_LSU1_TM_L1_HIT,Load tm hit in L1 ##000000E09A Load tm hit in L142 #266,u,g,n,n,n,PM_LSU1_TM_L1_MISS,Load tm L1 miss ##000000E0A2 Load tm L1 miss42 #267,u,g,n,n,n,PM_LSU2_FLUSH_LRQ,LS02Flush: LRQ ##000000C0B4 LS02Flush: LRQ42 #268,u,g,n,n,n,PM_LSU2_FLUSH_SRQ,LS2 Flush: SRQ ##000000C0BC LS2 Flush: SRQ42 #269,u,g,n,n,n,PM_LSU2_FLUSH_ULD,LS3 Flush: Unaligned Load ##000000C0A8 LS3 Flush: Unaligned Load42 #270,u,g,n,n,n,PM_LSU2_L1_CAM_CANCEL,ls2 l1 tm cam cancel ##000000F08C ls2 l1 tm cam cancel42 #271,v,g,n,n,n,PM_LSU2_LARX_FIN,Larx finished in LSU pipe2 ##000003E056 Larx finished in LSU pipe2. #272,u,g,n,n,n,PM_LSU2_LDF,LS2 Scalar Loads ##000000C084 LS2 Scalar Loads42 #273,u,g,n,n,n,PM_LSU2_LDX,LS0 Vector Loads ##000000C088 LS0 Vector Loads42 #274,v,g,n,n,n,PM_LSU2_LMQ_LHR_MERGE,LS0 Load Merged with another cacheline request ##000000D090 LS0 Load Merged with another cacheline request42 #275,u,g,n,n,n,PM_LSU2_PRIMARY_ERAT_HIT,Primary ERAT hit ##000000E094 Primary ERAT hit42 #276,v,g,n,n,n,PM_LSU2_REJECT,LSU2 reject ##000003E05A LSU2 reject . #277,u,g,n,n,n,PM_LSU2_SRQ_STFWD,LS2 SRQ forwarded data to a load ##000000C0A0 LS2 SRQ forwarded data to a load42 #278,u,g,n,n,n,PM_LSU2_TMA_REQ_L2, addrs only req to L2 only on the first one,Indication that Load footprint is not expanding ##000000E0AC addrs only req to L2 only on the first one,Indication that Load footprint is not expanding42 #279,u,g,n,n,n,PM_LSU2_TM_L1_HIT,Load tm hit in L1 ##000000E09C Load tm hit in L142 #280,u,g,n,n,n,PM_LSU2_TM_L1_MISS,Load tm L1 miss ##000000E0A4 Load tm L1 miss42 #281,u,g,n,n,n,PM_LSU3_FLUSH_LRQ,LS3 Flush: LRQ ##000000C0B6 LS3 Flush: LRQ42 #282,u,g,n,n,n,PM_LSU3_FLUSH_SRQ,LS13 Flush: SRQ ##000000C0BE LS13 Flush: SRQ42 #283,u,g,n,n,n,PM_LSU3_FLUSH_ULD,LS 14Flush: Unaligned Load ##000000C0AA LS 14Flush: Unaligned Load42 #284,u,g,n,n,n,PM_LSU3_L1_CAM_CANCEL,ls3 l1 tm cam cancel ##000000F08E ls3 l1 tm cam cancel42 #285,u,g,n,n,n,PM_LSU3_LDF,LS3 Scalar Loads ##000000C086 LS3 Scalar Loads 42 #286,u,g,n,n,n,PM_LSU3_LDX,LS1 Vector Loads ##000000C08A LS1 Vector Loads42 #287,v,g,n,n,n,PM_LSU3_LMQ_LHR_MERGE,LS1 Load Merge with another cacheline request ##000000D092 LS1 Load Merge with another cacheline request42 #288,u,g,n,n,n,PM_LSU3_PRIMARY_ERAT_HIT,Primary ERAT hit ##000000E096 Primary ERAT hit42 #289,u,g,n,n,n,PM_LSU3_SRQ_STFWD,LS3 SRQ forwarded data to a load ##000000C0A2 LS3 SRQ forwarded data to a load42 #290,u,g,n,n,n,PM_LSU3_TMA_REQ_L2, addrs only req to L2 only on the first one,Indication that Load footprint is not expanding ##000000E0AE addrs only req to L2 only on the first one,Indication that Load footprint is not expanding42 #291,u,g,n,n,n,PM_LSU3_TM_L1_HIT,Load tm hit in L1 ##000000E09E Load tm hit in L142 #292,u,g,n,n,n,PM_LSU3_TM_L1_MISS,Load tm L1 miss ##000000E0A6 Load tm L1 miss42 #293,u,g,n,n,n,PM_LSU_ERAT_MISS_PREF,Erat miss due to prefetch, on either pipe ##000000E880 LSU #294,v,g,n,n,n,PM_LSU_FIN,LSU Finished an instruction (up to 2 per cycle) ##0000030066 LSU Finished an instruction (up to 2 per cycle). #295,u,g,n,n,n,PM_LSU_FLUSH_UST,Unaligned Store Flush on either pipe ##000000C8AC LSU #296,u,g,n,n,n,PM_LSU_FOUR_TABLEWALK_CYC,Cycles when four tablewalks pending on this thread ##000000D0A4 Cycles when four tablewalks pending on this thread42 #297,u,g,n,n,n,PM_LSU_L1_PREF,hw initiated , include sw streaming forms as well , include sw streams as a separate event ##000000D8B8 LSU #298,u,g,n,n,n,PM_LSU_L1_SW_PREF,Software L1 Prefetches, including SW Transient Prefetches, on both pipes ##000000C898 LSU #299,u,g,n,n,n,PM_LSU_LDF,FPU loads only on LS2/LS3 ie LU0/LU1 ##000000C884 LSU #300,u,g,n,n,n,PM_LSU_LDX,Vector loads can issue only on LS2/LS3 ##000000C888 LSU #301,v,g,n,n,n,PM_LSU_LMQ_FULL_CYC,LMQ full ##000000D0A2 LMQ fullCycles LMQ full, #302,u,g,n,n,n,PM_LSU_LMQ_S0_ALLOC,Per thread - use edge detect to count allocates On a per thread basis, level signal indicating Slot 0 is valid. By instrumenting a single slot we can calculate service time for that slot. Previous machines required a separate signal indicating the slot was allocated. Because any signal can be routed to any counter in P8, we can count level in one PMC and edge detect in another PMC using the same signal ##000000D0A1 0.0 #303,v,g,n,n,n,PM_LSU_LMQ_S0_VALID,Slot 0 of LMQ valid ##000000D0A0 Slot 0 of LMQ validLMQ slot 0 valid #304,u,g,n,n,n,PM_LSU_LMQ_SRQ_EMPTY_ALL_CYC,ALL threads lsu empty (lmq and srq empty) ##000003001C ALL threads lsu empty (lmq and srq empty). Issue HW016541 #305,u,g,n,n,n,PM_LSU_LRQ_S0_ALLOC,Per thread - use edge detect to count allocates On a per thread basis, level signal indicating Slot 0 is valid. By instrumenting a single slot we can calculate service time for that slot. Previous machines required a separate signal indicating the slot was allocated. Because any signal can be routed to any counter in P8, we can count level in one PMC and edge detect in another PMC using the same signal ##000000D09F 0.0 #306,v,g,n,n,n,PM_LSU_LRQ_S0_VALID,Slot 0 of LRQ valid ##000000D09E Slot 0 of LRQ validLRQ slot 0 valid #307,u,g,n,n,n,PM_LSU_LRQ_S43_ALLOC,LRQ slot 43 was released ##000000F091 0.0 #308,u,g,n,n,n,PM_LSU_LRQ_S43_VALID,LRQ slot 43 was busy ##000000F090 LRQ slot 43 was busy42 #309,v,g,n,n,m,PM_LSU_MRK_DERAT_MISS,DERAT Reloaded (Miss) ##0000030162 DERAT Reloaded (Miss). #310,u,g,n,n,n,PM_LSU_NCLD,count at finish so can return only on ls0 or ls1 ##000000C88C LSU #311,u,g,n,n,n,PM_LSU_NCST,Non-cachable Stores sent to nest ##000000C092 Non-cachable Stores sent to nest42 #312,u,g,n,n,n,PM_LSU_SET_MPRED,Line already in cache at reload time ##000000D082 Line already in cache at reload time42 #313,u,g,n,n,n,PM_LSU_SRQ_S0_ALLOC,Per thread - use edge detect to count allocates On a per thread basis, level signal indicating Slot 0 is valid. By instrumenting a single slot we can calculate service time for that slot. Previous machines required a separate signal indicating the slot was allocated. Because any signal can be routed to any counter in P8, we can count level in one PMC and edge detect in another PMC using the same signal ##000000D09D 0.0 #314,v,g,n,n,n,PM_LSU_SRQ_S0_VALID,Slot 0 of SRQ valid ##000000D09C Slot 0 of SRQ validSRQ slot 0 valid #315,u,g,n,n,n,PM_LSU_SRQ_S39_ALLOC,SRQ slot 39 was released ##000000F093 0.0 #316,u,g,n,n,n,PM_LSU_SRQ_S39_VALID,SRQ slot 39 was busy ##000000F092 SRQ slot 39 was busy42 #317,u,g,n,n,n,PM_LSU_SRQ_SYNC,A sync in the SRQ ended ##000000D09B 0.0 #318,u,g,n,n,n,PM_LSU_SRQ_SYNC_CYC,A sync is in the SRQ (edge detect to count) ##000000D09A A sync is in the SRQ (edge detect to count)SRQ sync duration #319,u,g,n,n,n,PM_LSU_STORE_REJECT,Store reject on either pipe ##000000F084 LSU #320,u,g,n,n,n,PM_LSU_TWO_TABLEWALK_CYC,Cycles when two tablewalks pending on this thread ##000000D0A6 Cycles when two tablewalks pending on this thread42 #321,u,g,n,n,n,PM_LWSYNC,threaded version, IC Misses where we got EA dir hit but no sector valids were on. ICBI took line out ##0000005094 threaded version, IC Misses where we got EA dir hit but no sector valids were on. ICBI took line out #322,u,g,n,n,n,PM_LWSYNC_HELD,LWSYNC held at dispatch ##000000209A LWSYNC held at dispatch #323,u,g,n,s,n,PM_MEM_RWITM,Memory rwitm for this lpar ##000003C05E Memory rwitm for this lpar. #324,v,g,n,n,m,PM_MRK_BACK_BR_CMPL,Marked branch instruction completed with a target address less than current instruction address ##000003515E Marked branch instruction completed with a target address less than current instruction address. #325,v,g,n,n,m,PM_MRK_BR_MPRED_CMPL,Marked Branch Mispredicted ##00000301E4 Marked Branch Mispredicted. #326,v,g,n,n,m,PM_MRK_CRU_FIN,IFU non-branch finished ##000003013A IFU non-branch marked instruction finished. #327,v,g,n,n,m,PM_MRK_DATA_FROM_DL2L3_SHR,The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load ##000003D148 The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load. #328,v,g,n,n,m,PM_MRK_DATA_FROM_DL4,The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a marked load ##000003D14C The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a marked load. #329,v,g,n,n,m,PM_MRK_DATA_FROM_L21_SHR,The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a marked load ##000003D146 The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a marked load. #330,v,g,n,n,m,PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST,The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a marked load ##000003D140 The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a marked load. #331,v,g,n,n,m,PM_MRK_DATA_FROM_L31_ECO_SHR,The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a marked load ##000003D144 The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a marked load. #332,v,g,n,n,m,PM_MRK_DATA_FROM_L3_DISP_CONFLICT,The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a marked load ##000003D142 The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a marked load. #333,v,g,n,n,m,PM_MRK_DATA_FROM_RMEM,The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a marked load ##000003D14A The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a marked load. #334,v,g,n,n,m,PM_MRK_DERAT_MISS,Erat Miss (TLB Access) All page sizes ##00000301E6 Erat Miss (TLB Access) All page sizes. #335,u,g,n,n,m,PM_MRK_DERAT_MISS_16M,Marked Data ERAT Miss (Data TLB Access) page size 16M ##000003D154 Marked Data ERAT Miss (Data TLB Access) page size 16M. #336,u,g,n,n,m,PM_MRK_DPTEG_FROM_DL2L3_SHR,A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request ##000003F148 A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request. #337,u,g,n,n,m,PM_MRK_DPTEG_FROM_DL4,A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a marked data side request ##000003F14C A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a marked data side request. #338,u,g,n,n,m,PM_MRK_DPTEG_FROM_L21_SHR,A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a marked data side request ##000003F146 A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a marked data side request. #339,u,g,n,n,m,PM_MRK_DPTEG_FROM_L2_DISP_CONFLICT_LDHITST,A Page Table Entry was loaded into the TLB from local core's L2 with load hit store conflict due to a marked data side request ##000003F140 A Page Table Entry was loaded into the TLB from local core's L2 with load hit store conflict due to a marked data side request. #340,u,g,n,n,m,PM_MRK_DPTEG_FROM_L31_ECO_SHR,A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a marked data side request ##000003F144 A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a marked data side request. #341,u,g,n,n,m,PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT,A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a marked data side request ##000003F142 A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a marked data side request. #342,u,g,n,n,m,PM_MRK_DPTEG_FROM_RMEM,A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a marked data side request ##000003F14A A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a marked data side request. #343,v,g,n,n,m,PM_MRK_DTLB_MISS_64K,Marked Data TLB Miss page size 64K ##000003D156 Marked Data TLB Miss page size 64K. #344,u,g,n,n,m,PM_MRK_FAB_RSP_CLAIM_RTY,Sampled store did a rwitm and got a rty ##000003015E Sampled store did a rwitm and got a rty. #345,u,g,n,n,m,PM_MRK_FAB_RSP_DCLAIM,Marked store had to do a dclaim ##0000030154 Marked store had to do a dclaim. #346,u,g,n,n,m,PM_MRK_FAB_RSP_MATCH,ttype and cresp matched as specified in MMCR1 ##0000030156 ttype and cresp matched as specified in MMCR1. #347,u,g,n,n,m,PM_MRK_FILT_MATCH,Marked filter Match ##000003012E Marked filter Match. #348,v,g,n,n,m,PM_MRK_GRP_NTC,Marked group ntc cycles. ##000003013C Marked group ntc cycles. #349,v,g,n,n,m,PM_MRK_INST_FIN,marked instruction finished ##0000030130 marked instr finish any unit . #350,u,g,n,n,m,PM_MRK_L2_RC_DONE,Marked RC done ##000003012A Marked RC done. #351,u,g,n,n,m,PM_MRK_LSU_FLUSH,Flush: (marked) : All Cases ##000000D180 Flush: (marked) : All Cases42 #352,u,g,n,n,m,PM_MRK_LSU_FLUSH_LRQ,Flush: (marked) LRQ ##000000D188 Flush: (marked) LRQMarked LRQ flushes #353,u,g,n,n,m,PM_MRK_LSU_FLUSH_SRQ,Flush: (marked) SRQ ##000000D18A Flush: (marked) SRQMarked SRQ lhs flushes #354,u,g,n,n,m,PM_MRK_LSU_FLUSH_ULD,Flush: (marked) Unaligned Load ##000000D184 Flush: (marked) Unaligned LoadMarked unaligned load flushes #355,u,g,n,n,m,PM_MRK_LSU_FLUSH_UST,Flush: (marked) Unaligned Store ##000000D186 Flush: (marked) Unaligned StoreMarked unaligned store flushes #356,v,g,n,n,m,PM_MRK_LSU_REJECT_ERAT_MISS,LSU marked reject due to ERAT (up to 2 per cycle) ##0000030164 LSU marked reject due to ERAT (up to 2 per cycle). #357,u,g,n,n,m,PM_MRK_SRC_PREF_TRACK_INEFF,Prefetch tracked was ineffective for marked src ##000003D15A Prefetch tracked was ineffective for marked src. #358,u,g,n,n,m,PM_MRK_SRC_PREF_TRACK_MOD_L3,Prefetch tracked was moderate (L3 hit) for marked src ##000003D15C Prefetch tracked was moderate (L3 hit) for marked src. #359,v,g,n,n,m,PM_MRK_STALL_CMPLU_CYC,Marked Group completion Stall ##000003013E Marked Group Completion Stall cycles (use edge detect to count #). #360,v,g,n,n,m,PM_MRK_ST_CMPL,marked store completed and sent to nest ##00000301E2 Marked store completed. #361,v,g,n,n,m,PM_MRK_ST_CMPL_INT,marked store finished with intervention ##0000030134 marked store complete (data home) with intervention. #362,v,g,n,n,m,PM_MRK_STCX_FAIL,marked stcx failed ##000003E158 marked stcx failed. #363,u,g,n,n,m,PM_MRK_ST_DRAIN_TO_L2DISP_CYC,cycles to drain st from core to L2 ##000003F150 cycles to drain st from core to L2. #364,u,g,n,n,m,PM_MRK_ST_FWD,Marked st forwards ##000003012C Marked st forwards. #365,u,g,n,n,m,PM_MRK_TGT_PREF_TRACK_INEFF,Prefetch tracked was ineffective for marked target ##000003C15A Prefetch tracked was ineffective for marked target. #366,u,g,n,n,m,PM_MRK_TGT_PREF_TRACK_MOD_L3,Prefetch tracked was moderate (L3 hit) for marked target ##000003C15C Prefetch tracked was moderate (L3 hit) for marked target. #367,v,g,n,n,m,PM_MRK_VSU_FIN,VSU marked instr finish ##0000030132 vsu (fpu) marked instr finish. #368,u,g,n,n,m,PM_MULT_MRK,mult marked instr ##000003D15E mult marked instr. #369,v,g,n,n,n,PM_NESTED_TEND,Completion time nested tend ##00000020B0 Completion time nested tend #370,v,g,n,s,n,PM_NEST_REF_CLK,Multiply by 4 to obtain the number of PB cycles ##000003006E Nest reference clocks. #371,u,g,n,n,n,PM_NON_FAV_TBEGIN,Dispatch time non favored tbegin ##00000020B6 Dispatch time non favored tbegin #372,v,g,n,n,n,PM_OUTER_TBEGIN,Completion time outer tbegin ##00000020AC Completion time outer tbegin #373,v,g,n,n,n,PM_OUTER_TEND,Completion time outer tend ##00000020AE Completion time outer tend #374,u,g,n,n,n,PM_PMC2_OVERFLOW,Overflow from counter 2 ##0000030010 Overflow from counter 2. #375,v,g,n,n,n,PM_PMC2_REWIND,PMC2 Rewind Event (did not match condition) ##0000030020 PMC2 Rewind Event (did not match condition). #376,v,g,n,n,n,PM_PMC4_SAVED,PMC4 Rewind Value saved (matched condition) ##0000030022 PMC4 Rewind Value saved (matched condition). #377,v,g,n,n,n,PM_PMC6_OVERFLOW,Overflow from counter 6 ##0000030024 Overflow from counter 6. #378,u,g,n,n,n,PM_PREF_TRACK_INEFF,Prefetch tracked was ineffective ##000003005A Prefetch tracked was ineffective. #379,u,g,n,n,n,PM_PREF_TRACK_MOD_L3,Prefetch tracked was moderate (L3) ##000003005C Prefetch tracked was moderate (L3). #380,u,g,n,n,n,PM_PTE_PREFETCH,PTE prefetches ##000000E084 PTE prefetches42 #381,u,g,n,n,m,PM_RC_LIFETIME_EXC_1024,Number of times the RC machine for a sampled instruction was active for more than 1024 cycles ##DE200301EA Reload latency exceeded 1024 cyc #382,v,g,n,s,n,PM_RC_USAGE,Continuous 16 cycle(2to1) window where this signals rotates thru sampling each L2 RC machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running ##0000036088 Continuous 16 cycle(2to1) window where this signals rotates thru sampling each L2 RC machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running #383,v,g,n,n,n,PM_RUN_CYC_SMT2_MODE,Cycles run latch is set and core is in SMT2 mode ##000003006C Cycles run latch is set and core is in SMT2 mode. #384,u,g,n,n,n,PM_SEC_ERAT_HIT,secondary ERAT Hit ##000000F082 secondary ERAT Hit42 #385,u,g,n,n,n,PM_SHL_CREATED,Store-Hit-Load Table Entry Created ##000000508C Store-Hit-Load Table Entry Created #386,u,g,n,n,n,PM_SHL_ST_CONVERT,Store-Hit-Load Table Read Hit with entry Enabled ##000000508E Store-Hit-Load Table Read Hit with entry Enabled #387,u,g,n,n,n,PM_SHL_ST_DISABLE,Store-Hit-Load Table Read Hit with entry Disabled (entry was disabled due to the entry shown to not prevent the flush) ##0000005090 Store-Hit-Load Table Read Hit with entry Disabled (entry was disabled due to the entry shown to not prevent the flush) #388,v,g,n,s,n,PM_SNOOP_TLBIE,TLBIE snoop ##000000D0B2 TLBIE snoopSnoop TLBIE #389,u,g,n,s,n,PM_SNP_TM_HIT_M, snp tm st hit m mu ##0000338088 snp tm st hit m mu #390,u,g,n,s,n,PM_SNP_TM_HIT_T,snp tm_st_hit t tn te ##000033808A snp tm_st_hit t tn te #391,v,g,n,n,n,PM_STCX_LSU,STCX executed reported at sent to nest ##000000C090 STCX executed reported at sent to nest42 #392,v,g,n,n,n,PM_ST_MISS_L1,Store Missed L1 ##00000300F0 Store Missed L1. #393,v,g,n,n,n,PM_SUSPENDED,Counter OFF ##0000030000 Counter OFF. #394,u,g,n,s,n,PM_SWAP_CANCEL,SWAP cancel , rtag not available ##0000003090 SWAP cancel , rtag not available #395,u,g,n,s,n,PM_SWAP_CANCEL_GPR,SWAP cancel , rtag not available for gpr ##0000003092 SWAP cancel , rtag not available for gpr #396,v,g,n,s,n,PM_SWAP_COMPLETE,swap cast in completed ##000000308C swap cast in completed #397,v,g,n,s,n,PM_SWAP_COMPLETE_GPR,swap cast in completed fpr gpr ##000000308E swap cast in completed fpr gpr #398,u,g,n,n,n,PM_SYS_PUMP_CPRED,Initial and Final Pump Scope was system pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) ##0000030050 Initial and Final Pump Scope and data sourced across this scope was system pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate). #399,u,g,n,n,n,PM_SYS_PUMP_MPRED,Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) ##0000030052 Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or #400,u,g,n,n,n,PM_TABLEWALK_CYC_PREF,tablewalk qualified for pte prefetches ##000000E086 tablewalk qualified for pte prefetches42 #401,u,g,n,n,n,PM_TABORT_TRECLAIM,Completion time tabortnoncd, tabortcd, treclaim ##00000020B2 Completion time tabortnoncd, tabortcd, treclaim #402,v,g,n,s,n,PM_TB_BIT_TRANS,timebase event ##00000300F8 timebase event. #403,u,g,n,n,n,PM_TEND_PEND_CYC,TEND latency per thread ##000000E0BA TEND latency per thread42 #404,v,g,n,n,n,PM_THRD_CONC_RUN_INST,PPC Instructions Finished when both threads in run_cycles ##00000300F4 Concurrent Run Instructions. #405,u,g,n,n,n,PM_THRD_PRIO_0_1_CYC, Cycles thread running at priority level 0 or 1 ##00000040BC Cycles thread running at priority level 0 or 1 #406,u,g,n,n,n,PM_THRD_PRIO_2_3_CYC, Cycles thread running at priority level 2 or 3 ##00000040BE Cycles thread running at priority level 2 or 3 #407,u,g,n,n,n,PM_THRD_PRIO_4_5_CYC, Cycles thread running at priority level 4 or 5 ##0000005080 Cycles thread running at priority level 4 or 5 #408,u,g,n,n,n,PM_THRD_PRIO_6_7_CYC, Cycles thread running at priority level 6 or 7 ##0000005082 Cycles thread running at priority level 6 or 7 #409,u,g,n,n,n,PM_THRD_REBAL_CYC,cycles rebalance was active ##0000003098 cycles rebalance was active #410,v,g,t,n,m,PM_THRESH_EXC_1024,Threshold counter exceeded a value of 1024 ##00000301EA Threshold counter exceeded a value of 1024. #411,v,g,t,n,m,PM_THRESH_EXC_64,IFU non-branch finished ##00000301E8 Threshold counter exceeded a value of 64. #412,u,g,n,n,n,PM_TLBIE_FIN,tlbie finished ##0000030058 tlbie finished. #413,v,g,n,n,n,PM_TM_BEGIN_ALL,Tm any tbegin ##00000020B8 Tm any tbegin #414,v,g,n,n,n,PM_TM_END_ALL,Tm any tend ##00000020BA Tm any tend #415,u,g,n,n,n,PM_TM_FAIL_CONF_NON_TM,TEXAS fail reason @ completion ##0000003086 TEXAS fail reason @ completion #416,u,g,n,n,n,PM_TM_FAIL_CON_TM,TEXAS fail reason @ completion ##0000003088 TEXAS fail reason @ completion #417,u,g,n,n,n,PM_TM_FAIL_DISALLOW,TM fail disallow ##000000E0B2 TM fail disallow42 #418,u,g,n,n,n,PM_TM_FAIL_FOOTPRINT_OVERFLOW,TEXAS fail reason @ completion ##0000003084 TEXAS fail reason @ completion #419,u,g,n,n,n,PM_TM_FAIL_NON_TX_CONFLICT,Non transactional conflict from LSU whtver gets repoted to texas ##000000E0B8 Non transactional conflict from LSU whtver gets repoted to texas42 #420,u,g,n,n,n,PM_TM_FAIL_SELF,TEXAS fail reason @ completion ##000000308A TEXAS fail reason @ completion #421,u,g,n,n,n,PM_TM_FAIL_TLBIE,TLBIE hit bloom filter ##000000E0B4 TLBIE hit bloom filter42 #422,u,g,n,n,n,PM_TM_FAIL_TX_CONFLICT,Transactional conflict from LSU, whatever gets reported to texas ##000000E0B6 Transactional conflict from LSU, whatever gets reported to texas 42 #423,u,g,n,s,n,PM_TM_ST_CAUSED_FAIL,TM Store (fav or non-fav) caused another thread to fail ##000073708A TM Store (fav or non-fav) caused another thread to fail #424,u,g,n,s,n,PM_TM_ST_CONF,TM Store (fav or non-fav) ran into conflict (failed) ##0000737088 TM Store (fav or non-fav) ran into conflict (failed) #425,v,g,n,n,n,PM_TM_TBEGIN,Tm nested tbegin ##00000020BC Tm nested tbegin #426,u,g,n,n,n,PM_TM_TRANS_RUN_INST,Instructions completed in transactional state ##0000030060 Instructions completed in transactional state. #427,u,g,n,n,n,PM_TM_TRESUME,Tm resume ##0000003080 Tm resume #428,u,g,n,n,n,PM_TM_TSUSPEND,Tm suspend ##00000020BE Tm suspend #429,u,g,n,n,n,PM_UP_PREF_L3,Micropartition prefetch ##000000E08C Micropartition prefetch42 #430,u,g,n,n,n,PM_UP_PREF_POINTER,Micrpartition pointer prefetches ##000000E08E Micrpartition pointer prefetches42 #431,u,g,n,n,n,PM_VSU0_16FLOP,Sixteen flops operation (SP vector versions of fdiv,fsqrt) ##000000A0A4 Sixteen flops operation (SP vector versions of fdiv,fsqrt) #432,v,g,n,n,n,PM_VSU0_1FLOP,one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished ##000000A080 one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finishedDecode into 1,2,4 FLOP according to instr IOP, multiplied by #vector elements according to route( eg x1, x2, x4) Only if instr sends finish to ISU #433,u,g,n,n,n,PM_VSU0_2FLOP,two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) ##000000A098 two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) #434,u,g,n,n,n,PM_VSU0_4FLOP,four flops operation (scalar fdiv, fsqrt, DP vector version of fmadd, fnmadd, fmsub, fnmsub, SP vector versions of single flop instructions) ##000000A09C four flops operation (scalar fdiv, fsqrt, DP vector version of fmadd, fnmadd, fmsub, fnmsub, SP vector versions of single flop instructions) #435,u,g,n,n,n,PM_VSU0_8FLOP,eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) ##000000A0A0 eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) #436,u,g,n,n,n,PM_VSU0_COMPLEX_ISSUED,Complex VMX instruction issued ##000000B0A4 Complex VMX instruction issued #437,u,g,n,n,n,PM_VSU0_CY_ISSUED,Cryptographic instruction RFC02196 Issued ##000000B0B4 Cryptographic instruction RFC02196 Issued #438,u,g,n,n,n,PM_VSU0_DD_ISSUED,64BIT Decimal Issued ##000000B0A8 64BIT Decimal Issued #439,u,g,n,n,n,PM_VSU0_DP_2FLOP,DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg ##000000A08C DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg #440,u,g,n,n,n,PM_VSU0_DP_FMA,DP vector version of fmadd,fnmadd,fmsub,fnmsub ##000000A090 DP vector version of fmadd,fnmadd,fmsub,fnmsub #441,u,g,n,n,n,PM_VSU0_DP_FSQRT_FDIV,DP vector versions of fdiv,fsqrt ##000000A094 DP vector versions of fdiv,fsqrt #442,u,g,n,n,n,PM_VSU0_DQ_ISSUED,128BIT Decimal Issued ##000000B0AC 128BIT Decimal Issued #443,u,g,n,n,n,PM_VSU0_EX_ISSUED,Direct move 32/64b VRFtoGPR RFC02206 Issued ##000000B0B0 Direct move 32/64b VRFtoGPR RFC02206 Issued #444,u,g,n,n,n,PM_VSU0_FIN,VSU0 Finished an instruction ##000000A0BC VSU0 Finished an instruction #445,u,g,n,n,n,PM_VSU0_FMA,two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only! ##000000A084 two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only! #446,u,g,n,n,n,PM_VSU0_FPSCR,Move to/from FPSCR type instruction issued on Pipe 0 ##000000B098 Move to/from FPSCR type instruction issued on Pipe 0 #447,u,g,n,n,n,PM_VSU0_FSQRT_FDIV,four flops operation (fdiv,fsqrt) Scalar Instructions only! ##000000A088 four flops operation (fdiv,fsqrt) Scalar Instructions only! #448,u,g,n,n,n,PM_VSU0_PERMUTE_ISSUED,Permute VMX Instruction Issued ##000000B090 Permute VMX Instruction Issued #449,u,g,n,n,n,PM_VSU0_SCALAR_DP_ISSUED,Double Precision scalar instruction issued on Pipe0 ##000000B088 Double Precision scalar instruction issued on Pipe0 #450,u,g,n,n,n,PM_VSU0_SIMPLE_ISSUED,Simple VMX instruction issued ##000000B094 Simple VMX instruction issued #451,u,g,n,n,n,PM_VSU0_SINGLE,FPU single precision ##000000A0A8 FPU single precision #452,u,g,n,n,n,PM_VSU0_SQ,Store Vector Issued ##000000B09C Store Vector Issued #453,u,g,n,n,n,PM_VSU0_STF,FPU store (SP or DP) issued on Pipe0 ##000000B08C FPU store (SP or DP) issued on Pipe0 #454,u,g,n,n,n,PM_VSU0_VECTOR_DP_ISSUED,Double Precision vector instruction issued on Pipe0 ##000000B080 Double Precision vector instruction issued on Pipe0 #455,u,g,n,n,n,PM_VSU0_VECTOR_SP_ISSUED,Single Precision vector instruction issued (executed) ##000000B084 Single Precision vector instruction issued (executed) #456,u,g,n,n,n,PM_VSU1_16FLOP,Sixteen flops operation (SP vector versions of fdiv,fsqrt) ##000000A0A6 Sixteen flops operation (SP vector versions of fdiv,fsqrt) #457,v,g,n,n,n,PM_VSU1_1FLOP,one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished ##000000A082 one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished #458,u,g,n,n,n,PM_VSU1_2FLOP,two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) ##000000A09A two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) #459,u,g,n,n,n,PM_VSU1_4FLOP,four flops operation (scalar fdiv, fsqrt, DP vector version of fmadd, fnmadd, fmsub, fnmsub, SP vector versions of single flop instructions) ##000000A09E four flops operation (scalar fdiv, fsqrt, DP vector version of fmadd, fnmadd, fmsub, fnmsub, SP vector versions of single flop instructions) #460,u,g,n,n,n,PM_VSU1_8FLOP,eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) ##000000A0A2 eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) #461,u,g,n,n,n,PM_VSU1_COMPLEX_ISSUED,Complex VMX instruction issued ##000000B0A6 Complex VMX instruction issued #462,u,g,n,n,n,PM_VSU1_CY_ISSUED,Cryptographic instruction RFC02196 Issued ##000000B0B6 Cryptographic instruction RFC02196 Issued #463,u,g,n,n,n,PM_VSU1_DD_ISSUED,64BIT Decimal Issued ##000000B0AA 64BIT Decimal Issued #464,u,g,n,n,n,PM_VSU1_DP_2FLOP,DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg ##000000A08E DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg #465,u,g,n,n,n,PM_VSU1_DP_FMA,DP vector version of fmadd,fnmadd,fmsub,fnmsub ##000000A092 DP vector version of fmadd,fnmadd,fmsub,fnmsub #466,u,g,n,n,n,PM_VSU1_DP_FSQRT_FDIV,DP vector versions of fdiv,fsqrt ##000000A096 DP vector versions of fdiv,fsqrt #467,u,g,n,n,n,PM_VSU1_DQ_ISSUED,128BIT Decimal Issued ##000000B0AE 128BIT Decimal Issued #468,u,g,n,n,n,PM_VSU1_EX_ISSUED,Direct move 32/64b VRFtoGPR RFC02206 Issued ##000000B0B2 Direct move 32/64b VRFtoGPR RFC02206 Issued #469,u,g,n,n,n,PM_VSU1_FIN,VSU1 Finished an instruction ##000000A0BE VSU1 Finished an instruction #470,u,g,n,n,n,PM_VSU1_FMA,two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only! ##000000A086 two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only! #471,u,g,n,n,n,PM_VSU1_FPSCR,Move to/from FPSCR type instruction issued on Pipe 0 ##000000B09A Move to/from FPSCR type instruction issued on Pipe 0 #472,u,g,n,n,n,PM_VSU1_FSQRT_FDIV,four flops operation (fdiv,fsqrt) Scalar Instructions only! ##000000A08A four flops operation (fdiv,fsqrt) Scalar Instructions only! #473,u,g,n,n,n,PM_VSU1_PERMUTE_ISSUED,Permute VMX Instruction Issued ##000000B092 Permute VMX Instruction Issued #474,u,g,n,n,n,PM_VSU1_SCALAR_DP_ISSUED,Double Precision scalar instruction issued on Pipe1 ##000000B08A Double Precision scalar instruction issued on Pipe1 #475,u,g,n,n,n,PM_VSU1_SIMPLE_ISSUED,Simple VMX instruction issued ##000000B096 Simple VMX instruction issued #476,u,g,n,n,n,PM_VSU1_SINGLE,FPU single precision ##000000A0AA FPU single precision #477,u,g,n,n,n,PM_VSU1_SQ,Store Vector Issued ##000000B09E Store Vector Issued #478,u,g,n,n,n,PM_VSU1_STF,FPU store (SP or DP) issued on Pipe1 ##000000B08E FPU store (SP or DP) issued on Pipe1 #479,u,g,n,n,n,PM_VSU1_VECTOR_DP_ISSUED,Double Precision vector instruction issued on Pipe1 ##000000B082 Double Precision vector instruction issued on Pipe1 #480,u,g,n,n,n,PM_VSU1_VECTOR_SP_ISSUED,Single Precision vector instruction issued (executed) ##000000B086 Single Precision vector instruction issued (executed) #481,v,g,n,n,n,PM_VSU_1FLOP,one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished ##000000A880 one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished #482,v,g,n,n,n,PM_VSU_2FLOP,two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) ##000000A898 two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) #483,v,g,n,n,n,PM_VSU_4FLOP,four flops operation (scalar fdiv, fsqrt, DP vector version of fmadd, fnmadd, fmsub, fnmsub, SP vector versions of single flop instructions) ##000000A89C four flops operation (scalar fdiv, fsqrt, DP vector version of fmadd, fnmadd, fmsub, fnmsub, SP vector versions of single flop instructions) #484,v,g,n,n,n,PM_VSU_8FLOP,eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) ##000000A8A0 eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) #485,v,g,n,n,n,PM_VSU_FMA,two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only! ##000000A884 two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only! #486,v,g,n,n,n,PM_VSU_FSQRT_FDIV,four flops operation (fdiv,fsqrt) Scalar Instructions only! four flops operation (fdiv,fsqrt) Scalar Instructions only! ##000000A888 $$$$$$$$ { counter 4 } #0,v,g,n,n,n,PM_1PLUS_PPC_DISP,Cycles at least one Instr Dispatched ##00000400F2 Cycles at least one Instr Dispatched. Could be a group with only microcode. Issue HW016521 #1,u,g,n,s,n,PM_4LPAR_CYC,Number of cycles in 4 LPAR mode. Threads 0-1 belong to lpar0, threads 2-3 belong to lpar1, threads 4-5 belong to lpar2, and threads 6-7 belong to lpar3 ##000004E05E Number of cycles in 4 LPAR mode. #2,u,g,n,n,n,PM_ALL_PUMP_MPRED,Pump misprediction. Counts across all types of pumps for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate) ##0000640052 Pump Mis prediction Counts across all types of pumpsfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) #3,u,g,n,n,n,PM_ALL_SYS_PUMP_MPRED_RTY,Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate) ##0000640050 Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) #4,u,g,n,n,n,PM_BANK_CONFLICT,Read blocked due to interleave conflict. The ifar logic will detect an interleave conflict and kill the data that was read that cycle. ##0000004082 Read blocked due to interleave conflict. The ifar logic will detect an interleave conflict and kill the data that was read that cycle. #5,v,g,n,n,n,PM_BR_2PATH,two path branch ##0000040036 two path branch. #6,v,g,n,n,n,PM_BR_BC_8,Pairable BC+8 branch that has not been converted to a Resolve Finished in the BRU pipeline ##0000005086 Pairable BC+8 branch that has not been converted to a Resolve Finished in the BRU pipeline #7,v,g,n,n,n,PM_BR_BC_8_CONV,Pairable BC+8 branch that was converted to a Resolve Finished in the BRU pipeline. ##0000005084 Pairable BC+8 branch that was converted to a Resolve Finished in the BRU pipeline. #8,v,g,n,n,n,PM_BR_CMPL,Branch Instruction completed ##0000040060 Branch Instruction completed. #9,v,g,n,n,n,PM_BR_MPRED_CCACHE,Conditional Branch Completed that was Mispredicted due to the Count Cache Target Prediction ##00000040AC Conditional Branch Completed that was Mispredicted due to the Count Cache Target Prediction #10,v,g,n,n,n,PM_BR_MPRED_CMPL,Number of Branch Mispredicts ##00000400F6 Number of Branch Mispredicts. #11,v,g,n,n,n,PM_BR_MPRED_CR,Conditional Branch Completed that was Mispredicted due to the BHT Direction Prediction (taken/not taken). ##00000040B8 Conditional Branch Completed that was Mispredicted due to the BHT Direction Prediction (taken/not taken). #12,u,g,n,n,n,PM_BR_MPRED_LSTACK,Conditional Branch Completed that was Mispredicted due to the Link Stack Target Prediction ##00000040AE Conditional Branch Completed that was Mispredicted due to the Link Stack Target Prediction #13,u,g,n,n,n,PM_BR_MPRED_TA,Conditional Branch Completed that was Mispredicted due to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that resolved Taken set this event. ##00000040BA Conditional Branch Completed that was Mispredicted due to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that resolved Taken set this event. #14,v,g,n,n,m,PM_BR_MRK_2PATH,marked two path branch ##0000040138 marked two path branch. #15,v,g,n,n,n,PM_BR_PRED_BR0,Conditional Branch Completed on BR0 (1st branch in group) in which the HW predicted the Direction or Target ##000000409C Conditional Branch Completed on BR0 (1st branch in group) in which the HW predicted the Direction or Target #16,v,g,n,n,n,PM_BR_PRED_BR1,Conditional Branch Completed on BR1 (2nd branch in group) in which the HW predicted the Direction or Target. Note: BR1 can only be used in Single Thread Mode. In all of the SMT modes, only one branch can complete, thus BR1 is unused. ##000000409E Conditional Branch Completed on BR1 (2nd branch in group) in which the HW predicted the Direction or Target. Note: BR1 can only be used in Single Thread Mode. In all of the SMT modes, only one branch can complete, thus BR1 is unused. #17,u,g,n,n,n,PM_BR_PRED_BR_CMPL,Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred(0) OR if_pc_br0_br_pred(1). ##000000489C IFU #18,v,g,n,n,n,PM_BR_PRED_CCACHE_BR0,Conditional Branch Completed on BR0 that used the Count Cache for Target Prediction ##00000040A4 Conditional Branch Completed on BR0 that used the Count Cache for Target Prediction #19,v,g,n,n,n,PM_BR_PRED_CCACHE_BR1,Conditional Branch Completed on BR1 that used the Count Cache for Target Prediction ##00000040A6 Conditional Branch Completed on BR1 that used the Count Cache for Target Prediction #20,u,g,n,n,n,PM_BR_PRED_CCACHE_CMPL,Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred(0) AND if_pc_br0_pred_type. ##00000048A4 IFU #21,v,g,n,n,n,PM_BR_PRED_CR_BR0,Conditional Branch Completed on BR0 that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and branches ##00000040B0 Conditional Branch Completed on BR0 that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and bra #22,v,g,n,n,n,PM_BR_PRED_CR_BR1,Conditional Branch Completed on BR1 that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and branches ##00000040B2 Conditional Branch Completed on BR1 that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and bra #23,u,g,n,n,n,PM_BR_PRED_CR_CMPL,Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred(1)='1'. ##00000048B0 IFU #24,u,g,n,n,n,PM_BR_PRED_LSTACK_BR0,Conditional Branch Completed on BR0 that used the Link Stack for Target Prediction ##00000040A8 Conditional Branch Completed on BR0 that used the Link Stack for Target Prediction #25,u,g,n,n,n,PM_BR_PRED_LSTACK_BR1,Conditional Branch Completed on BR1 that used the Link Stack for Target Prediction ##00000040AA Conditional Branch Completed on BR1 that used the Link Stack for Target Prediction #26,u,g,n,n,n,PM_BR_PRED_LSTACK_CMPL,Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred(0) AND (not if_pc_br0_pred_type). ##00000048A8 IFU #27,u,g,n,n,n,PM_BR_PRED_TA_BR0,Conditional Branch Completed on BR0 that had its target address predicted. Only XL-form branches set this event. ##00000040B4 Conditional Branch Completed on BR0 that had its target address predicted. Only XL-form branches set this event. #28,u,g,n,n,n,PM_BR_PRED_TA_BR1,Conditional Branch Completed on BR1 that had its target address predicted. Only XL-form branches set this event. ##00000040B6 Conditional Branch Completed on BR1 that had its target address predicted. Only XL-form branches set this event. #29,u,g,n,n,n,PM_BR_PRED_TA_CMPL,Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred(0)='1'. ##00000048B4 IFU #30,v,g,n,n,n,PM_BR_UNCOND_BR0,Unconditional Branch Completed on BR0. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was coverted to a Resolve. ##00000040A0 Unconditional Branch Completed on BR0. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was coverted to a Resolve. #31,v,g,n,n,n,PM_BR_UNCOND_BR1,Unconditional Branch Completed on BR1. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was coverted to a Resolve. ##00000040A2 Unconditional Branch Completed on BR1. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was coverted to a Resolve. #32,u,g,n,n,n,PM_BR_UNCOND_CMPL,Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred=00 AND if_pc_br0_completed. ##00000048A0 IFU #33,v,g,n,s,n,PM_CASTOUT_ISSUED,Castouts issued ##0000003094 Castouts issued #34,v,g,n,s,n,PM_CASTOUT_ISSUED_GPR,Castouts issued GPR ##0000003096 Castouts issued GPR #35,u,g,n,n,n,PM_CLB_HELD,CLB Hold: Any Reason ##0000002090 CLB Hold: Any Reason #36,v,g,n,n,n,PM_CMPLU_STALL,Completion stall ##000004000A Completion stall. #37,v,g,n,n,n,PM_CMPLU_STALL_BRU,Completion stall due to a Branch Unit ##000004D018 Completion stall due to a Branch Unit. #38,v,g,n,n,n,PM_CMPLU_STALL_DMISS_L2L3_CONFLICT,Completion stall due to cache miss that resolves in the L2 or L3 with a conflict ##000004C016 Completion stall due to cache miss resolving in core's L2/L3 with a conflict. #39,v,g,n,n,n,PM_CMPLU_STALL_DMISS_L3MISS,Completion stall due to cache miss resolving missed the L3 ##000004C01A Completion stall due to cache miss resolving missed the L3. #40,v,g,n,n,n,PM_CMPLU_STALL_DMISS_LMEM,Completion stall due to cache miss that resolves in local memory ##000004C018 Completion stall due to cache miss resolving in core's Local Memory. #41,v,g,n,n,n,PM_CMPLU_STALL_ERAT_MISS,Completion stall due to LSU reject ERAT miss ##000004C012 Completion stall due to LSU reject ERAT miss. #42,v,g,n,n,n,PM_CMPLU_STALL_FXLONG,Completion stall due to a long latency fixed point instruction ##000004D016 Completion stall due to a long latency fixed point instruction. #43,v,g,n,n,n,PM_CMPLU_STALL_LOAD_FINISH,Completion stall due to a Load finish ##000004D014 Completion stall due to a Load finish. #44,v,g,n,n,n,PM_CMPLU_STALL_REJECT,Completion stall due to LSU reject ##000004C010 Completion stall due to LSU reject. #45,v,g,n,n,n,PM_CMPLU_STALL_REJ_LMQ_FULL,Completion stall due to LSU reject LMQ full ##000004C014 Completion stall due to LSU reject LMQ full. #46,v,g,n,n,n,PM_CMPLU_STALL_SCALAR,Completion stall due to VSU scalar instruction ##000004D010 Completion stall due to VSU scalar instruction. #47,v,g,n,n,n,PM_CMPLU_STALL_ST_FWD,Completion stall due to store forward ##000004C01C Completion stall due to store forward. #48,v,g,n,n,n,PM_CMPLU_STALL_VECTOR_LONG,Completion stall due to VSU vector long instruction ##000004D012 Completion stall due to VSU vector long instruction. #49,v,g,n,n,n,PM_CRU_FIN,IFU Finished a (non-branch) instruction ##0000040066 IFU Finished a (non-branch) instruction. #50,v,g,n,n,n,PM_CYC,Cycles ##000004001E Cycles . #51,u,g,n,n,n,PM_DATA_ALL_FROM_DL2L3_MOD,The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either demand loads or data prefetch ##000064C048 The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 #52,u,g,n,n,n,PM_DATA_ALL_FROM_DMEM,The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to either demand loads or data prefetch ##000064C04C The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 #53,u,g,n,n,n,PM_DATA_ALL_FROM_L21_MOD,The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to either demand loads or data prefetch ##000064C046 The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 #54,u,g,n,n,n,PM_DATA_ALL_FROM_L2_DISP_CONFLICT_OTHER,The processor's data cache was reloaded from local core's L2 with dispatch conflict due to either demand loads or data prefetch ##000064C040 The processor's data cache was reloaded from local core's L2 with dispatch conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 #55,u,g,n,n,n,PM_DATA_ALL_FROM_L3,The processor's data cache was reloaded from local core's L3 due to either demand loads or data prefetch ##000064C042 The processor's data cache was reloaded from local core's L3 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 #56,u,g,n,n,n,PM_DATA_ALL_FROM_L31_ECO_MOD,The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to either demand loads or data prefetch ##000064C044 The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 #57,u,g,n,n,n,PM_DATA_ALL_FROM_L3MISS_MOD,The processor's data cache was reloaded from a localtion other than the local core's L3 due to either demand loads or data prefetch ##000064C04E The processor's data cache was reloaded from a localtion other than the local core's L3 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 #58,u,g,n,n,n,PM_DATA_ALL_FROM_OFF_CHIP_CACHE,The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to either demand loads or data prefetch ##000064C04A The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 #59,u,g,n,n,n,PM_DATA_ALL_PUMP_MPRED,Pump misprediction. Counts across all types of pumps for either demand loads or data prefetch ##000064C052 Pump Mis prediction Counts across all types of pumpsfor a demand load #60,u,g,n,n,n,PM_DATA_ALL_SYS_PUMP_MPRED_RTY,Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for either demand loads or data prefetch ##000064C050 Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for a demand load #61,v,g,n,n,n,PM_DATA_FROM_DL2L3_MOD,The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load ##000004C048 The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. #62,v,g,n,n,n,PM_DATA_FROM_DMEM,The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a demand load ##000004C04C The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. #63,v,g,n,n,n,PM_DATA_FROM_L21_MOD,The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a demand load ##000004C046 The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. #64,v,g,n,n,n,PM_DATA_FROM_L2_DISP_CONFLICT_OTHER,The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a demand load ##000004C040 The processor's data cache was reloaded from local core's L2 with dispatch conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. #65,v,g,n,n,n,PM_DATA_FROM_L3,The processor's data cache was reloaded from local core's L3 due to a demand load ##000004C042 The processor's data cache was reloaded from local core's L3 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. #66,v,g,n,n,n,PM_DATA_FROM_L31_ECO_MOD,The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a demand load ##000004C044 The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. #67,v,g,n,n,n,PM_DATA_FROM_L3MISS_MOD,The processor's data cache was reloaded from a localtion other than the local core's L3 due to a demand load ##000004C04E The processor's data cache was reloaded from a localtion other than the local core's L3 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. #68,v,g,n,n,n,PM_DATA_FROM_MEM,The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a demand load ##00000400FE Data cache reload from memory (including L4). #69,v,g,n,n,n,PM_DATA_FROM_OFF_CHIP_CACHE,The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a demand load ##000004C04A The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. #70,u,g,n,n,n,PM_DATA_PUMP_MPRED,Pump misprediction. Counts across all types of pumps for a demand load ##000004C052 Pump Mis prediction Counts across all types of pumpsfor a demand load. #71,u,g,n,n,n,PM_DATA_SYS_PUMP_MPRED_RTY,Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for a demand load ##000004C050 Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for a demand load. #72,u,g,n,n,n,PM_DC_COLLISIONS,DATA Cache collisions ##000000E0BC DATA Cache collisions42 #73,u,g,n,n,n,PM_DC_PREF_STREAM_FUZZY_CONF,A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up) ##000004E050 A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up). #74,u,g,n,n,n,PM_DERAT_MISS_16G,Data ERAT Miss (Data TLB Access) page size 16G ##000004C054 Data ERAT Miss (Data TLB Access) page size 16G. #75,u,g,n,n,n,PM_DFU,Finish DFU (all finish) ##000000B0BA Finish DFU (all finish) #76,u,g,n,n,n,PM_DFU_DCFFIX,Convert from fixed opcode finish (dcffix,dcffixq) ##000000B0BE Convert from fixed opcode finish (dcffix,dcffixq) #77,u,g,n,n,n,PM_DFU_DENBCD,BCD->DPD opcode finish (denbcd, denbcdq) ##000000B0BC BCD->DPD opcode finish (denbcd, denbcdq) #78,u,g,n,n,n,PM_DFU_MC,Finish DFU multicycle ##000000B0B8 Finish DFU multicycle #79,u,g,n,n,n,PM_DISP_CLB_HELD_BAL,Dispatch/CLB Hold: Balance ##0000002092 Dispatch/CLB Hold: Balance #80,u,g,n,n,n,PM_DISP_CLB_HELD_RES,Dispatch/CLB Hold: Resource ##0000002094 Dispatch/CLB Hold: Resource #81,u,g,n,n,n,PM_DISP_CLB_HELD_SB,Dispatch/CLB Hold: Scoreboard ##00000020A8 Dispatch/CLB Hold: Scoreboard #82,u,g,n,n,n,PM_DISP_CLB_HELD_SYNC,Dispatch/CLB Hold: Sync type instruction ##0000002098 Dispatch/CLB Hold: Sync type instruction #83,v,g,n,n,n,PM_DISP_CLB_HELD_TLBIE,Dispatch Hold: Due to TLBIE ##0000002096 Dispatch Hold: Due to TLBIE #84,v,g,n,n,n,PM_DISP_HELD_SYNC_HOLD,Dispatch held due to SYNC hold ##000004003C Dispatch held due to SYNC hold. #85,u,g,n,n,n,PM_DISP_HOLD_GCT_FULL,Dispatch Hold Due to no space in the GCT ##00000030A6 Dispatch Hold Due to no space in the GCT #86,u,g,n,n,n,PM_DPTEG_FROM_DL2L3_MOD,A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request ##000004E048 A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request. #87,u,g,n,n,n,PM_DPTEG_FROM_DMEM,A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a data side request ##000004E04C A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a data side request. #88,u,g,n,n,n,PM_DPTEG_FROM_L21_MOD,A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a data side request ##000004E046 A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a data side request. #89,u,g,n,n,n,PM_DPTEG_FROM_L2_DISP_CONFLICT_OTHER,A Page Table Entry was loaded into the TLB from local core's L2 with dispatch conflict due to a data side request ##000004E040 A Page Table Entry was loaded into the TLB from local core's L2 with dispatch conflict due to a data side request. #90,u,g,n,n,n,PM_DPTEG_FROM_L3,A Page Table Entry was loaded into the TLB from local core's L3 due to a data side request ##000004E042 A Page Table Entry was loaded into the TLB from local core's L3 due to a data side request. #91,u,g,n,n,n,PM_DPTEG_FROM_L31_ECO_MOD,A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a data side request ##000004E044 A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a data side request. #92,u,g,n,n,n,PM_DPTEG_FROM_L3MISS,A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a data side request ##000004E04E A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a data side request. #93,u,g,n,n,n,PM_DPTEG_FROM_OFF_CHIP_CACHE,A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a data side request ##000004E04A A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a data side request. #94,v,g,n,n,n,PM_DSLB_MISS,Data SLB Miss - Total of all segment sizes ##000000D094 Data SLB Miss - Total of all segment sizesData SLB misses #95,u,g,n,n,n,PM_DTLB_MISS_16M,Data TLB Miss page size 16M ##000004C056 Data TLB Miss page size 16M. #96,u,g,n,n,n,PM_EAT_FORCE_MISPRED,XL-form branch was mispredicted due to the predicted target address missing from EAT. The EAT forces a mispredict in this case since there is no predicated target to validate. This is a rare case that may occur when the EAT is full and a branch is issue ##00000050A8 XL-form branch was mispredicted due to the predicted target address missing from EAT. The EAT forces a mispredict in this case since there is no predicated target to validate. This is a rare case that may occur when the EAT is full and a branch is #97,u,g,n,n,n,PM_EAT_FULL_CYC,Cycles No room in EAT ##0000004084 Cycles No room in EATSet on bank conflict and case where no ibuffers available. #98,u,g,n,n,n,PM_EE_OFF_EXT_INT,Ee off and external interrupt ##0000002080 Ee off and external interrupt #99,u,g,n,n,n,PM_FAV_TBEGIN,Dispatch time Favored tbegin ##00000020B4 Dispatch time Favored tbegin #100,u,g,n,n,n,PM_FLOP_SUM_SCALAR,flops summary scalar instructions ##000000A0AE flops summary scalar instructions #101,u,g,n,n,n,PM_FLOP_SUM_VEC,flops summary vector instructions ##000000A0AC flops summary vector instructions #102,v,g,n,n,n,PM_FLUSH,Flush (any type) ##00000400F8 Flush (any type). #103,u,g,n,n,n,PM_FLUSH_BR_MPRED,Flush caused by branch mispredict ##0000002084 Flush caused by branch mispredict #104,u,g,n,n,n,PM_FLUSH_DISP,Dispatch flush ##0000002082 Dispatch flush #105,u,g,n,n,n,PM_FLUSH_DISP_SB,Dispatch Flush: Scoreboard ##000000208C Dispatch Flush: Scoreboard #106,u,g,n,n,n,PM_FLUSH_DISP_SYNC,Dispatch Flush: Sync ##0000002088 Dispatch Flush: Sync #107,u,g,n,n,n,PM_FLUSH_DISP_TLBIE,Dispatch Flush: TLBIE ##000000208A Dispatch Flush: TLBIE #108,u,g,n,n,n,PM_FLUSH_LSU,Flush initiated by LSU ##000000208E Flush initiated by LSU #109,u,g,n,n,n,PM_FLUSH_PARTIAL,Partial flush ##0000002086 Partial flush #110,u,g,n,n,n,PM_FPU0_FCONV,Convert instruction executed ##000000A0B0 Convert instruction executed #111,u,g,n,n,n,PM_FPU0_FEST,Estimate instruction executed ##000000A0B8 Estimate instruction executed #112,u,g,n,n,n,PM_FPU0_FRSP,Round to single precision instruction executed ##000000A0B4 Round to single precision instruction executed #113,u,g,n,n,n,PM_FPU1_FCONV,Convert instruction executed ##000000A0B2 Convert instruction executed #114,u,g,n,n,n,PM_FPU1_FEST,Estimate instruction executed ##000000A0BA Estimate instruction executed #115,u,g,n,n,n,PM_FPU1_FRSP,Round to single precision instruction executed ##000000A0B6 Round to single precision instruction executed #116,u,g,n,n,n,PM_FREQ_UP,Power Management: Above Threshold A ##000004000C Frequency is being slewed up due to Power Management. #117,u,g,n,n,n,PM_FUSION_TOC_GRP0_1,One pair of instructions fused with TOC in Group0 ##00000050B0 One pair of instructions fused with TOC in Group0 #118,u,g,n,n,n,PM_FUSION_TOC_GRP0_2,Two pairs of instructions fused with TOCin Group0 ##00000050AE Two pairs of instructions fused with TOCin Group0 #119,u,g,n,n,n,PM_FUSION_TOC_GRP0_3,Three pairs of instructions fused with TOC in Group0 ##00000050AC Three pairs of instructions fused with TOC in Group0 #120,u,g,n,n,n,PM_FUSION_TOC_GRP1_1,One pair of instructions fused with TOX in Group1 ##00000050B2 One pair of instructions fused with TOX in Group1 #121,u,g,n,n,n,PM_FUSION_VSX_GRP0_1,One pair of instructions fused with VSX in Group0 ##00000050B8 One pair of instructions fused with VSX in Group0 #122,u,g,n,n,n,PM_FUSION_VSX_GRP0_2,Two pairs of instructions fused with VSX in Group0 ##00000050B6 Two pairs of instructions fused with VSX in Group0 #123,u,g,n,n,n,PM_FUSION_VSX_GRP0_3,Three pairs of instructions fused with VSX in Group0 ##00000050B4 Three pairs of instructions fused with VSX in Group0 #124,u,g,n,n,n,PM_FUSION_VSX_GRP1_1,One pair of instructions fused with VSX in Group1 ##00000050BA One pair of instructions fused with VSX in Group1 #125,v,g,n,n,n,PM_FXU1_BUSY_FXU0_IDLE,fxu0 idle and fxu1 busy. ##000004000E fxu0 idle and fxu1 busy. . #126,v,g,n,n,n,PM_FXU1_FIN,FXU1 Finished ##0000040004 FXU1 Finished. #127,v,g,n,n,n,PM_GCT_MERGE,Group dispatched on a merged GCT empty. GCT entries can be merged only within the same thread ##00000030A4 Group dispatched on a merged GCT empty. GCT entries can be merged only within the same thread #128,v,g,n,n,n,PM_GCT_NOSLOT_BR_MPRED,Gct empty for this thread due to branch mispred ##000004D01E Gct empty for this thread due to branch mispred. #129,v,g,n,n,n,PM_GCT_NOSLOT_BR_MPRED_ICMISS,Gct empty for this thread due to Icache Miss and branch mispred ##000004D01A Gct empty for this thread due to Icache Miss and branch mispred. #130,v,g,n,n,n,PM_GCT_NOSLOT_DISP_HELD_MAP,Gct empty for this thread due to dispatch hold on this thread due to Mapper full ##000004D01C Gct empty for this thread due to dispatch hold on this thread due to Mapper full. #131,v,g,n,n,n,PM_GCT_NOSLOT_IC_L3MISS,Gct empty for this thread due to icach l3 miss ##000004E010 Gct empty for this thread due to icach l3 miss. #132,u,g,n,n,n,PM_GCT_UTIL_11_14_ENTRIES,GCT Utilization 11-14 entries ##00000020A2 GCT Utilization 11-14 entries #133,u,g,n,n,n,PM_GCT_UTIL_1_2_ENTRIES,GCT Utilization 1-2 entries ##000000209C GCT Utilization 1-2 entries #134,u,g,n,n,n,PM_GCT_UTIL_15_17_ENTRIES,GCT Utilization 15-17 entries ##00000020A4 GCT Utilization 15-17 entries #135,v,g,n,n,n,PM_GCT_UTIL_18_ENTRIES,GCT Utilization 18+ entries ##00000020A6 GCT Utilization 18+ entries #136,u,g,n,n,n,PM_GCT_UTIL_3_6_ENTRIES,GCT Utilization 3-6 entries ##000000209E GCT Utilization 3-6 entries #137,u,g,n,n,n,PM_GCT_UTIL_7_10_ENTRIES,GCT Utilization 7-10 entries ##00000020A0 GCT Utilization 7-10 entries #138,u,g,n,n,n,PM_GRP_NON_FULL_GROUP,GROUPs where we did not have 6 non branch instructions in the group(ST mode), in SMT mode 3 non branches ##000000509C GROUPs where we did not have 6 non branch instructions in the group(ST mode), in SMT mode 3 non branches #139,u,g,n,n,n,PM_GRP_TERM_2ND_BRANCH,There were enough instructions in the Ibuffer, but 2nd branch ends group ##00000050A4 There were enough instructions in the Ibuffer, but 2nd branch ends group #140,u,g,n,n,n,PM_GRP_TERM_FPU_AFTER_BR,There were enough instructions in the Ibuffer, but FPU OP IN same group after a branch terminates a group, cant do partial flushes ##00000050A6 There were enough instructions in the Ibuffer, but FPU OP IN same group after a branch terminates a group, cant do partial flushes #141,u,g,n,n,n,PM_GRP_TERM_NOINST,Do not fill every slot in the group, Not enough instructions in the Ibuffer. This includes cases where the group started with enough instructions, but some got knocked out by a cache miss or branch redirect (which would also empty the Ibuffer). ##000000509E Do not fill every slot in the group, Not enough instructions in the Ibuffer. This includes cases where the group started with enough instructions, but some got knocked out by a cache miss or branch redirect (which would also empty the Ibuffer). #142,u,g,n,n,n,PM_GRP_TERM_OTHER,There were enough instructions in the Ibuffer, but the group terminated early for some other reason, most likely due to a First or Last. ##00000050A0 There were enough instructions in the Ibuffer, but the group terminated early for some other reason, most likely due to a First or Last. #143,u,g,n,n,n,PM_GRP_TERM_SLOT_LIMIT,There were enough instructions in the Ibuffer, but 3 src RA/RB/RC , 2 way crack caused a group termination ##00000050A2 There were enough instructions in the Ibuffer, but 3 src RA/RB/RC , 2 way crack caused a group termination #144,u,g,n,n,n,PM_IBUF_FULL_CYC,Cycles No room in ibuff ##0000004086 Cycles No room in ibufffully qualified tranfer (if5 valid). #145,u,g,n,n,n,PM_IC_DEMAND_L2_BHT_REDIRECT, L2 I cache demand request due to BHT redirect, branch redirect ( 2 bubbles 3 cycles) ##0000004098 L2 I cache demand request due to BHT redirect, branch redirect ( 2 bubbles 3 cycles) #146,u,g,n,n,n,PM_IC_DEMAND_L2_BR_REDIRECT, L2 I cache demand request due to branch Mispredict ( 15 cycle path) ##000000409A L2 I cache demand request due to branch Mispredict ( 15 cycle path) #147,u,g,n,n,n,PM_IC_DEMAND_REQ,Demand Instruction fetch request ##0000004088 Demand Instruction fetch request #148,u,g,n,n,n,PM_IC_INVALIDATE,Ic line invalidated ##000000508A Ic line invalidated #149,u,g,n,n,n,PM_IC_PREF_CANCEL_HIT,Prefetch Canceled due to icache hit ##0000004092 Prefetch Canceled due to icache hit #150,u,g,n,n,n,PM_IC_PREF_CANCEL_L2,L2 Squashed request ##0000004094 L2 Squashed request #151,u,g,n,n,n,PM_IC_PREF_CANCEL_PAGE,Prefetch Canceled due to page boundary ##0000004090 Prefetch Canceled due to page boundary #152,u,g,n,n,n,PM_IC_PREF_REQ,Instruction prefetch requests ##000000408A Instruction prefetch requests #153,v,g,n,n,n,PM_IC_PREF_WRITE,Instruction prefetch written into IL1 ##000000408E Instruction prefetch written into IL1 #154,u,g,n,n,n,PM_IC_RELOAD_PRIVATE,Reloading line was brought in private for a specific thread. Most lines are brought in shared for all eight thrreads. If RA does not match then invalidates and then brings it shared to other thread. In P7 line brought in private , then line was invalidat ##0000004096 Reloading line was brought in private for a specific thread. Most lines are brought in shared for all eight thrreads. If RA does not match then invalidates and then brings it shared to other thread. In P7 line brought in private , then line was inv #155,u,g,n,n,n,PM_IERAT_RELOAD_16M,IERAT Reloaded (Miss) for a 16M page ##000004006A IERAT Reloaded (Miss) for a 16M page. #156,u,g,n,n,n,PM_IFU_L2_TOUCH,L2 touch to update MRU on a line ##0000005088 L2 touch to update MRU on a line #157,u,g,n,n,n,PM_INST_ALL_FROM_DL2L3_MOD,The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to instruction fetches and prefetches ##0000544048 The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 #158,u,g,n,n,n,PM_INST_ALL_FROM_DMEM,The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Distant) due to instruction fetches and prefetches ##000054404C The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 #159,u,g,n,n,n,PM_INST_ALL_FROM_L21_MOD,The processor's Instruction cache was reloaded with Modified (M) data from another core's L2 on the same chip due to instruction fetches and prefetches ##0000544046 The processor's Instruction cache was reloaded with Modified (M) data from another core's L2 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 #160,u,g,n,n,n,PM_INST_ALL_FROM_L2_DISP_CONFLICT_OTHER,The processor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to instruction fetches and prefetches ##0000544040 The processor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 #161,u,g,n,n,n,PM_INST_ALL_FROM_L3,The processor's Instruction cache was reloaded from local core's L3 due to instruction fetches and prefetches ##0000544042 The processor's Instruction cache was reloaded from local core's L3 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 #162,u,g,n,n,n,PM_INST_ALL_FROM_L31_ECO_MOD,The processor's Instruction cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to instruction fetches and prefetches ##0000544044 The processor's Instruction cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 #163,u,g,n,n,n,PM_INST_ALL_FROM_L3MISS_MOD,The processor's Instruction cache was reloaded from a localtion other than the local core's L3 due to a instruction fetch ##000054404E The processor's Instruction cache was reloaded from a localtion other than the local core's L3 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 #164,u,g,n,n,n,PM_INST_ALL_FROM_OFF_CHIP_CACHE,The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to instruction fetches and prefetches ##000054404A The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 #165,u,g,n,n,n,PM_INST_ALL_PUMP_MPRED,Pump misprediction. Counts across all types of pumps for instruction fetches and prefetches ##0000544052 Pump Mis prediction Counts across all types of pumpsfor an instruction fetch #166,u,g,n,n,n,PM_INST_ALL_SYS_PUMP_MPRED_RTY,Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for instruction fetches and prefetches ##0000544050 Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for an instruction fetch #167,v,g,n,n,n,PM_INST_CMPL,Number of PowerPC Instructions that completed. ##0000040002 PPC Instructions Finished (completed). #168,u,g,n,n,n,PM_INST_FROM_DL2L3_MOD,The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction fetch (not prefetch) ##0000044048 The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . #169,u,g,n,n,n,PM_INST_FROM_DMEM,The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Distant) due to an instruction fetch (not prefetch) ##000004404C The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . #170,u,g,n,n,n,PM_INST_FROM_L1,Instruction fetches from L1 ##0000004080 Instruction fetches from L1 #171,u,g,n,n,n,PM_INST_FROM_L21_MOD,The processor's Instruction cache was reloaded with Modified (M) data from another core's L2 on the same chip due to an instruction fetch (not prefetch) ##0000044046 The processor's Instruction cache was reloaded with Modified (M) data from another core's L2 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . #172,u,g,n,n,n,PM_INST_FROM_L2_DISP_CONFLICT_OTHER,The processor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to an instruction fetch (not prefetch) ##0000044040 The processor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . #173,u,g,n,n,n,PM_INST_FROM_L3,The processor's Instruction cache was reloaded from local core's L3 due to an instruction fetch (not prefetch) ##0000044042 The processor's Instruction cache was reloaded from local core's L3 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . #174,u,g,n,n,n,PM_INST_FROM_L31_ECO_MOD,The processor's Instruction cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to an instruction fetch (not prefetch) ##0000044044 The processor's Instruction cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . #175,u,g,n,n,n,PM_INST_FROM_L3MISS_MOD,The processor's Instruction cache was reloaded from a localtion other than the local core's L3 due to a instruction fetch ##000004404E The processor's Instruction cache was reloaded from a localtion other than the local core's L3 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . #176,u,g,n,n,n,PM_INST_FROM_OFF_CHIP_CACHE,The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to an instruction fetch (not prefetch) ##000004404A The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . #177,u,g,n,n,n,PM_INST_PUMP_MPRED,Pump misprediction. Counts across all types of pumps for an instruction fetch ##0000044052 Pump Mis prediction Counts across all types of pumpsfor an instruction fetch. #178,u,g,n,n,n,PM_INST_SYS_PUMP_MPRED_RTY,Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for an instruction fetch ##0000044050 Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for an instruction fetch. #179,u,g,n,n,n,PM_IPTEG_FROM_DL2L3_MOD,A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request ##0000045048 A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request. #180,u,g,n,n,n,PM_IPTEG_FROM_DMEM,A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a instruction side request ##000004504C A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a instruction side request. #181,u,g,n,n,n,PM_IPTEG_FROM_L21_MOD,A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a instruction side request ##0000045046 A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a instruction side request. #182,u,g,n,n,n,PM_IPTEG_FROM_L2_DISP_CONFLICT_OTHER,A Page Table Entry was loaded into the TLB from local core's L2 with dispatch conflict due to a instruction side request ##0000045040 A Page Table Entry was loaded into the TLB from local core's L2 with dispatch conflict due to a instruction side request. #183,u,g,n,n,n,PM_IPTEG_FROM_L3,A Page Table Entry was loaded into the TLB from local core's L3 due to a instruction side request ##0000045042 A Page Table Entry was loaded into the TLB from local core's L3 due to a instruction side request. #184,u,g,n,n,n,PM_IPTEG_FROM_L31_ECO_MOD,A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a instruction side request ##0000045044 A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a instruction side request. #185,u,g,n,n,n,PM_IPTEG_FROM_L3MISS,A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a instruction side request ##000004504E A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a instruction side request. #186,u,g,n,n,n,PM_IPTEG_FROM_OFF_CHIP_CACHE,A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a instruction side request ##000004504A A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a instruction side request. #187,u,g,n,s,n,PM_ISIDE_L2MEMACC,valid when first beat of data comes in for an i-side fetch where data came from mem(or L4) ##000004608E valid when first beat of data comes in for an i-side fetch where data came from mem(or L4) #188,v,g,n,n,n,PM_ISIDE_MRU_TOUCH,Iside L2 MRU touch ##000044608E Iside L2 MRU touch #189,v,g,n,n,n,PM_ISLB_MISS,I SLB Miss. ##000000D096 I SLB Miss. #190,u,g,n,s,n,PM_ISU_REF_FX0,FX0 ISU reject ##00000030AC FX0 ISU reject #191,u,g,n,s,n,PM_ISU_REF_FX1,FX1 ISU reject ##00000030AE FX1 ISU reject #192,u,g,n,n,n,PM_ISU_REF_FXU,FXU ISU reject from either pipe ##00000038AC ISU #193,u,g,n,s,n,PM_ISU_REF_LS0,LS0 ISU reject ##00000030B0 LS0 ISU reject #194,u,g,n,s,n,PM_ISU_REF_LS1,LS1 ISU reject ##00000030B2 LS1 ISU reject #195,u,g,n,s,n,PM_ISU_REF_LS2,LS2 ISU reject ##00000030B4 LS2 ISU reject #196,u,g,n,s,n,PM_ISU_REF_LS3,LS3 ISU reject ##00000030B6 LS3 ISU reject #197,u,g,n,s,n,PM_ISU_REJECT_RES_NA,ISU reject due to resource not available ##00000030A2 ISU reject due to resource not available #198,v,g,n,s,n,PM_ISU_REJECTS_ALL,All isu rejects could be more than 1 per cycle ##000000309C All isu rejects could be more than 1 per cycle #199,v,g,n,s,n,PM_ISU_REJECT_SAR_BYPASS,Reject because of SAR bypass ##000000309E Reject because of SAR bypass #200,u,g,n,s,n,PM_ISU_REJECT_SRC_NA,ISU reject due to source not available ##00000030A0 ISU reject due to source not available #201,u,g,n,s,n,PM_ISU_REJ_VS0,VS0 ISU reject ##00000030A8 VS0 ISU reject #202,u,g,n,s,n,PM_ISU_REJ_VS1,VS1 ISU reject ##00000030AA VS1 ISU reject #203,u,g,n,n,n,PM_ISU_REJ_VSU,VSU ISU reject from either pipe ##00000038A8 ISU #204,u,g,n,n,n,PM_ISYNC,Isync count per thread ##00000030B8 Isync count per thread #205,v,g,n,n,n,PM_ITLB_MISS,ITLB Reloaded (always zero on POWER6) ##00000400FC ITLB Reloaded. #206,v,g,n,n,n,PM_L1_DEMAND_WRITE,Instruction Demand sectors wriittent into IL1 ##000000408C Instruction Demand sectors wriittent into IL1 #207,v,g,n,n,n,PM_L1_ICACHE_RELOADED_ALL,Counts all Icache reloads includes demand, prefetchm prefetch turned into demand and demand turned into prefetch ##0000040012 Counts all Icache reloads includes demand, prefetchm prefetch turned into demand and demand turned into prefetch. #208,u,g,n,n,m,PM_L1MISS_LAT_EXC_2048,L1 misses that took longer than 2048 cyles to resolve (miss to reload) ##67200401EC Reload latency exceeded 2048 cyc #209,c,g,n,s,n,PM_L2_CHIP_PUMP,RC requests that were local on chip pump attempts ##000064608C RC requests that were local on chip pump attempts #210,v,g,n,n,n,PM_L2_DISP_ALL_L2MISS,All successful Ld/St dispatches for this thread that were an L2miss. ##000044608C All successful Ld/St dispatches for this thread that were an L2miss. #211,c,g,n,s,n,PM_L2_GROUP_PUMP,RC requests that were on Node Pump attempts ##000064608E RC requests that were on Node Pump attempts #212,u,g,n,n,n,PM_L2_RCST_DISP_FAIL_OTHER, L2 RC store dispatch attempt failed due to other reasons ##000054608C L2 RC store dispatch attempt failed due to other reasons #213,u,g,n,s,n,PM_L2_RTY_LD,RC retries on PB for any load from core ##000004708C RC retries on PB for any load from core #214,u,g,n,s,n,PM_L2_SN_M_RD_DONE,SNP dispatched for a read and was M ##000054708C SNP dispatched for a read and was M #215,u,g,n,s,n,PM_L2_SN_M_WR_DONE,SNP dispatched for a write and was M ##000054708E SNP dispatched for a write and was M #216,v,g,n,n,n,PM_L2_ST_DISP,All successful store dispatches ##000044708C All successful store dispatches #217,v,g,n,n,n,PM_L2_ST_HIT,All successful store dispatches that were L2Hits ##000044708E All successful store dispatches that were L2Hits #218,u,g,n,s,n,PM_L3_LAT_CI_HIT,L3 Lateral Castins Hit ##000014808C L3 Lateral Castins Hit #219,u,g,n,s,n,PM_L3_LAT_CI_MISS,L3 Lateral Castins Miss ##000014808E L3 Lateral Castins Miss #220,u,g,n,s,n,PM_L3_P0_CO_L31,l3 CO to L3.1 (lco) port 0 ##000054808C l3 CO to L3.1 (lco) port 0 #221,u,g,n,s,n,PM_L3_P0_LCO_RTY,L3 LCO received retry port 0 ##0000A4908C L3 LCO received retry port 0 #222,u,g,n,s,n,PM_L3_P0_SN_MISS,L3 snoop miss port 0 ##000094908C L3 snoop miss port 0 #223,u,g,n,s,n,PM_L3_P1_CO_L31,l3 CO to L3.1 (lco) port 1 ##000054808E l3 CO to L3.1 (lco) port 1 #224,u,g,n,s,n,PM_L3_P1_LCO_RTY,L3 LCO received retry port 1 ##0000A4908E L3 LCO received retry port 1 #225,u,g,n,s,n,PM_L3_P1_SN_MISS,L3 snoop miss port 1 ##000094908E L3 snoop miss port 1 #226,u,g,n,n,n,PM_L3_PF0_ALLOC,lifetime, sample of PF machine 0 valid ##000084908D 0.0 #227,v,g,n,s,n,PM_L3_PF0_BUSY,lifetime, sample of PF machine 0 valid ##000084908C lifetime, sample of PF machine 0 valid #228,u,g,n,s,n,PM_L3_PF_OFF_CHIP_MEM,L3 Prefetch from Off chip memory ##000004808E L3 Prefetch from Off chip memory #229,v,g,n,s,n,PM_L3_PF_ON_CHIP_MEM,L3 Prefetch from On chip memory ##000004808C L3 Prefetch from On chip memory #230,v,g,n,n,n,PM_L3_PREF_ALL,Total HW L3 prefetches(Load+store) ##000004E052 Total HW L3 prefetches(Load+store). #231,u,g,n,n,n,PM_L3_RD0_ALLOC,lifetime, sample of RD machine 0 valid ##000084908F 0.0 #232,v,g,n,s,n,PM_L3_RD0_BUSY,lifetime, sample of RD machine 0 valid ##000084908E lifetime, sample of RD machine 0 valid #233,u,g,n,s,n,PM_L3_SYS_GUESS_WRONG,Initial scope=system but data from local or near. Predction too high ##0000B4908C Initial scope=system but data from local or near. Predction too high #234,u,g,n,s,n,PM_L3_TRANS_PF,L3 Transient prefetch ##000024808E L3 Transient prefetch #235,v,g,n,n,n,PM_LD_MISS_L1,Load Missed L1 ##00000400F0 Load Missed L1. #236,v,g,n,n,n,PM_LD_REF_L1_LSU0, LS0 L1 D cache load references counted at finish, gated by reject ##000000C080 LS0 L1 D cache load references counted at finish, gated by rejectLSU0 L1 D cache load references #237,v,g,n,n,n,PM_LD_REF_L1_LSU1, LS1 L1 D cache load references counted at finish, gated by reject ##000000C082 LS1 L1 D cache load references counted at finish, gated by rejectLSU1 L1 D cache load references #238,v,g,n,n,n,PM_LD_REF_L1_LSU2, LS2 L1 D cache load references counted at finish, gated by reject ##000000C094 LS2 L1 D cache load references counted at finish, gated by reject42 #239,v,g,n,n,n,PM_LD_REF_L1_LSU3, LS3 L1 D cache load references counted at finish, gated by reject ##000000C096 LS3 L1 D cache load references counted at finish, gated by reject42 #240,u,g,n,n,n,PM_LINK_STACK_INVALID_PTR,A flush were LS ptr is invalid, results in a pop , A lot of interrupts between push and pops ##000000509A A flush were LS ptr is invalid, results in a pop , A lot of interrupts between push and pops #241,u,g,n,n,n,PM_LINK_STACK_WRONG_ADD_PRED,Link stack predicts wrong address, because of link stack design limitation. ##0000005098 Link stack predicts wrong address, because of link stack design limitation. #242,u,g,n,n,n,PM_LS0_ERAT_MISS_PREF,LS0 Erat miss due to prefetch ##000000E080 LS0 Erat miss due to prefetch42 #243,v,g,n,n,n,PM_LS0_L1_PREF, LS0 L1 cache data prefetches ##000000D0B8 LS0 L1 cache data prefetches42 #244,v,g,n,n,n,PM_LS0_L1_SW_PREF,Software L1 Prefetches, including SW Transient Prefetches ##000000C098 Software L1 Prefetches, including SW Transient Prefetches42 #245,u,g,n,n,n,PM_LS1_ERAT_MISS_PREF,LS1 Erat miss due to prefetch ##000000E082 LS1 Erat miss due to prefetch42 #246,v,g,n,n,n,PM_LS1_L1_PREF, LS1 L1 cache data prefetches ##000000D0BA LS1 L1 cache data prefetches42 #247,v,g,n,n,n,PM_LS1_L1_SW_PREF,Software L1 Prefetches, including SW Transient Prefetches ##000000C09A Software L1 Prefetches, including SW Transient Prefetches42 #248,u,g,n,n,n,PM_LSU0_FLUSH_LRQ,LS0 Flush: LRQ ##000000C0B0 LS0 Flush: LRQLSU0 LRQ flushes #249,u,g,n,n,n,PM_LSU0_FLUSH_SRQ,LS0 Flush: SRQ ##000000C0B8 LS0 Flush: SRQLSU0 SRQ lhs flushes #250,u,g,n,n,n,PM_LSU0_FLUSH_ULD,LS0 Flush: Unaligned Load ##000000C0A4 LS0 Flush: Unaligned LoadLSU0 unaligned load flushes #251,u,g,n,n,n,PM_LSU0_FLUSH_UST,LS0 Flush: Unaligned Store ##000000C0AC LS0 Flush: Unaligned StoreLSU0 unaligned store flushes #252,u,g,n,n,n,PM_LSU0_L1_CAM_CANCEL,ls0 l1 tm cam cancel ##000000F088 ls0 l1 tm cam cancel42 #253,v,g,n,n,n,PM_LSU0_LMQ_LHR_MERGE,LS0 Load Merged with another cacheline request ##000000D08C LS0 Load Merged with another cacheline request42 #254,u,g,n,n,n,PM_LSU0_NCLD,LS0 Non-cachable Loads counted at finish ##000000C08C LS0 Non-cachable Loads counted at finishLSU0 non-cacheable loads #255,u,g,n,n,n,PM_LSU0_PRIMARY_ERAT_HIT,Primary ERAT hit ##000000E090 Primary ERAT hit42 #256,u,g,n,n,n,PM_LSU0_SRQ_STFWD,LS0 SRQ forwarded data to a load ##000000C09C LS0 SRQ forwarded data to a loadLSU0 SRQ store forwarded #257,v,g,n,n,n,PM_LSU0_STORE_REJECT,ls0 store reject ##000000F084 ls0 store reject42 #258,u,g,n,n,n,PM_LSU0_TMA_REQ_L2, addrs only req to L2 only on the first one,Indication that Load footprint is not expanding ##000000E0A8 addrs only req to L2 only on the first one,Indication that Load footprint is not expanding42 #259,u,g,n,n,n,PM_LSU0_TM_L1_HIT,Load tm hit in L1 ##000000E098 Load tm hit in L142 #260,u,g,n,n,n,PM_LSU0_TM_L1_MISS,Load tm L1 miss ##000000E0A0 Load tm L1 miss42 #261,u,g,n,n,n,PM_LSU1_FLUSH_LRQ,LS1 Flush: LRQ ##000000C0B2 LS1 Flush: LRQLSU1 LRQ flushes #262,u,g,n,n,n,PM_LSU1_FLUSH_SRQ,LS1 Flush: SRQ ##000000C0BA LS1 Flush: SRQLSU1 SRQ lhs flushes #263,u,g,n,n,n,PM_LSU1_FLUSH_ULD,LS 1 Flush: Unaligned Load ##000000C0A6 LS 1 Flush: Unaligned LoadLSU1 unaligned load flushes #264,u,g,n,n,n,PM_LSU1_FLUSH_UST,LS1 Flush: Unaligned Store ##000000C0AE LS1 Flush: Unaligned StoreLSU1 unaligned store flushes #265,u,g,n,n,n,PM_LSU1_L1_CAM_CANCEL,ls1 l1 tm cam cancel ##000000F08A ls1 l1 tm cam cancel42 #266,v,g,n,n,n,PM_LSU1_LMQ_LHR_MERGE,LS1 Load Merge with another cacheline request ##000000D08E LS1 Load Merge with another cacheline request42 #267,u,g,n,n,n,PM_LSU1_NCLD,LS1 Non-cachable Loads counted at finish ##000000C08E LS1 Non-cachable Loads counted at finishLSU1 non-cacheable loads #268,u,g,n,n,n,PM_LSU1_PRIMARY_ERAT_HIT,Primary ERAT hit ##000000E092 Primary ERAT hit42 #269,u,g,n,n,n,PM_LSU1_SRQ_STFWD,LS1 SRQ forwarded data to a load ##000000C09E LS1 SRQ forwarded data to a loadLSU1 SRQ store forwarded #270,v,g,n,n,n,PM_LSU1_STORE_REJECT,ls1 store reject ##000000F086 ls1 store reject42 #271,u,g,n,n,n,PM_LSU1_TMA_REQ_L2, addrs only req to L2 only on the first one,Indication that Load footprint is not expanding ##000000E0AA addrs only req to L2 only on the first one,Indication that Load footprint is not expanding42 #272,u,g,n,n,n,PM_LSU1_TM_L1_HIT,Load tm hit in L1 ##000000E09A Load tm hit in L142 #273,u,g,n,n,n,PM_LSU1_TM_L1_MISS,Load tm L1 miss ##000000E0A2 Load tm L1 miss42 #274,u,g,n,n,n,PM_LSU2_FLUSH_LRQ,LS02Flush: LRQ ##000000C0B4 LS02Flush: LRQ42 #275,u,g,n,n,n,PM_LSU2_FLUSH_SRQ,LS2 Flush: SRQ ##000000C0BC LS2 Flush: SRQ42 #276,u,g,n,n,n,PM_LSU2_FLUSH_ULD,LS3 Flush: Unaligned Load ##000000C0A8 LS3 Flush: Unaligned Load42 #277,u,g,n,n,n,PM_LSU2_L1_CAM_CANCEL,ls2 l1 tm cam cancel ##000000F08C ls2 l1 tm cam cancel42 #278,u,g,n,n,n,PM_LSU2_LDF,LS2 Scalar Loads ##000000C084 LS2 Scalar Loads42 #279,u,g,n,n,n,PM_LSU2_LDX,LS0 Vector Loads ##000000C088 LS0 Vector Loads42 #280,v,g,n,n,n,PM_LSU2_LMQ_LHR_MERGE,LS0 Load Merged with another cacheline request ##000000D090 LS0 Load Merged with another cacheline request42 #281,u,g,n,n,n,PM_LSU2_PRIMARY_ERAT_HIT,Primary ERAT hit ##000000E094 Primary ERAT hit42 #282,u,g,n,n,n,PM_LSU2_SRQ_STFWD,LS2 SRQ forwarded data to a load ##000000C0A0 LS2 SRQ forwarded data to a load42 #283,u,g,n,n,n,PM_LSU2_TMA_REQ_L2, addrs only req to L2 only on the first one,Indication that Load footprint is not expanding ##000000E0AC addrs only req to L2 only on the first one,Indication that Load footprint is not expanding42 #284,u,g,n,n,n,PM_LSU2_TM_L1_HIT,Load tm hit in L1 ##000000E09C Load tm hit in L142 #285,u,g,n,n,n,PM_LSU2_TM_L1_MISS,Load tm L1 miss ##000000E0A4 Load tm L1 miss42 #286,u,g,n,n,n,PM_LSU3_FLUSH_LRQ,LS3 Flush: LRQ ##000000C0B6 LS3 Flush: LRQ42 #287,u,g,n,n,n,PM_LSU3_FLUSH_SRQ,LS13 Flush: SRQ ##000000C0BE LS13 Flush: SRQ42 #288,u,g,n,n,n,PM_LSU3_FLUSH_ULD,LS 14Flush: Unaligned Load ##000000C0AA LS 14Flush: Unaligned Load42 #289,u,g,n,n,n,PM_LSU3_L1_CAM_CANCEL,ls3 l1 tm cam cancel ##000000F08E ls3 l1 tm cam cancel42 #290,v,g,n,n,n,PM_LSU3_LARX_FIN,Larx finished in LSU pipe3 ##000004E056 Larx finished in LSU pipe3. #291,u,g,n,n,n,PM_LSU3_LDF,LS3 Scalar Loads ##000000C086 LS3 Scalar Loads 42 #292,u,g,n,n,n,PM_LSU3_LDX,LS1 Vector Loads ##000000C08A LS1 Vector Loads42 #293,v,g,n,n,n,PM_LSU3_LMQ_LHR_MERGE,LS1 Load Merge with another cacheline request ##000000D092 LS1 Load Merge with another cacheline request42 #294,u,g,n,n,n,PM_LSU3_PRIMARY_ERAT_HIT,Primary ERAT hit ##000000E096 Primary ERAT hit42 #295,v,g,n,n,n,PM_LSU3_REJECT,LSU3 reject ##000004E05A LSU3 reject . #296,u,g,n,n,n,PM_LSU3_SRQ_STFWD,LS3 SRQ forwarded data to a load ##000000C0A2 LS3 SRQ forwarded data to a load42 #297,u,g,n,n,n,PM_LSU3_TMA_REQ_L2, addrs only req to L2 only on the first one,Indication that Load footprint is not expanding ##000000E0AE addrs only req to L2 only on the first one,Indication that Load footprint is not expanding42 #298,u,g,n,n,n,PM_LSU3_TM_L1_HIT,Load tm hit in L1 ##000000E09E Load tm hit in L142 #299,u,g,n,n,n,PM_LSU3_TM_L1_MISS,Load tm L1 miss ##000000E0A6 Load tm L1 miss42 #300,u,g,n,n,n,PM_LSU_ERAT_MISS_PREF,Erat miss due to prefetch, on either pipe ##000000E880 LSU #301,u,g,n,n,n,PM_LSU_FLUSH_UST,Unaligned Store Flush on either pipe ##000000C8AC LSU #302,u,g,n,n,n,PM_LSU_FOUR_TABLEWALK_CYC,Cycles when four tablewalks pending on this thread ##000000D0A4 Cycles when four tablewalks pending on this thread42 #303,u,g,n,n,n,PM_LSU_L1_PREF,hw initiated , include sw streaming forms as well , include sw streams as a separate event ##000000D8B8 LSU #304,u,g,n,n,n,PM_LSU_L1_SW_PREF,Software L1 Prefetches, including SW Transient Prefetches, on both pipes ##000000C898 LSU #305,u,g,n,n,n,PM_LSU_LDF,FPU loads only on LS2/LS3 ie LU0/LU1 ##000000C884 LSU #306,u,g,n,n,n,PM_LSU_LDX,Vector loads can issue only on LS2/LS3 ##000000C888 LSU #307,v,g,n,n,n,PM_LSU_LMQ_FULL_CYC,LMQ full ##000000D0A2 LMQ fullCycles LMQ full, #308,u,g,n,n,n,PM_LSU_LMQ_S0_ALLOC,Per thread - use edge detect to count allocates On a per thread basis, level signal indicating Slot 0 is valid. By instrumenting a single slot we can calculate service time for that slot. Previous machines required a separate signal indicating the slot was allocated. Because any signal can be routed to any counter in P8, we can count level in one PMC and edge detect in another PMC using the same signal ##000000D0A1 0.0 #309,v,g,n,n,n,PM_LSU_LMQ_S0_VALID,Slot 0 of LMQ valid ##000000D0A0 Slot 0 of LMQ validLMQ slot 0 valid #310,u,g,n,n,n,PM_LSU_LRQ_S0_ALLOC,Per thread - use edge detect to count allocates On a per thread basis, level signal indicating Slot 0 is valid. By instrumenting a single slot we can calculate service time for that slot. Previous machines required a separate signal indicating the slot was allocated. Because any signal can be routed to any counter in P8, we can count level in one PMC and edge detect in another PMC using the same signal ##000000D09F 0.0 #311,v,g,n,n,n,PM_LSU_LRQ_S0_VALID,Slot 0 of LRQ valid ##000000D09E Slot 0 of LRQ validLRQ slot 0 valid #312,u,g,n,n,n,PM_LSU_LRQ_S43_ALLOC,LRQ slot 43 was released ##000000F091 0.0 #313,u,g,n,n,n,PM_LSU_LRQ_S43_VALID,LRQ slot 43 was busy ##000000F090 LRQ slot 43 was busy42 #314,u,g,n,n,n,PM_LSU_NCLD,count at finish so can return only on ls0 or ls1 ##000000C88C LSU #315,u,g,n,n,n,PM_LSU_NCST,Non-cachable Stores sent to nest ##000000C092 Non-cachable Stores sent to nest42 #316,v,g,n,n,n,PM_LSU_REJECT_LHS,LSU Reject due to LHS (up to 4 per cycle) ##000004E05C LSU Reject due to LHS (up to 4 per cycle). #317,u,g,n,n,n,PM_LSU_SET_MPRED,Line already in cache at reload time ##000000D082 Line already in cache at reload time42 #318,v,g,n,s,n,PM_LSU_SRQ_EMPTY_CYC,ALL threads srq empty ##0000040008 All threads srq empty. #319,u,g,n,n,n,PM_LSU_SRQ_S0_ALLOC,Per thread - use edge detect to count allocates On a per thread basis, level signal indicating Slot 0 is valid. By instrumenting a single slot we can calculate service time for that slot. Previous machines required a separate signal indicating the slot was allocated. Because any signal can be routed to any counter in P8, we can count level in one PMC and edge detect in another PMC using the same signal ##000000D09D 0.0 #320,v,g,n,n,n,PM_LSU_SRQ_S0_VALID,Slot 0 of SRQ valid ##000000D09C Slot 0 of SRQ validSRQ slot 0 valid #321,u,g,n,n,n,PM_LSU_SRQ_S39_ALLOC,SRQ slot 39 was released ##000000F093 0.0 #322,u,g,n,n,n,PM_LSU_SRQ_S39_VALID,SRQ slot 39 was busy ##000000F092 SRQ slot 39 was busy42 #323,u,g,n,n,n,PM_LSU_SRQ_SYNC,A sync in the SRQ ended ##000000D09B 0.0 #324,u,g,n,n,n,PM_LSU_SRQ_SYNC_CYC,A sync is in the SRQ (edge detect to count) ##000000D09A A sync is in the SRQ (edge detect to count)SRQ sync duration #325,u,g,n,n,n,PM_LSU_STORE_REJECT,Store reject on either pipe ##000000F084 LSU #326,u,g,n,n,n,PM_LSU_TWO_TABLEWALK_CYC,Cycles when two tablewalks pending on this thread ##000000D0A6 Cycles when two tablewalks pending on this thread42 #327,u,g,n,n,n,PM_LWSYNC,threaded version, IC Misses where we got EA dir hit but no sector valids were on. ICBI took line out ##0000005094 threaded version, IC Misses where we got EA dir hit but no sector valids were on. ICBI took line out #328,u,g,n,n,n,PM_LWSYNC_HELD,LWSYNC held at dispatch ##000000209A LWSYNC held at dispatch #329,u,g,n,s,n,PM_MEM_CO,Memory castouts from this lpar ##000004C058 Memory castouts from this lpar. #330,u,g,n,n,n,PM_MEM_LOC_THRESH_LSU_HIGH,Local memory above threshold for LSU medium ##0000040056 Local memory above threshold for LSU medium. #331,v,g,n,n,m,PM_MRK_DATA_FROM_DL2L3_MOD,The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load ##000004D148 The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load. #332,v,g,n,n,m,PM_MRK_DATA_FROM_DMEM,The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a marked load ##000004D14C The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a marked load. #333,v,g,n,n,m,PM_MRK_DATA_FROM_L21_MOD,The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a marked load ##000004D146 The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a marked load. #334,v,g,n,n,m,PM_MRK_DATA_FROM_L2_CYC,Duration in cycles to reload from local core's L2 due to a marked load ##000004C122 Duration in cycles to reload from local core's L2 due to a marked load. #335,v,g,n,n,m,PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER,The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a marked load ##000004D140 The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a marked load. #336,v,g,n,n,m,PM_MRK_DATA_FROM_L2_MEPF_CYC,Duration in cycles to reload from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load ##000004D120 Duration in cycles to reload from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load. #337,v,g,n,n,m,PM_MRK_DATA_FROM_L2MISS,Data cache reload L2 miss ##00000401E8 Data cache reload L2 miss. #338,v,g,n,n,m,PM_MRK_DATA_FROM_L2MISS_CYC,Duration in cycles to reload from a localtion other than the local core's L2 due to a marked load ##000004C12E Duration in cycles to reload from a localtion other than the local core's L2 due to a marked load. #339,v,g,n,n,m,PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC,Duration in cycles to reload from local core's L2 without conflict due to a marked load ##000004C120 Duration in cycles to reload from local core's L2 without conflict due to a marked load. #340,v,g,n,n,m,PM_MRK_DATA_FROM_L3,The processor's data cache was reloaded from local core's L3 due to a marked load ##000004D142 The processor's data cache was reloaded from local core's L3 due to a marked load. #341,v,g,n,n,m,PM_MRK_DATA_FROM_L31_ECO_MOD,The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a marked load ##000004D144 The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a marked load. #342,v,g,n,n,m,PM_MRK_DATA_FROM_L31_MOD_CYC,Duration in cycles to reload with Modified (M) data from another core's L3 on the same chip due to a marked load ##000004D124 Duration in cycles to reload with Modified (M) data from another core's L3 on the same chip due to a marked load. #343,v,g,n,n,m,PM_MRK_DATA_FROM_L31_SHR_CYC,Duration in cycles to reload with Shared (S) data from another core's L3 on the same chip due to a marked load ##000004C126 Duration in cycles to reload with Shared (S) data from another core's L3 on the same chip due to a marked load. #344,v,g,n,n,m,PM_MRK_DATA_FROM_L3_MEPF_CYC,Duration in cycles to reload from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load ##000004D122 Duration in cycles to reload from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load. #345,v,g,n,n,m,PM_MRK_DATA_FROM_L3MISS,The processor's data cache was reloaded from a localtion other than the local core's L3 due to a marked load ##000004D14E The processor's data cache was reloaded from a localtion other than the local core's L3 due to a marked load. #346,v,g,n,n,m,PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC,Duration in cycles to reload from local core's L3 without conflict due to a marked load ##000004C124 Duration in cycles to reload from local core's L3 without conflict due to a marked load. #347,v,g,n,n,m,PM_MRK_DATA_FROM_LL4_CYC,Duration in cycles to reload from the local chip's L4 cache due to a marked load ##000004C12C Duration in cycles to reload from the local chip's L4 cache due to a marked load. #348,v,g,n,n,m,PM_MRK_DATA_FROM_LMEM_CYC,Duration in cycles to reload from the local chip's Memory due to a marked load ##000004D128 Duration in cycles to reload from the local chip's Memory due to a marked load. #349,v,g,n,n,m,PM_MRK_DATA_FROM_MEMORY_CYC,Duration in cycles to reload from a memory location including L4 from local remote or distant due to a marked load ##000004D12C Duration in cycles to reload from a memory location including L4 from local remote or distant due to a marked load. #350,v,g,n,n,m,PM_MRK_DATA_FROM_OFF_CHIP_CACHE,The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load ##000004D14A The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load. #351,v,g,n,n,m,PM_MRK_DATA_FROM_ON_CHIP_CACHE_CYC,Duration in cycles to reload either shared or modified data from another core's L2/L3 on the same chip due to a marked load ##000004C128 Duration in cycles to reload either shared or modified data from another core's L2/L3 on the same chip due to a marked load. #352,v,g,n,n,m,PM_MRK_DATA_FROM_RL2L3_MOD_CYC,Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load ##000004D126 Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load. #353,v,g,n,n,m,PM_MRK_DATA_FROM_RL2L3_SHR_CYC,Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load ##000004C12A Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load. #354,v,g,n,n,m,PM_MRK_DATA_FROM_RL4_CYC,Duration in cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load ##000004D12A Duration in cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load. #355,v,g,n,s,m,PM_MRK_DCACHE_RELOAD_INTV,Combined Intervention event ##0000040118 Combined Intervention event. #356,u,g,n,n,m,PM_MRK_DERAT_MISS_16G,Marked Data ERAT Miss (Data TLB Access) page size 16G ##000004D154 Marked Data ERAT Miss (Data TLB Access) page size 16G. #357,u,g,n,n,m,PM_MRK_DPTEG_FROM_DL2L3_MOD,A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request ##000004F148 A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request. #358,u,g,n,n,m,PM_MRK_DPTEG_FROM_DMEM,A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a marked data side request ##000004F14C A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a marked data side request. #359,u,g,n,n,m,PM_MRK_DPTEG_FROM_L21_MOD,A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a marked data side request ##000004F146 A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a marked data side request. #360,u,g,n,n,m,PM_MRK_DPTEG_FROM_L2_DISP_CONFLICT_OTHER,A Page Table Entry was loaded into the TLB from local core's L2 with dispatch conflict due to a marked data side request ##000004F140 A Page Table Entry was loaded into the TLB from local core's L2 with dispatch conflict due to a marked data side request. #361,u,g,n,n,m,PM_MRK_DPTEG_FROM_L3,A Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side request ##000004F142 A Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side request. #362,u,g,n,n,m,PM_MRK_DPTEG_FROM_L31_ECO_MOD,A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a marked data side request ##000004F144 A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a marked data side request. #363,u,g,n,n,m,PM_MRK_DPTEG_FROM_L3MISS,A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a marked data side request ##000004F14E A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a marked data side request. #364,u,g,n,n,m,PM_MRK_DPTEG_FROM_OFF_CHIP_CACHE,A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked data side request ##000004F14A A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked data side request. #365,v,g,n,n,m,PM_MRK_DTLB_MISS,Marked dtlb miss ##00000401E4 Marked dtlb miss. #366,u,g,n,n,m,PM_MRK_DTLB_MISS_16M,Marked Data TLB Miss page size 16M ##000004D156 Marked Data TLB Miss page size 16M. #367,u,g,n,n,m,PM_MRK_FAB_RSP_BKILL,Marked store had to do a bkill ##0000040154 Marked store had to do a bkill. #368,u,g,n,n,m,PM_MRK_FAB_RSP_MATCH_CYC,cresp/ttype match cycles ##000004F152 cresp/ttype match cycles. #369,u,g,n,n,m,PM_MRK_FAB_RSP_RD_RTY,Sampled L2 reads retry count ##000004015E Sampled L2 reads retry count. #370,u,g,n,n,m,PM_MRK_FAB_RSP_RWITM_CYC,cycles L2 RC took for a rwitm ##000004F150 cycles L2 RC took for a rwitm. #371,v,g,n,n,m,PM_MRK_GRP_CMPL,marked instruction finished (completed) ##0000040130 marked instruction finished (completed). #372,v,g,n,n,m,PM_MRK_GRP_IC_MISS,Marked Group experienced I cache miss ##000004013A Marked Group experienced I cache miss. #373,v,g,n,n,m,PM_MRK_INST_CMPL,marked instruction completed ##00000401E0 marked instruction completed. #374,v,g,n,n,m,PM_MRK_INST_FROM_L3MISS,Marked instruction was reloaded from a location beyond the local chiplet ##00000401E6 . #375,v,g,n,n,m,PM_MRK_INST_TIMEO,marked Instruction finish timeout (instruction lost) ##0000040134 marked Instruction finish timeout (instruction lost). #376,v,g,n,n,m,PM_MRK_LARX_FIN,Larx finished ##0000040116 Larx finished . #377,v,g,n,n,m,PM_MRK_LD_MISS_L1_CYC,Marked ld latency ##000004013E Marked ld latency. #378,v,g,n,n,m,PM_MRK_LSU_FIN,lsu marked instr finish ##0000040132 lsu marked instr finish. #379,u,g,n,n,m,PM_MRK_LSU_FLUSH,Flush: (marked) : All Cases ##000000D180 Flush: (marked) : All Cases42 #380,u,g,n,n,m,PM_MRK_LSU_FLUSH_LRQ,Flush: (marked) LRQ ##000000D188 Flush: (marked) LRQMarked LRQ flushes #381,u,g,n,n,m,PM_MRK_LSU_FLUSH_SRQ,Flush: (marked) SRQ ##000000D18A Flush: (marked) SRQMarked SRQ lhs flushes #382,u,g,n,n,m,PM_MRK_LSU_FLUSH_ULD,Flush: (marked) Unaligned Load ##000000D184 Flush: (marked) Unaligned LoadMarked unaligned load flushes #383,u,g,n,n,m,PM_MRK_LSU_FLUSH_UST,Flush: (marked) Unaligned Store ##000000D186 Flush: (marked) Unaligned StoreMarked unaligned store flushes #384,v,g,n,n,m,PM_MRK_LSU_REJECT,LSU marked reject (up to 2 per cycle) ##0000040164 LSU marked reject (up to 2 per cycle). #385,u,g,n,n,m,PM_MRK_SRC_PREF_TRACK_MOD,Prefetch tracked was moderate for marked src ##000004D15C Prefetch tracked was moderate for marked src. #386,u,g,n,n,m,PM_MRK_TGT_PREF_TRACK_MOD,Prefetch tracked was moderate for marked target ##000004C15C Prefetch tracked was moderate for marked target. #387,v,g,n,n,n,PM_NESTED_TEND,Completion time nested tend ##00000020B0 Completion time nested tend #388,u,g,n,n,n,PM_NON_FAV_TBEGIN,Dispatch time non favored tbegin ##00000020B6 Dispatch time non favored tbegin #389,v,g,n,n,n,PM_OUTER_TBEGIN,Completion time outer tbegin ##00000020AC Completion time outer tbegin #390,v,g,n,n,n,PM_OUTER_TEND,Completion time outer tend ##00000020AE Completion time outer tend #391,v,g,n,n,n,PM_PMC3_OVERFLOW,Overflow from counter 3 ##0000040010 Overflow from counter 3. #392,u,g,n,n,n,PM_PREF_TRACK_MOD,Prefetch tracked was moderate ##000004005A Prefetch tracked was moderate. #393,u,g,n,n,n,PM_PROBE_NOP_DISP,ProbeNops dispatched ##0000040014 ProbeNops dispatched. #394,u,g,n,n,n,PM_PTE_PREFETCH,PTE prefetches ##000000E084 PTE prefetches42 #395,u,g,n,n,n,PM_PUMP_MPRED,Pump misprediction. Counts across all types of pumps for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) ##0000040052 Pump Mis prediction Counts across all types of pumpsfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate). #396,u,g,n,n,m,PM_RC_LIFETIME_EXC_2048,Number of times the RC machine for a sampled instruction was active for more than 2048 cycles ##DE200401EC Threshold counter exceeded a value of 2048 #397,u,g,n,s,n,PM_RD_CLEARING_SC,rd clearing sc ##000034808E rd clearing sc #398,u,g,n,s,n,PM_RD_FORMING_SC,rd forming sc ##000034808C rd forming sc #399,v,g,n,n,n,PM_RUN_CYC_SMT8_MODE,Cycles run latch is set and core is in SMT8 mode ##000004006C Cycles run latch is set and core is in SMT8 mode. #400,v,g,n,n,n,PM_RUN_INST_CMPL,Run_Instructions ##00000400FA Run_Instructions. #401,u,g,n,n,n,PM_RUN_PURR,Run_PURR ##00000400F4 Run_PURR. #402,u,g,n,n,n,PM_SEC_ERAT_HIT,secondary ERAT Hit ##000000F082 secondary ERAT Hit42 #403,u,g,n,n,n,PM_SHL_CREATED,Store-Hit-Load Table Entry Created ##000000508C Store-Hit-Load Table Entry Created #404,u,g,n,n,n,PM_SHL_ST_CONVERT,Store-Hit-Load Table Read Hit with entry Enabled ##000000508E Store-Hit-Load Table Read Hit with entry Enabled #405,u,g,n,n,n,PM_SHL_ST_DISABLE,Store-Hit-Load Table Read Hit with entry Disabled (entry was disabled due to the entry shown to not prevent the flush) ##0000005090 Store-Hit-Load Table Read Hit with entry Disabled (entry was disabled due to the entry shown to not prevent the flush) #406,v,g,n,s,n,PM_SNOOP_TLBIE,TLBIE snoop ##000000D0B2 TLBIE snoopSnoop TLBIE #407,v,g,n,s,n,PM_SN_USAGE,Continuous 16 cycle(2to1) window where this signals rotates thru sampling each L2 SN machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running ##000004608C Continuous 16 cycle(2to1) window where this signals rotates thru sampling each L2 SN machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running #408,v,g,n,n,n,PM_STCX_LSU,STCX executed reported at sent to nest ##000000C090 STCX executed reported at sent to nest42 #409,v,g,n,n,n,PM_SUSPENDED,Counter OFF ##0000040000 Counter OFF. #410,u,g,n,s,n,PM_SWAP_CANCEL,SWAP cancel , rtag not available ##0000003090 SWAP cancel , rtag not available #411,u,g,n,s,n,PM_SWAP_CANCEL_GPR,SWAP cancel , rtag not available for gpr ##0000003092 SWAP cancel , rtag not available for gpr #412,v,g,n,s,n,PM_SWAP_COMPLETE,swap cast in completed ##000000308C swap cast in completed #413,v,g,n,s,n,PM_SWAP_COMPLETE_GPR,swap cast in completed fpr gpr ##000000308E swap cast in completed fpr gpr #414,u,g,n,n,n,PM_SYS_PUMP_MPRED_RTY,Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) ##0000040050 Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate). #415,u,g,n,n,n,PM_TABLEWALK_CYC_PREF,tablewalk qualified for pte prefetches ##000000E086 tablewalk qualified for pte prefetches42 #416,u,g,n,n,n,PM_TABORT_TRECLAIM,Completion time tabortnoncd, tabortcd, treclaim ##00000020B2 Completion time tabortnoncd, tabortcd, treclaim #417,u,g,n,n,n,PM_TEND_PEND_CYC,TEND latency per thread ##000000E0BA TEND latency per thread42 #418,u,g,n,n,n,PM_THRD_PRIO_0_1_CYC, Cycles thread running at priority level 0 or 1 ##00000040BC Cycles thread running at priority level 0 or 1 #419,u,g,n,n,n,PM_THRD_PRIO_2_3_CYC, Cycles thread running at priority level 2 or 3 ##00000040BE Cycles thread running at priority level 2 or 3 #420,u,g,n,n,n,PM_THRD_PRIO_4_5_CYC, Cycles thread running at priority level 4 or 5 ##0000005080 Cycles thread running at priority level 4 or 5 #421,u,g,n,n,n,PM_THRD_PRIO_6_7_CYC, Cycles thread running at priority level 6 or 7 ##0000005082 Cycles thread running at priority level 6 or 7 #422,u,g,n,n,n,PM_THRD_REBAL_CYC,cycles rebalance was active ##0000003098 cycles rebalance was active #423,v,g,t,n,m,PM_THRESH_EXC_128,Threshold counter exceeded a value of 128 ##00000401EA Threshold counter exceeded a value of 128. #424,v,g,t,n,m,PM_THRESH_EXC_2048,Threshold counter exceeded a value of 2048 ##00000401EC Threshold counter exceeded a value of 2048. #425,v,g,t,n,m,PM_THRESH_NOT_MET,Threshold counter did not meet threshold ##000004016E Threshold counter did not meet threshold. #426,v,g,n,n,n,PM_TM_BEGIN_ALL,Tm any tbegin ##00000020B8 Tm any tbegin #427,u,g,n,s,n,PM_TM_CAP_OVERFLOW,TM Footprint Capactiy Overflow ##000074708C TM Footprint Capactiy Overflow #428,v,g,n,n,n,PM_TM_END_ALL,Tm any tend ##00000020BA Tm any tend #429,u,g,n,n,n,PM_TM_FAIL_CONF_NON_TM,TEXAS fail reason @ completion ##0000003086 TEXAS fail reason @ completion #430,u,g,n,n,n,PM_TM_FAIL_CON_TM,TEXAS fail reason @ completion ##0000003088 TEXAS fail reason @ completion #431,u,g,n,n,n,PM_TM_FAIL_DISALLOW,TM fail disallow ##000000E0B2 TM fail disallow42 #432,u,g,n,n,n,PM_TM_FAIL_FOOTPRINT_OVERFLOW,TEXAS fail reason @ completion ##0000003084 TEXAS fail reason @ completion #433,u,g,n,n,n,PM_TM_FAIL_NON_TX_CONFLICT,Non transactional conflict from LSU whtver gets repoted to texas ##000000E0B8 Non transactional conflict from LSU whtver gets repoted to texas42 #434,u,g,n,n,n,PM_TM_FAIL_SELF,TEXAS fail reason @ completion ##000000308A TEXAS fail reason @ completion #435,u,g,n,n,n,PM_TM_FAIL_TLBIE,TLBIE hit bloom filter ##000000E0B4 TLBIE hit bloom filter42 #436,u,g,n,n,n,PM_TM_FAIL_TX_CONFLICT,Transactional conflict from LSU, whatever gets reported to texas ##000000E0B6 Transactional conflict from LSU, whatever gets reported to texas 42 #437,v,g,n,n,n,PM_TM_TBEGIN,Tm nested tbegin ##00000020BC Tm nested tbegin #438,u,g,n,n,n,PM_TM_TRESUME,Tm resume ##0000003080 Tm resume #439,u,g,n,n,n,PM_TM_TSUSPEND,Tm suspend ##00000020BE Tm suspend #440,u,g,n,n,n,PM_TM_TX_PASS_RUN_INST,run instructions spent in successful transactions. ##000004E014 run instructions spent in successful transactions. #441,u,g,n,n,n,PM_UP_PREF_L3,Micropartition prefetch ##000000E08C Micropartition prefetch42 #442,u,g,n,n,n,PM_UP_PREF_POINTER,Micrpartition pointer prefetches ##000000E08E Micrpartition pointer prefetches42 #443,u,g,n,n,n,PM_VSU0_16FLOP,Sixteen flops operation (SP vector versions of fdiv,fsqrt) ##000000A0A4 Sixteen flops operation (SP vector versions of fdiv,fsqrt) #444,v,g,n,n,n,PM_VSU0_1FLOP,one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished ##000000A080 one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finishedDecode into 1,2,4 FLOP according to instr IOP, multiplied by #vector elements according to route( eg x1, x2, x4) Only if instr sends finish to ISU #445,u,g,n,n,n,PM_VSU0_2FLOP,two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) ##000000A098 two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) #446,u,g,n,n,n,PM_VSU0_4FLOP,four flops operation (scalar fdiv, fsqrt, DP vector version of fmadd, fnmadd, fmsub, fnmsub, SP vector versions of single flop instructions) ##000000A09C four flops operation (scalar fdiv, fsqrt, DP vector version of fmadd, fnmadd, fmsub, fnmsub, SP vector versions of single flop instructions) #447,u,g,n,n,n,PM_VSU0_8FLOP,eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) ##000000A0A0 eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) #448,u,g,n,n,n,PM_VSU0_COMPLEX_ISSUED,Complex VMX instruction issued ##000000B0A4 Complex VMX instruction issued #449,u,g,n,n,n,PM_VSU0_CY_ISSUED,Cryptographic instruction RFC02196 Issued ##000000B0B4 Cryptographic instruction RFC02196 Issued #450,u,g,n,n,n,PM_VSU0_DD_ISSUED,64BIT Decimal Issued ##000000B0A8 64BIT Decimal Issued #451,u,g,n,n,n,PM_VSU0_DP_2FLOP,DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg ##000000A08C DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg #452,u,g,n,n,n,PM_VSU0_DP_FMA,DP vector version of fmadd,fnmadd,fmsub,fnmsub ##000000A090 DP vector version of fmadd,fnmadd,fmsub,fnmsub #453,u,g,n,n,n,PM_VSU0_DP_FSQRT_FDIV,DP vector versions of fdiv,fsqrt ##000000A094 DP vector versions of fdiv,fsqrt #454,u,g,n,n,n,PM_VSU0_DQ_ISSUED,128BIT Decimal Issued ##000000B0AC 128BIT Decimal Issued #455,u,g,n,n,n,PM_VSU0_EX_ISSUED,Direct move 32/64b VRFtoGPR RFC02206 Issued ##000000B0B0 Direct move 32/64b VRFtoGPR RFC02206 Issued #456,u,g,n,n,n,PM_VSU0_FIN,VSU0 Finished an instruction ##000000A0BC VSU0 Finished an instruction #457,u,g,n,n,n,PM_VSU0_FMA,two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only! ##000000A084 two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only! #458,u,g,n,n,n,PM_VSU0_FPSCR,Move to/from FPSCR type instruction issued on Pipe 0 ##000000B098 Move to/from FPSCR type instruction issued on Pipe 0 #459,u,g,n,n,n,PM_VSU0_FSQRT_FDIV,four flops operation (fdiv,fsqrt) Scalar Instructions only! ##000000A088 four flops operation (fdiv,fsqrt) Scalar Instructions only! #460,u,g,n,n,n,PM_VSU0_PERMUTE_ISSUED,Permute VMX Instruction Issued ##000000B090 Permute VMX Instruction Issued #461,u,g,n,n,n,PM_VSU0_SCALAR_DP_ISSUED,Double Precision scalar instruction issued on Pipe0 ##000000B088 Double Precision scalar instruction issued on Pipe0 #462,u,g,n,n,n,PM_VSU0_SIMPLE_ISSUED,Simple VMX instruction issued ##000000B094 Simple VMX instruction issued #463,u,g,n,n,n,PM_VSU0_SINGLE,FPU single precision ##000000A0A8 FPU single precision #464,u,g,n,n,n,PM_VSU0_SQ,Store Vector Issued ##000000B09C Store Vector Issued #465,u,g,n,n,n,PM_VSU0_STF,FPU store (SP or DP) issued on Pipe0 ##000000B08C FPU store (SP or DP) issued on Pipe0 #466,u,g,n,n,n,PM_VSU0_VECTOR_DP_ISSUED,Double Precision vector instruction issued on Pipe0 ##000000B080 Double Precision vector instruction issued on Pipe0 #467,u,g,n,n,n,PM_VSU0_VECTOR_SP_ISSUED,Single Precision vector instruction issued (executed) ##000000B084 Single Precision vector instruction issued (executed) #468,u,g,n,n,n,PM_VSU1_16FLOP,Sixteen flops operation (SP vector versions of fdiv,fsqrt) ##000000A0A6 Sixteen flops operation (SP vector versions of fdiv,fsqrt) #469,v,g,n,n,n,PM_VSU1_1FLOP,one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished ##000000A082 one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished #470,u,g,n,n,n,PM_VSU1_2FLOP,two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) ##000000A09A two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) #471,u,g,n,n,n,PM_VSU1_4FLOP,four flops operation (scalar fdiv, fsqrt, DP vector version of fmadd, fnmadd, fmsub, fnmsub, SP vector versions of single flop instructions) ##000000A09E four flops operation (scalar fdiv, fsqrt, DP vector version of fmadd, fnmadd, fmsub, fnmsub, SP vector versions of single flop instructions) #472,u,g,n,n,n,PM_VSU1_8FLOP,eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) ##000000A0A2 eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) #473,u,g,n,n,n,PM_VSU1_COMPLEX_ISSUED,Complex VMX instruction issued ##000000B0A6 Complex VMX instruction issued #474,u,g,n,n,n,PM_VSU1_CY_ISSUED,Cryptographic instruction RFC02196 Issued ##000000B0B6 Cryptographic instruction RFC02196 Issued #475,u,g,n,n,n,PM_VSU1_DD_ISSUED,64BIT Decimal Issued ##000000B0AA 64BIT Decimal Issued #476,u,g,n,n,n,PM_VSU1_DP_2FLOP,DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg ##000000A08E DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg #477,u,g,n,n,n,PM_VSU1_DP_FMA,DP vector version of fmadd,fnmadd,fmsub,fnmsub ##000000A092 DP vector version of fmadd,fnmadd,fmsub,fnmsub #478,u,g,n,n,n,PM_VSU1_DP_FSQRT_FDIV,DP vector versions of fdiv,fsqrt ##000000A096 DP vector versions of fdiv,fsqrt #479,u,g,n,n,n,PM_VSU1_DQ_ISSUED,128BIT Decimal Issued ##000000B0AE 128BIT Decimal Issued #480,u,g,n,n,n,PM_VSU1_EX_ISSUED,Direct move 32/64b VRFtoGPR RFC02206 Issued ##000000B0B2 Direct move 32/64b VRFtoGPR RFC02206 Issued #481,u,g,n,n,n,PM_VSU1_FIN,VSU1 Finished an instruction ##000000A0BE VSU1 Finished an instruction #482,u,g,n,n,n,PM_VSU1_FMA,two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only! ##000000A086 two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only! #483,u,g,n,n,n,PM_VSU1_FPSCR,Move to/from FPSCR type instruction issued on Pipe 0 ##000000B09A Move to/from FPSCR type instruction issued on Pipe 0 #484,u,g,n,n,n,PM_VSU1_FSQRT_FDIV,four flops operation (fdiv,fsqrt) Scalar Instructions only! ##000000A08A four flops operation (fdiv,fsqrt) Scalar Instructions only! #485,u,g,n,n,n,PM_VSU1_PERMUTE_ISSUED,Permute VMX Instruction Issued ##000000B092 Permute VMX Instruction Issued #486,u,g,n,n,n,PM_VSU1_SCALAR_DP_ISSUED,Double Precision scalar instruction issued on Pipe1 ##000000B08A Double Precision scalar instruction issued on Pipe1 #487,u,g,n,n,n,PM_VSU1_SIMPLE_ISSUED,Simple VMX instruction issued ##000000B096 Simple VMX instruction issued #488,u,g,n,n,n,PM_VSU1_SINGLE,FPU single precision ##000000A0AA FPU single precision #489,u,g,n,n,n,PM_VSU1_SQ,Store Vector Issued ##000000B09E Store Vector Issued #490,u,g,n,n,n,PM_VSU1_STF,FPU store (SP or DP) issued on Pipe1 ##000000B08E FPU store (SP or DP) issued on Pipe1 #491,u,g,n,n,n,PM_VSU1_VECTOR_DP_ISSUED,Double Precision vector instruction issued on Pipe1 ##000000B082 Double Precision vector instruction issued on Pipe1 #492,u,g,n,n,n,PM_VSU1_VECTOR_SP_ISSUED,Single Precision vector instruction issued (executed) ##000000B086 Single Precision vector instruction issued (executed) #493,v,g,n,n,n,PM_VSU_1FLOP,one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished ##000000A880 one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished #494,v,g,n,n,n,PM_VSU_2FLOP,two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) ##000000A898 two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) #495,v,g,n,n,n,PM_VSU_4FLOP,four flops operation (scalar fdiv, fsqrt, DP vector version of fmadd, fnmadd, fmsub, fnmsub, SP vector versions of single flop instructions) ##000000A89C four flops operation (scalar fdiv, fsqrt, DP vector version of fmadd, fnmadd, fmsub, fnmsub, SP vector versions of single flop instructions) #496,v,g,n,n,n,PM_VSU_8FLOP,eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) ##000000A8A0 eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) #497,v,g,n,n,n,PM_VSU_FMA,two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only! ##000000A884 two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only! #498,v,g,n,n,n,PM_VSU_FSQRT_FDIV,four flops operation (fdiv,fsqrt) Scalar Instructions only! ##000000A888 four flops operation (fdiv,fsqrt) Scalar Instructions only! $$$$$$$$ { counter 5 } #0,v,g,n,n,n,PM_RUN_INST_CMPL,Run_Instructions ##0009 Number of run instructions completed. $$$$$$$$ { counter 6 } #0,v,g,n,n,n,PM_RUN_CYC,Run_cycles ##0005 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared i n the OS idle loop. Gating by the run latch filters out the idle loop.