# IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # # bos720 src/bos/usr/sbin/perf/pmapi/events/POWER8.dms 1.3 # # Licensed Materials - Property of IBM # # Restricted Materials of IBM # # COPYRIGHT International Business Machines Corp. 2013,2014 # All Rights Reserved # # US Government Users Restricted Rights - Use, duplication or # disclosure restricted by GSA ADP Schedule Contract with IBM Corp. # # IBM_PROLOG_END_TAG # Global variables CACHE_LINE_SIZE = 128; MEM_LINE_SIZE = 128; # Derived metric descriptions @PMD_CPI;Cycles per instruction @@PM_CYC / PM_INST_CMPL @@@group=General @PMD_IPC;Instructions per cycles @@PM_INST_CMPL / PM_CYC @@@group=General @PMD_SMT_BENEFIT;IPC of all instructions completed by the core while this thread was stalled @@PM_CMPLU_STALL_OTHER_CMPL/PM_RUN_CYC @@@group=General @PMD_RUN_CPI;Run cycles per run instruction @@PM_RUN_CYC / PM_RUN_INST_CMPL @@@group=General @PMD_CYC_GROUP;Cycles per group @@PM_CYC / PM_1PLUS_PPC_CMPL @@@group=General @PMD_INST_GROUP;Instructions per group @@PM_INST_CMPL / PM_1PLUS_PPC_CMPL @@@group=General @PMD_RUN_CYCLES;Run cycles per cycle;% @@PM_RUN_CYC / PM_CYC*100 @@@group=General @PMD_CYC_GRP_DISPATCHED;Percentage Cycles a group dispatched;% @@PM_1PLUS_PPC_DISP / PM_CYC * 100 @@@group=General @PMD_CYC_GRP_COMPLETED;Percentage Cycles a group completed;% @@PM_GRP_CMPL / PM_CYC * 100 @@@group=General @PMD_SPECULATION;Instruction dispatch-to-completion ratio @@PM_INST_DISP / PM_INST_CMPL @@@group=General @PMD_GROUP_SIZE;Avg group size @@PM_INST_CMPL / PM_1PLUS_PPC_CMPL @@@group=General @PMD_L1_LD_MISS_RATIO;Percentage of L1 load misses per L1 load ref;% @@PM_LD_MISS_L1 / PM_LD_REF_L1 @@@group=General @PMD_L1_ST_MISS_RATIO;Percentage of L1 store misses per L1 store ref;% @@PM_ST_MISS_L1 / PM_ST_FIN * 100 @@@group=General @PMD_L1_ST_MISS_RATE;Percentage of L1 store misses per run instruction;% @@PM_ST_MISS_L1 * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_L1_LD_MISS_RATE;L2 dmand Load Miss Rate (per run instruction);% @@PM_DATA_FROM_L2MISS * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_L2_LD_MISS_RATE;Percentage of L1 demand load misses per run instruction;% @@PM_LD_MISS_L1 * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_L3_LD_MISS_RATE;L3 demand Load Miss Rate (per run instruction);% @@PM_DATA_FROM_L3MISS * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_L1_INST_MISS_RATE;Instruction Cache Miss Rate (Per run Instruction);% @@PM_L1_ICACHE_MISS * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_L2_INST_MISS_RATE;L2 Instruction Miss Rate (per instruction);% @@PM_INST_FROM_L2MISS * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_L3_INST_MISS_RATE;L3 Instruction Miss Rate (per instruction);% @@PM_INST_FROM_L3MISS * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_BRANCH_MISPREDICT_RATE;Branch predict rate;% @@PM_BR_MPRED_CMPL / PM_RUN_INST_CMPL * 100 @@@group=General @PMD_DTLB_MISS_RATE;DTLB miss rate per inst;% @@PM_DTLB_MISS / PM_RUN_INST_CMPL *100 @@@group=General @PMD_ITLB_MISS_RATE;ITLB miss rate per inst;% @@PM_ITLB_MISS / PM_RUN_INST_CMPL *100 @@@group=General @PMD_ICACHE_PREF;% of ICache reloads due to prefetch;% @@PM_IC_PREF_WRITE * 100 / PM_L1_ICACHE_MISS @@@group=General @PMD_DERAT_MISS_RATE;DERAT Miss Rate (per run instruction);% @@PM_LSU_DERAT_MISS * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_L2_PTEG_MISS_RATE;L2 PTEG Miss Rate (per run instruction);% @@PM_DPTEG_FROM_L2MISS * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_L3_PTEG_MISS_RATE;L3 PTEG Miss Rate (per run instruction);% @@PM_DPTEG_FROM_L3MISS * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_FLUSH_RATE;Flush rate;% @@PM_FLUSH * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_DISP_FLUSH_RATE;GCT empty cycles;% @@(PM_FLUSH_DISP / PM_RUN_INST_CMPL) * 100 @@@group=General @PMD_BR_MPRED_FLUSH_RATE;Branch Mispredict flushes per instruction;% @@PM_FLUSH_BR_MPRED / PM_RUN_INST_CMPL * 100 @@@group=General @PMD_AVERAGE_SYNC_CYC;average service time for SYNC @@PM_LSU_SRQ_SYNC_CYC / PM_LSU_SRQ_SYNC @@@group=General @PMD_AVG_LMQ_LIFE_TIME;Cycles LMQ slot0 was active on an average @@PM_LSU_LMQ_S0_VALID / PM_LSU_LMQ_S0_ALLOC @@@group=General @PMD_AVG_LRQ_LIFE_TIME_EVEN;Average number of cycles LRQ stays active for one load. Slot 0 is VALID ONLY FOR EVEN THREADS @@PM_LSU_LRQ_S0_VALID / PM_LSU_LRQ_S0_ALLOC @@@group=General @PMD_AVG_LRQ_LIFE_TIME_ODD;Average number of cycles LRQ stays active for one load. Slot 43 is valid ONLY FOR ODD THREADS @@PM_LSU_LRQ_S43_VALID / PM_LSU_LRQ_S43_ALLOC @@@group=General @PMD_AVG_SRQ_LIFE_TIME_EVEN;Average number of cycles SRQ stays active for one load. Slot 0 is VALID ONLY FOR EVEN THREADS @@PM_LSU_SRQ_S0_VALID / PM_LSU_SRQ_S0_ALLOC @@@group=General @PMD_AVG_SRQ_LIFE_TIME_ODD;Average number of cycles SRQ stays active for one load. Slot 39 is valid ONLY FOR ODD THREADS @@PM_LSU_SRQ_S39_VALID / PM_LSU_SRQ_S39_ALLOC @@@group=General @PMD_GCT_UTIL_1TO2_SLOTS;GCT slot utilization (1 to 2) as a % of cycles this thread had atleast 1 slot valid;% @@PM_GCT_UTIL_1_2_ENTRIES / ( PM_RUN_CYC - PM_GCT_NOSLOT_CYC) * 100 @@@group=General @PMD_GCT_UTIL_3TO6_SLOTS;GCT slot utilization (3 to 6) as a % of cycles this thread had atleast 1 slot valid;% @@PM_GCT_UTIL_3_6_ENTRIES / ( PM_RUN_CYC - PM_GCT_NOSLOT_CYC) * 100 @@@group=General @PMD_GCT_UTIL_7TO10_SLOTS;GCT slot utilization (7 to 10) as a % of cycles this thread had atleast 1 slot valid;% @@PM_GCT_UTIL_7_10_ENTRIES / ( PM_RUN_CYC - PM_GCT_NOSLOT_CYC) * 100 @@@group=General @PMD_GCT_UTIL_11TO14_SLOTS;GCT slot utilization (11 to 14) as a % of cycles this thread had atleast 1 slot valid;% @@PM_GCT_UTIL_11_14_ENTRIES / ( PM_RUN_CYC - PM_GCT_NOSLOT_CYC) * 100 @@@group=General @PMD_RUN_CPI;Run cycles per run instruction @@PM_RUN_CYC / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_STALL_CPI;Completion Stall Cycles @@PM_CMPLU_STALL / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_FXU_STALL_CPI;Cycles stalled by FXU @@PM_CMPLU_STALL_FXU / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_FXU_MULTI_CYC_CPI;Cycles stalled by FXU Multi-Cycle Instructions @@PM_CMPLU_STALL_FXLONG / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_FXU_STALL_OTHER_CPI;Other cycles stalled by FXU @@PMD_FXU_STALL_CPI - PMD_FXU_MULTI_CYC_CPI @@@group=CPI_Breakdown @PMD_VSU_STALL_CPI;Cycles stalled by VSU @@PM_CMPLU_STALL_VSU / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_VSU_STALL_SCALAR_CPI;Cycles stalled by VSU Scalar Operations @@PM_CMPLU_STALL_SCALAR / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_VSU_STALL_SCALAR_LONG_CPI;Cycles stalled by VSU Scalar Long Operations @@PM_CMPLU_STALL_SCALAR_LONG / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_VSU_STALL_SCALAR_OTHER_CPI;Cycles stalled by Other VSU Scalar Operations @@PMD_VSU_STALL_SCALAR_CPI - PMD_VSU_STALL_SCALAR_LONG_CPI @@@group=CPI_Breakdown @PMD_VSU_STALL_VECTOR_CPI;Cycles stalled by VSU Vector Operations @@PM_CMPLU_STALL_VECTOR / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_VSU_STALL_VECTOR_LONG_CPI;Cycles stalled by VSU Vector Long Operations @@PM_CMPLU_STALL_VECTOR_LONG / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_VSU_STALL_VECTOR_OTHER_CPI;Cycles stalled by other VSU Vector Operations @@(PM_CMPLU_STALL_VECTOR - PM_CMPLU_STALL_VECTOR_LONG) / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_LSU_STALL_CPI;Cycles stalled by LSU @@PM_CMPLU_STALL_LSU / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_LSU_STALL_REJECT_CPI;Cycles stalled by LSU Rejects @@PM_CMPLU_STALL_REJECT / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_LSU_STALL_ERAT_MISS_CPI;Cycles stalled by ERAT Translation rejects @@PM_CMPLU_STALL_ERAT_MISS / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_LSU_STALL_LHS_CPI;Cycles stalled by LHS rejects @@PM_CMPLU_STALL_REJECT_LHS / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_LSU_STALL_LMQ_FULL_CPI;Cycles stalled by LMQ Full rejects @@PM_CMPLU_STALL_REJ_LMQ_FULL / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_LSU_STALL_REJECT_OTHER_CPI;Cycles stalled by Other LSU Rejects @@PMD_LSU_STALL_REJECT_CPI - PMD_LSU_STALL_LHS_CPI - PMD_LSU_STALL_ERAT_MISS_CPI - PMD_LSU_STALL_LMQ_FULL_CPI @@@group=CPI_Breakdown @PMD_LSU_STALL_DCACHE_MISS_CPI;Cycles stalled by D-Cache Misses @@PM_CMPLU_STALL_DCACHE_MISS / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_LSU_STALL_STORE_CPI;Cycles stalled by LSU Stores @@PM_CMPLU_STALL_STORE / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_LSU_STALL_LD_FIN_CPI;Cycles stalled by LSU load finishes @@PM_CMPLU_STALL_LOAD_FINISH / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_LSU_STALL_ST_FWD_CPI;Cycles stalled by LSU store forwarding @@PM_CMPLU_STALL_ST_FWD / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_BRU_CRU_STALL_CPI;Cycles stalled due to CRU or BRU operations @@PM_CMPLU_STALL_BRU_CRU / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_LSU_STALL_OTHER_CPI;Cycles stalled by LSU Stores @@PMD_LSU_STALL_CPI - PMD_LSU_STALL_DCACHE_MISS_CPI - PMD_LSU_STALL_REJECT_CPI - PMD_LSU_STALL_STORE_CPI - PMD_LSU_STALL_LD_FIN_CPI - PMD_LSU_STALL_ST_FWD_CPI @@@group=CPI_Breakdown @PMD_NTCG_FLUSH_CPI;Cycles stalled due to flushed instructions @@PM_CMPLU_STALL_NTCG_FLUSH / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_GCT_EMPTY_CPI;GCT empty cycles @@PM_GCT_NOSLOT_CYC / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_GCT_EMPTY_IC_MISS_CPI;Cycles stalled by GCT empty due to Icache misses @@PM_GCT_NOSLOT_IC_MISS / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_GCT_EMPTY_BR_MPRED_CPI;Cycles GCT empty due to Branch Mispredicts @@PM_GCT_NOSLOT_BR_MPRED / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_GCT_EMPTY_BR_MPRED_IC_MISS_CPI;Cycles GCT empty due to Branch Mispredicts and Icache Misses @@PM_GCT_NOSLOT_BR_MPRED_ICMISS / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_GCT_EMPTY_DISP_HELD_MAP_CPI;Cycles GCT empty where dispatch was held due to maps @@PM_GCT_NOSLOT_DISP_HELD_MAP / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_GCT_EMPTY_DISP_HELD_SRQ_CPI;Cycles GCT empty where dispatch was held due to SRQ @@PM_GCT_NOSLOT_DISP_HELD_SRQ / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_GCT_EMPTY_DISP_HELD_ISSQ_CPI;Cycles GCT empty where dispatch was held due to issue queue @@PM_GCT_NOSLOT_DISP_HELD_ISSQ / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_GCT_EMPTY_DISP_HELD_OTHER_CPI;Cycles GCT empty where dispatch was held due to syncs and other effects @@PM_GCT_NOSLOT_DISP_HELD_OTHER / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_GCT_EMPTY_DISP_HELD_CPI;Cycles GCT empty where dispatch was held @@PMD_GCT_EMPTY_DISP_HELD_MAP_CPI + PMD_GCT_EMPTY_DISP_HELD_SRQ_CPI + PMD_GCT_EMPTY_DISP_HELD_ISSQ_CPI + PMD_GCT_EMPTY_DISP_HELD_OTHER_CPI @@@group=CPI_Breakdown @PMD_GCT_EMPTY_OTHER_CPI;Other GCT empty cycles @@PMD_GCT_EMPTY_CPI - PMD_GCT_EMPTY_IC_MISS_CPI - PMD_GCT_EMPTY_BR_MPRED_CPI - PMD_GCT_EMPTY_BR_MPRED_IC_MISS_CPI - PMD_GCT_EMPTY_DISP_HELD_CPI @@@group=CPI_Breakdown @PMD_COMPLETION_CPI;Cycles in which a Group Completed @@PM_GRP_CMPL / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_BASE_COMPLETION_CPI;Base Completion Cycles @@PM_1PLUS_PPC_CMPL / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_EXPANSION_OVERHEAD_CPI;Overhead of expansion cycles @@PMD_COMPLETION_CPI - PMD_BASE_COMPLETION_CPI @@@group=CPI_Breakdown @PMD_LOADS_PER_INST;PCT instruction loads @@PM_LD_REF_L1 / PM_RUN_INST_CMPL @@@group=Instruction_Mix @PMD_STORES_PER_INST;PCT instruction stores @@PM_ST_FIN / PM_RUN_INST_CMPL @@@group=Instruction_Mix @PMD_BRANCHES_PER_INST;% Branches per instruction @@PM_BRU_FIN / PM_RUN_INST_CMPL @@@group=Instruction_Mix @PMD_FIXED_PER_INST;Total Fixed point operations @@(PM_FXU0_FIN + PM_FXU1_FIN)/PM_RUN_INST_CMPL @@@group=Instruction_Mix @PMD_FXU0_FIN;Fraction of cycles that FXU0 is in use @@PM_FXU0_FIN / PM_RUN_CYC @@@group=Instruction_Mix @PMD_FXU1_FIN;Fraction of cycles that FXU1 is in use @@PM_FXU1_FIN / PM_RUN_CYC @@@group=Instruction_Mix @PMD_FXU_BOTH_BUSY;Fraction of cycles that FXU1 is in use @@PM_FXU1_FIN / PM_RUN_CYC @@@group=Instruction_Mix @PMD_FXU0_ONLY_BUSY;FXU0 only Busy @@PM_FXU0_BUSY_FXU1_IDLE / PM_CYC @@@group=Instruction_Mix @PMD_FXU1_ONLY_BUSY;FXU1 only Busy @@PM_FXU1_BUSY_FXU0_IDLE / PM_CYC @@@group=Instruction_Mix @PMD_FXU_BOTH_IDLE;Both FXU Idle @@PM_FXU_IDLE / PM_CYC @@@group=Instruction_Mix @PMD_FXU0_BALANCE;FXU0 balance @@PM_FXU0_FIN / (PM_FXU0_FIN + PM_FXU1_FIN) @@@group=Instruction_Mix @PMD_BRANCH_MISPREDICT_RATE;Branch mispredict rate;% @@PM_BR_MPRED_CMPL / PM_RUN_INST_CMPL * 100 @@@group=Branch_Prediction @PMD_CR_MISPREDICT_RATE;CR MisPredictions per Instruction;% @@PM_BR_MPRED_CR / PM_RUN_INST_CMPL * 100 @@@group=Branch_Prediction @PMD_TA_MISPREDICT_RATE;TA MisPredictions per Instruction;% @@PM_BR_MPRED_TA / PM_RUN_INST_CMPL * 100 @@@group=Branch_Prediction @PMD_LSTACK_MISPREDICT_RATE;Link stack branch misprediction;% @@(PM_BR_MPRED_TA - PM_BR_MPRED_CCACHE) / PM_RUN_INST_CMPL * 100 @@@group=Branch_Prediction @PMD_CCACHE_MISPREDICT_RATE;Count cache branch misprediction per instruction;% @@(PM_BR_MPRED_TA - PM_BR_MPRED_CCACHE) / PM_RUN_INST_CMPL * 100 @@@group=Branch_Prediction @PMD_TAKEN_BRANCHES;Percent of branches completed that were taken;% @@PM_BR_TAKEN_CMPL * 100 / PM_BR_CMPL @@@group=Branch_Prediction @PMD_BR_MISPREDICTION;Percent of mispredicted branches out of all predicted (correctly and incorrectly) branches that completed;% @@PM_BR_MPRED_CMPL / (PM_BR_PRED_BR0 + PM_BR_PRED_BR1) * 100 @@@group=Branch_Prediction @PMD_CR_MISPREDICTION;Percent of direction mispredictions out of all completed branches that required direction prediction;% @@PM_BR_MPRED_CR / (PM_BR_PRED_CR_BR0 + PM_BR_PRED_CR_BR0) * 100 @@@group=Branch_Prediction @PMD_TA_MISPREDICTION;Percent of target address mispredictions out of all completed branches that required address prediction;% @@PM_BR_MPRED_TA / (PM_BR_PRED_CCACHE_BR0 + PM_BR_PRED_CCACHE_BR1 + PM_BR_PRED_LSTACK_BR0 + PM_BR_PRED_LSTACK_BR1) * 100 @@@group=Branch_Prediction @PMD_CCACHE_MISPREDICTION;Percent of count catch mispredictions out of all completed branches that required count cache prediction;% @@PM_BR_MPRED_CCACHE / (PM_BR_PRED_CCACHE_BR0 + PM_BR_PRED_CCACHE_BR1) * 100 @@@group=Branch_Prediction @PMD_LSTACK_MISPREDICTION;Percent of link stack mispredictions out of all completed branches that required link stack prediction;% @@(PM_BR_MPRED_TA - PM_BR_MPRED_CCACHE) / (PM_BR_PRED_LSTACK_BR0 + PM_BR_PRED_LSTACK_BR1) * 100 @@@group=Branch_Prediction @PMD_DL1_MISS_RELOADS;% of DL1 misses that result in a cache reload;% @@PM_L1_DCACHE_RELOAD_VALID * 100 / PM_LD_MISS_L1 @@@group=dL1_Reloads @PMD_DL1_RELOAD_FROM_L2;% of DL1 reloads from L2;% @@PM_DATA_FROM_L2MISS * 100 / PM_L1_DCACHE_RELOAD_VALID @@@group=dL1_Reloads @PMD_DL1_RELOAD_FROM_L21_MOD;% of DL1 reloads from Private L2, other core;% @@PM_DATA_FROM_L21_MOD * 100 / PM_L1_DCACHE_RELOAD_VALID @@@group=dL1_Reloads @PMD_DL1_RELOAD_FROM_L21_SHR;% of DL1 reloads from Private L2, other core;% @@PM_DATA_FROM_L21_SHR * 100 / PM_L1_DCACHE_RELOAD_VALID @@@group=dL1_Reloads @PMD_DL1_RELOAD_FROM_L31_MOD;% of DL1 reloads from Private L3, other core;% @@PM_DATA_FROM_L31_MOD * 100 / PM_L1_DCACHE_RELOAD_VALID @@@group=dL1_Reloads @PMD_DL1_RELOAD_FROM_L31_SHR;% of DL1 reloads from Private L3, other core;% @@PM_DATA_FROM_L31_SHR * 100 / PM_L1_DCACHE_RELOAD_VALID @@@group=dL1_Reloads @PMD_DL1_RELOAD_FROM_L3;% of DL1 Reloads from L3;% @@PM_DATA_FROM_L3 * 100 / PM_L1_DCACHE_RELOAD_VALID @@@group=dL1_Reloads @PMD_DL1_RELOAD_FROM_RL2L3_SHR;% of DL1 dL1_Reloads from Remote L2 or L3 (Shared);% @@PM_DATA_FROM_RL2L3_SHR * 100 / PM_L1_DCACHE_RELOAD_VALID @@@group=dL1_Reloads @PMD_DL1_RELOAD_FROM_RL2L3_SHR;% of DL1 dL1_Reloads from Remote L2 or L3 (Modified);% @@PM_DATA_FROM_RL2L3_MOD * 100 / PM_L1_DCACHE_RELOAD_VALID @@@group=dL1_Reloads @PMD_DL1_RELOAD_FROM_DL2L3_MOD;% of DL1 dL1_Reloads from Distant L2 or L3 (Modified);% @@PM_DATA_FROM_DL2L3_MOD * 100 / PM_L1_DCACHE_RELOAD_VALID @@@group=dL1_Reloads @PMD_DL1_RELOAD_FROM_DL2L3_SHR;% of DL1 dL1_Reloads from Distant L2 or L3 (Shared);% @@PM_DATA_FROM_DL2L3_SHR * 100 / PM_L1_DCACHE_RELOAD_VALID @@@group=dL1_Reloads @PMD_DL1_RELOAD_FROM_LL4;% of DL1 Reloads from Local L4 per Inst;% @@PM_DATA_FROM_LL4 * 100 / PM_L1_DCACHE_RELOAD_VALID @@@group=dL1_Reloads @PMD_DL1_RELOAD_FROM_LMEM;% of DL1 dL1_Reloads from Local Memory;% @@PM_DATA_FROM_LMEM * 100 / PM_L1_DCACHE_RELOAD_VALID @@@group=dL1_Reloads @PMD_DL1_RELOAD_FROM_RL4;% of DL1 dL1_Reloads from Remote L4;% @@PM_DATA_FROM_RL4 * 100 / PM_L1_DCACHE_RELOAD_VALID @@@group=dL1_Reloads @PMD_DL1_RELOAD_FROM_RMEM;% of DL1 dL1_Reloads from Remote Memory;% @@PM_DATA_FROM_RMEM * 100 / PM_L1_DCACHE_RELOAD_VALID @@@group=dL1_Reloads @PMD_DL1_RELOAD_FROM_DL4;% of DL1 dL1_Reloads from Distant L4;% @@PM_DATA_FROM_DL4 * 100 / PM_L1_DCACHE_RELOAD_VALID @@@group=dL1_Reloads @PMD_DL1_RELOAD_FROM_DMEM;% of DL1 dL1_Reloads from Distant Memory;% @@PM_DATA_FROM_DMEM * 100 / PM_L1_DCACHE_RELOAD_VALID @@@group=dL1_Reloads @PMD_AVERAGE_IL1_MISS_LATENCY;Average icache miss latency @@(PM_IC_DEMAND_CYC / PM_IC_DEMAND_REQ) @@@group=Latency @PMD_ESTIMATED_DL1MISS_LATENCY;average L1 miss latency using marked events @@PM_MRK_LD_MISS_L1_CYC / PM_MRK_LD_MISS_L1 @@@group=Latency @PMD_L2_LATENCY;Marked L2 Load latency @@PM_MRK_DATA_FROM_L2_CYC/ PM_MRK_DATA_FROM_L2 @@@group=Latency @PMD_L3_LATENCY;Marked L3 Load latency @@PM_MRK_DATA_FROM_L3_CYC/ PM_MRK_DATA_FROM_L3 @@@group=Latency @PMD_L3PREF_LATENCY;Latency for marked reloads that hit in the L3 on the MEPF state @@PM_MRK_DATA_FROM_L3_MEPF_CYC/ PM_MRK_DATA_FROM_L3_MEPF @@@group=Latency @PMD_ON_CHIP_CACHE_LATENCY;Latency for marked reloads that hit in the L2 or L3 of any other core on the same chip @@PM_MRK_DATA_FROM_ON_CHIP_CACHE_CYC/ PM_MRK_DATA_FROM_ON_CHIP_CACHE @@@group=Latency @PMD_L21_MOD_LATENCY;Marked L21 Load latency @@PM_MRK_DATA_FROM_L21_MOD_CYC/ PM_MRK_DATA_FROM_L21_MOD @@@group=Latency @PMD_L21_SHR_LATENCY;Marked L21 Load latency @@PM_MRK_DATA_FROM_L21_MOD_CYC/ PM_MRK_DATA_FROM_L21_MOD @@@group=Latency @PMD_L31_MOD_LATENCY;Marked L31 Load latency @@PM_MRK_DATA_FROM_L31_MOD_CYC/ PM_MRK_DATA_FROM_L31_MOD @@@group=Latency @PMD_L31_SHR_LATENCY;Marked L31 Load latency @@PM_MRK_DATA_FROM_L31_SHR_CYC/ PM_MRK_DATA_FROM_L31_SHR @@@group=Latency @PMD_RL2L3_SHR_LATENCY;Marked L2L3 remote Load latency @@PM_MRK_DATA_FROM_RL2L3_SHR_CYC/ PM_MRK_DATA_FROM_RL2L3_SHR @@@group=Latency @PMD_RL2L3_MOD_LATENCY;Marked L2L3 remote Load latency @@PM_MRK_DATA_FROM_RL2L3_MOD_CYC/ PM_MRK_DATA_FROM_RL2L3_MOD @@@group=Latency @PMD_DL2L3_MOD_LATENCY;Marked L2L3 remote Load latency @@PM_MRK_DATA_FROM_DL2L3_MOD_CYC/ PM_MRK_DATA_FROM_DL2L3_MOD @@@group=Latency @PMD_DL2L3_SHR_LATENCY;Marked L2L3 distant Load latency @@PM_MRK_DATA_FROM_DL2L3_SHR_CYC/ PM_MRK_DATA_FROM_DL2L3_SHR @@@group=Latency @PMD_LL4_LATENCY;Local L4 average load latency @@PM_MRK_DATA_FROM_LL4_CYC/ PM_MRK_DATA_FROM_LL4 @@@group=Latency @PMD_LMEM_LATENCY;Marked Lmem Load latency @@PM_MRK_DATA_FROM_LMEM_CYC/ PM_MRK_DATA_FROM_LMEM @@@group=Latency @PMD_RL4_LATENCY;Remote L4 average load latency @@PM_MRK_DATA_FROM_RL4_CYC/ PM_MRK_DATA_FROM_RL4 @@@group=Latency @PMD_RMEM_LATENCY;Marked Rmem Load latency @@PM_MRK_DATA_FROM_RMEM_CYC/ PM_MRK_DATA_FROM_RMEM @@@group=Latency @PMD_DL4_LATENCY;Distant L4 average load latency @@PM_MRK_DATA_FROM_DL4_CYC/ PM_MRK_DATA_FROM_DL4 @@@group=Latency @PMD_DMEM_LATENCY;Marked Dmem Load latency @@PM_MRK_DATA_FROM_DMEM_CYC/ PM_MRK_DATA_FROM_DMEM @@@group=Latency @PMD_BKILL_LATENCY;Marked background kill latency, measured in L2 @@PM_MRK_FAB_RSP_BKILL_CYC / PM_MRK_FAB_RSP_BKILL @@@group=Latency @PMD_DCLAIM_LATENCY;Marked dclaim latency, measured in L2 @@PM_MRK_FAB_RSP_DCLAIM_CYC / PM_MRK_FAB_RSP_DCLAIM @@@group=Latency @PMD_AVERAGE_SYNC_CYC;average service time for SYNC @@PM_LSU_SRQ_SYNC_CYC / PM_LSU_SRQ_SYNC @@@group=Latency @PMD_AVG_LMQ_LIFE_TIME;Cycles LMQ slot0 was active on an average @@PM_LSU_LMQ_S0_VALID / PM_LSU_LMQ_S0_ALLOC @@@group=Latency @PMD_AVG_LRQ_LIFE_TIME_EVENt;Average number of cycles LRQ stays active for one load. Slot 0 is VALID ONLY FOR EVEN THREADS @@PM_LSU_LRQ_S0_VALID / PM_LSU_LRQ_S0_ALLOC @@@group=Latency @PMD_AVG_LRQ_LIFE_TIME_ODD;Average number of cycles LRQ stays active for one load. Slot 43 is valid ONLY FOR ODD THREADS @@PM_LSU_LRQ_S43_VALID / PM_LSU_LRQ_S43_ALLOC @@@group=Latency @PMD_AVG_SRQ_LIFE_TIME_EVEN;Average number of cycles SRQ stays active for one load. Slot 0 is VALID ONLY FOR EVEN THREADS @@PM_LSU_SRQ_S0_VALID / PM_LSU_SRQ_S0_ALLOC @@@group=Latency @PMD_AVG_SRQ_LIFE_TIME_ODD;Average number of cycles SRQ stays active for one load. Slot 39 is valid ONLY FOR ODD THREADS @@PM_LSU_SRQ_S39_VALID / PM_LSU_SRQ_S39_ALLOC @@@group=Latency @PMD_DCACHE_MISS_CPI;dL1 miss portion of CPI;% @@(PMD_LSU_STALL_DCACHE_MISS_CPI / PMD_RUN_CPI) * 100 @@@group=Estimated_Dcache_Miss_CPI @PMD_L2_CPI;estimate of dl2 miss rates with measured L2 latency as a %of dcache miss cpi;% @@( PMD_LSU_STALL_DCACHE_MISS_CPI/ PMD_RUN_CPI) * 100 @@@group=Estimated_Dcache_Miss_CPI @PMD_L21_MOD_CPI;estimate of dl21 MOD miss rates with measured L21 MOD latency as a %of dcache miss cpi;% @@ (((PM_DATA_FROM_L21_MOD / PM_RUN_INST_CMPL) * PMD_L21_MOD_LATENCY) / PMD_LSU_STALL_DCACHE_MISS_CPI) *100 @@@group=Estimated_Dcache_Miss_CPI @PMD_L21_SHR_CPI; estimate of dl21 SHR miss rates with measured L21 SHR latency as a %of dcache miss cpi;% @@ (((PM_DATA_FROM_L21_SHR / PM_RUN_INST_CMPL) * PMD_L21_SHR_LATENCY) / PMD_LSU_STALL_DCACHE_MISS_CPI) *100 @@@group=Estimated_Dcache_Miss_CPI @PMD_L31_MOD_CPI; estimate of dl31 MOD miss rates with measured L31 MOD latency as a %of dcache miss cpi;% @@(((PM_DATA_FROM_L31_MOD / PM_RUN_INST_CMPL) * PMD_L31_MOD_LATENCY) / PMD_LSU_STALL_DCACHE_MISS_CPI) *100 @@@group=Estimated_Dcache_Miss_CPI @PMD_L31_SHR_CPI; estimate of dl31 SHR miss rates with measured L31 SHR latency as a %of dcache miss cpi;% @@(((PM_DATA_FROM_L31_SHR / PM_RUN_INST_CMPL) * PMD_L31_SHR_LATENCY) / PMD_LSU_STALL_DCACHE_MISS_CPI) *100 @@@group=Estimated_Dcache_Miss_CPI @PMD_L3_CPI; estimate of dl3 miss rates with measured L3 latency as a % of dcache miss cpi;% @@(((PM_DATA_FROM_L3 / PM_RUN_INST_CMPL) * PMD_L3_LATENCY) / PMD_LSU_STALL_DCACHE_MISS_CPI) * 100 @@@group=Estimated_Dcache_Miss_CPI @PMD_RL2L3_SHR_CPI; estimate of dl2l3 shared miss rates with measured RL2L3 SHR latency as a %of dcache miss cpi;% @@(((PM_DATA_FROM_RL2L3_SHR / PM_RUN_INST_CMPL) * PMD_RL2L3_SHR_LATENCY) / PMD_LSU_STALL_DCACHE_MISS_CPI) * 100 @@@group=Estimated_Dcache_Miss_CPI @PMD_RL2L3_MOD_CPI; estimate of dl2l3 remote MOD miss rates with measured RL2L3 MOD latency as a %of dcache miss cpi;% @@(((PM_DATA_FROM_RL2L3_MOD / PM_RUN_INST_CMPL) * PMD_RL2L3_MOD_LATENCY) / PMD_LSU_STALL_DCACHE_MISS_CPI) *100 @@@group=Estimated_Dcache_Miss_CPI @PMD_DL2L3_MOD_CPI; estimate of dl2l3 distant MOD miss rates with measured DL2L3 MOD latency as a %of dcache miss cpi;% @@(((PM_DATA_FROM_DL2L3_MOD / PM_RUN_INST_CMPL) * PMD_DL2L3_MOD_LATENCY) / PMD_LSU_STALL_DCACHE_MISS_CPI) *100 @@@group=Estimated_Dcache_Miss_CPI @PMD_DL2L3_SHR_CPI; estimate of dl2l3 distant SHR miss rates with measured DL2L3 SHR latency as a %of dcache miss cpi;% @@(((PM_DATA_FROM_DL2L3_SHR / PM_RUN_INST_CMPL) * PMD_DL2L3_SHR_LATENCY) / PMD_LSU_STALL_DCACHE_MISS_CPI) *100 @@@group=Estimated_Dcache_Miss_CPI @PMD_DL2L3_SHR_CPI; estimate of Local L4 miss rates with measured LL4 latency as a %of dcache miss cpi;% @@(((PM_DATA_FROM_LL4 / PM_RUN_INST_CMPL) * PMD_LL4_LATENCY) / PMD_LSU_STALL_DCACHE_MISS_CPI) *100 @@@group=Estimated_Dcache_Miss_CPI @PMD_LMEM_CPI; estimate of Local memory miss rates with measured LMEM latency as a %of dcache miss cpi;% @@(((PM_DATA_FROM_LMEM / PM_RUN_INST_CMPL) * PMD_LMEM_LATENCY) / PMD_LSU_STALL_DCACHE_MISS_CPI) *100 @@@group=Estimated_Dcache_Miss_CPI @PMD_RL4_CPI; estimate of remote L4 miss rates with measured RL4 latency as a %of dcache miss cpi;% @@(((PM_DATA_FROM_RL4 / PM_RUN_INST_CMPL) * PMD_RL4_LATENCY) / PMD_LSU_STALL_DCACHE_MISS_CPI) *100 @@@group=Estimated_Dcache_Miss_CPI @PMD_RMEM_CPI;estimate of remote memory miss rates with measured RMEM latency as a %of dcache miss cpi;% @@(((PM_DATA_FROM_RMEM / PM_RUN_INST_CMPL) * PMD_RMEM_LATENCY) / PMD_LSU_STALL_DCACHE_MISS_CPI) *100 @@@group=Estimated_Dcache_Miss_CPI @PMD_DL4_CPI;estimate of distant L4 miss rates with measured DL4 latency as a %of dcache miss cpi;% @@(((PM_DATA_FROM_RMEM / PM_RUN_INST_CMPL) * PMD_RMEM_LATENCY) / PMD_LSU_STALL_DCACHE_MISS_CPI) *100 @@@group=Estimated_Dcache_Miss_CPI @PMD_DMEM_CPI;estimate of distant memory miss rates with measured DMEM latency as a %of dcache miss cpi;% @@(((PM_DATA_FROM_DMEM / PM_RUN_INST_CMPL) * PMD_DMEM_LATENCY) / PMD_LSU_STALL_DCACHE_MISS_CPI) *100 @@@group=Estimated_Dcache_Miss_CPI @PMD_L1_LD_MISS_RATE;Percentage of L1 demand load misses per run instruction;% @@PM_LD_MISS_L1 * 100 / PM_RUN_INST_CMPL @@@group=dL1_Reloads @PMD_DL1_RELOAD_FROM_L2_Rate;% of DL1 reloads from L2 per Inst;% @@PM_DATA_FROM_L2 * 100 / PM_RUN_INST_CMPL @@@group=dL1_Reloads @PMD_DL1_RELOAD_FROM_L21_MOD_Rate;% of DL1 reloads from Private L2, other core per Inst;% @@PM_DATA_FROM_L21_MOD * 100 / PM_RUN_INST_CMPL @@@group=dL1_Reloads @PMD_DL1_RELOAD_FROM_L21_SHR_Rate;% of DL1 reloads from Private L2, other core per Inst;% @@PM_DATA_FROM_L21_SHR * 100 / PM_RUN_INST_CMPL @@@group=dL1_Reloads @PMD_DL1_RELOAD_FROM_L31_MOD_Rate;% of DL1 reloads from Private L3 M state, other core per Inst;% @@PM_DATA_FROM_L31_MOD * 100 / PM_RUN_INST_CMPL @@@group=dL1_Reloads @PMD_DL1_RELOAD_FROM_L31_SHR_Rate;% of DL1 reloads from Private L3 S tate, other core per Inst;% @@PM_DATA_FROM_L31_SHR * 100 / PM_RUN_INST_CMPL @@@group=dL1_Reloads @PMD_DL1_RELOAD_FROM_L2_Miss_Rate;% of DL1 reloads from L2 per Inst;% @@PM_DATA_FROM_L2MISS * 100 / PM_RUN_INST_CMPL @@@group=dL1_Reloads @PMD_DL1_RELOAD_FROM_L3_Rate;% of DL1 Reloads from L3 per Inst;% @@PM_DATA_FROM_L3 * 100 / PM_RUN_INST_CMPL @@@group=dL1_Reloads @PMD_DL1_RELOAD_FROM_L3_Miss_Rate;% of DL1 reloads from L3 per Inst;% @@PM_DATA_FROM_L3MISS * 100 / PM_RUN_INST_CMPL @@@group=dL1_Reloads @PMD_DL1_RELOAD_FROM_RL2L3_SHR_Rate;% of DL1 reloads from L3 per Inst;% @@PM_DATA_FROM_L3MISS * 100 / PM_RUN_INST_CMPL @@@group=dL1_Reloads @PMD_DL1_RELOAD_FROM_RL2L3_MOD_RATE;% of DL1 reloads from L3 per Inst;% @@PM_DATA_FROM_L3MISS * 100 / PM_RUN_INST_CMPL @@@group=dL1_Reloads @PMD_DL1_RELOAD_FROM_DL2L3_MOD_Rate;% of DL1 Reloads from Distant L2 or L3 (Modified) per Inst;% @@PM_DATA_FROM_DL2L3_MOD * 100 / PM_RUN_INST_CMPL @@@group=dL1_Reloads @PMD_DL1_RELOAD_FROM_DL2L3_SHR_Rate;% of DL1 Reloads from Distant L2 or L3 (Modified) per Inst;% @@PM_DATA_FROM_DL2L3_MOD * 100 / PM_RUN_INST_CMPL @@@group=dL1_Reloads @PMD_DL1_RELOAD_FROM_LL4_Rate;% of DL1 Reloads from Local L4 per Inst;% @@PM_DATA_FROM_LL4 * 100 / PM_RUN_INST_CMPL @@@group=dL1_Reloads @PMD_DL1_RELOAD_FROM_LMEM_Rate;% of DL1 Reloads from Local Memory per Inst;% @@PM_DATA_FROM_LMEM * 100 / PM_RUN_INST_CMPL @@@group=dL1_Reloads @PMD_DL1_RELOAD_FROM_RL4_Rate;% of DL1 Reloads from Remote Memory per Inst;% @@PM_DATA_FROM_RL4 * 100 / PM_RUN_INST_CMPL @@@group=dL1_Reloads @PMD_DL1_RELOAD_FROM_RMEM_Rate;% of DL1 Reloads from Remote Memory per Inst;% @@PM_DATA_FROM_RMEM * 100 / PM_RUN_INST_CMPL @@@group=dL1_Reloads @PMD_DL1_RELOAD_FROM_DL4_Rate;% of DL1 Reloads from Distant L4 per Inst;% @@PM_DATA_FROM_DL4 * 100 / PM_RUN_INST_CMPL @@@group=dL1_Reloads @PMD_DL1_RELOAD_FROM_DMEM_Rate;% of DL1 Reloads from Distant Memory per Inst;% @@PM_DATA_FROM_DMEM * 100 / PM_RUN_INST_CMPL @@@group=dL1_Reloads @PMD_MEM_LOCALITY;Memory locality;% @@PM_DATA_FROM_LMEM * 100/ (PM_DATA_FROM_LMEM + PM_DATA_FROM_RMEM + PM_DATA_FROM_DMEM) @@@group=Memory @PMD_LD_LMEM_PER_LD_RMEM;Number of loads from local memory per loads from remote memory @@PM_DATA_FROM_LMEM / PM_DATA_FROM_RMEM @@@group=Memory @PMD_LD_LMEM_PER_LD_DMEM;Number of loads from local memory per loads from distant memory @@PM_DATA_FROM_LMEM / PM_DATA_FROM_DMEM @@@group=Memory @PMD_LD_LMEM_PER_LD_MEM;Number of loads from local memory per loads from remote and distant memory @@PM_DATA_FROM_LMEM / (PM_DATA_FROM_DMEM + PM_DATA_FROM_RMEM) @@@group=Memory @PMD_LD_RMEM_PER_LD_DMEM;Number of loads from remote memory per loads from distant memory @@PM_DATA_FROM_RMEM / PM_DATA_FROM_DMEM @@@group=Memory @PMD_L4_LOCALITY;L4 locality(%);% @@PM_DATA_FROM_LL4 * 100 / (PM_DATA_FROM_LL4 + PM_DATA_FROM_RL4 + PM_DATA_FROM_DL4) @@@group=Memory @PMD_LD_LL4_PER_LD_RL4;Ratio of reloads from local L4 to remote L4 @@PM_DATA_FROM_LL4 / PM_DATA_FROM_RL4 @@@group=Memory @PMD_LD_LL4_PER_LD_DMEM;Ratio of reloads from local L4 to distant L4 @@PM_DATA_FROM_LL4 / PM_DATA_FROM_DL4 @@@group=Memory @PMD_LD_LL4_PER_LD_MEM;Ratio of reloads from local L4 to remote+distant L4 @@PM_DATA_FROM_LL4 / (PM_DATA_FROM_DL4 + PM_DATA_FROM_RL4) @@@group=Memory @PMD_DERAT_MISS_RATE;DERAT Miss Rate (per run instruction);% @@PM_LSU_DERAT_MISS * 100 / PM_RUN_INST_CMPL @@@group=Translation @PMD_DERAT_4K_MISS_RATE;% DERAT miss rate for 4K page per inst;% @@PM_DERAT_MISS_4K * 100 / PM_RUN_INST_CMPL @@@group=Translation @PMD_DERAT_64K_MISS_RATE;% DERAT miss ratio for 64K page per inst;% @@PM_DERAT_MISS_64K * 100 / PM_RUN_INST_CMPL @@@group=Translation @PMD_DERAT_16M_MISS_RATE;% DERAT miss rate for 16M page per inst;% @@PM_DERAT_MISS_16M * 100 / PM_RUN_INST_CMPL @@@group=Translation @PMD_DERAT_16G_MISS_RATE;% DERAT miss rate for 16M page per inst;% @@PM_DERAT_MISS_16M * 100 / PM_RUN_INST_CMPL @@@group=Translation @PMD_DSLB_MISS_RATE;% DSLB_Miss_Rate per inst;% @@PM_DSLB_MISS * 100 / PM_RUN_INST_CMPL @@@group=Translation @PMD_DERAT_MISS_RATIO;DERAT miss ratio @@PM_LSU_DERAT_MISS / PM_LSU_DERAT_MISS @@@group=Translation @PMD_DERAT_4K_MISS_RATIO;DERAT miss ratio for 4K page @@PM_DERAT_MISS_4K / PM_LSU_DERAT_MISS @@@group=Translation @PMD_DERAT_64K_MISS_RATIO;DERAT miss ratio for 64K page @@PM_DERAT_MISS_64K / PM_LSU_DERAT_MISS @@@group=Translation @PMD_DERAT_16M_MISS_RATIO;DERAT miss ratio for 16M page @@PM_DERAT_MISS_16M / PM_LSU_DERAT_MISS @@@group=Translation @PMD_DERAT_16G_MISS_RATIO;DERAT miss ratio for 16G page @@PM_DERAT_MISS_16G / PM_LSU_DERAT_MISS @@@group=Translation @PMD_L1_INST_MISS_RATE;Instruction Cache Miss Rate (Per run Instruction);% @@PM_L1_ICACHE_MISS * 100 / PM_RUN_INST_CMPL @@@group=Translation @PMD_ISLB_MISS_RATE;% ISLB miss rate per inst;% @@PM_ISLB_MISS * 100 / PM_RUN_INST_CMPL @@@group=Translation @PMD_DERAT_MISS_RELOAD;% of DERAT misses that result in an ERAT reload;% @@PM_DTLB_MISS * 100 / PM_LSU_DERAT_MISS @@@group=PTEG_Reloads(% per ref) @PMD_PTEG_FROM_L2;% of DERAT reloads from L2;% @@PM_DPTEG_FROM_L2 * 100 / PM_DTLB_MISS @@@group=PTEG_Reloads(% per ref) @PMD_PTEG_FROM_L21_MOD;% of DERAT reloads from Private L2, other core per inst;% @@PM_DPTEG_FROM_L21_MOD * 100 / PM_RUN_INST_CMPL @@@group=PTEG_Reloads(% per ref) @PMD_PTEG_FROM_L21_SHR;% of DERAT reloads from Private L2, other core;% @@PM_DPTEG_FROM_L21_SHR * 100 / PM_DTLB_MISS @@@group=PTEG_Reloads(% per ref) @PMD_PTEG_FROM_L31_MOD;% of DERAT reloads from Private L3, other core per inst;% @@PM_DPTEG_FROM_L31_MOD * 100 / PM_RUN_INST_CMPL @@@group=PTEG_Reloads(% per ref) @PMD_PTEG_FROM_L31_SHR;% of DERAT reloads from Private L3, other core;% @@PM_DPTEG_FROM_L31_SHR * 100 / PM_DTLB_MISS @@@group=PTEG_Reloads(% per ref) @PMD_PTEG_FROM_L3;% of DERAT reloads from L3;% @@PM_DPTEG_FROM_L3 * 100 / PM_DTLB_MISS @@@group=PTEG_Reloads(% per ref) @PMD_PTEG_FROM_RL2L3_SHR;% of DERAT reloads from Remote L2 or L3 (Shared);% @@PM_DPTEG_FROM_RL2L3_SHR * 100 / PM_DTLB_MISS @@@group=PTEG_Reloads(% per ref) @PMD_PTEG_FROM_RL2L3_MOD;% of DERAT reloads from Remote L2 or L3 (Modified);% @@PM_DPTEG_FROM_RL2L3_MOD * 100 / PM_DTLB_MISS @@@group=PTEG_Reloads(% per ref) @PMD_PTEG_FROM_DL2L3_MOD;% of DERAT reloads from Distant L2 or L3 (Modified);% @@PM_DPTEG_FROM_DL2L3_MOD * 100 / PM_DTLB_MISS @@@group=PTEG_Reloads(% per ref) @PMD_PTEG_FROM_DL2L3_SHR;% of DERAT reloads from Distant L2 or L3 (Shared);% @@PM_DPTEG_FROM_DL2L3_SHR * 100 / PM_DTLB_MISS @@@group=PTEG_Reloads(% per ref) @PMD_PTEG_FROM_LL4;% of DERAT reloads from Local L4 per inst;% @@PM_DPTEG_FROM_LL4 * 100 / PM_RUN_INST_CMPL @@@group=PTEG_Reloads(% per ref) @PMD_PTEG_FROM_LMEM;% of DERAT reloads from Local Memory;% @@PM_DPTEG_FROM_LMEM * 100 / PM_DTLB_MISS @@@group=PTEG_Reloads(% per ref) @PMD_PTEG_FROM_RL4;% of DERAT reloads from Remote L4;% @@PM_DPTEG_FROM_RL4 * 100 / PM_DTLB_MISS @@@group=PTEG_Reloads(% per ref) @PMD_PTEG_FROM_RMEM;% of DERAT reloads from Remote Memory;% @@PM_DPTEG_FROM_RMEM * 100 / PM_DTLB_MISS @@@group=PTEG_Reloads(% per ref) @PMD_PTEG_FROM_DL4;% of DERAT reloads from Distant L4 per inst;% @@PM_DPTEG_FROM_DL4 * 100 / PM_RUN_INST_CMPL @@@group=PTEG_Reloads(% per ref) @PMD_PTEG_FROM_DMEM;% of DERAT reloads from Distant Memory;% @@PM_DPTEG_FROM_DMEM * 100 / PM_DTLB_MISS @@@group=PTEG_Reloads(% per ref) @PMD_DERAT_MISS_RATE;DERAT Miss Rate (per run instruction)(%);% @@PM_LSU_DERAT_MISS * 100 / PM_RUN_INST_CMPL @@@group=PTEG_Reloads(% per inst) @PMD_PTEG_FROM_L2_RATE;% of DERAT reloads from L2 per inst;% @@PM_DPTEG_FROM_L2 * 100 / PM_RUN_INST_CMPL @@@group=PTEG_Reloads(% per inst) @PMD_PTEG_FROM_L21_MOD_RATE;% of DERAT reloads from L2 per inst;% @@PM_DPTEG_FROM_L2 * 100 / PM_RUN_INST_CMPL @@@group=PTEG_Reloads(% per inst) @PMD_PTEG_FROM_L21_SHR_RATE;% of DERAT reloads from Private L2, other core per inst;% @@PM_DPTEG_FROM_L21_SHR * 100 / PM_RUN_INST_CMPL @@@group=PTEG_Reloads(% per inst) @PMD_PTEG_FROM_L31_MOD_RATE;% of DERAT reloads from Private L3, other core per inst;% @@PM_DPTEG_FROM_L31_MOD * 100 / PM_RUN_INST_CMPL @@@group=PTEG_Reloads(% per inst) @PMD_PTEG_FROM_L31_SHR_RATE;% of DERAT reloads from Private L3, other core per inst;% @@PM_DPTEG_FROM_L31_SHR * 100 / PM_RUN_INST_CMPL @@@group=PTEG_Reloads(% per inst) @PMD_PTEG_FROM_L3_RATE;% of DERAT reloads from L3 per inst;% @@PM_DPTEG_FROM_L3 * 100 / PM_RUN_INST_CMPL @@@group=PTEG_Reloads(% per inst) @PMD_PTEG_FROM_RL2L3_SHR_RATE;% of DERAT reloads from Remote L2 or L3 (Shared) per inst;% @@PM_DPTEG_FROM_RL2L3_SHR * 100 / PM_RUN_INST_CMPL @@@group=PTEG_Reloads(% per inst) @PMD_PTEG_FROM_RL2L3_MOD_RATE;% of DERAT reloads from Remote L2 or L3 (Modified) per inst;% @@PM_DPTEG_FROM_RL2L3_MOD * 100 / PM_RUN_INST_CMPL @@@group=PTEG_Reloads(% per inst) @PMD_PTEG_FROM_DL2L3_MOD_RATE;% of DERAT reloads from Distant L2 or L3 (Modified) per inst;% @@PM_DPTEG_FROM_DL2L3_MOD * 100 / PM_RUN_INST_CMPL @@@group=PTEG_Reloads(% per inst) @PMD_PTEG_FROM_DL2L3_SHR_RATE;% of DERAT reloads from Distant L2 or L3 (Shared) per inst;% @@PM_DPTEG_FROM_DL2L3_SHR * 100 / PM_RUN_INST_CMPL @@@group=PTEG_Reloads(% per inst) @PMD_PTEG_FROM_LL4_RATE;% of DERAT reloads from Local L4 per inst;% @@PM_DPTEG_FROM_LL4 * 100 / PM_RUN_INST_CMPL @@@group=PTEG_Reloads(% per inst) @PMD_PTEG_FROM_LMEM_RATE;% of DERAT reloads from Local Memory per inst;% @@PM_DPTEG_FROM_LMEM * 100 / PM_RUN_INST_CMPL @@@group=PTEG_Reloads(% per inst) @PMD_PTEG_FROM_RL4_RATE;% of DERAT reloads from Remote L4 per inst;% @@PM_DPTEG_FROM_RL4 * 100 / PM_RUN_INST_CMPL @@@group=PTEG_Reloads(% per inst) @PMD_PTEG_FROM_RMEM_RATE;% of DERAT reloads from Remote Memory per inst;% @@PM_DPTEG_FROM_RMEM * 100 / PM_RUN_INST_CMPL @@@group=PTEG_Reloads(% per inst) @PMD_PTEG_FROM_DL4_RATE;% of DERAT reloads from Distant L4 per inst;% @@PM_DPTEG_FROM_DL4 * 100 / PM_RUN_INST_CMPL @@@group=PTEG_Reloads(% per inst) @PMD_PTEG_FROM_DMEM_RATE;% of DERAT reloads from Distant Memory per inst;% @@PM_DPTEG_FROM_DMEM * 100 / PM_RUN_INST_CMPL @@@group=PTEG_Reloads(% per inst) @PMD_LSU_REJECT_RATIO;LSU reject ratio;% @@PM_LSU_REJECT *100/ (PM_LSU_FIN - PM_LSU_FX_FIN) @@@group=LSU_Rejects @PMD_LHS_REJECT_RATIO;LHS reject ratio;% @@PM_LSU_REJECT_LHS *100/ (PM_LSU_FIN - PM_LSU_FX_FIN) @@@group=LSU_Rejects @PMD_ERAT_REJECT_RATIO;ERAT miss reject ratio;% @@PM_LSU_REJECT_ERAT_MISS * 100 / (PM_LSU_FIN - PM_LSU_FX_FIN) @@@group=LSU_Rejects @PMD_LSU_REJECT_RATE;LSU_Reject_Rate;% @@PM_LSU_REJECT *100/ PM_RUN_INST_CMPL @@@group=LSU_Rejects @PMD_LHS_REJECT_RATE;LHS reject ratio;% @@PM_LSU_REJECT_LHS *100/ PM_RUN_INST_CMPL @@@group=LSU_Rejects @PMD_SET_MPRED_REJECT_RATE;ERAT miss reject ratio;% @@PM_LSU_REJECT_LMQ_FULL * 100 / PM_RUN_INST_CMPL @@@group=LSU_Rejects @PMD_LMQ_FULL_REJECT_RATIO;ERAT miss reject ratio;% @@PM_LSU_REJECT_LMQ_FULL * 100 / PM_LD_REF_L1 @@@group=LSU_Rejects @PMD_ERAT_REJECT_RATE;ERAT miss reject ratio;% @@PM_LSU_REJECT_ERAT_MISS * 100 / PM_RUN_INST_CMPL @@@group=LSU_Rejects @PMD_LMQ_FULL_REJECT_RATE;ERAT miss reject ratio;% @@PM_LSU_REJECT_LMQ_FULL * 100 / PM_RUN_INST_CMPL @@@group=LSU_Rejects @PMD_ICACHE_PREF;% of ICache reloads due to prefetch;% @@PM_IC_PREF_WRITE * 100 / PM_L1_ICACHE_MISS @@@group=Instruction_Stats(% per ref) @PMD_ICACHE_MISS_RELOAD;Icache Fetchs per Icache Miss @@(PM_L1_ICACHE_MISS - PM_IC_PREF_WRITE) / PM_L1_ICACHE_MISS @@@group=Instruction_Stats(% per ref) @PMD_INST_FROM_L2;% of ICache reloads from L2;% @@PM_INST_FROM_L2 * 100 / PM_L1_ICACHE_MISS @@@group=Instruction_Stats(% per ref) @PMD_INST_FROM_L21_MOD;% of ICache reloads from Private L2, other core;% @@PM_INST_FROM_L21_MOD * 100 / PM_L1_ICACHE_MISS @@@group=Instruction_Stats(% per ref) @PMD_INST_FROM_L21_SHR;% of ICache reloads from Private L2, other core;% @@PM_INST_FROM_L21_SHR * 100 / PM_L1_ICACHE_MISS @@@group=Instruction_Stats(% per ref) @PMD_INST_FROM_L31_MOD;% of ICache reloads from Private L3, other core;% @@PM_INST_FROM_L31_MOD * 100 / PM_L1_ICACHE_MISS @@@group=Instruction_Stats(% per ref) @PMD_INST_FROM_L31_SHR;% of ICache reloads from Private L3, other core;% @@PM_INST_FROM_L31_SHR * 100 / PM_L1_ICACHE_MISS @@@group=Instruction_Stats(% per ref) @PMD_INST_FROM_L3;% of ICache reloads from L3;% @@PM_INST_FROM_L3 * 100 / PM_L1_ICACHE_MISS @@@group=Instruction_Stats(% per ref) @PMD_INST_FROM_RL2L3_SHR;% of ICache reloads from Remote L2 or L3 (Shared) per Inst;% @@PM_INST_FROM_RL2L3_SHR * 100 / PM_RUN_INST_CMPL @@@group=Instruction_Stats(% per ref) @PMD_INST_FROM_RL2L3_MOD;% of ICache reloads from Remote L2 or L3 (Modified);% @@PM_INST_FROM_RL2L3_MOD * 100 / PM_L1_ICACHE_MISS @@@group=Instruction_Stats(% per ref) @PMD_INST_FROM_DL2L3_MOD;% of ICache reloads from Distant L2 or L3 (Modified);% @@PM_INST_FROM_DL2L3_MOD * 100 / PM_L1_ICACHE_MISS @@@group=Instruction_Stats(% per ref) @PMD_INST_FROM_DL2L3_SHR;% of ICache reloads from Distant L2 or L3 (Shared);% @@PM_INST_FROM_DL2L3_SHR * 100 / PM_L1_ICACHE_MISS @@@group=Instruction_Stats(% per ref) @PMD_INST_FROM_LL4;% of ICache reloads from Local L4;% @@PM_INST_FROM_LL4 * 100 / PM_L1_ICACHE_MISS @@@group=Instruction_Stats(% per ref) @PMD_INST_FROM_LMEM;% of ICache reloads from Local Memory;% @@PM_INST_FROM_LMEM * 100 / PM_L1_ICACHE_MISS @@@group=Instruction_Stats(% per ref) @PMD_INST_FROM_RL4;% of ICache reloads from Remote L4;% @@PM_INST_FROM_RL4 * 100 / PM_RUN_INST_CMPL @@@group=Instruction_Stats(% per ref) @PMD_INST_FROM_RMEM;% of ICache reloads from Remote Memory;% @@PM_INST_FROM_RMEM * 100 / PM_L1_ICACHE_MISS @@@group=Instruction_Stats(% per ref) @PMD_INST_FROM_DL4;% of ICache reloads from Distant L4;% @@PM_INST_FROM_DL4 * 100 / PM_L1_ICACHE_MISS @@@group=Instruction_Stats(% per ref) @PMD_INST_FROM_DMEM;% of ICache reloads from Distant Memory;% @@PM_INST_FROM_DMEM * 100 / PM_L1_ICACHE_MISS @@@group=Instruction_Stats(% per ref) @PMD_L1_INST_MISS_RATE;Instruction Cache Miss Rate (Per run Instruction);% @@PM_L1_ICACHE_MISS * 100 / PM_RUN_INST_CMPL @@@group=Instruction_Misses(% per inst) @PMD_L1_INST_FROM_L2_RATE;% of ICache reloads from L2 per Inst;% @@PM_INST_FROM_L2 * 100 / PM_RUN_INST_CMPL @@@group=Instruction_Misses(% per inst) @PMD_L1_INST_FROM_L21_MOD_RATE;% of ICache reloads from L2 per Inst;% @@PM_INST_FROM_L2 * 100 / PM_RUN_INST_CMPL @@@group=Instruction_Misses(% per inst) @PMD_INST_FROM_L21_SHR_RATE;% of ICache reloads from Private L2, other core per Inst;% @@PM_INST_FROM_L21_SHR * 100 / PM_RUN_INST_CMPL @@@group=Instruction_Misses(% per inst) @PMD_INST_FROM_L31_MOD_RATE;% of ICache reloads from Private L3, other core per Inst;% @@PM_INST_FROM_L31_MOD * 100 / PM_RUN_INST_CMPL @@@group=Instruction_Misses(% per inst) @PMD_INST_FROM_L31_SHR_RATE;% of ICache reloads from Private L3 other core per Inst;% @@PM_INST_FROM_L31_SHR * 100 / PM_RUN_INST_CMPL @@@group=Instruction_Misses(% per inst) @PMD_INST_FROM_L3_RATE;% of ICache reloads from L3 per Inst;% @@PM_INST_FROM_L3 * 100 / PM_RUN_INST_CMPL @@@group=Instruction_Misses(% per inst) @PMD_INST_FROM_RL2L3_SHR_RATE;% of ICache reloads from Remote L2 or L3 (Shared) per Inst;% @@PM_INST_FROM_RL2L3_SHR * 100 / PM_RUN_INST_CMPL @@@group=Instruction_Misses(% per inst) @PMD_INST_FROM_RL2L3_MOD_RATE;% of ICache reloads from Remote L2 or L3 (Modified) per Inst;% @@PM_INST_FROM_RL2L3_MOD * 100 / PM_RUN_INST_CMPL @@@group=Instruction_Misses(% per inst) @PMD_INST_FROM_DL2L3_MOD_RATE;% of ICache reloads from Distant L2 or L3 (Modified) per Inst;% @@PM_INST_FROM_DL2L3_MOD * 100 / PM_RUN_INST_CMPL @@@group=Instruction_Misses(% per inst) @PMD_INST_FROM_DL2L3_SHR_RATE;% of ICache reloads from Distant L2 or L3 (Shared) per Inst;% @@PM_INST_FROM_DL2L3_SHR * 100 / PM_RUN_INST_CMPL @@@group=Instruction_Misses(% per inst) @PMD_INST_FROM_LL4_RATE;% of ICache reloads from Local L4 per Inst;% @@PM_INST_FROM_LL4 * 100 / PM_RUN_INST_CMPL @@@group=Instruction_Misses(% per inst) @PMD_INST_FROM_LMEM_RATE;% of ICache reloads from Local Memory per Inst;% @@PM_INST_FROM_LMEM * 100 / PM_RUN_INST_CMPL @@@group=Instruction_Misses(% per inst) @PMD_INST_FROM_RL4_RATE;% of ICache reloads from Remote L4 per Inst;% @@PM_INST_FROM_RL4 * 100 / PM_RUN_INST_CMPL @@@group=Instruction_Misses(% per inst) @PMD_INST_FROM_RMEM_RATE;% of ICache reloads from Remote Memory per Inst;% @@PM_INST_FROM_RMEM * 100 / PM_RUN_INST_CMPL @@@group=Instruction_Misses(% per inst) @PMD_INST_FROM_DL4_RATE;% of ICache reloads from Remote Memory per Inst;% @@PM_INST_FROM_RMEM * 100 / PM_RUN_INST_CMPL @@@group=Instruction_Misses(% per inst) @PMD_INST_FROM_DMEM_RATE;% of ICache reloads from Distant Memory per Inst;% @@PM_INST_FROM_DMEM * 100 / PM_RUN_INST_CMPL @@@group=Instruction_Misses(% per inst)