{ @(#)M 1.3.1.5 src/bos/usr/sbin/perf/pmapi/events/POWER7.evs, pmapi, bos720 12/1/11 01:51:31 { IBM_PROLOG_BEGIN_TAG { This is an automatically generated prolog. { { bos720 src/bos/usr/sbin/perf/pmapi/events/POWER7.evs 1.3.1.5 { { Licensed Materials - Property of IBM { { Restricted Materials of IBM { { COPYRIGHT International Business Machines Corp. 2009,2011 { All Rights Reserved { { US Government Users Restricted Rights - Use, duplication or { disclosure restricted by GSA ADP Schedule Contract with IBM Corp. { { IBM_PROLOG_END_TAG 315,314,307,307,1,1 { counter 1 } #0,v,g,n,n,n,PM_1PLUS_PPC_CMPL,1 or more ppc insts finished ##00F2 A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once. #1,v,g,n,n,n,PM_ANY_THRD_RUN_CYC,One of threads in run_cycles ##00FA One of threads in run_cycles #2,v,g,n,n,n,PM_BC_PLUS_8_CONV,BC+8 Converted ##40B8 BC+8 Converted #3,v,g,n,n,n,PM_BC_PLUS_8_RSLV_TAKEN,BC+8 Resolve outcome was Taken, resulting in the conditional instruction being canceled ##40BA BC+8 Resolve outcome was Taken, resulting in the conditional instruction being canceled #4,v,g,n,n,n,PM_BR_MPRED_CCACHE,Branch Mispredict due to Count Cache prediction ##40A4 A branch instruction target was incorrectly predicted by the count cache. This will result in a branch redirect flush if not overwritten by a flush of an older instruction. #5,v,g,n,n,n,PM_BR_MPRED_CR,Branch mispredict - taken/not taken ##40AC A conditional branch instruction was incorrectly predicted as taken or not taken. The branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This will result in a branch redirect flush if not overfidden by a flush of an older instruction. #6,v,g,n,n,n,PM_BR_MPRED_CR_TA,Branch mispredict - taken/not taken and target ##48AE Branch mispredict - taken/not taken and target #7,v,g,n,n,n,PM_BR_MPRED_LSTACK,Branch Mispredict due to Link Stack ##40A6 Branch Mispredict due to Link Stack #8,v,g,n,n,n,PM_BR_MPRED_TA,Branch mispredict - target address ##40AE A branch instruction target was incorrectly predicted. This will result in a branch mispredict flush unless a flush is detected from an older instruction. #9,v,g,n,n,n,PM_BR_PRED,Branch Predictions made ##409C A branch prediction was made. This could have been a target prediction, a condition prediction, or both #10,v,g,n,n,n,PM_BR_PRED_CCACHE,Count Cache Predictions ##40A0 The count value of a Branch and Count instruction was predicted #11,v,g,n,n,n,PM_BR_PRED_CR,Branch predict - taken/not taken ##40A8 A conditional branch instruction was predicted as taken or not taken. #12,v,g,n,n,n,PM_BR_PRED_CR_TA,Branch predict - taken/not taken and target ##48AA Both the condition (taken or not taken) and the target address of a branch instruction was predicted. #13,v,g,n,n,n,PM_BR_PRED_LSTACK,Link Stack Predictions ##40A2 The target address of a Branch to Link instruction was predicted by the link stack. #14,v,g,n,n,n,PM_BR_PRED_TA,Branch predict - target address ##40AA The target address of a branch instruction was predicted. #15,v,g,n,n,n,PM_BR_UNCOND,Unconditional Branch ##409E An unconditional branch was executed. #16,v,g,n,n,n,PM_BRU_FIN,Branch Instruction Finished ##0068 The Branch execution unit finished an instruction #17,v,g,n,n,n,PM_BTAC_HIT,BTAC Correct Prediction ##508A BTAC Correct Prediction #18,v,g,n,n,n,PM_BTAC_MISS,BTAC Mispredicted ##5088 BTAC Mispredicted #19,v,g,n,n,n,PM_CMPLU_STALL_END_GCT_NOSLOT,Count ended because GCT went empty ##0028 Count ended because GCT went empty #20,v,g,n,n,n,PM_CMPLU_STALL_THRD,Completion Stalled due to thread conflict. Group ready to complete but it was another thread's turn ##001C Completion Stalled due to thread conflict. Group ready to complete but it was another thread's turn #21,v,g,n,s,n,PM_CYC,Cycles ##001E Processor Cycles #22,v,g,n,n,n,PM_DATA_FROM_DMEM,Data loaded from distant memory ##C04A The processor's Data Cache was reloaded with data from memory attached to a distant module due to a demand load #23,v,g,n,n,n,PM_DATA_FROM_L2,Data loaded from L2 ##C040 The processor's Data Cache was reloaded from the local L2 due to a demand load. #24,v,g,n,n,n,PM_DATA_FROM_L3,Data loaded from L3 ##C048 The processor's Data Cache was reloaded from the local L3 due to a demand load. #25,v,g,n,n,n,PM_DATA_FROM_L31_MOD,Data loaded from another L3 on same chip modified ##C044 Data loaded from another L3 on same chip modified #26,v,g,n,n,n,PM_DATA_FROM_L31_SHR,Data loaded from another L3 on same chip shared ##C04E Data loaded from another L3 on same chip shared #27,v,g,n,n,n,PM_DATA_FROM_RL2L3_MOD,Data loaded from remote L2 or L3 modified ##C042 The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a remote module due to a demand load #28,v,g,n,n,n,PM_DATA_FROM_RL2L3_SHR,Data loaded from remote L2 or L3 shared ##C04C The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load #29,v,g,n,n,n,PM_DC_PREF_DST,Data Stream Touch ##D0B0 A prefetch stream was started using the DST instruction. #30,v,g,n,n,n,PM_DERAT_MISS_4K,DERAT misses for 4K page ##C05C A data request (load or store) missed the ERAT for 4K page and resulted in an ERAT reload. #31,v,g,n,n,n,PM_DISP_CLB_HELD,CLB Hold: Any Reason ##2090 CLB Hold: Any Reason #32,v,g,n,n,n,PM_DISP_CLB_HELD_BAL,Dispatch/CLB Hold: Balance ##2092 Dispatch/CLB Hold: Balance #33,v,g,n,n,n,PM_DISP_CLB_HELD_RES,Dispatch/CLB Hold: Resource ##2094 Dispatch/CLB Hold: Resource #34,v,g,n,n,n,PM_DISP_CLB_HELD_SB,Dispatch/CLB Hold: Scoreboard ##20A8 Dispatch/CLB Hold: Scoreboard #35,v,g,n,n,n,PM_DISP_CLB_HELD_SYNC,Dispatch/CLB Hold: Sync type instruction ##2098 Dispatch/CLB Hold: Sync type instruction #36,v,g,n,n,n,PM_DISP_CLB_HELD_TLBIE,Dispatch Hold: Due to TLBIE ##2096 Dispatch Hold: Due to TLBIE #37,v,g,n,n,n,PM_DISP_HELD,Dispatch Held ##0006 Dispatch Held #38,v,g,n,n,n,PM_DSEG,DSEG Exception ##20A6 DSEG Exception #39,v,g,n,n,n,PM_DSLB_MISS,Data SLB Miss - Total of all segment sizes ##D090 A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve. #40,v,g,n,n,n,PM_DTLB_MISS_16G,Data TLB miss for 16G page ##C05E Data TLB references to 16GB pages that missed the TLB. Page size is determined at TLB reload time. #41,v,g,n,n,n,PM_EE_OFF_EXT_INT,ee off and external interrupt ##2080 Cycles when an interrupt due to an external exception is pending but external exceptions were masked. #42,v,g,n,n,n,PM_FLOP,Floating Point Operation Finished ##00F4 A floating point operation has completed #43,v,g,n,n,n,PM_FLUSH_BR_MPRED,Flush caused by branch mispredict ##2084 A flush was caused by a branch mispredict. #44,v,g,n,n,n,PM_FLUSH_DISP,Dispatch flush ##2082 Dispatch flush #45,v,g,n,n,n,PM_FLUSH_DISP_SB,Dispatch Flush: Scoreboard ##208C Dispatch Flush: Scoreboard #46,v,g,n,n,n,PM_FLUSH_DISP_SYNC,Dispatch Flush: Sync ##2088 Dispatch Flush: Sync #47,v,g,n,n,n,PM_FLUSH_DISP_TLBIE,Dispatch Flush: TLBIE ##208A Dispatch Flush: TLBIE #48,v,g,n,n,n,PM_FLUSH_PARTIAL,Partial flush ##2086 Partial flush #49,v,g,n,n,n,PM_FXU_IDLE,fxu0 idle and fxu1 idle ##000E FXU0 and FXU1 are both idle. #50,v,g,n,n,n,PM_FXU0_FIN,FXU0 Finished ##0004 The Fixed Point unit 0 finished an instruction and produced a result. Instructions that finish may not necessary complete. #51,v,g,n,s,n,PM_GCT_FULL_CYC,Cycles No room in EAT ##4086 The Global Completion Table is completely full. #52,v,g,n,n,n,PM_GCT_NOSLOT_CYC,No itags assigned ##00F8 Cycles when the Global Completion Table has no slots from this thread. #53,v,g,n,n,n, PM_GCT_UTIL_1_TO_2_SLOTS,GCT Utilization 1-2 entries ##209C GCT Utilization 1-2 entries #54,v,g,n,n,n,PM_GCT_UTIL_11_PLUS_SLOTS,GCT Utilization 11+ entries ##20A2 GCT Utilization 11+ entries #55,v,g,n,n,n,PM_GCT_UTIL_3_TO_6_SLOTS,GCT Utilization 3-6 entries ##209E GCT Utilization 3-6 entries #56,v,g,n,n,n,PM_GCT_UTIL_7_TO_10_SLOTS,GCT Utilization 7-10 entries ##20A0 GCT Utilization 7-10 entries #57,v,g,n,n,n,PM_GRP_BR_MPRED_NONSPEC,Group experienced non-speculative branch redirect ##000A Group experienced non-speculative branch redirect #58,v,g,n,n,n,PM_GRP_IC_MISS_NONSPEC,Group experienced non-speculative I cache miss ##000C Number of groups, counted at completion, that have encountered an instruction cache miss. #59,v,g,t,n,m,PM_GRP_MRK,IDU Marked Instruction ##0031 A group was sampled (marked). The group is called a marked group. One instruction within the group is tagged for detailed monitoring. The sampled instruction is called a marked instructions. Events associated with the marked instruction are annotated with the marked term. #60,v,g,n,n,m,PM_GRP_MRK_CYC,cycles IDU marked instruction before dispatch ##0030 cycles IDU marked instruction before dispatch #61,v,g,n,n,n,PM_IBUF_FULL_CYC,Cycles No room in ibuff ##4084 Cycles with the Instruction Buffer was full. The Instruction Buffer is a circular queue of 64 instructions per thread, organized as 16 groups of 4 instructions. #62,v,g,n,n,n,PM_IC_BANK_CONFLICT,Read blocked due to interleave conflict. ##4082 Read blocked due to interleave conflict. #63,v,g,n,n,n,PM_IC_DEMAND_CYC,Cycles when a demand ifetch was pending ##0018 Cycles when a demand ifetch was pending #64,v,g,n,n,n,PM_IC_DEMAND_L2_BHT_REDIRECT, L2 I cache demand request due to BHT redirect ##4098 A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (CR mispredict). #65,v,g,n,n,n,PM_IC_DEMAND_L2_BR_ALL, L2 I cache demand request due to BHT or redirect ##4898 L2 I cache demand request due to BHT or redirect #66,v,g,n,n,n,PM_IC_DEMAND_L2_BR_REDIRECT, L2 I cache demand request due to branch redirect ##409A A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (either ALL mispredicted or Target). #67,v,g,n,n,n,PM_IC_DEMAND_REQ,Demand Instruction fetch request ##4088 Demand Instruction fetch request #68,v,g,n,n,n,PM_IC_PREF_CANCEL_ALL,Prefetch Canceled due to page boundary or icache hit ##4890 Prefetch Canceled due to page boundary or icache hit #69,v,g,n,n,n,PM_IC_PREF_CANCEL_HIT,Prefetch Canceled due to icache hit ##4092 Prefetch Canceled due to icache hit #70,v,g,n,n,n,PM_IC_PREF_CANCEL_L2,L2 Squashed request ##4094 L2 Squashed request #71,v,g,n,n,n,PM_IC_PREF_CANCEL_PAGE,Prefetch Canceled due to page boundary ##4090 Prefetch Canceled due to page boundary #72,v,g,n,n,n,PM_IC_PREF_REQ,Instruction prefetch requests ##408A An instruction prefetch request has been made. #73,v,g,n,n,n,PM_IC_PREF_WRITE,Instruction prefetch written into IL1 ##408E Number of Instruction Cache entries written because of prefetch. Prefetch entries are marked least recently used and are candidates for eviction if they are not needed to satify a demand fetch. #74,v,g,n,n,n,PM_IC_RELOAD_SHR,Reloading line to be shared between the threads ##4096 An Instruction Cache request was made by this thread and the cache line was already in the cache for the other thread. The line is marked valid for all threads. #75,v,g,n,n,n,PM_IC_REQ_ALL,Icache requests, prefetch + demand ##4888 Icache requests, prefetch + demand #76,v,g,n,n,n,PM_IC_WRITE_ALL,Icache sectors written, prefetch + demand ##488C Icache sectors written, prefetch + demand #77,v,g,n,n,n,PM_IERAT_MISS,IERAT Miss (Not implemented as DI on POWER6) ##00F6 A translation request missed the Instruction Effective to Real Address Translation (ERAT) table #78,v,g,n,n,n,PM_IERAT_WR_64K,large page 64k ##40BE large page 64k #79,v,g,n,n,n,PM_IERAT_XLATE_WR_16MPLUS,large page 16M+ ##40BC large page 16M+ #80,v,g,n,n,n,PM_INST_CMPL,# PPC Instructions Finished ##0002 Number of PowerPC Instructions that completed. #81,v,g,n,n,n,PM_INST_FROM_DMEM,Instruction fetched from distant memory ##404A An instruction fetch group was fetched from memory attached to a distant module. Fetch groups can contain up to 8 instructions #82,v,g,n,n,n,PM_INST_FROM_L1,Instruction fetches from L1 ##4080 An instruction fetch group was fetched from L1. Fetch Groups can contain up to 8 instructions #83,v,g,n,n,n,PM_INST_FROM_L2,Instruction fetched from L2 ##4040 An instruction fetch group was fetched from L2. Fetch Groups can contain up to 8 instructions #84,v,g,n,n,n,PM_INST_FROM_L3,Instruction fetched from L3 ##4048 An instruction fetch group was fetched from L3. Fetch Groups can contain up to 8 instructions #85,v,g,n,n,n,PM_INST_FROM_L31_MOD,Instruction fetched from another L3 on same chip modified ##4044 Instruction fetched from another L3 on same chip modified #86,v,g,n,n,n,PM_INST_FROM_L31_SHR,Instruction fetched from another L3 on same chip shared ##404E Instruction fetched from another L3 on same chip shared #87,v,g,n,n,n,PM_INST_FROM_PREF,Instruction fetched from prefetch ##4046 An instruction fetch group was fetched from the prefetch buffer. Fetch groups can contain up to 8 instructions #88,v,g,n,n,n,PM_INST_FROM_RL2L3_MOD,Instruction fetched from remote L2 or L3 modified ##4042 An instruction fetch group was fetched with modified (M) data from an L2 or L3 on a remote module. Fetch groups can contain up to 8 instructions #89,v,g,n,n,n,PM_INST_FROM_RL2L3_SHR,Instruction fetched from remote L2 or L3 shared ##404C An instruction fetch group was fetched with shared (S) data from the L2 or L3 on a remote module. Fetch groups can contain up to 8 instructions #90,v,g,n,n,n,PM_INST_IMC_MATCH_CMPL,IMC Match Count ##00F0 Number of instructions resulting from the marked instructions expansion that completed. #91,v,g,n,n,n,PM_INST_PTEG_FROM_L2,Instruction PTEG loaded from L2 ##E050 Instruction PTEG loaded from L2 #92,v,g,n,n,n,PM_INST_PTEG_FROM_L31_MOD,Instruction PTEG loaded from another L3 on same chip modified ##E054 Instruction PTEG loaded from another L3 on same chip modified #93,v,g,n,n,n,PM_INST_PTEG_FROM_RL2L3_MOD,Instruction PTEG loaded from remote L2 or L3 modified ##E052 Instruction PTEG loaded from remote L2 or L3 modified #94,v,g,n,n,n,PM_IOPS_CMPL,Internal Operations completed ##0014 Number of internal operations that completed. #95,v,g,n,n,n,PM_ISEG,ISEG Exception ##20A4 ISEG Exception #96,v,g,n,n,n,PM_ISLB_MISS,Instruction SLB Miss - Tota of all segment sizes ##D092 A SLB miss for an instruction fetch as occurred #97,v,g,n,n,n,PM_L1_DEMAND_WRITE,Instruction Demand sectors wriittent into IL1 ##408C Instruction Demand sectors wriittent into IL1 #98,v,g,n,n,n,PM_L1_PREF,L1 Prefetches ##D8B8 A request to prefetch data into the L1 was made #99,v,g,n,s,n,PM_L2_CASTOUT_MOD,L2 Castouts - Modified (M, Mu, Me) ##6180 An L2 line in the Modified state was castout. Total for all slices. #100,v,g,n,s,n,PM_L2_CASTOUT_SHR,L2 Castouts - Shared (T, Te, Si, S) ##6182 An L2 line in the Shared state was castout. Total for all slices. #101,v,g,n,s,n,PM_L2_CO_FAIL_BUSY, L2 RC Cast Out dispatch attempt failed due to all CO machines busy ##6382 L2 RC Cast Out dispatch attempt failed due to all CO machines busy #102,v,g,n,s,n,PM_L2_GLOB_GUESS_CORRECT,L2 guess glb and guess was correct (ie data remote) ##6482 L2 guess glb and guess was correct (ie data remote) #103,v,g,n,n,n,PM_L2_LD,Data Load Count ##6080 Data Load Count #104,v,g,n,s,n,PM_L2_LDST,Data Load+Store Count ##6880 Data Load+Store Count #105,v,g,n,s,n,PM_L2_LOC_GUESS_CORRECT,L2 guess loc and guess was correct (ie data local) ##6480 L2 guess loc and guess was correct (ie data local) #106,v,g,n,s,n,PM_L2_RCLD_DISP, L2 RC load dispatch attempt ##6280 L2 RC load dispatch attempt #107,v,g,n,s,n,PM_L2_RCLD_DISP_FAIL_ADDR, L2 RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ ##6282 L2 RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ #108,v,g,n,n,n,PM_L2_ST,Data Store Count ##6082 Data Store Count #109,v,g,n,s,n,PM_L3_HIT,L3 Hits ##F080 L3 Hits #110,v,g,n,s,n,PM_L3_MISS,L3 Misses ##F082 L3 Misses #111,v,g,n,n,n,PM_L3_PREF_LD,L3 cache LD prefetches ##D0AC L3 cache LD prefetches #112,v,g,n,n,n,PM_L3_PREF_LDST,L3 cache prefetches LD + ST ##D8AC L3 cache prefetches LD + ST #113,v,g,n,n,n,PM_L3_PREF_ST,L3 cache ST prefetches ##D0AE L3 cache ST prefetches #114,v,g,n,n,n,PM_LARX_LSU,Larx Finished ##C894 Larx Finished #115,v,g,n,n,n,PM_LARX_LSU0,ls0 Larx Finished ##C094 A larx (lwarx or ldarx) was executed on side 0 #116,v,g,n,n,n,PM_LARX_LSU1,ls1 Larx Finished ##C096 A larx (lwarx or ldarx) was executed on side 1 #117,v,g,n,n,n,PM_LD_REF_L1, L1 D cache load references counted at finish ##C880 L1 D cache load references counted at finish #118,v,g,n,n,n,PM_LD_REF_L1_LSU0,LS0 L1 D cache load references counted at finish ##C080 Load references to Level 1 Data Cache, by unit 0. #119,v,g,n,n,n,PM_LD_REF_L1_LSU1,LS1 L1 D cache load references counted at finish ##C082 Load references to Level 1 Data Cache, by unit 1. #120,v,g,n,n,n,PM_LSU_DC_PREF_STREAM_ALLOC,D cache new prefetch stream allocated ##D8A8 D cache new prefetch stream allocated #121,v,g,n,n,n,PM_LSU_DC_PREF_STREAM_CONFIRM,Dcache new prefetch stream confirmed ##D8B4 Dcache new prefetch stream confirmed #122,v,g,n,n,n,PM_LSU_DC_PREF_STRIDED_STREAM_CONFIRM,Dcache Strided prefetch stream confirmed (software + hardware) ##D8BC Dcache Strided prefetch stream confirmed (software + hardware) #123,v,g,n,n,n,PM_LSU_DCACHE_RELOAD_VALID,count per sector of lines reloaded in L1 (demand + prefetch) ##D0A2 count per sector of lines reloaded in L1 (demand + prefetch) #124,v,g,n,n,n,PM_LSU_FLUSH,Flush initiated by LSU ##208E A flush was initiated by the Load Store Unit. #125,v,g,n,n,n,PM_LSU_FLUSH_LRQ,Flush: LRQ ##C8B8 Load Hit Load or Store Hit Load flush. A younger load was flushed because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. Combined Unit 0 + 1. #126,v,g,n,n,n,PM_LSU_FLUSH_SRQ,Flush: SRQ ##C8BC Load Hit Store flush. A younger load was flushed because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. Combined Unit 0 + 1. #127,v,g,n,n,n,PM_LSU_FLUSH_ULD,Flush: Unaligned Load ##C8B0 A load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1). Combined Unit 0 + 1. #128,v,g,n,n,n,PM_LSU_FLUSH_UST,Flush: Unaligned Store ##C8B4 A store was flushed because it was unaligned (crossed a 4K boundary). Combined Unit 0 + 1. #129,v,g,n,n,n,PM_LSU_FX_FIN,LSU Finished a FX operation (up to 2 per cycle) ##0066 LSU Finished a FX operation (up to 2 per cycle) #130,v,g,n,n,n,PM_LSU_LDF,All Scalar Loads ##C884 LSU executed Floating Point load instruction. Combined Unit 0 + 1. #131,v,g,n,n,n,PM_LSU_LDX,All Vector loads (vsx vector + vmx vector) ##C888 All Vector loads (vsx vector + vmx vector) #132,v,g,n,n,n,PM_LSU_LMQ_FULL_CYC,LMQ full ##D0A4 The Load Miss Queue was full. #133,v,g,n,n,n,PM_LSU_LMQ_S0_ALLOC,Slot 0 of LMQ valid ##D0A1 Slot 0 of LMQ valid #134,v,g,n,n,n,PM_LSU_LMQ_S0_VALID,Slot 0 of LMQ valid ##D0A0 This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the LRQ is split between the two threads (16 entries each). #135,v,g,n,n,n,PM_LSU_LRQ_S0_ALLOC,Slot 0 of LRQ valid ##D09F Slot 0 of LRQ valid #136,v,g,n,n,n,PM_LSU_LRQ_S0_VALID,Slot 0 of LRQ valid ##D09E This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the LRQ is split between the two threads (16 entries each). #137,v,g,n,n,n,PM_LSU_NCLD,Non-cachable Loads counted at finish ##C88C A non-cacheable load was executed. Combined Unit 0 + 1. #138,v,g,n,n,n,PM_LSU_NCST,Non-cachable Stores sent to nest ##C090 Non-cachable Stores sent to nest #139,v,g,n,n,n,PM_LSU_PARTIAL_CDF,A partial cacheline was returned from the L3 ##C0AA A partial cacheline was returned from the L3 #140,v,g,n,n,n,PM_LSU_REJECT,LSU Reject (up to 2 per cycle) ##0064 The Load Store Unit rejected an instruction. Combined Unit 0 + 1 #141,v,g,n,n,n,PM_LSU_REJECT_LHS,Reject: Load Hit Store ##C8AC The Load Store Unit rejected a load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully. Combined Unit 0 + 1 #142,v,g,n,n,n,PM_LSU_REJECT_LMQ_FULL,Reject: LMQ Full (LHR) ##C8A4 Total cycles the Load Store Unit is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all the eight entries are full, subsequent load instructions are rejected. Combined unit 0 + 1. #143,v,g,n,n,n,PM_LSU_REJECT_SET_MPRED,Reject: Set Predict Wrong ##C8A8 The Load Store Unit rejected an instruction because the cache set was improperly predicted. This is a fast reject and will be immediately redispatched. Combined Unit 0 + 1 #144,v,g,n,n,n,PM_LSU_SET_MPRED,Line already in cache at reload time ##C0A8 Line already in cache at reload time #145,v,g,n,n,n,PM_LSU_SRQ_FULL_CYC,Storage Queue is full and is blocking dispatch ##001A Cycles the Store Request Queue is full. #146,v,g,n,n,n,PM_LSU_SRQ_S0_ALLOC,Slot 0 of SRQ valid ##D09D Slot 0 of SRQ valid #147,v,g,n,n,n,PM_LSU_SRQ_S0_VALID,Slot 0 of SRQ valid ##D09C This signal is asserted every cycle that the Store Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the SRQ is split between the two threads (16 entries each). #148,v,g,n,n,n,PM_LSU_SRQ_STFWD,Load got data from a store ##C8A0 Data from a store instruction was forwarded to a load. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss. Combined Unit 0 + 1. #149,v,g,n,n,n,PM_LSU_SRQ_SYNC_COUNT,SRQ sync count (edge of PM_LSU_SRQ_SYNC_CYC) ##D097 SRQ sync count (edge of PM_LSU_SRQ_SYNC_CYC) #150,v,g,n,n,n,PM_LSU_SRQ_SYNC_CYC,A sync is in the SRQ ##D096 Cycles that a sync instruction is active in the Store Request Queue. #151,v,g,n,n,n,PM_LSU_TWO_TABLEWALK_CYC,Cycles when two tablewalks pending on this thread ##D0A6 Cycles when two tablewalks pending on this thread #152,v,g,n,n,n,PM_LSU0_DC_PREF_STREAM_ALLOC,LS0 D cache new prefetch stream allocated ##D0A8 LS0 D cache new prefetch stream allocated #153,v,g,n,n,n,PM_LSU0_DC_PREF_STREAM_CONFIRM,LS0 Dcache prefetch stream confirmed ##D0B4 LS0 Dcache prefetch stream confirmed #154,v,g,n,n,n,PM_LSU0_DC_PREF_STREAM_CONFIRM_STRIDE,LS0 Dcache Strided prefetch stream confirmed ##D0BC LS0 Dcache Strided prefetch stream confirmed #155,v,g,n,n,n,PM_LSU0_FLUSH_LRQ,LS0 Flush: LRQ ##C0B8 Load Hit Load or Store Hit Load flush. A younger load was flushed from unit 0 because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. #156,v,g,n,n,n,PM_LSU0_FLUSH_SRQ,LS0 Flush: SRQ ##C0BC Load Hit Store flush. A younger load was flushed from unit 0 because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. #157,v,g,n,n,n,PM_LSU0_FLUSH_ULD,LS0 Flush: Unaligned Load ##C0B0 A load was flushed from unit 0 because it was unaligned (crossed a 64 byte boundary, or 32 byte if it missed the L1) #158,v,g,n,n,n,PM_LSU0_FLUSH_UST,LS0 Flush: Unaligned Store ##C0B4 A store was flushed from unit 0 because it was unaligned (crossed a 4K boundary). #159,v,g,n,n,n,PM_LSU0_L1_PREF, LS0 L1 cache data prefetches ##D0B8 LS0 L1 cache data prefetches #160,v,g,n,n,n,PM_LSU0_L1_SW_PREF,LSU0 Software L1 Prefetches, including SW Transient Prefetches ##C09C LSU0 Software L1 Prefetches, including SW Transient Prefetches #161,v,g,n,n,n,PM_LSU0_LDF,LS0 Scalar Loads ##C084 A floating point load was executed by LSU0 #162,v,g,n,n,n,PM_LSU0_LDX,LS0 Vector Loads ##C088 LS0 Vector Loads #163,v,g,n,n,n,PM_LSU0_LMQ_LHR_MERGE,LS0 Load Merged with another cacheline request ##D098 LS0 Load Merged with another cacheline request #164,v,g,n,n,n,PM_LSU0_NCLD,LS0 Non-cachable Loads counted at finish ##C08C A non-cacheable load was executed by unit 0. #165,v,g,n,n,n,PM_LSU0_REJECT_LHS,LS0 Reject: Load Hit Store ##C0AC Load Store Unit 0 rejected a load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully. #166,v,g,n,n,n,PM_LSU0_REJECT_LMQ_FULL,LS0 Reject: LMQ Full (LHR) ##C0A4 Total cycles the Load Store Unit 0 is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all eight entries are full, subsequent load instructions are rejected. #167,v,g,n,n,n,PM_LSU0_SRQ_STFWD,LS0 SRQ forwarded data to a load ##C0A0 Data from a store instruction was forwarded to a load on unit 0. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss. #168,v,g,n,n,n,PM_LSU1_DC_PREF_STREAM_ALLOC,LS 1 D cache new prefetch stream allocated ##D0AA LS 1 D cache new prefetch stream allocated #169,v,g,n,n,n,PM_LSU1_DC_PREF_STREAM_CONFIRM,LS1 'Dcache prefetch stream confirmed ##D0B6 LS1 'Dcache prefetch stream confirmed #170,v,g,n,n,n,PM_LSU1_DC_PREF_STREAM_CONFIRM_STRIDE,LS1 Dcache Strided prefetch stream confirmed ##D0BE LS1 Dcache Strided prefetch stream confirmed #171,v,g,n,n,n,PM_LSU1_FLUSH_LRQ,LS1 Flush: LRQ ##C0BA Load Hit Load or Store Hit Load flush. A younger load was flushed from unit 1 because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. #172,v,g,n,n,n,PM_LSU1_FLUSH_SRQ,LS1 Flush: SRQ ##C0BE Load Hit Store flush. A younger load was flushed from unit 1 because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. #173,v,g,n,n,n,PM_LSU1_FLUSH_ULD,LS 1 Flush: Unaligned Load ##C0B2 A load was flushed from unit 1 because it was unaligned (crossed a 64 byte boundary, or 32 byte if it missed the L1). #174,v,g,n,n,n,PM_LSU1_FLUSH_UST,LS1 Flush: Unaligned Store ##C0B6 A store was flushed from unit 1 because it was unaligned (crossed a 4K boundary) #175,v,g,n,n,n,PM_LSU1_L1_PREF, LS1 L1 cache data prefetches ##D0BA LS1 L1 cache data prefetches #176,v,g,n,n,n,PM_LSU1_L1_SW_PREF,LSU1 Software L1 Prefetches, including SW Transient Prefetches ##C09E LSU1 Software L1 Prefetches, including SW Transient Prefetches #177,v,g,n,n,n,PM_LSU1_LDF,LS1 Scalar Loads ##C086 A floating point load was executed by LSU1 #178,v,g,n,n,n,PM_LSU1_LDX,LS1 Vector Loads ##C08A LS1 Vector Loads #179,v,g,n,n,n,PM_LSU1_LMQ_LHR_MERGE,LS1 Load Merge with another cacheline request ##D09A LS1 Load Merge with another cacheline request #180,v,g,n,n,n,PM_LSU1_NCLD,LS1 Non-cachable Loads counted at finish ##C08E A non-cacheable load was executed by Unit 0. #181,v,g,n,n,n,PM_LSU1_REJECT_LHS,LS1 Reject: Load Hit Store ##C0AE Load Store Unit 1 rejected a load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully. #182,v,g,n,n,n,PM_LSU1_REJECT_LMQ_FULL,LS1 Reject: LMQ Full (LHR) ##C0A6 Total cycles the Load Store Unit 1 is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all eight entries are full, subsequent load instructions are rejected. #183,v,g,n,n,n,PM_LSU1_SRQ_STFWD,LS1 SRQ forwarded data to a load ##C0A2 Data from a store instruction was forwarded to a load on unit 1. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss. #184,v,g,n,n,n,PM_LWSYNC,lwsync count (easier to use than IMC) ##D094 lwsync count (easier to use than IMC) #185,v,g,n,n,n,PM_LWSYNC_HELD,LWSYNC held at dispatch ##209A Cycles a LWSYNC instruction was held at dispatch. LWSYNC instructions are held at dispatch until all previous loads are done and all previous stores have issued. LWSYNC enters the Store Request Queue and is sent to the storage subsystem but does not wait for a response. #186,v,g,n,n,m,PM_MRK_BR_TAKEN,Marked Branch Taken ##0036 A marked branch was taken #187,v,g,n,n,m,PM_MRK_DATA_FROM_DMEM,Marked data loaded from distant memory ##D04A The processor's Data Cache was reloaded with data from memory attached to a distant module due to a marked load. #188,v,g,n,n,m,PM_MRK_DATA_FROM_L2,Marked data loaded from L2 ##D040 The processor's Data Cache was reloaded from the local L2 due to a marked load. #189,v,g,n,n,m,PM_MRK_DATA_FROM_L3,Marked data loaded from L3 ##D048 The processor's Data Cache was reloaded from the local L3 due to a marked load. #190,v,g,n,n,m,PM_MRK_DATA_FROM_L31_MOD,Marked data loaded from another L3 on same chip modified ##D044 Marked data loaded from another L3 on same chip modified #191,v,g,n,n,m,PM_MRK_DATA_FROM_L31_SHR,Marked data loaded from another L3 on same chip shared ##D04E Marked data loaded from another L3 on same chip shared #192,v,g,n,n,m,PM_MRK_DATA_FROM_RL2L3_MOD,Marked data loaded from remote L2 or L3 modified ##D042 The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a remote module due to a marked load. #193,v,g,n,n,m,PM_MRK_DATA_FROM_RL2L3_SHR,Marked data loaded from remote L2 or L3 shared ##D04C The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a remote module due to a marked load #194,v,g,n,n,m,PM_MRK_DERAT_MISS_4K,Marked DERAT misses for 4K page ##D05C A marked data request (load or store) missed the ERAT for 4K page and resulted in an ERAT reload. #195,v,g,n,n,m,PM_MRK_DTLB_MISS_16G,Marked Data TLB misses for 16G page ##D05E Data TLB references to 16GB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time. #196,v,g,n,n,m,PM_MRK_FIN_STALL_CYC,Marked instruction Finish Stall cycles (marked finish after NTC) ##003C Marked instruction Finish Stall cycles (marked finish after NTC) #197,v,g,n,n,m,PM_MRK_FIN_STALL_CYC_COUNT,Marked instruction Finish Stall cycles (marked finish after NTC) (use edge detect to count #) ##003D Marked instruction Finish Stall cycles (marked finish after NTC) (use edge detect to count #) #198,v,g,n,n,m,PM_MRK_INST_ISSUED,Marked instruction issued ##0032 A marked instruction was issued to an execution unit. #199,v,g,n,n,m,PM_MRK_LD_MISS_EXPOSED_CYC,Marked Load exposed Miss ##003E Marked Load exposed Miss #200,v,g,n,n,m,PM_MRK_LD_MISS_EXPOSED_CYC_COUNT,Marked Load exposed Miss (use edge detect to count #) ##003F Marked Load exposed Miss (use edge detect to count #) #201,v,g,n,n,m,PM_MRK_LSU_FLUSH,Flush: (marked) : All Cases ##D08C Marked flush initiated by LSU #202,v,g,n,n,m,PM_MRK_LSU_FLUSH_LRQ,Flush: (marked) LRQ ##D088 Load Hit Load or Store Hit Load flush. A marked load was flushed because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. #203,v,g,n,n,m,PM_MRK_LSU_FLUSH_SRQ,Flush: (marked) SRQ ##D08A Load Hit Store flush. A marked load was flushed because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. #204,v,g,n,n,m,PM_MRK_LSU_FLUSH_ULD,Flush: (marked) Unaligned Load ##D084 A marked load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1) #205,v,g,n,n,m,PM_MRK_LSU_FLUSH_UST,Flush: (marked) Unaligned Store ##D086 A marked store was flushed because it was unaligned #206,v,g,n,n,m,PM_MRK_LSU_PARTIAL_CDF,A partial cacheline was returned from the L3 for a marked load ##D080 A partial cacheline was returned from the L3 for a marked load #207,v,g,n,n,m,PM_MRK_LSU_REJECT_LHS, Reject(marked): Load Hit Store ##D082 The Load Store Unit rejected a marked load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully #208,v,g,n,n,m,PM_MRK_PTEG_FROM_L2,Marked PTEG loaded from L2 ##D050 A Page Table Entry was loaded into the ERAT from the local L2 due to a marked load or store. #209,v,g,n,n,m,PM_MRK_PTEG_FROM_L31_MOD,Marked PTEG loaded from another L3 on same chip modified ##D054 Marked PTEG loaded from another L3 on same chip modified #210,v,g,n,n,m,PM_MRK_PTEG_FROM_RL2L3_MOD,Marked PTEG loaded from remote L2 or L3 modified ##D052 A Page Table Entry was loaded into the ERAT with shared (T or SL) data from an L2 or L3 on a remote module due to a marked load or store. #211,v,g,n,n,m,PM_MRK_ST_CMPL,marked store finished (was complete) ##0034 A sampled store has completed (data home) #212,v,g,n,n,m,PM_MRK_STCX_FAIL,Marked STCX failed ##D08E A marked stcx (stwcx or stdcx) failed #213,v,g,n,c,n,PM_PB_NODE_PUMP, Nest events (MC0/MC1/PB/GX), Pair0 Bit0 ##0081 Nest events (MC0/MC1/PB/GX), Pair0 Bit0 #214,v,g,n,c,n,PM_MEM0_RQ_DISP, Nest events (MC0/MC1/PB/GX), Pair0 Bit1 ##0083 Nest events (MC0/MC1/PB/GX), Pair0 Bit1 #215,v,g,n,c,n,PM_NEST_PAIR0_ADD, Nest events (MC0/MC1/PB/GX), Pair0 ADD ##0881 Nest events (MC0/MC1/PB/GX), Pair0 ADD #216,v,g,n,c,n,PM_NEST_PAIR0_AND, Nest events (MC0/MC1/PB/GX), Pair0 AND ##0883 Nest events (MC0/MC1/PB/GX), Pair0 AND #217,v,g,n,n,n,PM_PMC2_SAVED,PMC2 Rewind Value saved ##0022 PMC2 was counting speculatively. The speculative condition was met and the counter value was committed by copying it to the backup register. #218,v,g,n,n,n,PM_PMC4_OVERFLOW,Overflow from counter 4 ##0010 Overflows from PMC4 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow. #219,v,g,n,n,n,PM_PMC4_REWIND,PMC4 Rewind Event ##0020 PMC4 was counting speculatively. The speculative condition was not met and the counter was restored to its previous value. #220,v,g,n,n,n,PM_PMC5_OVERFLOW,Overflow from counter 5 ##0024 Overflows from PMC5 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow. #221,v,g,n,n,n,PM_POWER_EVENT1,Power Management Event 1 ##006E Power Management Event 1 #222,v,g,n,n,n,PM_PTEG_FROM_L2,PTEG loaded from L2 ##C050 A Page Table Entry was loaded into the ERAT from the local L2 due to a demand load or store. #223,v,g,n,n,n,PM_PTEG_FROM_L31_MOD,PTEG loaded from another L3 on same chip modified ##C054 PTEG loaded from another L3 on same chip modified #224,v,g,n,n,n,PM_PTEG_FROM_RL2L3_MOD,PTEG loaded from remote L2 or L3 modified ##C052 A Page Table Entry was loaded into the ERAT with modified (M) data from an L2 or L3 on a remote module due to a demand load or store. #225,v,g,n,c,n,PM_RUN_SPURR,Run SPURR ##0008 Run SPURR #226,v,g,n,n,n,PM_SEG_EXCEPTION,ISEG + DSEG Exception ##28A4 ISEG + DSEG Exception #227,v,g,n,n,n,PM_SHL_CREATED,SHL table entry Created ##5082 SHL table entry Created #228,v,g,n,n,n,PM_SHL_DEALLOCATED,SHL Table entry deallocated ##5080 SHL Table entry deallocated #229,v,g,n,n,n,PM_SHL_MATCH,SHL Table Match ##5086 SHL Table Match #230,v,g,n,n,n,PM_SHL_MERGED,SHL table entry merged with existing ##5084 SHL table entry merged with existing #231,v,g,n,n,n,PM_SLB_MISS,Data + Instruction SLB Miss - Total of all segment sizes ##D890 Total of all Segment Lookaside Buffer (SLB) misses, Instructions + Data. #232,v,g,n,c,n,PM_SNOOP_TLBIE,TLBIE snoop ##D0B2 A tlbie was snooped from another processor. #233,v,g,n,n,n,PM_STCX_CMPL,STCX executed ##C098 Conditional stores with reservation completed #234,v,g,n,n,n,PM_STCX_FAIL,STCX failed ##C09A A stcx (stwcx or stdcx) failed #235,v,g,n,n,n,PM_SUSPENDED,Counter OFF ##0000 The counter is suspended (does not count) #236,v,g,n,n,n,PM_TABLEWALK_CYC,Cycles when a tablewalk (I or D) is active ##0026 Cycles doing instruction or data tablewalks #237,v,g,n,c,n,PM_THERMAL_WARN,Processor in Thermal Warning ##0016 Processor in Thermal Warning #238,v,g,n,c,n,PM_THRD_1_RUN_CYC,1 thread in Run Cycles ##0060 At least one thread has set its run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. This event does not respect FCWAIT. #239,v,g,n,c,n,PM_THRD_3_CONC_RUN_INST,3 thread Concurrent Run Instructions ##0062 3 thread Concurrent Run Instructions #240,v,g,n,c,n,PM_THRD_GRP_CMPL_BOTH_CYC,Cycles group completed by both threads ##0012 Cycles that both threads completed. #241,v,g,n,n,n,PM_THRD_PRIO_0_1_CYC, Cycles thread running at priority level 0 or 1 ##40B0 Cycles thread running at priority level 0 or 1 #242,v,g,n,n,n,PM_THRD_PRIO_2_3_CYC, Cycles thread running at priority level 2 or 3 ##40B2 Cycles thread running at priority level 2 or 3 #243,v,g,n,n,n,PM_THRD_PRIO_4_5_CYC, Cycles thread running at priority level 4 or 5 ##40B4 Cycles thread running at priority level 4 or 5 #244,v,g,n,n,n,PM_THRD_PRIO_6_7_CYC, Cycles thread running at priority level 6 or 7 ##40B6 Cycles thread running at priority level 6 or 7 #245,v,g,n,n,n,PM_THRESH_TIMEO,Threshold timeout event ##0038 The threshold timer expired #246,v,g,n,n,n,PM_VMX_RESULT_SAT_1,Valid result with sat=1 ##B0A0 Valid result with sat=1 #247,v,g,n,n,n,PM_VSU_1FLOP,one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished ##A880 one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished #248,v,g,n,n,n,PM_VSU_2FLOP,two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) ##A898 two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) #249,v,g,n,n,n,PM_VSU_2FLOP_DOUBLE,DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg ##A88C DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg #250,v,g,n,n,n,PM_VSU_4FLOP,four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions) ##A89C four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions) #251,v,g,n,n,n,PM_VSU_8FLOP,eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) ##A8A0 eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) #252,v,g,n,n,n,PM_VSU_DENORM,Vector or Scalar denorm operand ##A8AC Vector or Scalar denorm operand #253,v,g,n,n,n,PM_VSU_FCONV,Convert instruction executed ##A8B0 Convert instruction executed #254,v,g,n,n,n,PM_VSU_FEST,Estimate instruction executed ##A8B8 Estimate instruction executed #255,v,g,n,n,n,PM_VSU_FIN,VSU0 Finished an instruction ##A8BC VSU0 Finished an instruction #256,v,g,n,n,n,PM_VSU_FMA,two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only! ##A884 two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only! #257,v,g,n,n,n,PM_VSU_FMA_DOUBLE,DP vector version of fmadd,fnmadd,fmsub,fnmsub ##A890 DP vector version of fmadd,fnmadd,fmsub,fnmsub #258,v,g,n,n,n,PM_VSU_FRSP,Round to single precision instruction executed ##A8B4 Round to single precision instruction executed #259,v,g,n,n,n,PM_VSU_FSQRT_FDIV,four flops operation (fdiv,fsqrt) Scalar Instructions only! ##A888 DP vector versions of fdiv,fsqrt #260,v,g,n,n,n,PM_VSU_FSQRT_FDIV_DOUBLE,DP vector versions of fdiv,fsqrt ##A894 DP vector versions of fdiv,fsqrt #261,v,g,n,n,n,PM_VSU_SCALAR_DOUBLE_ISSUED,Double Precision scalar instruction issued on Pipe0 ##B888 Double Precision scalar instruction issued on Pipe0 #262,v,g,n,n,n,PM_VSU_SCALAR_SINGLE_ISSUED,Single Precision scalar instruction issued on Pipe0 ##B884 Single Precision scalar instruction issued on Pipe0 #263,v,g,n,n,n,PM_VSU_SIMPLE_ISSUED,Simple VMX instruction issued ##B894 Simple VMX instruction issued #264,v,g,n,n,n,PM_VSU_SINGLE,Vector or Scalar single precision ##A8A8 Vector or Scalar single precision #265,v,g,n,n,n,PM_VSU_STF,FPU store (SP or DP) issued on Pipe0 ##B88C FPU store (SP or DP) issued on Pipe0 #266,v,g,n,n,n,PM_VSU_VECTOR_DOUBLE_ISSUED,Double Precision vector instruction issued on Pipe0 ##B880 Double Precision vector instruction issued on Pipe0 #267,v,g,n,n,n,PM_VSU_VECTOR_SINGLE_ISSUED,Single Precision vector instruction issued (executed) ##B890 Single Precision vector instruction issued (executed) #268,v,g,n,n,n,PM_VSU0_16FLOP,Sixteen flops operation (SP vector versions of fdiv,fsqrt) ##A0A4 Sixteen flops operation (SP vector versions of fdiv,fsqrt) #269,v,g,n,n,n,PM_VSU0_1FLOP,one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg, xsadd, xsmul, xssub, xscmp, xssel, xsabs, xsnabs, xsre, xssqrte, xsneg) operation finished ##A080 one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg, xsadd, xsmul, xssub, xscmp, xssel, xsabs, xsnabs, xsre, xssqrte, xsneg) operation finished #270,v,g,n,n,n,PM_VSU0_2FLOP,two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) ##A098 two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) #271,v,g,n,n,n,PM_VSU0_2FLOP_DOUBLE,two flop DP vector operation (xvadddp, xvmuldp, xvsubdp, xvcmpdp, xvseldp, xvabsdp, xvnabsdp, xvredp ,xvsqrtedp, vxnegdp) ##A08C two flop DP vector operation (xvadddp, xvmuldp, xvsubdp, xvcmpdp, xvseldp, xvabsdp, xvnabsdp, xvredp ,xvsqrtedp, vxnegdp) #272,v,g,n,n,n,PM_VSU0_4FLOP,four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions) ##A09C four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions) #273,v,g,n,n,n,PM_VSU0_8FLOP,eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) ##A0A0 eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) #274,v,g,n,n,n,PM_VSU0_COMPLEX_ISSUED,Complex VMX instruction issued ##B096 Complex VMX instruction issued #275,v,g,n,n,n,PM_VSU0_DENORM,FPU denorm operand ##A0AC VSU0 received denormalized data #276,v,g,n,n,n,PM_VSU0_FCONV,Convert instruction executed ##A0B0 Convert instruction executed #277,v,g,n,n,n,PM_VSU0_FEST,Estimate instruction executed ##A0B8 Estimate instruction executed #278,v,g,n,n,n,PM_VSU0_FIN,VSU0 Finished an instruction ##A0BC VSU0 Finished an instruction #279,v,g,n,n,n,PM_VSU0_FMA,two flops operation (fmadd, fnmadd, fmsub, fnmsub, xsmadd, xsnmadd, xsmsub, xsnmsub) Scalar instructions only! ##A084 two flops operation (fmadd, fnmadd, fmsub, fnmsub, xsmadd, xsnmadd, xsmsub, xsnmsub) Scalar instructions only! #280,v,g,n,n,n,PM_VSU0_FMA_DOUBLE,four flop DP vector operations (xvmadddp, xvnmadddp, xvmsubdp, xvmsubdp) ##A090 four flop DP vector operations (xvmadddp, xvnmadddp, xvmsubdp, xvmsubdp) #281,v,g,n,n,n,PM_VSU0_FPSCR,Move to/from FPSCR type instruction issued on Pipe 0 ##B09C Move to/from FPSCR type instruction issued on Pipe 0 #282,v,g,n,n,n,PM_VSU0_FRSP,Round to single precision instruction executed ##A0B4 Round to single precision instruction executed #283,v,g,n,n,n,PM_VSU0_FSQRT_FDIV,four flops operation (fdiv,fsqrt,xsdiv,xssqrt) Scalar Instructions only! ##A088 four flops operation (fdiv,fsqrt,xsdiv,xssqrt) Scalar Instructions only! #284,v,g,n,n,n,PM_VSU0_FSQRT_FDIV_DOUBLE,eight flop DP vector operations (xvfdivdp, xvsqrtdp ##A094 eight flop DP vector operations (xvfdivdp, xvsqrtdp #285,v,g,n,n,n,PM_VSU0_SCAL_DOUBLE_ISSUED,Double Precision scalar instruction issued on Pipe0 ##B088 Double Precision scalar instruction issued on Pipe0 #286,v,g,n,n,n,PM_VSU0_SCAL_SINGLE_ISSUED,Single Precision scalar instruction issued on Pipe0 ##B084 Single Precision scalar instruction issued on Pipe0 #287,v,g,n,n,n,PM_VSU0_SIMPLE_ISSUED,Simple VMX instruction issued ##B094 Simple VMX instruction issued #288,v,g,n,n,n,PM_VSU0_SINGLE,FPU single precision ##A0A8 VSU0 executed single precision instruction #289,v,g,n,n,n,PM_VSU0_STF,FPU store (SP or DP) issued on Pipe0 ##B08C FPU store (SP or DP) issued on Pipe0 #290,v,g,n,n,n,PM_VSU0_VECT_DOUBLE_ISSUED,Double Precision vector instruction issued on Pipe0 ##B080 Double Precision vector instruction issued on Pipe0 #291,v,g,n,n,n,PM_VSU0_VECTOR_SP_ISSUED,Single Precision vector instruction issued (executed) ##B090 Single Precision vector instruction issued (executed) #292,v,g,n,n,n,PM_VSU1_1FLOP,one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg, xsadd, xsmul, xssub, xscmp, xssel, xsabs, xsnabs, xsre, xssqrte, xsneg) operation finished ##A082 one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg, xsadd, xsmul, xssub, xscmp, xssel, xsabs, xsnabs, xsre, xssqrte, xsneg) operation finished #293,v,g,n,n,n,PM_VSU1_2FLOP,two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) ##A09A two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) #294,v,g,n,n,n,PM_VSU1_2FLOP_DOUBLE,two flop DP vector operation (xvadddp, xvmuldp, xvsubdp, xvcmpdp, xvseldp, xvabsdp, xvnabsdp, xvredp ,xvsqrtedp, vxnegdp) ##A08E two flop DP vector operation (xvadddp, xvmuldp, xvsubdp, xvcmpdp, xvseldp, xvabsdp, xvnabsdp, xvredp ,xvsqrtedp, vxnegdp) #295,v,g,n,n,n,PM_VSU1_4FLOP,four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions) ##A09E four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions) #296,v,g,n,n,n,PM_VSU1_8FLOP,eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) ##A0A2 eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) #297,v,g,n,n,n,PM_VSU1_DD_ISSUED,64BIT Decimal Issued on Pipe1 ##B098 64BIT Decimal Issued on Pipe1 #298,v,g,n,n,n,PM_VSU1_DENORM,FPU denorm operand ##A0AE VSU1 received denormalized data #299,v,g,n,n,n,PM_VSU1_DQ_ISSUED,128BIT Decimal Issued on Pipe1 ##B09A 128BIT Decimal Issued on Pipe1 #300,v,g,n,n,n,PM_VSU1_FCONV,Convert instruction executed ##A0B2 Convert instruction executed #301,v,g,n,n,n,PM_VSU1_FEST,Estimate instruction executed ##A0BA Estimate instruction executed #302,v,g,n,n,n,PM_VSU1_FIN,VSU1 Finished an instruction ##A0BE VSU1 Finished an instruction #303,v,g,n,n,n,PM_VSU1_FMA,two flops operation (fmadd, fnmadd, fmsub, fnmsub, xsmadd, xsnmadd, xsmsub, xsnmsub) Scalar instructions only! ##A086 two flops operation (fmadd, fnmadd, fmsub, fnmsub, xsmadd, xsnmadd, xsmsub, xsnmsub) Scalar instructions only! #304,v,g,n,n,n,PM_VSU1_FMA_DOUBLE,four flop DP vector operations (xvmadddp, xvnmadddp, xvmsubdp, xvmsubdp) ##A092 four flop DP vector operations (xvmadddp, xvnmadddp, xvmsubdp, xvmsubdp) #305,v,g,n,n,n,PM_VSU1_FRSP,Round to single precision instruction executed ##A0B6 Round to single precision instruction executed #306,v,g,n,n,n,PM_VSU1_FSQRT_FDIV,four flops operation (fdiv,fsqrt,xsdiv,xssqrt) Scalar Instructions only! ##A08A four flops operation (fdiv,fsqrt,xsdiv,xssqrt) Scalar Instructions only! #307,v,g,n,n,n,PM_VSU1_FSQRT_FDIV_DOUBLE,eight flop DP vector operations (xvfdivdp, xvsqrtdp ##A096 eight flop DP vector operations (xvfdivdp, xvsqrtdp #308,v,g,n,n,n,PM_VSU1_PERMUTE_ISSUED,Permute VMX Instruction Issued ##B092 Permute VMX Instruction Issued #309,v,g,n,n,n,PM_VSU1_SCAL_DOUBLE_ISSUED,Double Precision scalar instruction issued on Pipe1 ##B08A Double Precision scalar instruction issued on Pipe1 #310,v,g,n,n,n,PM_VSU1_SCAL_SINGLE_ISSUED,Single Precision scalar instruction issued on Pipe1 ##B086 Single Precision scalar instruction issued on Pipe1 #311,v,g,n,n,n,PM_VSU1_SINGLE,FPU single precision ##A0AA VSU1 executed single precision instruction #312,v,g,n,n,n,PM_VSU1_SQ,Store Vector Issued on Pipe1 ##B09E Store Vector Issued on Pipe1 #313,v,g,n,n,n,PM_VSU1_STF,FPU store (SP or DP) issued on Pipe1 ##B08E FPU store (SP or DP) issued on Pipe1 #314,v,g,n,n,n,PM_VSU1_VECT_DOUBLE_ISSUED,Double Precision vector instruction issued on Pipe1 ##B082 Double Precision vector instruction issued on Pipe1 $$$$$$$$ { counter 2 } #0,v,g,n,n,n,PM_BC_PLUS_8_CONV,BC+8 Converted ##40B8 BC+8 Converted #1,v,g,n,n,n,PM_BC_PLUS_8_RSLV_TAKEN,BC+8 Resolve outcome was Taken, resulting in the conditional instruction being canceled ##40BA BC+8 Resolve outcome was Taken, resulting in the conditional instruction being canceled #2,v,g,n,n,n,PM_BR_MPRED_CCACHE,Branch Mispredict due to Count Cache prediction ##40A4 A branch instruction target was incorrectly predicted by the count cache. This will result in a branch redirect flush if not overwritten by a flush of an older instruction. #3,v,g,n,n,n,PM_BR_MPRED_CR,Branch mispredict - taken/not taken ##40AC A conditional branch instruction was incorrectly predicted as taken or not taken. The branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This will result in a branch redirect flush if not overfidden by a flush of an older instruction. #4,v,g,n,n,n,PM_BR_MPRED_CR_TA,Branch mispredict - taken/not taken and target ##48AE Branch mispredict - taken/not taken and target #5,v,g,n,n,n,PM_BR_MPRED_LSTACK,Branch Mispredict due to Link Stack ##40A6 Branch Mispredict due to Link Stack #6,v,g,n,n,n,PM_BR_MPRED_TA,Branch mispredict - target address ##40AE A branch instruction target was incorrectly predicted. This will result in a branch mispredict flush unless a flush is detected from an older instruction. #7,v,g,n,n,n,PM_BR_PRED,Branch Predictions made ##409C A branch prediction was made. This could have been a target prediction, a condition prediction, or both #8,v,g,n,n,n,PM_BR_PRED_CCACHE,Count Cache Predictions ##40A0 The count value of a Branch and Count instruction was predicted #9,v,g,n,n,n,PM_BR_PRED_CR,Branch predict - taken/not taken ##40A8 A conditional branch instruction was predicted as taken or not taken. #10,v,g,n,n,n,PM_BR_PRED_CR_TA,Branch predict - taken/not taken and target ##48AA Both the condition (taken or not taken) and the target address of a branch instruction was predicted. #11,v,g,n,n,n,PM_BR_PRED_LSTACK,Link Stack Predictions ##40A2 The target address of a Branch to Link instruction was predicted by the link stack. #12,v,g,n,n,n,PM_BR_PRED_TA,Branch predict - target address ##40AA The target address of a branch instruction was predicted. #13,v,g,n,n,n,PM_BR_TAKEN,Branch Taken ##0004 A branch instruction was taken. This could have been a conditional branch or an unconditional branch #14,v,g,n,n,n,PM_BR_UNCOND,Unconditional Branch ##409E An unconditional branch was executed. #15,v,g,n,n,n,PM_BTAC_HIT,BTAC Correct Prediction ##508A BTAC Correct Prediction #16,v,g,n,n,n,PM_BTAC_MISS,BTAC Mispredicted ##5088 BTAC Mispredicted #17,v,g,n,n,n,PM_CMPLU_STALL_DCACHE_MISS,Completion stall caused by D cache miss ##0016 Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered a Data Cache Miss. Data Cache Miss has higher priority than any other Load/Store delay, so if an instruction encounters multiple delays only the Data Cache Miss will be reported and the entire delay period will be charged to Data Cache Miss. This is a subset of PM_CMPLU_STALL_LSU. #18,v,g,n,n,n,PM_CMPLU_STALL_DFU,Completion stall caused by Decimal Floating Point Unit ##003C Completion stall caused by Decimal Floating Point Unit #19,v,g,n,n,n,PM_CMPLU_STALL_FXU,Completion stall caused by FXU instruction ##0014 Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a fixed point instruction. #20,v,g,n,n,n,PM_CMPLU_STALL_LSU,Completion stall caused by LSU instruction ##0012 Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a load/store instruction. #21,v,g,n,n,n,PM_CMPLU_STALL_SCALAR_LONG,Completion stall caused by long latency scalar instruction ##0018 Completion stall caused by long latency scalar instruction #22,v,g,n,n,n,PM_CMPLU_STALL_STORE,Completion stall due to store instruction ##004A Completion stall due to store instruction #23,v,g,n,n,n,PM_CMPLU_STALL_VECTOR,Completion stall caused by Vector instruction ##001C Completion stall caused by Vector instruction #24,v,g,n,s,n,PM_CYC,Cycles ##001E Processor Cycles #25,v,g,n,n,n,PM_DATA_FROM_DMEM,Data loaded from distant memory ##C042 The processor's Data Cache was reloaded with data from memory attached to a distant module due to a demand load #26,v,g,n,n,n,PM_DATA_FROM_L2MISS,Demand LD - L2 Miss (not L2 hit) ##00FE The processor's Data Cache was reloaded but not from the local L2. #27,v,g,n,n,n,PM_DATA_FROM_L3,Data loaded from L3 ##C040 The processor's Data Cache was reloaded from the local L3 due to a demand load. #28,v,g,n,n,n,PM_DATA_FROM_L31_SHR,Data loaded from another L3 on same chip shared ##C046 Data loaded from another L3 on same chip shared #29,v,g,n,n,n,PM_DATA_FROM_L3MISS,Demand LD - L3 Miss (not L2 hit and not L3 hit) ##C048 The processor's Data Cache was reloaded from beyond L3 due to a demand load #30,v,g,n,n,n,PM_DATA_FROM_RL2L3_SHR,Data loaded from remote L2 or L3 shared ##C044 The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load #31,v,g,n,n,n,PM_DC_PREF_DST,Data Stream Touch ##D0B0 A prefetch stream was started using the DST instruction. #32,v,g,n,n,n,PM_DERAT_MISS_64K,DERAT misses for 64K page ##C05C A data request (load or store) missed the ERAT for 64K page and resulted in an ERAT reload. #33,v,g,n,n,n,PM_DISP_CLB_HELD,CLB Hold: Any Reason ##2090 CLB Hold: Any Reason #34,v,g,n,n,n,PM_DISP_CLB_HELD_BAL,Dispatch/CLB Hold: Balance ##2092 Dispatch/CLB Hold: Balance #35,v,g,n,n,n,PM_DISP_CLB_HELD_RES,Dispatch/CLB Hold: Resource ##2094 Dispatch/CLB Hold: Resource #36,v,g,n,n,n,PM_DISP_CLB_HELD_SB,Dispatch/CLB Hold: Scoreboard ##20A8 Dispatch/CLB Hold: Scoreboard #37,v,g,n,n,n,PM_DISP_CLB_HELD_SYNC,Dispatch/CLB Hold: Sync type instruction ##2098 Dispatch/CLB Hold: Sync type instruction #38,v,g,n,n,n,PM_DISP_CLB_HELD_TLBIE,Dispatch Hold: Due to TLBIE ##2096 Dispatch Hold: Due to TLBIE #39,v,g,n,n,n,PM_DPU_HELD_POWER,Dispatch Held due to Power Management ##0006 Cycles that Instruction Dispatch was held due to power management. More than one hold condition can exist at the same time #40,v,g,n,n,n,PM_DSEG,DSEG Exception ##20A6 DSEG Exception #41,v,g,n,n,n,PM_DSLB_MISS,Data SLB Miss - Total of all segment sizes ##D090 A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve. #42,v,g,n,n,n,PM_DTLB_MISS_4K,Data TLB miss for 4K page ##C05A,C05E Data TLB references to 4KB pages that missed the TLB. Page size is determined at TLB reload time. #43,v,g,n,n,n,PM_EE_OFF_EXT_INT,ee off and external interrupt ##2080 Cycles when an interrupt due to an external exception is pending but external exceptions were masked. #44,v,g,n,n,n,PM_EXT_INT,external interrupt ##00F8 An interrupt due to an external exception occurred #45,v,g,n,n,n,PM_FLUSH_BR_MPRED,Flush caused by branch mispredict ##2084 A flush was caused by a branch mispredict. #46,v,g,n,n,n,PM_FLUSH_DISP,Dispatch flush ##2082 Dispatch flush #47,v,g,n,n,n,PM_FLUSH_DISP_SB,Dispatch Flush: Scoreboard ##208C Dispatch Flush: Scoreboard #48,v,g,n,n,n,PM_FLUSH_DISP_SYNC,Dispatch Flush: Sync ##2088 Dispatch Flush: Sync #49,v,g,n,n,n,PM_FLUSH_DISP_TLBIE,Dispatch Flush: TLBIE ##208A Dispatch Flush: TLBIE #50,v,g,n,n,n,PM_FLUSH_PARTIAL,Partial flush ##2086 Partial flush #51,v,g,n,n,n,PM_FXU_BUSY,fxu0 busy and fxu1 busy. ##000E Cycles when both FXU0 and FXU1 are busy. #52,v,g,n,s,n,PM_GCT_EMPTY_CYC,GCT empty, all threads ##0008 Cycles when the Global Completion Table was completely empty. No thread had an entry allocated. #53,v,g,n,s,n,PM_GCT_FULL_CYC,Cycles No room in EAT ##4086 The Global Completion Table is completely full. #54,v,g,n,n,n,PM_GCT_NOSLOT_IC_MISS,GCT empty by I cache miss ##001A Cycles when the Global Completion Table has no slots from this thread because of an Instruction Cache miss. #55,v,g,n,n,n, PM_GCT_UTIL_1_TO_2_SLOTS,GCT Utilization 1-2 entries ##209C GCT Utilization 1-2 entries #56,v,g,n,n,n,PM_GCT_UTIL_11_PLUS_SLOTS,GCT Utilization 11+ entries ##20A2 GCT Utilization 11+ entries #57,v,g,n,n,n,PM_GCT_UTIL_3_TO_6_SLOTS,GCT Utilization 3-6 entries ##209E GCT Utilization 3-6 entries #58,v,g,n,n,n,PM_GCT_UTIL_7_TO_10_SLOTS,GCT Utilization 7-10 entries ##20A0 GCT Utilization 7-10 entries #59,v,g,n,c,n,PM_HV_CYC,cycles in hypervisor mode ##000A Cycles when the processor is executing in Hypervisor (MSR[HV] = 1 and MSR[PR]=0) #60,v,g,n,n,n,PM_IBUF_FULL_CYC,Cycles No room in ibuff ##4084 Cycles with the Instruction Buffer was full. The Instruction Buffer is a circular queue of 64 instructions per thread, organized as 16 groups of 4 instructions. #61,v,g,n,n,n,PM_IC_BANK_CONFLICT,Read blocked due to interleave conflict. ##4082 Read blocked due to interleave conflict. #62,v,g,n,n,n,PM_IC_DEMAND_L2_BHT_REDIRECT, L2 I cache demand request due to BHT redirect ##4098 A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (CR mispredict). #63,v,g,n,n,n,PM_IC_DEMAND_L2_BR_ALL, L2 I cache demand request due to BHT or redirect ##4898 L2 I cache demand request due to BHT or redirect #64,v,g,n,n,n,PM_IC_DEMAND_L2_BR_REDIRECT, L2 I cache demand request due to branch redirect ##409A A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (either ALL mispredicted or Target). #65,v,g,n,n,n,PM_IC_DEMAND_REQ,Demand Instruction fetch request ##4088 Demand Instruction fetch request #66,v,g,n,n,n,PM_IC_PREF_CANCEL_ALL,Prefetch Canceled due to page boundary or icache hit ##4890 Prefetch Canceled due to page boundary or icache hit #67,v,g,n,n,n,PM_IC_PREF_CANCEL_HIT,Prefetch Canceled due to icache hit ##4092 Prefetch Canceled due to icache hit #68,v,g,n,n,n,PM_IC_PREF_CANCEL_L2,L2 Squashed request ##4094 L2 Squashed request #69,v,g,n,n,n,PM_IC_PREF_CANCEL_PAGE,Prefetch Canceled due to page boundary ##4090 Prefetch Canceled due to page boundary #70,v,g,n,n,n,PM_IC_PREF_REQ,Instruction prefetch requests ##408A An instruction prefetch request has been made. #71,v,g,n,n,n,PM_IC_PREF_WRITE,Instruction prefetch written into IL1 ##408E Number of Instruction Cache entries written because of prefetch. Prefetch entries are marked least recently used and are candidates for eviction if they are not needed to satify a demand fetch. #72,v,g,n,n,n,PM_IC_RELOAD_SHR,Reloading line to be shared between the threads ##4096 An Instruction Cache request was made by this thread and the cache line was already in the cache for the other thread. The line is marked valid for all threads. #73,v,g,n,n,n,PM_IC_REQ_ALL,Icache requests, prefetch + demand ##4888 Icache requests, prefetch + demand #74,v,g,n,n,n,PM_IC_WRITE_ALL,Icache sectors written, prefetch + demand ##488C Icache sectors written, prefetch + demand #75,v,g,n,n,n,PM_IERAT_WR_64K,large page 64k ##40BE large page 64k #76,v,g,n,n,n,PM_IERAT_XLATE_WR_16MPLUS,large page 16M+ ##40BC large page 16M+ #77,v,g,n,n,n,PM_INST_CMPL,# PPC Instructions Finished ##0002 Number of PowerPC Instructions that completed. #78,v,g,n,n,n,PM_INST_DISP,# PPC Dispatched ##00F2 Number of PowerPC instructions successfully dispatched. #79,v,g,n,n,n,PM_INST_FROM_DMEM,Instruction fetched from distant memory ##4042 An instruction fetch group was fetched from memory attached to a distant module. Fetch groups can contain up to 8 instructions #80,v,g,n,n,n,PM_INST_FROM_L1,Instruction fetches from L1 ##4080 An instruction fetch group was fetched from L1. Fetch Groups can contain up to 8 instructions #81,v,g,n,n,n,PM_INST_FROM_L3,Instruction fetched from L3 ##4040 An instruction fetch group was fetched from L3. Fetch Groups can contain up to 8 instructions #82,v,g,n,n,n,PM_INST_FROM_L31_SHR,Instruction fetched from another L3 on same chip shared ##4046 Instruction fetched from another L3 on same chip shared #83,v,g,n,n,n,PM_INST_FROM_L3MISS,Instruction fetched missed L3 ##4048 An instruction fetch group was fetched from beyond L3. Fetch groups can contain up to 8 instructions. #84,v,g,n,n,n,PM_INST_FROM_RL2L3_SHR,Instruction fetched from remote L2 or L3 shared ##4044 An instruction fetch group was fetched with shared (S) data from the L2 or L3 on a remote module. Fetch groups can contain up to 8 instructions #85,v,g,n,n,n,PM_INST_PTEG_FROM_DMEM,Instruction PTEG loaded from distant memory ##E052 Instruction PTEG loaded from distant memory #86,v,g,n,n,n,PM_INST_PTEG_FROM_L3,Instruction PTEG loaded from L3 ##E050 Instruction PTEG loaded from L3 #87,v,g,n,n,n,PM_INST_PTEG_FROM_L31_SHR,Instruction PTEG loaded from another L3 on same chip shared ##E056 Instruction PTEG loaded from another L3 on same chip shared #88,v,g,n,n,n,PM_INST_PTEG_FROM_L3MISS,Instruction PTEG loaded from L3 miss ##E058 Instruction PTEG loaded from L3 miss #89,v,g,n,n,n,PM_INST_PTEG_FROM_RL2L3_SHR,Instruction PTEG loaded from remote L2 or L3 shared ##E054 Instruction PTEG loaded from remote L2 or L3 shared #90,v,g,n,n,n,PM_ISEG,ISEG Exception ##20A4 ISEG Exception #91,v,g,n,n,n,PM_ISLB_MISS,Instruction SLB Miss - Tota of all segment sizes ##D092 A SLB miss for an instruction fetch as occurred #92,v,g,n,n,n,PM_L1_DEMAND_WRITE,Instruction Demand sectors wriittent into IL1 ##408C Instruction Demand sectors wriittent into IL1 #93,v,g,n,n,n,PM_L1_ICACHE_MISS,Demand iCache Miss ##00FC An instruction fetch request missed the L1 cache. #94,v,g,n,n,n,PM_L1_PREF,L1 Prefetches ##D8B8 A request to prefetch data into the L1 was made #95,v,g,n,s,n,PM_L2_DC_INV,Dcache invalidates from L2 ##6182 The L2 invalidated a line in processor's data cache. This is caused by the L2 line being cast out or invalidated. Total for all slices #96,v,g,n,s,n,PM_L2_GLOB_GUESS_WRONG,L2 guess glb and guess was not correct (ie data local) ##6482 L2 guess glb and guess was not correct (ie data local) #97,v,g,n,s,n,PM_L2_IC_INV,Icache Invalidates from L2 ##6180 Icache Invalidates from L2 #98,v,g,n,n,n,PM_L2_LD_MISS,Data Load Miss ##6080 Data Load Miss #99,v,g,n,s,n,PM_L2_LDST_MISS,Data Load+Store Miss ##6880 Data Load+Store Miss #100,v,g,n,s,n,PM_L2_LOC_GUESS_WRONG,L2 guess loc and guess was not correct (ie data remote) ##6480 L2 guess loc and guess was not correct (ie data remote) #101,v,g,n,s,n,PM_L2_RCLD_DISP_FAIL_OTHER, L2 RC load dispatch attempt failed due to other reasons ##6280 L2 RC load dispatch attempt failed due to other reasons #102,v,g,n,s,n,PM_L2_RCST_BUSY_RC_FULL, L2 activated Busy to the core for stores due to all RC full ##6282 L2 activated Busy to the core for stores due to all RC full #103,v,g,n,n,n,PM_L2_ST_MISS,Data Store Miss ##6082 Data Store Miss #104,v,g,n,s,n,PM_L3_LD_HIT,L3 demand LD Hits ##F080 L3 demand LD Hits #105,v,g,n,s,n,PM_L3_LD_MISS,L3 demand LD Miss ##F082 L3 demand LD Miss #106,v,g,n,n,n,PM_L3_PREF_LD,L3 cache LD prefetches ##D0AC L3 cache LD prefetches #107,v,g,n,n,n,PM_L3_PREF_LDST,L3 cache prefetches LD + ST ##D8AC L3 cache prefetches LD + ST #108,v,g,n,n,n,PM_L3_PREF_ST,L3 cache ST prefetches ##D0AE L3 cache ST prefetches #109,v,g,n,n,n,PM_LARX_LSU,Larx Finished ##C894 Larx Finished #110,v,g,n,n,n,PM_LARX_LSU0,ls0 Larx Finished ##C094 A larx (lwarx or ldarx) was executed on side 0 #111,v,g,n,n,n,PM_LARX_LSU1,ls1 Larx Finished ##C096 A larx (lwarx or ldarx) was executed on side 1 #112,v,g,n,n,n,PM_LD_REF_L1, L1 D cache load references counted at finish ##C880 L1 D cache load references counted at finish #113,v,g,n,n,n,PM_LD_REF_L1_LSU0,LS0 L1 D cache load references counted at finish ##C080 Load references to Level 1 Data Cache, by unit 0. #114,v,g,n,n,n,PM_LD_REF_L1_LSU1,LS1 L1 D cache load references counted at finish ##C082 Load references to Level 1 Data Cache, by unit 1. #115,v,g,n,n,n,PM_LSU_DC_PREF_STREAM_ALLOC,D cache new prefetch stream allocated ##D8A8 D cache new prefetch stream allocated #116,v,g,n,n,n,PM_LSU_DC_PREF_STREAM_CONFIRM,Dcache new prefetch stream confirmed ##D8B4 Dcache new prefetch stream confirmed #117,v,g,n,n,n,PM_LSU_DC_PREF_STRIDED_STREAM_CONFIRM,Dcache Strided prefetch stream confirmed (software + hardware) ##D8BC Dcache Strided prefetch stream confirmed (software + hardware) #118,v,g,n,n,n,PM_LSU_DCACHE_RELOAD_VALID,count per sector of lines reloaded in L1 (demand + prefetch) ##D0A2 count per sector of lines reloaded in L1 (demand + prefetch) #119,v,g,n,n,n,PM_LSU_DERAT_MISS,DERAT Reloaded due to a DERAT miss ##00F6 Total D-ERAT Misses. Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction. Combined Unit 0 + 1. #120,v,g,n,n,n,PM_LSU_FLUSH,Flush initiated by LSU ##208E A flush was initiated by the Load Store Unit. #121,v,g,n,n,n,PM_LSU_FLUSH_LRQ,Flush: LRQ ##C8B8 Load Hit Load or Store Hit Load flush. A younger load was flushed because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. Combined Unit 0 + 1. #122,v,g,n,n,n,PM_LSU_FLUSH_SRQ,Flush: SRQ ##C8BC Load Hit Store flush. A younger load was flushed because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. Combined Unit 0 + 1. #123,v,g,n,n,n,PM_LSU_FLUSH_ULD,Flush: Unaligned Load ##C8B0 A load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1). Combined Unit 0 + 1. #124,v,g,n,n,n,PM_LSU_FLUSH_UST,Flush: Unaligned Store ##C8B4 A store was flushed because it was unaligned (crossed a 4K boundary). Combined Unit 0 + 1. #125,v,g,n,n,n,PM_LSU_LDF,All Scalar Loads ##C884 LSU executed Floating Point load instruction. Combined Unit 0 + 1. #126,v,g,n,n,n,PM_LSU_LDX,All Vector loads (vsx vector + vmx vector) ##C888 All Vector loads (vsx vector + vmx vector) #127,v,g,n,n,n,PM_LSU_LMQ_FULL_CYC,LMQ full ##D0A4 The Load Miss Queue was full. #128,v,g,n,n,n,PM_LSU_LMQ_S0_ALLOC,Slot 0 of LMQ valid ##D0A1 Slot 0 of LMQ valid #129,v,g,n,n,n,PM_LSU_LMQ_S0_VALID,Slot 0 of LMQ valid ##D0A0 This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the LRQ is split between the two threads (16 entries each). #130,v,g,n,c,n,PM_LSU_LMQ_SRQ_EMPTY_CYC,LSU empty (lmq and srq empty) ##003E Cycles when both the LMQ and SRQ are empty (LSU is idle) #131,v,g,n,n,n,PM_LSU_LRQ_S0_ALLOC,Slot 0 of LRQ valid ##D09F Slot 0 of LRQ valid #132,v,g,n,n,n,PM_LSU_LRQ_S0_VALID,Slot 0 of LRQ valid ##D09E This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the LRQ is split between the two threads (16 entries each). #133,v,g,n,n,n,PM_LSU_NCLD,Non-cachable Loads counted at finish ##C88C A non-cacheable load was executed. Combined Unit 0 + 1. #134,v,g,n,n,n,PM_LSU_NCST,Non-cachable Stores sent to nest ##C090 Non-cachable Stores sent to nest #135,v,g,n,n,n,PM_LSU_PARTIAL_CDF,A partial cacheline was returned from the L3 ##C0AA A partial cacheline was returned from the L3 #136,v,g,n,n,n,PM_LSU_REJECT_ERAT_MISS,LSU Reject due to ERAT (up to 2 per cycles) ##0064 Total cycles the Load Store Unit is busy rejecting instructions due to an ERAT miss. Combined unit 0 + 1. Requests that miss the Derat are rejected and retried until the request hits in the Erat. #137,v,g,n,n,n,PM_LSU_REJECT_LHS,Reject: Load Hit Store ##C8AC The Load Store Unit rejected a load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully. Combined Unit 0 + 1 #138,v,g,n,n,n,PM_LSU_REJECT_LMQ_FULL,Reject: LMQ Full (LHR) ##C8A4 Total cycles the Load Store Unit is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all the eight entries are full, subsequent load instructions are rejected. Combined unit 0 + 1. #139,v,g,n,n,n,PM_LSU_REJECT_SET_MPRED,Reject: Set Predict Wrong ##C8A8 The Load Store Unit rejected an instruction because the cache set was improperly predicted. This is a fast reject and will be immediately redispatched. Combined Unit 0 + 1 #140,v,g,n,n,n,PM_LSU_SET_MPRED,Line already in cache at reload time ##C0A8 Line already in cache at reload time #141,v,g,n,n,n,PM_LSU_SRQ_S0_ALLOC,Slot 0 of SRQ valid ##D09D Slot 0 of SRQ valid #142,v,g,n,n,n,PM_LSU_SRQ_S0_VALID,Slot 0 of SRQ valid ##D09C This signal is asserted every cycle that the Store Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the SRQ is split between the two threads (16 entries each). #143,v,g,n,n,n,PM_LSU_SRQ_STFWD,Load got data from a store ##C8A0 Data from a store instruction was forwarded to a load. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss. Combined Unit 0 + 1. #144,v,g,n,n,n,PM_LSU_SRQ_SYNC_COUNT,SRQ sync count (edge of PM_LSU_SRQ_SYNC_CYC) ##D097 SRQ sync count (edge of PM_LSU_SRQ_SYNC_CYC) #145,v,g,n,n,n,PM_LSU_SRQ_SYNC_CYC,A sync is in the SRQ ##D096 Cycles that a sync instruction is active in the Store Request Queue. #146,v,g,n,n,n,PM_LSU_TWO_TABLEWALK_CYC,Cycles when two tablewalks pending on this thread ##D0A6 Cycles when two tablewalks pending on this thread #147,v,g,n,n,n,PM_LSU0_DC_PREF_STREAM_ALLOC,LS0 D cache new prefetch stream allocated ##D0A8 LS0 D cache new prefetch stream allocated #148,v,g,n,n,n,PM_LSU0_DC_PREF_STREAM_CONFIRM,LS0 Dcache prefetch stream confirmed ##D0B4 LS0 Dcache prefetch stream confirmed #149,v,g,n,n,n,PM_LSU0_DC_PREF_STREAM_CONFIRM_STRIDE,LS0 Dcache Strided prefetch stream confirmed ##D0BC LS0 Dcache Strided prefetch stream confirmed #150,v,g,n,n,n,PM_LSU0_FLUSH_LRQ,LS0 Flush: LRQ ##C0B8 Load Hit Load or Store Hit Load flush. A younger load was flushed from unit 0 because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. #151,v,g,n,n,n,PM_LSU0_FLUSH_SRQ,LS0 Flush: SRQ ##C0BC Load Hit Store flush. A younger load was flushed from unit 0 because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. #152,v,g,n,n,n,PM_LSU0_FLUSH_ULD,LS0 Flush: Unaligned Load ##C0B0 A load was flushed from unit 0 because it was unaligned (crossed a 64 byte boundary, or 32 byte if it missed the L1) #153,v,g,n,n,n,PM_LSU0_FLUSH_UST,LS0 Flush: Unaligned Store ##C0B4 A store was flushed from unit 0 because it was unaligned (crossed a 4K boundary). #154,v,g,n,n,n,PM_LSU0_L1_PREF, LS0 L1 cache data prefetches ##D0B8 LS0 L1 cache data prefetches #155,v,g,n,n,n,PM_LSU0_L1_SW_PREF,LSU0 Software L1 Prefetches, including SW Transient Prefetches ##C09C LSU0 Software L1 Prefetches, including SW Transient Prefetches #156,v,g,n,n,n,PM_LSU0_LDF,LS0 Scalar Loads ##C084 A floating point load was executed by LSU0 #157,v,g,n,n,n,PM_LSU0_LDX,LS0 Vector Loads ##C088 LS0 Vector Loads #158,v,g,n,n,n,PM_LSU0_LMQ_LHR_MERGE,LS0 Load Merged with another cacheline request ##D098 LS0 Load Merged with another cacheline request #159,v,g,n,n,n,PM_LSU0_NCLD,LS0 Non-cachable Loads counted at finish ##C08C A non-cacheable load was executed by unit 0. #160,v,g,n,n,n,PM_LSU0_REJECT_LHS,LS0 Reject: Load Hit Store ##C0AC Load Store Unit 0 rejected a load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully. #161,v,g,n,n,n,PM_LSU0_REJECT_LMQ_FULL,LS0 Reject: LMQ Full (LHR) ##C0A4 Total cycles the Load Store Unit 0 is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all eight entries are full, subsequent load instructions are rejected. #162,v,g,n,n,n,PM_LSU0_SRQ_STFWD,LS0 SRQ forwarded data to a load ##C0A0 Data from a store instruction was forwarded to a load on unit 0. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss. #163,v,g,n,n,n,PM_LSU1_DC_PREF_STREAM_ALLOC,LS 1 D cache new prefetch stream allocated ##D0AA LS 1 D cache new prefetch stream allocated #164,v,g,n,n,n,PM_LSU1_DC_PREF_STREAM_CONFIRM,LS1 'Dcache prefetch stream confirmed ##D0B6 LS1 'Dcache prefetch stream confirmed #165,v,g,n,n,n,PM_LSU1_DC_PREF_STREAM_CONFIRM_STRIDE,LS1 Dcache Strided prefetch stream confirmed ##D0BE LS1 Dcache Strided prefetch stream confirmed #166,v,g,n,n,n,PM_LSU1_FLUSH_LRQ,LS1 Flush: LRQ ##C0BA Load Hit Load or Store Hit Load flush. A younger load was flushed from unit 1 because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. #167,v,g,n,n,n,PM_LSU1_FLUSH_SRQ,LS1 Flush: SRQ ##C0BE Load Hit Store flush. A younger load was flushed from unit 1 because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. #168,v,g,n,n,n,PM_LSU1_FLUSH_ULD,LS 1 Flush: Unaligned Load ##C0B2 A load was flushed from unit 1 because it was unaligned (crossed a 64 byte boundary, or 32 byte if it missed the L1). #169,v,g,n,n,n,PM_LSU1_FLUSH_UST,LS1 Flush: Unaligned Store ##C0B6 A store was flushed from unit 1 because it was unaligned (crossed a 4K boundary) #170,v,g,n,n,n,PM_LSU1_L1_PREF, LS1 L1 cache data prefetches ##D0BA LS1 L1 cache data prefetches #171,v,g,n,n,n,PM_LSU1_L1_SW_PREF,LSU1 Software L1 Prefetches, including SW Transient Prefetches ##C09E LSU1 Software L1 Prefetches, including SW Transient Prefetches #172,v,g,n,n,n,PM_LSU1_LDF,LS1 Scalar Loads ##C086 A floating point load was executed by LSU1 #173,v,g,n,n,n,PM_LSU1_LDX,LS1 Vector Loads ##C08A LS1 Vector Loads #174,v,g,n,n,n,PM_LSU1_LMQ_LHR_MERGE,LS1 Load Merge with another cacheline request ##D09A LS1 Load Merge with another cacheline request #175,v,g,n,n,n,PM_LSU1_NCLD,LS1 Non-cachable Loads counted at finish ##C08E A non-cacheable load was executed by Unit 0. #176,v,g,n,n,n,PM_LSU1_REJECT_LHS,LS1 Reject: Load Hit Store ##C0AE Load Store Unit 1 rejected a load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully. #177,v,g,n,n,n,PM_LSU1_REJECT_LMQ_FULL,LS1 Reject: LMQ Full (LHR) ##C0A6 Total cycles the Load Store Unit 1 is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all eight entries are full, subsequent load instructions are rejected. #178,v,g,n,n,n,PM_LSU1_SRQ_STFWD,LS1 SRQ forwarded data to a load ##C0A2 Data from a store instruction was forwarded to a load on unit 1. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss. #179,v,g,n,n,n,PM_LWSYNC,lwsync count (easier to use than IMC) ##D094 lwsync count (easier to use than IMC) #180,v,g,n,n,n,PM_LWSYNC_HELD,LWSYNC held at dispatch ##209A Cycles a LWSYNC instruction was held at dispatch. LWSYNC instructions are held at dispatch until all previous loads are done and all previous stores have issued. LWSYNC enters the Store Request Queue and is sent to the storage subsystem but does not wait for a response. #181,v,g,n,n,m,PM_MRK_BRU_FIN,bru marked instr finish ##003A The branch unit finished a marked instruction. Instructions that finish may not necessary complete. #182,v,g,n,n,m,PM_MRK_DATA_FROM_DL2L3_SHR_CYC,Marked ld latency Data Source 1010 (Distant L2.75/L3.75 S) ##002A Marked ld latency Data Source 1010 (Distant L2.75/L3.75 S) #183,v,g,n,n,m,PM_MRK_DATA_FROM_DMEM,Marked data loaded from distant memory ##D042 The processor's Data Cache was reloaded with data from memory attached to a distant module due to a marked load. #184,v,g,n,n,m,PM_MRK_DATA_FROM_DMEM_CYC,Marked ld latency Data Source 1110 (Distant Memory) ##002E Marked ld latency Data Source 1110 (Distant Memory) #185,v,g,n,n,m,PM_MRK_DATA_FROM_L2_CYC,Marked ld latency Data source 0000 (L2 hit) ##0020 Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level. #186,v,g,n,n,m,PM_MRK_DATA_FROM_L21_SHR_CYC,Marked ld latency Data source 0100 (L2.1 S) ##0024 Marked load latency Data source 0100 (L2.1 S) #187,v,g,n,n,m,PM_MRK_DATA_FROM_L3,Marked data loaded from L3 ##D040 The processor's Data Cache was reloaded from the local L3 due to a marked load. #188,v,g,n,n,m,PM_MRK_DATA_FROM_L31_SHR,Marked data loaded from another L3 on same chip shared ##D046 Marked data loaded from another L3 on same chip shared #189,v,g,n,n,m,PM_MRK_DATA_FROM_L31_SHR_CYC,Marked ld latency Data source 0110 (L3.1 S) ##0026 Marked load latency Data source 0110 (L3.1 S) #190,v,g,n,n,m,PM_MRK_DATA_FROM_L3MISS,Marked data loaded from L3 miss ##D048 DL1 was reloaded from beyond L3 due to a marked load. #191,v,g,n,n,m,PM_MRK_DATA_FROM_LMEM_CYC,Marked ld latency Data Source 1100 (Local Memory) ##002C Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level. #192,v,g,n,n,m,PM_MRK_DATA_FROM_RL2L3_SHR,Marked data loaded from remote L2 or L3 shared ##D044 The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a remote module due to a marked load #193,v,g,n,n,m,PM_MRK_DATA_FROM_RL2L3_SHR_CYC,Marked ld latency Data Source 1000 (Remote L2.5/L3.5 S) ##0028 Marked load latency Data Source 1000 (Remote L2.5/L3.5 S) #194,v,g,n,n,m,PM_MRK_DERAT_MISS_64K,Marked DERAT misses for 64K page ##D05C A marked data request (load or store) missed the ERAT for 64K page and resulted in an ERAT reload. #195,v,g,n,n,m,PM_MRK_DFU_FIN,Decimal Unit marked Instruction Finish ##0032 The Decimal Floating Point Unit finished a marked instruction. #196,v,g,n,n,m,PM_MRK_DTLB_MISS_4K,Marked Data TLB misses for 4K page ##D05A,D05E Data TLB references to 4KB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time. #197,v,g,n,n,m,PM_MRK_FXU_FIN,fxu marked instr finish ##0038 One of the Fixed Point Units finished a marked instruction. Instructions that finish may not necessary complete. #198,v,g,t,n,m,PM_MRK_INST_DISP,marked instruction dispatch ##0030 A marked instruction was dispatched #199,v,g,t,n,m,PM_MRK_LD_MISS_L1,Marked DL1 Demand Miss ##0036 Marked L1 D cache load misses #200,v,g,n,n,m,PM_MRK_LSU_FLUSH,Flush: (marked) : All Cases ##D08C Marked flush initiated by LSU #201,v,g,n,n,m,PM_MRK_LSU_FLUSH_LRQ,Flush: (marked) LRQ ##D088 Load Hit Load or Store Hit Load flush. A marked load was flushed because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. #202,v,g,n,n,m,PM_MRK_LSU_FLUSH_SRQ,Flush: (marked) SRQ ##D08A Load Hit Store flush. A marked load was flushed because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. #203,v,g,n,n,m,PM_MRK_LSU_FLUSH_ULD,Flush: (marked) Unaligned Load ##D084 A marked load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1) #204,v,g,n,n,m,PM_MRK_LSU_FLUSH_UST,Flush: (marked) Unaligned Store ##D086 A marked store was flushed because it was unaligned #205,v,g,n,n,m,PM_MRK_LSU_PARTIAL_CDF,A partial cacheline was returned from the L3 for a marked load ##D080 A partial cacheline was returned from the L3 for a marked load #206,v,g,n,n,m,PM_MRK_LSU_REJECT_LHS, Reject(marked): Load Hit Store ##D082 The Load Store Unit rejected a marked load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully #207,v,g,n,n,m,PM_MRK_PTEG_FROM_DMEM,Marked PTEG loaded from distant memory ##D052 A Page Table Entry was loaded into the ERAT from memory attached to a different module than this proccessor is located on due to a marked load or store. #208,v,g,n,n,m,PM_MRK_PTEG_FROM_L3,Marked PTEG loaded from L3 ##D050 A Page Table Entry was loaded into the ERAT from the local L3 due to a marked load or store. #209,v,g,n,n,m,PM_MRK_PTEG_FROM_L31_SHR,Marked PTEG loaded from another L3 on same chip shared ##D056 Marked PTEG loaded from another L3 on same chip shared #210,v,g,n,n,m,PM_MRK_PTEG_FROM_L3MISS,Marked PTEG loaded from L3 miss ##D058 A Page Table Entry was loaded into the ERAT from beyond the L3 due to a marked load or store #211,v,g,n,n,m,PM_MRK_PTEG_FROM_RL2L3_SHR,Marked PTEG loaded from remote L2 or L3 shared ##D054 A Page Table Entry was loaded into the ERAT from memory attached to a different module than this proccessor is located on due to a marked load or store. #212,v,g,n,n,m,PM_MRK_ST_NEST,marked store sent to Nest ##0034 A sampled store has been sent to the memory subsystem #213,v,g,n,n,m,PM_MRK_STCX_FAIL,Marked STCX failed ##D08E A marked stcx (stwcx or stdcx) failed #214,v,g,n,c,n,PM_PB_SYS_PUMP, Nest events (MC0/MC1/PB/GX), Pair1 Bit0 ##0081 Nest events (MC0/MC1/PB/GX), Pair1 Bit0 #215,v,g,n,c,n,PM_MEM0_PREFETCH_DISP, Nest events (MC0/MC1/PB/GX), Pair1 Bit1 ##0083 Nest events (MC0/MC1/PB/GX), Pair1 Bit1 #216,v,g,n,c,n,PM_NEST_PAIR1_ADD, Nest events (MC0/MC1/PB/GX), Pair1 ADD ##0881 Nest events (MC0/MC1/PB/GX), Pair1 ADD #217,v,g,n,c,n,PM_NEST_PAIR1_AND, Nest events (MC0/MC1/PB/GX), Pair1 AND ##0883 Nest events (MC0/MC1/PB/GX), Pair1 AND #218,v,g,n,n,n,PM_PMC1_OVERFLOW,Overflow from counter 1 ##0010 Overflows from PMC1 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow. #219,v,g,n,n,n,PM_POWER_EVENT2,Power Management Event 2 ##006E Power Management Event 2 #220,v,g,n,n,n,PM_PTEG_FROM_DMEM,PTEG loaded from distant memory ##C052 A Page Table Entry was loaded into the ERAT with data from memory attached to a distant module due to a demand load or store. #221,v,g,n,n,n,PM_PTEG_FROM_L3,PTEG loaded from L3 ##C050 A Page Table Entry was loaded into the TLB from the local L3 due to a demand load. #222,v,g,n,n,n,PM_PTEG_FROM_L31_SHR,PTEG loaded from another L3 on same chip shared ##C056 PTEG loaded from another L3 on same chip shared #223,v,g,n,n,n,PM_PTEG_FROM_L3MISS,PTEG loaded from L3 miss ##C058 Page Table Entry was loaded into the ERAT from beyond the L3 due to a demand load or store. #224,v,g,n,n,n,PM_PTEG_FROM_RL2L3_SHR,PTEG loaded from remote L2 or L3 shared ##C054 A Page Table Entry was loaded into the ERAT with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load or store. #225,v,g,n,n,n,PM_RUN_CYC,Run_cycles ##00F4 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop. #226,v,g,n,n,n,PM_SEG_EXCEPTION,ISEG + DSEG Exception ##28A4 ISEG + DSEG Exception #227,v,g,n,n,n,PM_SHL_CREATED,SHL table entry Created ##5082 SHL table entry Created #228,v,g,n,n,n,PM_SHL_DEALLOCATED,SHL Table entry deallocated ##5080 SHL Table entry deallocated #229,v,g,n,n,n,PM_SHL_MATCH,SHL Table Match ##5086 SHL Table Match #230,v,g,n,n,n,PM_SHL_MERGED,SHL table entry merged with existing ##5084 SHL table entry merged with existing #231,v,g,n,n,n,PM_SLB_MISS,Data + Instruction SLB Miss - Total of all segment sizes ##D890 Total of all Segment Lookaside Buffer (SLB) misses, Instructions + Data. #232,v,g,n,c,n,PM_SNOOP_TLBIE,TLBIE snoop ##D0B2 A tlbie was snooped from another processor. #233,v,g,n,n,n,PM_ST_FIN,Store Instructions Finished ##00F0 Store requests sent to the nest. #234,v,g,n,n,n,PM_STCX_CMPL,STCX executed ##C098 Conditional stores with reservation completed #235,v,g,n,n,n,PM_STCX_FAIL,STCX failed ##C09A A stcx (stwcx or stdcx) failed #236,v,g,n,n,n,PM_SUSPENDED,Counter OFF ##0000 The counter is suspended (does not count) #237,v,g,n,c,n,PM_THRD_2_RUN_CYC,2 thread in Run Cycles ##0060 2 thread in Run Cycles #238,v,g,n,c,n,PM_THRD_4_CONC_RUN_INST,4 thread Concurrent Run Instructions ##0062 4 thread Concurrent Run Instructions #239,v,g,n,c,n,PM_THRD_ALL_RUN_CYC,All Threads in run_cycles ##000C Cycles when all threads had their run latches set. Operating systems use the run latch to indicate when they are doing useful work. #240,v,g,n,n,n,PM_THRD_PRIO_0_1_CYC, Cycles thread running at priority level 0 or 1 ##40B0 Cycles thread running at priority level 0 or 1 #241,v,g,n,n,n,PM_THRD_PRIO_2_3_CYC, Cycles thread running at priority level 2 or 3 ##40B2 Cycles thread running at priority level 2 or 3 #242,v,g,n,n,n,PM_THRD_PRIO_4_5_CYC, Cycles thread running at priority level 4 or 5 ##40B4 Cycles thread running at priority level 4 or 5 #243,v,g,n,n,n,PM_THRD_PRIO_6_7_CYC, Cycles thread running at priority level 6 or 7 ##40B6 Cycles thread running at priority level 6 or 7 #244,v,g,n,n,n,PM_TLB_MISS,TLB Miss (I + D) ##0066 Total of Data TLB mises + Instruction TLB misses #245,v,g,n,n,n,PM_VMX_RESULT_SAT_1,Valid result with sat=1 ##B0A0 Valid result with sat=1 #246,v,g,n,n,n,PM_VSU_1FLOP,one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished ##A880 one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished #247,v,g,n,n,n,PM_VSU_2FLOP,two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) ##A898 two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) #248,v,g,n,n,n,PM_VSU_2FLOP_DOUBLE,DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg ##A88C DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg #249,v,g,n,n,n,PM_VSU_4FLOP,four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions) ##A89C four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions) #250,v,g,n,n,n,PM_VSU_8FLOP,eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) ##A8A0 eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) #251,v,g,n,n,n,PM_VSU_DENORM,Vector or Scalar denorm operand ##A8AC Vector or Scalar denorm operand #252,v,g,n,n,n,PM_VSU_FCONV,Convert instruction executed ##A8B0 Convert instruction executed #253,v,g,n,n,n,PM_VSU_FEST,Estimate instruction executed ##A8B8 Estimate instruction executed #254,v,g,n,n,n,PM_VSU_FIN,VSU0 Finished an instruction ##A8BC VSU0 Finished an instruction #255,v,g,n,n,n,PM_VSU_FMA,two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only! ##A884 two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only! #256,v,g,n,n,n,PM_VSU_FMA_DOUBLE,DP vector version of fmadd,fnmadd,fmsub,fnmsub ##A890 DP vector version of fmadd,fnmadd,fmsub,fnmsub #257,v,g,n,n,n,PM_VSU_FRSP,Round to single precision instruction executed ##A8B4 Round to single precision instruction executed #258,v,g,n,n,n,PM_VSU_FSQRT_FDIV,four flops operation (fdiv,fsqrt) Scalar Instructions only! ##A888 DP vector versions of fdiv,fsqrt #259,v,g,n,n,n,PM_VSU_FSQRT_FDIV_DOUBLE,DP vector versions of fdiv,fsqrt ##A894 DP vector versions of fdiv,fsqrt #260,v,g,n,n,n,PM_VSU_SCALAR_DOUBLE_ISSUED,Double Precision scalar instruction issued on Pipe0 ##B888 Double Precision scalar instruction issued on Pipe0 #261,v,g,n,n,n,PM_VSU_SCALAR_SINGLE_ISSUED,Single Precision scalar instruction issued on Pipe0 ##B884 Single Precision scalar instruction issued on Pipe0 #262,v,g,n,n,n,PM_VSU_SIMPLE_ISSUED,Simple VMX instruction issued ##B894 Simple VMX instruction issued #263,v,g,n,n,n,PM_VSU_SINGLE,Vector or Scalar single precision ##A8A8 Vector or Scalar single precision #264,v,g,n,n,n,PM_VSU_STF,FPU store (SP or DP) issued on Pipe0 ##B88C FPU store (SP or DP) issued on Pipe0 #265,v,g,n,n,n,PM_VSU_VECTOR_DOUBLE_ISSUED,Double Precision vector instruction issued on Pipe0 ##B880 Double Precision vector instruction issued on Pipe0 #266,v,g,n,n,n,PM_VSU_VECTOR_SINGLE_ISSUED,Single Precision vector instruction issued (executed) ##B890 Single Precision vector instruction issued (executed) #267,v,g,n,n,n,PM_VSU0_16FLOP,Sixteen flops operation (SP vector versions of fdiv,fsqrt) ##A0A4 Sixteen flops operation (SP vector versions of fdiv,fsqrt) #268,v,g,n,n,n,PM_VSU0_1FLOP,one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg, xsadd, xsmul, xssub, xscmp, xssel, xsabs, xsnabs, xsre, xssqrte, xsneg) operation finished ##A080 one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg, xsadd, xsmul, xssub, xscmp, xssel, xsabs, xsnabs, xsre, xssqrte, xsneg) operation finished #269,v,g,n,n,n,PM_VSU0_2FLOP,two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) ##A098 two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) #270,v,g,n,n,n,PM_VSU0_2FLOP_DOUBLE,two flop DP vector operation (xvadddp, xvmuldp, xvsubdp, xvcmpdp, xvseldp, xvabsdp, xvnabsdp, xvredp ,xvsqrtedp, vxnegdp) ##A08C two flop DP vector operation (xvadddp, xvmuldp, xvsubdp, xvcmpdp, xvseldp, xvabsdp, xvnabsdp, xvredp ,xvsqrtedp, vxnegdp) #271,v,g,n,n,n,PM_VSU0_4FLOP,four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions) ##A09C four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions) #272,v,g,n,n,n,PM_VSU0_8FLOP,eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) ##A0A0 eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) #273,v,g,n,n,n,PM_VSU0_COMPLEX_ISSUED,Complex VMX instruction issued ##B096 Complex VMX instruction issued #274,v,g,n,n,n,PM_VSU0_DENORM,FPU denorm operand ##A0AC VSU0 received denormalized data #275,v,g,n,n,n,PM_VSU0_FCONV,Convert instruction executed ##A0B0 Convert instruction executed #276,v,g,n,n,n,PM_VSU0_FEST,Estimate instruction executed ##A0B8 Estimate instruction executed #277,v,g,n,n,n,PM_VSU0_FIN,VSU0 Finished an instruction ##A0BC VSU0 Finished an instruction #278,v,g,n,n,n,PM_VSU0_FMA,two flops operation (fmadd, fnmadd, fmsub, fnmsub, xsmadd, xsnmadd, xsmsub, xsnmsub) Scalar instructions only! ##A084 two flops operation (fmadd, fnmadd, fmsub, fnmsub, xsmadd, xsnmadd, xsmsub, xsnmsub) Scalar instructions only! #279,v,g,n,n,n,PM_VSU0_FMA_DOUBLE,four flop DP vector operations (xvmadddp, xvnmadddp, xvmsubdp, xvmsubdp) ##A090 four flop DP vector operations (xvmadddp, xvnmadddp, xvmsubdp, xvmsubdp) #280,v,g,n,n,n,PM_VSU0_FPSCR,Move to/from FPSCR type instruction issued on Pipe 0 ##B09C Move to/from FPSCR type instruction issued on Pipe 0 #281,v,g,n,n,n,PM_VSU0_FRSP,Round to single precision instruction executed ##A0B4 Round to single precision instruction executed #282,v,g,n,n,n,PM_VSU0_FSQRT_FDIV,four flops operation (fdiv,fsqrt,xsdiv,xssqrt) Scalar Instructions only! ##A088 four flops operation (fdiv,fsqrt,xsdiv,xssqrt) Scalar Instructions only! #283,v,g,n,n,n,PM_VSU0_FSQRT_FDIV_DOUBLE,eight flop DP vector operations (xvfdivdp, xvsqrtdp ##A094 eight flop DP vector operations (xvfdivdp, xvsqrtdp #284,v,g,n,n,n,PM_VSU0_SCAL_DOUBLE_ISSUED,Double Precision scalar instruction issued on Pipe0 ##B088 Double Precision scalar instruction issued on Pipe0 #285,v,g,n,n,n,PM_VSU0_SCAL_SINGLE_ISSUED,Single Precision scalar instruction issued on Pipe0 ##B084 Single Precision scalar instruction issued on Pipe0 #286,v,g,n,n,n,PM_VSU0_SIMPLE_ISSUED,Simple VMX instruction issued ##B094 Simple VMX instruction issued #287,v,g,n,n,n,PM_VSU0_SINGLE,FPU single precision ##A0A8 VSU0 executed single precision instruction #288,v,g,n,n,n,PM_VSU0_STF,FPU store (SP or DP) issued on Pipe0 ##B08C FPU store (SP or DP) issued on Pipe0 #289,v,g,n,n,n,PM_VSU0_VECT_DOUBLE_ISSUED,Double Precision vector instruction issued on Pipe0 ##B080 Double Precision vector instruction issued on Pipe0 #290,v,g,n,n,n,PM_VSU0_VECTOR_SP_ISSUED,Single Precision vector instruction issued (executed) ##B090 Single Precision vector instruction issued (executed) #291,v,g,n,n,n,PM_VSU1_1FLOP,one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg, xsadd, xsmul, xssub, xscmp, xssel, xsabs, xsnabs, xsre, xssqrte, xsneg) operation finished ##A082 one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg, xsadd, xsmul, xssub, xscmp, xssel, xsabs, xsnabs, xsre, xssqrte, xsneg) operation finished #292,v,g,n,n,n,PM_VSU1_2FLOP,two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) ##A09A two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) #293,v,g,n,n,n,PM_VSU1_2FLOP_DOUBLE,two flop DP vector operation (xvadddp, xvmuldp, xvsubdp, xvcmpdp, xvseldp, xvabsdp, xvnabsdp, xvredp ,xvsqrtedp, vxnegdp) ##A08E two flop DP vector operation (xvadddp, xvmuldp, xvsubdp, xvcmpdp, xvseldp, xvabsdp, xvnabsdp, xvredp ,xvsqrtedp, vxnegdp) #294,v,g,n,n,n,PM_VSU1_4FLOP,four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions) ##A09E four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions) #295,v,g,n,n,n,PM_VSU1_8FLOP,eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) ##A0A2 eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) #296,v,g,n,n,n,PM_VSU1_DD_ISSUED,64BIT Decimal Issued on Pipe1 ##B098 64BIT Decimal Issued on Pipe1 #297,v,g,n,n,n,PM_VSU1_DENORM,FPU denorm operand ##A0AE VSU1 received denormalized data #298,v,g,n,n,n,PM_VSU1_DQ_ISSUED,128BIT Decimal Issued on Pipe1 ##B09A 128BIT Decimal Issued on Pipe1 #299,v,g,n,n,n,PM_VSU1_FCONV,Convert instruction executed ##A0B2 Convert instruction executed #300,v,g,n,n,n,PM_VSU1_FEST,Estimate instruction executed ##A0BA Estimate instruction executed #301,v,g,n,n,n,PM_VSU1_FIN,VSU1 Finished an instruction ##A0BE VSU1 Finished an instruction #302,v,g,n,n,n,PM_VSU1_FMA,two flops operation (fmadd, fnmadd, fmsub, fnmsub, xsmadd, xsnmadd, xsmsub, xsnmsub) Scalar instructions only! ##A086 two flops operation (fmadd, fnmadd, fmsub, fnmsub, xsmadd, xsnmadd, xsmsub, xsnmsub) Scalar instructions only! #303,v,g,n,n,n,PM_VSU1_FMA_DOUBLE,four flop DP vector operations (xvmadddp, xvnmadddp, xvmsubdp, xvmsubdp) ##A092 four flop DP vector operations (xvmadddp, xvnmadddp, xvmsubdp, xvmsubdp) #304,v,g,n,n,n,PM_VSU1_FRSP,Round to single precision instruction executed ##A0B6 Round to single precision instruction executed #305,v,g,n,n,n,PM_VSU1_FSQRT_FDIV,four flops operation (fdiv,fsqrt,xsdiv,xssqrt) Scalar Instructions only! ##A08A four flops operation (fdiv,fsqrt,xsdiv,xssqrt) Scalar Instructions only! #306,v,g,n,n,n,PM_VSU1_FSQRT_FDIV_DOUBLE,eight flop DP vector operations (xvfdivdp, xvsqrtdp ##A096 eight flop DP vector operations (xvfdivdp, xvsqrtdp #307,v,g,n,n,n,PM_VSU1_PERMUTE_ISSUED,Permute VMX Instruction Issued ##B092 Permute VMX Instruction Issued #308,v,g,n,n,n,PM_VSU1_SCAL_DOUBLE_ISSUED,Double Precision scalar instruction issued on Pipe1 ##B08A Double Precision scalar instruction issued on Pipe1 #309,v,g,n,n,n,PM_VSU1_SCAL_SINGLE_ISSUED,Single Precision scalar instruction issued on Pipe1 ##B086 Single Precision scalar instruction issued on Pipe1 #310,v,g,n,n,n,PM_VSU1_SINGLE,FPU single precision ##A0AA VSU1 executed single precision instruction #311,v,g,n,n,n,PM_VSU1_SQ,Store Vector Issued on Pipe1 ##B09E Store Vector Issued on Pipe1 #312,v,g,n,n,n,PM_VSU1_STF,FPU store (SP or DP) issued on Pipe1 ##B08E FPU store (SP or DP) issued on Pipe1 #313,v,g,n,n,n,PM_VSU1_VECT_DOUBLE_ISSUED,Double Precision vector instruction issued on Pipe1 ##B082 Double Precision vector instruction issued on Pipe1 $$$$$$$$ { counter 3 } #0,v,g,n,n,n,PM_1THRD_CON_RUN_INSTR,1 thread Concurrent Run Instructions ##0062 1 thread Concurrent Run Instructions #1,v,g,n,n,n,PM_BC_PLUS_8_CONV,BC+8 Converted ##40B8 BC+8 Converted #2,v,g,n,n,n,PM_BC_PLUS_8_RSLV_TAKEN,BC+8 Resolve outcome was Taken, resulting in the conditional instruction being canceled ##40BA BC+8 Resolve outcome was Taken, resulting in the conditional instruction being canceled #3,v,g,n,n,n,PM_BR_MPRED_CCACHE,Branch Mispredict due to Count Cache prediction ##40A4 A branch instruction target was incorrectly predicted by the count cache. This will result in a branch redirect flush if not overwritten by a flush of an older instruction. #4,v,g,n,n,n,PM_BR_MPRED_CR,Branch mispredict - taken/not taken ##40AC A conditional branch instruction was incorrectly predicted as taken or not taken. The branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This will result in a branch redirect flush if not overfidden by a flush of an older instruction. #5,v,g,n,n,n,PM_BR_MPRED_CR_TA,Branch mispredict - taken/not taken and target ##48AE Branch mispredict - taken/not taken and target #6,v,g,n,n,n,PM_BR_MPRED_LSTACK,Branch Mispredict due to Link Stack ##40A6 Branch Mispredict due to Link Stack #7,v,g,n,n,n,PM_BR_MPRED_TA,Branch mispredict - target address ##40AE A branch instruction target was incorrectly predicted. This will result in a branch mispredict flush unless a flush is detected from an older instruction. #8,v,g,n,n,n,PM_BR_PRED,Branch Predictions made ##409C A branch prediction was made. This could have been a target prediction, a condition prediction, or both #9,v,g,n,n,n,PM_BR_PRED_CCACHE,Count Cache Predictions ##40A0 The count value of a Branch and Count instruction was predicted #10,v,g,n,n,n,PM_BR_PRED_CR,Branch predict - taken/not taken ##40A8 A conditional branch instruction was predicted as taken or not taken. #11,v,g,n,n,n,PM_BR_PRED_CR_TA,Branch predict - taken/not taken and target ##48AA Both the condition (taken or not taken) and the target address of a branch instruction was predicted. #12,v,g,n,n,n,PM_BR_PRED_LSTACK,Link Stack Predictions ##40A2 The target address of a Branch to Link instruction was predicted by the link stack. #13,v,g,n,n,n,PM_BR_PRED_TA,Branch predict - target address ##40AA The target address of a branch instruction was predicted. #14,v,g,n,n,n,PM_BR_UNCOND,Unconditional Branch ##409E An unconditional branch was executed. #15,v,g,n,n,n,PM_BTAC_HIT,BTAC Correct Prediction ##508A BTAC Correct Prediction #16,v,g,n,n,n,PM_BTAC_MISS,BTAC Mispredicted ##5088 BTAC Mispredicted #17,v,g,n,s,n,PM_CYC,Cycles ##001E Processor Cycles #18,v,g,n,n,n,PM_DATA_FROM_DL2L3_MOD,Data loaded from distant L2 or L3 modified ##C04C The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a distant module due to a demand load #19,v,g,n,n,n,PM_DATA_FROM_DL2L3_SHR,Data loaded from distant L2 or L3 shared ##C044 The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a distant module due to a demand load #20,v,g,n,n,n,PM_DATA_FROM_L21_MOD,Data loaded from another L2 on same chip modified ##C046 Data loaded from another L2 on same chip modified #21,v,g,n,n,n,PM_DATA_FROM_L21_SHR,Data loaded from another L2 on same chip shared ##C04E Data loaded from another L2 on same chip shared #22,v,g,n,n,n,PM_DATA_FROM_L3MISS,Demand LD - L3 Miss (not L2 hit and not L3 hit) ##00FE The processor's Data Cache was reloaded from beyond L3 due to a demand load #23,v,g,n,n,n,PM_DATA_FROM_LMEM,Data loaded from local memory ##C04A The processor’s Data Cache was reloaded from memory attached to the same module this proccessor is located on. #24,v,g,n,n,n,PM_DATA_FROM_RMEM,Data loaded from remote memory ##C042 The processor’s Data Cache was reloaded from memory attached to a different module than this proccessor is located on. #25,v,g,n,n,n,PM_DATA_TABLEWALK_CYC,Data Tablewalk Active ##001A Cycles a translation tablewalk is active. While a tablewalk is active any request attempting to access the TLB will be rejected and retried. #26,v,g,n,n,n,PM_DC_PREF_DST,Data Stream Touch ##D0B0 A prefetch stream was started using the DST instruction. #27,v,g,n,n,n,PM_DERAT_MISS_16M,DERAT misses for 16M page ##C05C A data request (load or store) missed the ERAT for 16M page and resulted in an ERAT reload. #28,v,g,n,n,n,PM_DISP_CLB_HELD,CLB Hold: Any Reason ##2090 CLB Hold: Any Reason #29,v,g,n,n,n,PM_DISP_CLB_HELD_BAL,Dispatch/CLB Hold: Balance ##2092 Dispatch/CLB Hold: Balance #30,v,g,n,n,n,PM_DISP_CLB_HELD_RES,Dispatch/CLB Hold: Resource ##2094 Dispatch/CLB Hold: Resource #31,v,g,n,n,n,PM_DISP_CLB_HELD_SB,Dispatch/CLB Hold: Scoreboard ##20A8 Dispatch/CLB Hold: Scoreboard #32,v,g,n,n,n,PM_DISP_CLB_HELD_SYNC,Dispatch/CLB Hold: Sync type instruction ##2098 Dispatch/CLB Hold: Sync type instruction #33,v,g,n,n,n,PM_DISP_CLB_HELD_TLBIE,Dispatch Hold: Due to TLBIE ##2096 Dispatch Hold: Due to TLBIE #34,v,g,n,n,n,PM_DISP_HELD_THERMAL,Dispatch Held due to Thermal ##0006 Dispatch Held due to Thermal #35,v,g,n,n,n,PM_DISP_WT,Dispatched Starved (not held, nothing to dispatch) ##0008 Dispatched Starved (not held, nothing to dispatch) #36,v,g,n,n,n,PM_DSEG,DSEG Exception ##20A6 DSEG Exception #37,v,g,n,n,n,PM_DSLB_MISS,Data SLB Miss - Total of all segment sizes ##D090 A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve. #38,v,g,n,n,n,PM_DTLB_MISS,TLB reload valid ##00FC Data TLB misses, all page sizes. #39,v,g,n,n,n,PM_DTLB_MISS_64K,Data TLB miss for 64K page ##C05E Data TLB references to 64KB pages that missed the TLB. Page size is determined at TLB reload time. #40,v,g,n,n,n,PM_EE_OFF_EXT_INT,ee off and external interrupt ##2080 Cycles when an interrupt due to an external exception is pending but external exceptions were masked. #41,v,g,n,n,n,PM_FLUSH_BR_MPRED,Flush caused by branch mispredict ##2084 A flush was caused by a branch mispredict. #42,v,g,n,n,n,PM_FLUSH_COMPLETION,Completion Flush ##0012 Completion Flush #43,v,g,n,n,n,PM_FLUSH_DISP,Dispatch flush ##2082 Dispatch flush #44,v,g,n,n,n,PM_FLUSH_DISP_SB,Dispatch Flush: Scoreboard ##208C Dispatch Flush: Scoreboard #45,v,g,n,n,n,PM_FLUSH_DISP_SYNC,Dispatch Flush: Sync ##2088 Dispatch Flush: Sync #46,v,g,n,n,n,PM_FLUSH_DISP_TLBIE,Dispatch Flush: TLBIE ##208A Dispatch Flush: TLBIE #47,v,g,n,n,n,PM_FLUSH_PARTIAL,Partial flush ##2086 Partial flush #48,v,g,n,n,n,PM_FREQ_DOWN,Frequency is being slewed down due to Power Management ##000C Processor frequency was slowed down due to power management #49,v,g,n,n,n,PM_FXU0_BUSY_FXU1_IDLE,fxu0 busy and fxu1 idle ##000E FXU0 is busy while FXU1 was idle #50,v,g,n,s,n,PM_GCT_FULL_CYC,Cycles No room in EAT ##4086 The Global Completion Table is completely full. #51,v,g,n,n,n, PM_GCT_UTIL_1_TO_2_SLOTS,GCT Utilization 1-2 entries ##209C GCT Utilization 1-2 entries #52,v,g,n,n,n,PM_GCT_UTIL_11_PLUS_SLOTS,GCT Utilization 11+ entries ##20A2 GCT Utilization 11+ entries #53,v,g,n,n,n,PM_GCT_UTIL_3_TO_6_SLOTS,GCT Utilization 3-6 entries ##209E GCT Utilization 3-6 entries #54,v,g,n,n,n,PM_GCT_UTIL_7_TO_10_SLOTS,GCT Utilization 7-10 entries ##20A0 GCT Utilization 7-10 entries #55,v,g,n,n,n,PM_GRP_CMPL,group completed ##0004 A group completed. Microcoded instructions that span multiple groups will generate this event once per group. #56,v,g,n,n,n,PM_GRP_DISP,dispatch_success (Group Dispatched) ##000A A group was dispatched #57,v,g,n,n,n,PM_IBUF_FULL_CYC,Cycles No room in ibuff ##4084 Cycles with the Instruction Buffer was full. The Instruction Buffer is a circular queue of 64 instructions per thread, organized as 16 groups of 4 instructions. #58,v,g,n,n,n,PM_IC_BANK_CONFLICT,Read blocked due to interleave conflict. ##4082 Read blocked due to interleave conflict. #59,v,g,n,n,n,PM_IC_DEMAND_L2_BHT_REDIRECT, L2 I cache demand request due to BHT redirect ##4098 A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (CR mispredict). #60,v,g,n,n,n,PM_IC_DEMAND_L2_BR_ALL, L2 I cache demand request due to BHT or redirect ##4898 L2 I cache demand request due to BHT or redirect #61,v,g,n,n,n,PM_IC_DEMAND_L2_BR_REDIRECT, L2 I cache demand request due to branch redirect ##409A A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (either ALL mispredicted or Target). #62,v,g,n,n,n,PM_IC_DEMAND_REQ,Demand Instruction fetch request ##4088 Demand Instruction fetch request #63,v,g,n,n,n,PM_IC_PREF_CANCEL_ALL,Prefetch Canceled due to page boundary or icache hit ##4890 Prefetch Canceled due to page boundary or icache hit #64,v,g,n,n,n,PM_IC_PREF_CANCEL_HIT,Prefetch Canceled due to icache hit ##4092 Prefetch Canceled due to icache hit #65,v,g,n,n,n,PM_IC_PREF_CANCEL_L2,L2 Squashed request ##4094 L2 Squashed request #66,v,g,n,n,n,PM_IC_PREF_CANCEL_PAGE,Prefetch Canceled due to page boundary ##4090 Prefetch Canceled due to page boundary #67,v,g,n,n,n,PM_IC_PREF_REQ,Instruction prefetch requests ##408A An instruction prefetch request has been made. #68,v,g,n,n,n,PM_IC_PREF_WRITE,Instruction prefetch written into IL1 ##408E Number of Instruction Cache entries written because of prefetch. Prefetch entries are marked least recently used and are candidates for eviction if they are not needed to satify a demand fetch. #69,v,g,n,n,n,PM_IC_RELOAD_SHR,Reloading line to be shared between the threads ##4096 An Instruction Cache request was made by this thread and the cache line was already in the cache for the other thread. The line is marked valid for all threads. #70,v,g,n,n,n,PM_IC_REQ_ALL,Icache requests, prefetch + demand ##4888 Icache requests, prefetch + demand #71,v,g,n,n,n,PM_IC_WRITE_ALL,Icache sectors written, prefetch + demand ##488C Icache sectors written, prefetch + demand #72,v,g,n,n,n,PM_IERAT_WR_64K,large page 64k ##40BE large page 64k #73,v,g,n,n,n,PM_IERAT_XLATE_WR_16MPLUS,large page 16M+ ##40BC large page 16M+ #74,v,g,n,n,n,PM_INST_CMPL,# PPC Instructions Finished ##0002 Number of PowerPC Instructions that completed. #75,v,g,n,n,n,PM_INST_DISP,# PPC Dispatched ##00F2 Number of PowerPC instructions successfully dispatched. #76,v,g,n,n,n,PM_INST_FROM_DL2L3_MOD,Instruction fetched from distant L2 or L3 modified ##404C An instruction fetch group was fetched with modified (M) data from an L2 or L3 on a distant module. Fetch groups can contain up to 8 instructions #77,v,g,n,n,n,PM_INST_FROM_DL2L3_SHR,Instruction fetched from distant L2 or L3 shared ##4044 An instruction fetch group was fetched with shared (S) data from the L2 or L3 on a distant module. Fetch groups can contain up to 8 instructions #78,v,g,n,n,n,PM_INST_FROM_L1,Instruction fetches from L1 ##4080 An instruction fetch group was fetched from L1. Fetch Groups can contain up to 8 instructions #79,v,g,n,n,n,PM_INST_FROM_L21_MOD,Instruction fetched from another L2 on same chip modified ##4046 Instruction fetched from another L2 on same chip modified #80,v,g,n,n,n,PM_INST_FROM_L21_SHR,Instruction fetched from another L2 on same chip shared ##404E Instruction fetched from another L2 on same chip shared #81,v,g,n,n,n,PM_INST_FROM_LMEM,Instruction fetched from local memory ##404A An instruction fetch group was fetched from memory attached to the same module this proccessor is located on. Fetch groups can contain up to 8 instructions #82,v,g,n,n,n,PM_INST_FROM_RMEM,Instruction fetched from remote memory ##4042 An instruction fetch group was fetched from memory attached to a different module than this proccessor is located on. Fetch groups can contain up to 8 instructions #83,v,g,n,n,n,PM_INST_IMC_MATCH_DISP,IMC Matches dispatched ##0016 IMC Matches dispatched #84,v,g,n,n,n,PM_INST_PTEG_FROM_L21_MOD,Instruction PTEG loaded from another L2 on same chip modified ##E056 Instruction PTEG loaded from another L2 on same chip modified #85,v,g,n,n,n,PM_INST_PTEG_FROM_DL2L3_SHR,Instruction PTEG loaded from remote L2 or L3 shared ##E054 Instruction PTEG loaded from remote L2 or L3 shared #86,v,g,n,n,n,PM_INST_PTEG_FROM_RMEM,Instruction PTEG loaded from remote memory ##E052 Instruction PTEG loaded from remote memory #87,v,g,n,n,n,PM_IOPS_DISP,IOPS dispatched ##0014 IOPS dispatched #88,v,g,n,n,n,PM_ISEG,ISEG Exception ##20A4 ISEG Exception #89,v,g,n,n,n,PM_ISLB_MISS,Instruction SLB Miss - Tota of all segment sizes ##D092 A SLB miss for an instruction fetch as occurred #90,v,g,n,n,n,PM_L1_DCACHE_RELOAD_VALID,L1 reload data source valid ##00F6 The data source information is valid,the data cache has been reloaded. Prior to POWER5+ this included data cache reloads due to prefetch activity. With POWER5+ this now only includes reloads due to demand loads. #91,v,g,n,n,n,PM_L1_DEMAND_WRITE,Instruction Demand sectors wriittent into IL1 ##408C Instruction Demand sectors wriittent into IL1 #92,v,g,n,n,n,PM_L1_PREF,L1 Prefetches ##D8B8 A request to prefetch data into the L1 was made #93,v,g,n,n,n,PM_L2_INST,Instruction Load Count ##6080 Instruction Load Count #94,v,g,n,n,n,PM_L2_INST_MISS,Instruction Load Misses ##6082 Instruction Load Misses #95,v,g,n,s,n,PM_L2_LD_DISP,All successful load dispatches ##6180 All successful load dispatches #96,v,g,n,s,n,PM_L2_LD_HIT,All successful load dispatches that were L2 hits ##6182 A load request (data or instruction) hit in the L2 directory. Includes speculative, prefetched, and demand requests. This event includes all requests to this L2 from all sources. Total for all slices #97,v,g,n,s,n,PM_L2_NODE_PUMP,RC req that was a local (aka node) pump attempt ##6480 RC req that was a local (aka node) pump attempt #98,v,g,n,s,n,PM_L2_RC_ST_DONE,RC did st to line that was Tx or Sx ##6380 RC did st to line that was Tx or Sx #99,v,g,n,s,n,PM_L2_RCST_DISP, L2 RC store dispatch attempt ##6280 L2 RC store dispatch attempt #100,v,g,n,s,n,PM_L2_RCST_DISP_FAIL_ADDR, L2 RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ ##6282 L2 RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ #101,v,g,n,s,n,PM_L2_SN_SX_I_DONE,SNP dispatched and went from Sx or Tx to Ix ##6382 SNP dispatched and went from Sx or Tx to Ix #102,v,g,n,s,n,PM_L2_SYS_PUMP,RC req that was a global (aka system) pump attempt ##6482 RC req that was a global (aka system) pump attempt #103,v,g,n,s,n,PM_L3_PREF_HIT,L3 Prefetch Directory Hit ##F080 L3 Prefetch Directory Hit #104,v,g,n,n,n,PM_L3_PREF_LD,L3 cache LD prefetches ##D0AC L3 cache LD prefetches #105,v,g,n,n,n,PM_L3_PREF_LDST,L3 cache prefetches LD + ST ##D8AC L3 cache prefetches LD + ST #106,v,g,n,s,n,PM_L3_PREF_MISS,L3 Prefetch Directory Miss ##F082 L3 Prefetch Directory Miss #107,v,g,n,n,n,PM_L3_PREF_ST,L3 cache ST prefetches ##D0AE L3 cache ST prefetches #108,v,g,n,n,n,PM_LARX_LSU,Larx Finished ##C894 Larx Finished #109,v,g,n,n,n,PM_LARX_LSU0,ls0 Larx Finished ##C094 A larx (lwarx or ldarx) was executed on side 0 #110,v,g,n,n,n,PM_LARX_LSU1,ls1 Larx Finished ##C096 A larx (lwarx or ldarx) was executed on side 1 #111,v,g,n,n,n,PM_LD_REF_L1, L1 D cache load references counted at finish ##C880 L1 D cache load references counted at finish #112,v,g,n,n,n,PM_LD_REF_L1_LSU0,LS0 L1 D cache load references counted at finish ##C080 Load references to Level 1 Data Cache, by unit 0. #113,v,g,n,n,n,PM_LD_REF_L1_LSU1,LS1 L1 D cache load references counted at finish ##C082 Load references to Level 1 Data Cache, by unit 1. #114,v,g,n,n,n,PM_LSU_DC_PREF_STREAM_ALLOC,D cache new prefetch stream allocated ##D8A8 D cache new prefetch stream allocated #115,v,g,n,n,n,PM_LSU_DC_PREF_STREAM_CONFIRM,Dcache new prefetch stream confirmed ##D8B4 Dcache new prefetch stream confirmed #116,v,g,n,n,n,PM_LSU_DC_PREF_STRIDED_STREAM_CONFIRM,Dcache Strided prefetch stream confirmed (software + hardware) ##D8BC Dcache Strided prefetch stream confirmed (software + hardware) #117,v,g,n,n,n,PM_LSU_DCACHE_RELOAD_VALID,count per sector of lines reloaded in L1 (demand + prefetch) ##D0A2 count per sector of lines reloaded in L1 (demand + prefetch) #118,v,g,n,n,n,PM_LSU_DERAT_MISS,DERAT Reloaded due to a DERAT miss ##C05A Total D-ERAT Misses. Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction. Combined Unit 0 + 1. #119,v,g,n,n,n,PM_LSU_FIN,LSU Finished an instruction (up to 2 per cycle) ##0066 LSU Finished an instruction (up to 2 per cycle) #120,v,g,n,n,n,PM_LSU_FLUSH,Flush initiated by LSU ##208E A flush was initiated by the Load Store Unit. #121,v,g,n,n,n,PM_LSU_FLUSH_LRQ,Flush: LRQ ##C8B8 Load Hit Load or Store Hit Load flush. A younger load was flushed because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. Combined Unit 0 + 1. #122,v,g,n,n,n,PM_LSU_FLUSH_SRQ,Flush: SRQ ##C8BC Load Hit Store flush. A younger load was flushed because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. Combined Unit 0 + 1. #123,v,g,n,n,n,PM_LSU_FLUSH_ULD,Flush: Unaligned Load ##C8B0 A load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1). Combined Unit 0 + 1. #124,v,g,n,n,n,PM_LSU_FLUSH_UST,Flush: Unaligned Store ##C8B4 A store was flushed because it was unaligned (crossed a 4K boundary). Combined Unit 0 + 1. #125,v,g,n,n,n,PM_LSU_LDF,All Scalar Loads ##C884 LSU executed Floating Point load instruction. Combined Unit 0 + 1. #126,v,g,n,n,n,PM_LSU_LDX,All Vector loads (vsx vector + vmx vector) ##C888 All Vector loads (vsx vector + vmx vector) #127,v,g,n,n,n,PM_LSU_LMQ_FULL_CYC,LMQ full ##D0A4 The Load Miss Queue was full. #128,v,g,n,n,n,PM_LSU_LMQ_S0_ALLOC,Slot 0 of LMQ valid ##D0A1 Slot 0 of LMQ valid #129,v,g,n,n,n,PM_LSU_LMQ_S0_VALID,Slot 0 of LMQ valid ##D0A0 This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the LRQ is split between the two threads (16 entries each). #130,v,g,n,c,n,PM_LSU_LMQ_SRQ_EMPTY_ALL_CYC,ALL threads lsu empty (lmq and srq empty) ##001C ALL threads lsu empty (lmq and srq empty) #131,v,g,n,n,n,PM_LSU_LRQ_S0_ALLOC,Slot 0 of LRQ valid ##D09F Slot 0 of LRQ valid #132,v,g,n,n,n,PM_LSU_LRQ_S0_VALID,Slot 0 of LRQ valid ##D09E This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the LRQ is split between the two threads (16 entries each). #133,v,g,n,n,n,PM_LSU_NCLD,Non-cachable Loads counted at finish ##C88C A non-cacheable load was executed. Combined Unit 0 + 1. #134,v,g,n,n,n,PM_LSU_NCST,Non-cachable Stores sent to nest ##C090 Non-cachable Stores sent to nest #135,v,g,n,n,n,PM_LSU_PARTIAL_CDF,A partial cacheline was returned from the L3 ##C0AA A partial cacheline was returned from the L3 #136,v,g,n,n,n,PM_LSU_REJECT_LHS,Reject: Load Hit Store ##C8AC The Load Store Unit rejected a load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully. Combined Unit 0 + 1 #137,v,g,n,n,n,PM_LSU_REJECT_LMQ_FULL,Reject: LMQ Full (LHR) ##C8A4 Total cycles the Load Store Unit is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all the eight entries are full, subsequent load instructions are rejected. Combined unit 0 + 1. #138,v,g,n,n,n,PM_LSU_REJECT_SET_MPRED,Reject: Set Predict Wrong ##C8A8 The Load Store Unit rejected an instruction because the cache set was improperly predicted. This is a fast reject and will be immediately redispatched. Combined Unit 0 + 1 #139,v,g,n,n,n,PM_LSU_SET_MPRED,Line already in cache at reload time ##C0A8 Line already in cache at reload time #140,v,g,n,n,n,PM_LSU_SRQ_S0_ALLOC,Slot 0 of SRQ valid ##D09D Slot 0 of SRQ valid #141,v,g,n,n,n,PM_LSU_SRQ_S0_VALID,Slot 0 of SRQ valid ##D09C This signal is asserted every cycle that the Store Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the SRQ is split between the two threads (16 entries each). #142,v,g,n,n,n,PM_LSU_SRQ_STFWD,Load got data from a store ##C8A0 Data from a store instruction was forwarded to a load. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss. Combined Unit 0 + 1. #143,v,g,n,n,n,PM_LSU_SRQ_SYNC_COUNT,SRQ sync count (edge of PM_LSU_SRQ_SYNC_CYC) ##D097 SRQ sync count (edge of PM_LSU_SRQ_SYNC_CYC) #144,v,g,n,n,n,PM_LSU_SRQ_SYNC_CYC,A sync is in the SRQ ##D096 Cycles that a sync instruction is active in the Store Request Queue. #145,v,g,n,n,n,PM_LSU_TWO_TABLEWALK_CYC,Cycles when two tablewalks pending on this thread ##D0A6 Cycles when two tablewalks pending on this thread #146,v,g,n,n,n,PM_LSU0_DC_PREF_STREAM_ALLOC,LS0 D cache new prefetch stream allocated ##D0A8 LS0 D cache new prefetch stream allocated #147,v,g,n,n,n,PM_LSU0_DC_PREF_STREAM_CONFIRM,LS0 Dcache prefetch stream confirmed ##D0B4 LS0 Dcache prefetch stream confirmed #148,v,g,n,n,n,PM_LSU0_DC_PREF_STREAM_CONFIRM_STRIDE,LS0 Dcache Strided prefetch stream confirmed ##D0BC LS0 Dcache Strided prefetch stream confirmed #149,v,g,n,n,n,PM_LSU0_FLUSH_LRQ,LS0 Flush: LRQ ##C0B8 Load Hit Load or Store Hit Load flush. A younger load was flushed from unit 0 because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. #150,v,g,n,n,n,PM_LSU0_FLUSH_SRQ,LS0 Flush: SRQ ##C0BC Load Hit Store flush. A younger load was flushed from unit 0 because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. #151,v,g,n,n,n,PM_LSU0_FLUSH_ULD,LS0 Flush: Unaligned Load ##C0B0 A load was flushed from unit 0 because it was unaligned (crossed a 64 byte boundary, or 32 byte if it missed the L1) #152,v,g,n,n,n,PM_LSU0_FLUSH_UST,LS0 Flush: Unaligned Store ##C0B4 A store was flushed from unit 0 because it was unaligned (crossed a 4K boundary). #153,v,g,n,n,n,PM_LSU0_L1_PREF, LS0 L1 cache data prefetches ##D0B8 LS0 L1 cache data prefetches #154,v,g,n,n,n,PM_LSU0_L1_SW_PREF,LSU0 Software L1 Prefetches, including SW Transient Prefetches ##C09C LSU0 Software L1 Prefetches, including SW Transient Prefetches #155,v,g,n,n,n,PM_LSU0_LDF,LS0 Scalar Loads ##C084 A floating point load was executed by LSU0 #156,v,g,n,n,n,PM_LSU0_LDX,LS0 Vector Loads ##C088 LS0 Vector Loads #157,v,g,n,n,n,PM_LSU0_LMQ_LHR_MERGE,LS0 Load Merged with another cacheline request ##D098 LS0 Load Merged with another cacheline request #158,v,g,n,n,n,PM_LSU0_NCLD,LS0 Non-cachable Loads counted at finish ##C08C A non-cacheable load was executed by unit 0. #159,v,g,n,n,n,PM_LSU0_REJECT_LHS,LS0 Reject: Load Hit Store ##C0AC Load Store Unit 0 rejected a load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully. #160,v,g,n,n,n,PM_LSU0_REJECT_LMQ_FULL,LS0 Reject: LMQ Full (LHR) ##C0A4 Total cycles the Load Store Unit 0 is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all eight entries are full, subsequent load instructions are rejected. #161,v,g,n,n,n,PM_LSU0_SRQ_STFWD,LS0 SRQ forwarded data to a load ##C0A0 Data from a store instruction was forwarded to a load on unit 0. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss. #162,v,g,n,n,n,PM_LSU1_DC_PREF_STREAM_ALLOC,LS 1 D cache new prefetch stream allocated ##D0AA LS 1 D cache new prefetch stream allocated #163,v,g,n,n,n,PM_LSU1_DC_PREF_STREAM_CONFIRM,LS1 'Dcache prefetch stream confirmed ##D0B6 LS1 'Dcache prefetch stream confirmed #164,v,g,n,n,n,PM_LSU1_DC_PREF_STREAM_CONFIRM_STRIDE,LS1 Dcache Strided prefetch stream confirmed ##D0BE LS1 Dcache Strided prefetch stream confirmed #165,v,g,n,n,n,PM_LSU1_FLUSH_LRQ,LS1 Flush: LRQ ##C0BA Load Hit Load or Store Hit Load flush. A younger load was flushed from unit 1 because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. #166,v,g,n,n,n,PM_LSU1_FLUSH_SRQ,LS1 Flush: SRQ ##C0BE Load Hit Store flush. A younger load was flushed from unit 1 because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. #167,v,g,n,n,n,PM_LSU1_FLUSH_ULD,LS 1 Flush: Unaligned Load ##C0B2 A load was flushed from unit 1 because it was unaligned (crossed a 64 byte boundary, or 32 byte if it missed the L1). #168,v,g,n,n,n,PM_LSU1_FLUSH_UST,LS1 Flush: Unaligned Store ##C0B6 A store was flushed from unit 1 because it was unaligned (crossed a 4K boundary) #169,v,g,n,n,n,PM_LSU1_L1_PREF, LS1 L1 cache data prefetches ##D0BA LS1 L1 cache data prefetches #170,v,g,n,n,n,PM_LSU1_L1_SW_PREF,LSU1 Software L1 Prefetches, including SW Transient Prefetches ##C09E LSU1 Software L1 Prefetches, including SW Transient Prefetches #171,v,g,n,n,n,PM_LSU1_LDF,LS1 Scalar Loads ##C086 A floating point load was executed by LSU1 #172,v,g,n,n,n,PM_LSU1_LDX,LS1 Vector Loads ##C08A LS1 Vector Loads #173,v,g,n,n,n,PM_LSU1_LMQ_LHR_MERGE,LS1 Load Merge with another cacheline request ##D09A LS1 Load Merge with another cacheline request #174,v,g,n,n,n,PM_LSU1_NCLD,LS1 Non-cachable Loads counted at finish ##C08E A non-cacheable load was executed by Unit 0. #175,v,g,n,n,n,PM_LSU1_REJECT_LHS,LS1 Reject: Load Hit Store ##C0AE Load Store Unit 1 rejected a load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully. #176,v,g,n,n,n,PM_LSU1_REJECT_LMQ_FULL,LS1 Reject: LMQ Full (LHR) ##C0A6 Total cycles the Load Store Unit 1 is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all eight entries are full, subsequent load instructions are rejected. #177,v,g,n,n,n,PM_LSU1_SRQ_STFWD,LS1 SRQ forwarded data to a load ##C0A2 Data from a store instruction was forwarded to a load on unit 1. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss. #178,v,g,n,n,n,PM_LWSYNC,lwsync count (easier to use than IMC) ##D094 lwsync count (easier to use than IMC) #179,v,g,n,n,n,PM_LWSYNC_HELD,LWSYNC held at dispatch ##209A Cycles a LWSYNC instruction was held at dispatch. LWSYNC instructions are held at dispatch until all previous loads are done and all previous stores have issued. LWSYNC enters the Store Request Queue and is sent to the storage subsystem but does not wait for a response. #180,v,g,n,n,m,PM_MRK_BR_MPRED,Marked Branch Mispredicted ##0036 A marked branch was mispredicted #181,v,g,n,n,m,PM_MRK_DATA_FROM_DL2L3_MOD,Marked data loaded from distant L2 or L3 modified ##D04C The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a distant module due to a marked load. #182,v,g,n,n,m,PM_MRK_DATA_FROM_DL2L3_SHR,Marked data loaded from distant L2 or L3 shared ##D044 The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a distant module due to a marked load. #183,v,g,n,n,m,PM_MRK_DATA_FROM_L21_MOD,Marked data loaded from another L2 on same chip modified ##D046 Marked data loaded from another L2 on same chip modified #184,v,g,n,n,m,PM_MRK_DATA_FROM_L21_SHR,Marked data loaded from another L2 on same chip shared ##D04E Marked data loaded from another L2 on same chip shared #185,v,g,n,n,m,PM_MRK_DATA_FROM_LMEM,Marked data loaded from local memory ##D04A The processor’s Data Cache was reloaded due to a marked load from memory attached to the same module this proccessor is located on. #186,v,g,n,n,m,PM_MRK_DATA_FROM_RMEM,Marked data loaded from remote memory ##D042 The processor’s Data Cache was reloaded due to a marked load from memory attached to a different module than this proccessor is located on. #187,v,g,n,n,m,PM_MRK_DERAT_MISS_16M,Marked DERAT misses for 16M page ##D05C A marked data request (load or store) missed the ERAT for 16M page and resulted in an ERAT reload. #188,v,g,n,n,m,PM_MRK_DTLB_MISS_64K,Marked Data TLB misses for 64K page ##D05E Data TLB references to 64KB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time. #189,v,g,n,n,m,PM_MRK_IFU_FIN,IFU non-branch marked instruction finished ##003A The Instruction Fetch Unit finished a marked instruction. #190,v,g,t,n,m,PM_MRK_INST_FIN,marked instr finish any unit ##0030 One of the execution units finished a marked instruction. Instructions that finish may not necessary complete #191,v,g,n,n,m,PM_MRK_LSU_DERAT_MISS,Marked DERAT Miss ##D05A Marked DERAT Miss #192,v,g,n,n,m,PM_MRK_LSU_FLUSH,Flush: (marked) : All Cases ##D08C Marked flush initiated by LSU #193,v,g,n,n,m,PM_MRK_LSU_FLUSH_LRQ,Flush: (marked) LRQ ##D088 Load Hit Load or Store Hit Load flush. A marked load was flushed because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. #194,v,g,n,n,m,PM_MRK_LSU_FLUSH_SRQ,Flush: (marked) SRQ ##D08A Load Hit Store flush. A marked load was flushed because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. #195,v,g,n,n,m,PM_MRK_LSU_FLUSH_ULD,Flush: (marked) Unaligned Load ##D084 A marked load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1) #196,v,g,n,n,m,PM_MRK_LSU_FLUSH_UST,Flush: (marked) Unaligned Store ##D086 A marked store was flushed because it was unaligned #197,v,g,n,n,m,PM_MRK_LSU_PARTIAL_CDF,A partial cacheline was returned from the L3 for a marked load ##D080 A partial cacheline was returned from the L3 for a marked load #198,v,g,n,n,m,PM_MRK_LSU_REJECT_ERAT_MISS,LSU marked reject due to ERAT (up to 2 per cycle) ##0064 LSU marked reject due to ERAT (up to 2 per cycle) #199,v,g,n,n,m,PM_MRK_LSU_REJECT_LHS, Reject(marked): Load Hit Store ##D082 The Load Store Unit rejected a marked load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully #200,v,g,n,n,m,PM_MRK_PTEG_FROM_L21_MOD,Marked PTEG loaded from another L2 on same chip modified ##D056 Marked PTEG loaded from another L2 on same chip modified #201,v,g,n,n,m,PM_MRK_PTEG_FROM_DL2L3_SHR,Marked PTEG loaded from remote L2 or L3 shared ##D054 A Page Table Entry was loaded into the ERAT from memory attached to a different module than this proccessor is located on due to a marked load or store. #202,v,g,n,n,m,PM_MRK_PTEG_FROM_RMEM,Marked PTEG loaded from remote memory ##D052 A Page Table Entry was loaded into the ERAT. POWER6 does not have a TLB #203,v,g,n,n,m,PM_MRK_ST_CMPL_INT,marked store complete (data home) with intervention ##0034 A marked store previously sent to the memory subsystem completed (data home) after requiring intervention #204,v,g,n,n,m,PM_MRK_STALL_CMPLU_CYC,Marked Group Completion Stall cycles ##003E Marked Group Completion Stall cycles #205,v,g,n,n,m,PM_MRK_STALL_CMPLU_CYC_COUNT,Marked Group Completion Stall cycles (use edge detect to count #) ##003F Marked Group Completion Stall cycles (use edge detect to count #) #206,v,g,n,n,m,PM_MRK_STCX_FAIL,Marked STCX failed ##D08E A marked stcx (stwcx or stdcx) failed #207,v,g,n,n,m,PM_MRK_VSU_FIN,vsu (fpu) marked instr finish ##0032 vsu (fpu) marked instr finish #208,v,g,n,c,n,PM_PB_RETRY_NODE_PUMP, Nest events (MC0/MC1/PB/GX), Pair2 Bit0 ##0081 Nest events (MC0/MC1/PB/GX), Pair2 Bit0 #209,v,g,n,c,n,PM_MEM0_PB_RD_CL, Nest events (MC0/MC1/PB/GX), Pair2 Bit1 ##0083 Nest events (MC0/MC1/PB/GX), Pair2 Bit1 #210,v,g,n,c,n,PM_NEST_PAIR2_ADD, Nest events (MC0/MC1/PB/GX), Pair2 ADD ##0881 Nest events (MC0/MC1/PB/GX), Pair2 ADD #211,v,g,n,c,n,PM_NEST_PAIR2_AND, Nest events (MC0/MC1/PB/GX), Pair2 AND ##0883 Nest events (MC0/MC1/PB/GX), Pair2 AND #212,v,g,n,n,n,PM_PMC2_OVERFLOW,Overflow from counter 2 ##0010 Overflows from PMC2 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow. #213,v,g,n,n,n,PM_PMC2_REWIND,PMC2 Rewind Event (did not match condition) ##0020 PMC2 was counting speculatively. The speculative condition was not met and the counter was restored to its previous value. #214,v,g,n,n,n,PM_PMC4_SAVED,PMC4 Rewind Value saved (matched condition) ##0022 PMC4 was counting speculatively. The speculative condition was met and the counter value was committed by copying it to the backup register. #215,v,g,n,n,n,PM_PMC6_OVERFLOW,Overflow from counter 6 ##0024 Overflows from PMC6 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow. #216,v,g,n,n,n,PM_POWER_EVENT3,Power Management Event 3 ##006E Power Management Event 3 #217,v,g,n,n,n,PM_PTEG_FROM_L21_MOD,PTEG loaded from another L2 on same chip modified ##C056 PTEG loaded from another L2 on same chip modified #218,v,g,n,n,n,PM_PTEG_FROM_DL2L3_SHR,PTEG loaded from remote L2 or L3 shared ##C054 A Page Table Entry was loaded into the ERAT with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load or store. #219,v,g,n,n,n,PM_PTEG_FROM_RMEM,PTEG loaded from remote memory ##C052 A Page Table Entry was loaded into the TLB from memory attached to a different module than this proccessor is located on. #220,v,g,n,n,n,PM_SEG_EXCEPTION,ISEG + DSEG Exception ##28A4 ISEG + DSEG Exception #221,v,g,n,n,n,PM_SHL_CREATED,SHL table entry Created ##5082 SHL table entry Created #222,v,g,n,n,n,PM_SHL_DEALLOCATED,SHL Table entry deallocated ##5080 SHL Table entry deallocated #223,v,g,n,n,n,PM_SHL_MATCH,SHL Table Match ##5086 SHL Table Match #224,v,g,n,n,n,PM_SHL_MERGED,SHL table entry merged with existing ##5084 SHL table entry merged with existing #225,v,g,n,n,n,PM_SLB_MISS,Data + Instruction SLB Miss - Total of all segment sizes ##D890 Total of all Segment Lookaside Buffer (SLB) misses, Instructions + Data. #226,v,g,n,c,n,PM_SNOOP_TLBIE,TLBIE snoop ##D0B2 A tlbie was snooped from another processor. #227,v,g,n,n,n,PM_ST_MISS_L1,L1 D cache store misses ##00F0 A store missed the dcache. Combined Unit 0 + 1. #228,v,g,n,n,n,PM_STCX_CMPL,STCX executed ##C098 Conditional stores with reservation completed #229,v,g,n,n,n,PM_STCX_FAIL,STCX failed ##C09A A stcx (stwcx or stdcx) failed #230,v,g,n,n,n,PM_SUSPENDED,Counter OFF ##0000 The counter is suspended (does not count) #231,v,g,n,c,n,PM_TB_BIT_TRANS,Time Base bit transition ##00F8 When the selected time base bit (as specified in MMCR0[TBSEL])transitions from 0 to 1 #232,v,g,n,c,n,PM_THRD_3_RUN_CYC,3 thread in Run Cycles ##0060 3 thread in Run Cycles #233,v,g,n,c,n,PM_THRD_CONC_RUN_INST,Concurrent Run Instructions ##00F4 Instructions completed by this thread when both threads had their run latches set. #234,v,g,n,n,n,PM_THRD_PRIO_0_1_CYC, Cycles thread running at priority level 0 or 1 ##40B0 Cycles thread running at priority level 0 or 1 #235,v,g,n,n,n,PM_THRD_PRIO_2_3_CYC, Cycles thread running at priority level 2 or 3 ##40B2 Cycles thread running at priority level 2 or 3 #236,v,g,n,n,n,PM_THRD_PRIO_4_5_CYC, Cycles thread running at priority level 4 or 5 ##40B4 Cycles thread running at priority level 4 or 5 #237,v,g,n,n,n,PM_THRD_PRIO_6_7_CYC, Cycles thread running at priority level 6 or 7 ##40B6 Cycles thread running at priority level 6 or 7 #238,v,g,n,n,n,PM_VMX_RESULT_SAT_1,Valid result with sat=1 ##B0A0 Valid result with sat=1 #239,v,g,n,n,n,PM_VSU_1FLOP,one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished ##A880 one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished #240,v,g,n,n,n,PM_VSU_2FLOP,two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) ##A898 two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) #241,v,g,n,n,n,PM_VSU_2FLOP_DOUBLE,DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg ##A88C DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg #242,v,g,n,n,n,PM_VSU_4FLOP,four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions) ##A89C four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions) #243,v,g,n,n,n,PM_VSU_8FLOP,eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) ##A8A0 eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) #244,v,g,n,n,n,PM_VSU_DENORM,Vector or Scalar denorm operand ##A8AC Vector or Scalar denorm operand #245,v,g,n,n,n,PM_VSU_FCONV,Convert instruction executed ##A8B0 Convert instruction executed #246,v,g,n,n,n,PM_VSU_FEST,Estimate instruction executed ##A8B8 Estimate instruction executed #247,v,g,n,n,n,PM_VSU_FIN,VSU0 Finished an instruction ##A8BC VSU0 Finished an instruction #248,v,g,n,n,n,PM_VSU_FMA,two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only! ##A884 two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only! #249,v,g,n,n,n,PM_VSU_FMA_DOUBLE,DP vector version of fmadd,fnmadd,fmsub,fnmsub ##A890 DP vector version of fmadd,fnmadd,fmsub,fnmsub #250,v,g,n,n,n,PM_VSU_FRSP,Round to single precision instruction executed ##A8B4 Round to single precision instruction executed #251,v,g,n,n,n,PM_VSU_FSQRT_FDIV,four flops operation (fdiv,fsqrt) Scalar Instructions only! ##A888 DP vector versions of fdiv,fsqrt #252,v,g,n,n,n,PM_VSU_FSQRT_FDIV_DOUBLE,DP vector versions of fdiv,fsqrt ##A894 DP vector versions of fdiv,fsqrt #253,v,g,n,n,n,PM_VSU_SCALAR_DOUBLE_ISSUED,Double Precision scalar instruction issued on Pipe0 ##B888 Double Precision scalar instruction issued on Pipe0 #254,v,g,n,n,n,PM_VSU_SCALAR_SINGLE_ISSUED,Single Precision scalar instruction issued on Pipe0 ##B884 Single Precision scalar instruction issued on Pipe0 #255,v,g,n,n,n,PM_VSU_SIMPLE_ISSUED,Simple VMX instruction issued ##B894 Simple VMX instruction issued #256,v,g,n,n,n,PM_VSU_SINGLE,Vector or Scalar single precision ##A8A8 Vector or Scalar single precision #257,v,g,n,n,n,PM_VSU_STF,FPU store (SP or DP) issued on Pipe0 ##B88C FPU store (SP or DP) issued on Pipe0 #258,v,g,n,n,n,PM_VSU_VECTOR_DOUBLE_ISSUED,Double Precision vector instruction issued on Pipe0 ##B880 Double Precision vector instruction issued on Pipe0 #259,v,g,n,n,n,PM_VSU_VECTOR_SINGLE_ISSUED,Single Precision vector instruction issued (executed) ##B890 Single Precision vector instruction issued (executed) #260,v,g,n,n,n,PM_VSU0_16FLOP,Sixteen flops operation (SP vector versions of fdiv,fsqrt) ##A0A4 Sixteen flops operation (SP vector versions of fdiv,fsqrt) #261,v,g,n,n,n,PM_VSU0_1FLOP,one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg, xsadd, xsmul, xssub, xscmp, xssel, xsabs, xsnabs, xsre, xssqrte, xsneg) operation finished ##A080 one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg, xsadd, xsmul, xssub, xscmp, xssel, xsabs, xsnabs, xsre, xssqrte, xsneg) operation finished #262,v,g,n,n,n,PM_VSU0_2FLOP,two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) ##A098 two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) #263,v,g,n,n,n,PM_VSU0_2FLOP_DOUBLE,two flop DP vector operation (xvadddp, xvmuldp, xvsubdp, xvcmpdp, xvseldp, xvabsdp, xvnabsdp, xvredp ,xvsqrtedp, vxnegdp) ##A08C two flop DP vector operation (xvadddp, xvmuldp, xvsubdp, xvcmpdp, xvseldp, xvabsdp, xvnabsdp, xvredp ,xvsqrtedp, vxnegdp) #264,v,g,n,n,n,PM_VSU0_4FLOP,four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions) ##A09C four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions) #265,v,g,n,n,n,PM_VSU0_8FLOP,eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) ##A0A0 eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) #266,v,g,n,n,n,PM_VSU0_COMPLEX_ISSUED,Complex VMX instruction issued ##B096 Complex VMX instruction issued #267,v,g,n,n,n,PM_VSU0_DENORM,FPU denorm operand ##A0AC VSU0 received denormalized data #268,v,g,n,n,n,PM_VSU0_FCONV,Convert instruction executed ##A0B0 Convert instruction executed #269,v,g,n,n,n,PM_VSU0_FEST,Estimate instruction executed ##A0B8 Estimate instruction executed #270,v,g,n,n,n,PM_VSU0_FIN,VSU0 Finished an instruction ##A0BC VSU0 Finished an instruction #271,v,g,n,n,n,PM_VSU0_FMA,two flops operation (fmadd, fnmadd, fmsub, fnmsub, xsmadd, xsnmadd, xsmsub, xsnmsub) Scalar instructions only! ##A084 two flops operation (fmadd, fnmadd, fmsub, fnmsub, xsmadd, xsnmadd, xsmsub, xsnmsub) Scalar instructions only! #272,v,g,n,n,n,PM_VSU0_FMA_DOUBLE,four flop DP vector operations (xvmadddp, xvnmadddp, xvmsubdp, xvmsubdp) ##A090 four flop DP vector operations (xvmadddp, xvnmadddp, xvmsubdp, xvmsubdp) #273,v,g,n,n,n,PM_VSU0_FPSCR,Move to/from FPSCR type instruction issued on Pipe 0 ##B09C Move to/from FPSCR type instruction issued on Pipe 0 #274,v,g,n,n,n,PM_VSU0_FRSP,Round to single precision instruction executed ##A0B4 Round to single precision instruction executed #275,v,g,n,n,n,PM_VSU0_FSQRT_FDIV,four flops operation (fdiv,fsqrt,xsdiv,xssqrt) Scalar Instructions only! ##A088 four flops operation (fdiv,fsqrt,xsdiv,xssqrt) Scalar Instructions only! #276,v,g,n,n,n,PM_VSU0_FSQRT_FDIV_DOUBLE,eight flop DP vector operations (xvfdivdp, xvsqrtdp ##A094 eight flop DP vector operations (xvfdivdp, xvsqrtdp #277,v,g,n,n,n,PM_VSU0_SCAL_DOUBLE_ISSUED,Double Precision scalar instruction issued on Pipe0 ##B088 Double Precision scalar instruction issued on Pipe0 #278,v,g,n,n,n,PM_VSU0_SCAL_SINGLE_ISSUED,Single Precision scalar instruction issued on Pipe0 ##B084 Single Precision scalar instruction issued on Pipe0 #279,v,g,n,n,n,PM_VSU0_SIMPLE_ISSUED,Simple VMX instruction issued ##B094 Simple VMX instruction issued #280,v,g,n,n,n,PM_VSU0_SINGLE,FPU single precision ##A0A8 VSU0 executed single precision instruction #281,v,g,n,n,n,PM_VSU0_STF,FPU store (SP or DP) issued on Pipe0 ##B08C FPU store (SP or DP) issued on Pipe0 #282,v,g,n,n,n,PM_VSU0_VECT_DOUBLE_ISSUED,Double Precision vector instruction issued on Pipe0 ##B080 Double Precision vector instruction issued on Pipe0 #283,v,g,n,n,n,PM_VSU0_VECTOR_SP_ISSUED,Single Precision vector instruction issued (executed) ##B090 Single Precision vector instruction issued (executed) #284,v,g,n,n,n,PM_VSU1_1FLOP,one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg, xsadd, xsmul, xssub, xscmp, xssel, xsabs, xsnabs, xsre, xssqrte, xsneg) operation finished ##A082 one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg, xsadd, xsmul, xssub, xscmp, xssel, xsabs, xsnabs, xsre, xssqrte, xsneg) operation finished #285,v,g,n,n,n,PM_VSU1_2FLOP,two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) ##A09A two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) #286,v,g,n,n,n,PM_VSU1_2FLOP_DOUBLE,two flop DP vector operation (xvadddp, xvmuldp, xvsubdp, xvcmpdp, xvseldp, xvabsdp, xvnabsdp, xvredp ,xvsqrtedp, vxnegdp) ##A08E two flop DP vector operation (xvadddp, xvmuldp, xvsubdp, xvcmpdp, xvseldp, xvabsdp, xvnabsdp, xvredp ,xvsqrtedp, vxnegdp) #287,v,g,n,n,n,PM_VSU1_4FLOP,four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions) ##A09E four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions) #288,v,g,n,n,n,PM_VSU1_8FLOP,eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) ##A0A2 eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) #289,v,g,n,n,n,PM_VSU1_DD_ISSUED,64BIT Decimal Issued on Pipe1 ##B098 64BIT Decimal Issued on Pipe1 #290,v,g,n,n,n,PM_VSU1_DENORM,FPU denorm operand ##A0AE VSU1 received denormalized data #291,v,g,n,n,n,PM_VSU1_DQ_ISSUED,128BIT Decimal Issued on Pipe1 ##B09A 128BIT Decimal Issued on Pipe1 #292,v,g,n,n,n,PM_VSU1_FCONV,Convert instruction executed ##A0B2 Convert instruction executed #293,v,g,n,n,n,PM_VSU1_FEST,Estimate instruction executed ##A0BA Estimate instruction executed #294,v,g,n,n,n,PM_VSU1_FIN,VSU1 Finished an instruction ##A0BE VSU1 Finished an instruction #295,v,g,n,n,n,PM_VSU1_FMA,two flops operation (fmadd, fnmadd, fmsub, fnmsub, xsmadd, xsnmadd, xsmsub, xsnmsub) Scalar instructions only! ##A086 two flops operation (fmadd, fnmadd, fmsub, fnmsub, xsmadd, xsnmadd, xsmsub, xsnmsub) Scalar instructions only! #296,v,g,n,n,n,PM_VSU1_FMA_DOUBLE,four flop DP vector operations (xvmadddp, xvnmadddp, xvmsubdp, xvmsubdp) ##A092 four flop DP vector operations (xvmadddp, xvnmadddp, xvmsubdp, xvmsubdp) #297,v,g,n,n,n,PM_VSU1_FRSP,Round to single precision instruction executed ##A0B6 Round to single precision instruction executed #298,v,g,n,n,n,PM_VSU1_FSQRT_FDIV,four flops operation (fdiv,fsqrt,xsdiv,xssqrt) Scalar Instructions only! ##A08A four flops operation (fdiv,fsqrt,xsdiv,xssqrt) Scalar Instructions only! #299,v,g,n,n,n,PM_VSU1_FSQRT_FDIV_DOUBLE,eight flop DP vector operations (xvfdivdp, xvsqrtdp ##A096 eight flop DP vector operations (xvfdivdp, xvsqrtdp #300,v,g,n,n,n,PM_VSU1_PERMUTE_ISSUED,Permute VMX Instruction Issued ##B092 Permute VMX Instruction Issued #301,v,g,n,n,n,PM_VSU1_SCAL_DOUBLE_ISSUED,Double Precision scalar instruction issued on Pipe1 ##B08A Double Precision scalar instruction issued on Pipe1 #302,v,g,n,n,n,PM_VSU1_SCAL_SINGLE_ISSUED,Single Precision scalar instruction issued on Pipe1 ##B086 Single Precision scalar instruction issued on Pipe1 #303,v,g,n,n,n,PM_VSU1_SINGLE,FPU single precision ##A0AA VSU1 executed single precision instruction #304,v,g,n,n,n,PM_VSU1_SQ,Store Vector Issued on Pipe1 ##B09E Store Vector Issued on Pipe1 #305,v,g,n,n,n,PM_VSU1_STF,FPU store (SP or DP) issued on Pipe1 ##B08E FPU store (SP or DP) issued on Pipe1 #306,v,g,n,n,n,PM_VSU1_VECT_DOUBLE_ISSUED,Double Precision vector instruction issued on Pipe1 ##B082 Double Precision vector instruction issued on Pipe1 $$$$$$$$ { counter 4 } #0,v,g,n,n,n,PM_1PLUS_PPC_DISP,Cycles at least one Instr Dispatched ##00F2 A group containing at least one PPC instruction was dispatched. For microcoded instructions that span multiple groups, this will only occur once. #1,v,g,n,n,n,PM_BC_PLUS_8_CONV,BC+8 Converted ##40B8 BC+8 Converted #2,v,g,n,n,n,PM_BC_PLUS_8_RSLV_TAKEN,BC+8 Resolve outcome was Taken, resulting in the conditional instruction being canceled ##40BA BC+8 Resolve outcome was Taken, resulting in the conditional instruction being canceled #3,v,g,n,n,n,PM_BR_MPRED,Number of Branch Mispredicts ##00F6 A branch instruction was incorrectly predicted. This could have been a target prediction, a condition prediction, or both #4,v,g,n,n,n,PM_BR_MPRED_CCACHE,Branch Mispredict due to Count Cache prediction ##40A4 A branch instruction target was incorrectly predicted by the count cache. This will result in a branch redirect flush if not overwritten by a flush of an older instruction. #5,v,g,n,n,n,PM_BR_MPRED_CR,Branch mispredict - taken/not taken ##40AC A conditional branch instruction was incorrectly predicted as taken or not taken. The branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This will result in a branch redirect flush if not overfidden by a flush of an older instruction. #6,v,g,n,n,n,PM_BR_MPRED_CR_TA,Branch mispredict - taken/not taken and target ##48AE Branch mispredict - taken/not taken and target #7,v,g,n,n,n,PM_BR_MPRED_LSTACK,Branch Mispredict due to Link Stack ##40A6 Branch Mispredict due to Link Stack #8,v,g,n,n,n,PM_BR_MPRED_TA,Branch mispredict - target address ##40AE A branch instruction target was incorrectly predicted. This will result in a branch mispredict flush unless a flush is detected from an older instruction. #9,v,g,n,n,n,PM_BR_PRED,Branch Predictions made ##409C A branch prediction was made. This could have been a target prediction, a condition prediction, or both #10,v,g,n,n,n,PM_BR_PRED_CCACHE,Count Cache Predictions ##40A0 The count value of a Branch and Count instruction was predicted #11,v,g,n,n,n,PM_BR_PRED_CR,Branch predict - taken/not taken ##40A8 A conditional branch instruction was predicted as taken or not taken. #12,v,g,n,n,n,PM_BR_PRED_CR_TA,Branch predict - taken/not taken and target ##48AA Both the condition (taken or not taken) and the target address of a branch instruction was predicted. #13,v,g,n,n,n,PM_BR_PRED_LSTACK,Link Stack Predictions ##40A2 The target address of a Branch to Link instruction was predicted by the link stack. #14,v,g,n,n,n,PM_BR_PRED_TA,Branch predict - target address ##40AA The target address of a branch instruction was predicted. #15,v,g,n,n,n,PM_BR_UNCOND,Unconditional Branch ##409E An unconditional branch was executed. #16,v,g,n,n,n,PM_BTAC_HIT,BTAC Correct Prediction ##508A BTAC Correct Prediction #17,v,g,n,n,n,PM_BTAC_MISS,BTAC Mispredicted ##5088 BTAC Mispredicted #18,v,g,n,n,n,PM_CMPLU_STALL,No groups completed, GCT not empty ##000A No groups completed, GCT not empty #19,v,g,n,n,n,PM_CMPLU_STALL_BRU,Completion stall due to BRU ##004E Completion stall due to BRU #20,v,g,n,n,n,PM_CMPLU_STALL_COUNT,No groups completed, GCT not empty ##000B Count of Cycles where a thread was not completing any groups , when the group completion table had entries for that thread. #21,v,g,n,n,n,PM_CMPLU_STALL_DIV,Completion stall caused by DIV instruction ##0014 Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a fixed point divide instruction. This is a subset of PM_CMPLU_STALL_FXU. #22,v,g,n,n,n,PM_CMPLU_STALL_ERAT_MISS,Completion stall caused by ERAT miss ##0018 Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered an ERAT miss. This is a subset of PM_CMPLU_STALL_REJECT. #23,v,g,n,n,n,PM_CMPLU_STALL_IFU,Completion stall due to IFU ##004C Completion stall due to IFU #24,v,g,n,n,n,PM_CMPLU_STALL_REJECT,Completion stall caused by reject ##0016 Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered a load/store reject. This is a subset of PM_CMPLU_STALL_LSU. #25,v,g,n,n,n,PM_CMPLU_STALL_SCALAR,Completion stall caused by FPU instruction ##0012 Completion stall caused by FPU instruction #26,v,g,n,n,n,PM_CMPLU_STALL_VECTOR_LONG,completion stall due to long latency vector instruction ##004A completion stall due to long latency vector instruction #27,v,g,n,s,n,PM_CYC,Cycles ##001E Processor Cycles #28,v,g,n,n,n,PM_DATA_FROM_DL2L3_MOD,Data loaded from distant L2 or L3 modified ##C044 The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a distant module due to a demand load #29,v,g,n,n,n,PM_DATA_FROM_L21_SHR,Data loaded from another L2 on same chip shared ##C046 Data loaded from another L2 on same chip shared #30,v,g,n,n,n,PM_DATA_FROM_L2MISS,Demand LD - L2 Miss (not L2 hit) ##C048 The processor's Data Cache was reloaded but not from the local L2. #31,v,g,n,n,n,PM_DATA_FROM_LMEM,Data loaded from local memory ##C042 The processor’s Data Cache was reloaded from memory attached to the same module this proccessor is located on. #32,v,g,n,n,n,PM_DC_PREF_DST,Data Stream Touch ##D0B0 A prefetch stream was started using the DST instruction. #33,v,g,n,n,n,PM_DERAT_MISS_16G,DERAT misses for 16G page ##C05C A data request (load or store) missed the ERAT for 16G page and resulted in an ERAT reload. #34,v,g,n,n,n,PM_DISP_CLB_HELD,CLB Hold: Any Reason ##2090 CLB Hold: Any Reason #35,v,g,n,n,n,PM_DISP_CLB_HELD_BAL,Dispatch/CLB Hold: Balance ##2092 Dispatch/CLB Hold: Balance #36,v,g,n,n,n,PM_DISP_CLB_HELD_RES,Dispatch/CLB Hold: Resource ##2094 Dispatch/CLB Hold: Resource #37,v,g,n,n,n,PM_DISP_CLB_HELD_SB,Dispatch/CLB Hold: Scoreboard ##20A8 Dispatch/CLB Hold: Scoreboard #38,v,g,n,n,n,PM_DISP_CLB_HELD_SYNC,Dispatch/CLB Hold: Sync type instruction ##2098 Dispatch/CLB Hold: Sync type instruction #39,v,g,n,n,n,PM_DISP_CLB_HELD_TLBIE,Dispatch Hold: Due to TLBIE ##2096 Dispatch Hold: Due to TLBIE #40,v,g,n,n,n,PM_DSEG,DSEG Exception ##20A6 DSEG Exception #41,v,g,n,n,n,PM_DSLB_MISS,Data SLB Miss - Total of all segment sizes ##D090 A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve. #42,v,g,n,n,n,PM_DTLB_MISS_16M,Data TLB miss for 16M page ##C05E Data TLB references to 16MB pages that missed the TLB. Page size is determined at TLB reload time. #43,v,g,n,n,n,PM_EE_OFF_EXT_INT,ee off and external interrupt ##2080 Cycles when an interrupt due to an external exception is pending but external exceptions were masked. #44,v,g,n,n,n,PM_FLUSH,Flush (any type) ##00F8 Flushes occurred including LSU and Branch flushes. #45,v,g,n,n,n,PM_FLUSH_BR_MPRED,Flush caused by branch mispredict ##2084 A flush was caused by a branch mispredict. #46,v,g,n,n,n,PM_FLUSH_DISP,Dispatch flush ##2082 Dispatch flush #47,v,g,n,n,n,PM_FLUSH_DISP_SB,Dispatch Flush: Scoreboard ##208C Dispatch Flush: Scoreboard #48,v,g,n,n,n,PM_FLUSH_DISP_SYNC,Dispatch Flush: Sync ##2088 Dispatch Flush: Sync #49,v,g,n,n,n,PM_FLUSH_DISP_TLBIE,Dispatch Flush: TLBIE ##208A Dispatch Flush: TLBIE #50,v,g,n,n,n,PM_FLUSH_PARTIAL,Partial flush ##2086 Partial flush #51,v,g,n,n,n,PM_FREQ_UP,Power Management: Above Threshold A ##000C Processor frequency was sped up due to power management #52,v,g,n,n,n,PM_FXU1_BUSY_FXU0_IDLE,fxu0 idle and fxu1 busy. ##000E FXU0 was idle while FXU1 was busy #53,v,g,n,n,n,PM_FXU1_FIN,FXU1 Finished ##0004 The Fixed Point unit 1 finished an instruction and produced a result. Instructions that finish may not necessary complete. #54,v,g,n,s,n,PM_GCT_FULL_CYC,Cycles No room in EAT ##4086 The Global Completion Table is completely full. #55,v,g,n,n,n,PM_GCT_NOSLOT_BR_MPRED,GCT empty by branch mispredict ##001A Cycles when the Global Completion Table has no slots from this thread because of a branch misprediction. #56,v,g,n,n,n,PM_GCT_NOSLOT_BR_MPRED_IC_MISS,GCT empty by branch mispredict + IC miss ##001C No slot in GCT caused by branch mispredict or I cache miss #57,v,g,n,n,n, PM_GCT_UTIL_1_TO_2_SLOTS,GCT Utilization 1-2 entries ##209C GCT Utilization 1-2 entries #58,v,g,n,n,n,PM_GCT_UTIL_11_PLUS_SLOTS,GCT Utilization 11+ entries ##20A2 GCT Utilization 11+ entries #59,v,g,n,n,n,PM_GCT_UTIL_3_TO_6_SLOTS,GCT Utilization 3-6 entries ##209E GCT Utilization 3-6 entries #60,v,g,n,n,n,PM_GCT_UTIL_7_TO_10_SLOTS,GCT Utilization 7-10 entries ##20A0 GCT Utilization 7-10 entries #61,v,g,n,n,n,PM_IBUF_FULL_CYC,Cycles No room in ibuff ##4084 Cycles with the Instruction Buffer was full. The Instruction Buffer is a circular queue of 64 instructions per thread, organized as 16 groups of 4 instructions. #62,v,g,n,n,n,PM_IC_BANK_CONFLICT,Read blocked due to interleave conflict. ##4082 Read blocked due to interleave conflict. #63,v,g,n,n,n,PM_IC_DEMAND_L2_BHT_REDIRECT, L2 I cache demand request due to BHT redirect ##4098 A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (CR mispredict). #64,v,g,n,n,n,PM_IC_DEMAND_L2_BR_ALL, L2 I cache demand request due to BHT or redirect ##4898 L2 I cache demand request due to BHT or redirect #65,v,g,n,n,n,PM_IC_DEMAND_L2_BR_REDIRECT, L2 I cache demand request due to branch redirect ##409A A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (either ALL mispredicted or Target). #66,v,g,n,n,n,PM_IC_DEMAND_REQ,Demand Instruction fetch request ##4088 Demand Instruction fetch request #67,v,g,n,n,n,PM_IC_PREF_CANCEL_ALL,Prefetch Canceled due to page boundary or icache hit ##4890 Prefetch Canceled due to page boundary or icache hit #68,v,g,n,n,n,PM_IC_PREF_CANCEL_HIT,Prefetch Canceled due to icache hit ##4092 Prefetch Canceled due to icache hit #69,v,g,n,n,n,PM_IC_PREF_CANCEL_L2,L2 Squashed request ##4094 L2 Squashed request #70,v,g,n,n,n,PM_IC_PREF_CANCEL_PAGE,Prefetch Canceled due to page boundary ##4090 Prefetch Canceled due to page boundary #71,v,g,n,n,n,PM_IC_PREF_REQ,Instruction prefetch requests ##408A An instruction prefetch request has been made. #72,v,g,n,n,n,PM_IC_PREF_WRITE,Instruction prefetch written into IL1 ##408E Number of Instruction Cache entries written because of prefetch. Prefetch entries are marked least recently used and are candidates for eviction if they are not needed to satify a demand fetch. #73,v,g,n,n,n,PM_IC_RELOAD_SHR,Reloading line to be shared between the threads ##4096 An Instruction Cache request was made by this thread and the cache line was already in the cache for the other thread. The line is marked valid for all threads. #74,v,g,n,n,n,PM_IC_REQ_ALL,Icache requests, prefetch + demand ##4888 Icache requests, prefetch + demand #75,v,g,n,n,n,PM_IC_WRITE_ALL,Icache sectors written, prefetch + demand ##488C Icache sectors written, prefetch + demand #76,v,g,n,n,n,PM_IERAT_WR_64K,large page 64k ##40BE large page 64k #77,v,g,n,n,n,PM_IERAT_XLATE_WR_16MPLUS,large page 16M+ ##40BC large page 16M+ #78,v,g,n,n,n,PM_IFU_FIN,IFU Finished a (non-branch) instruction ##0066 The Instruction Fetch Unit finished an instruction #79,v,g,n,n,n,PM_INST_CMPL,# PPC Instructions Finished ##0002 Number of PowerPC Instructions that completed. #80,v,g,n,n,n,PM_INST_FROM_DL2L3_MOD,Instruction fetched from distant L2 or L3 modified ##4044 An instruction fetch group was fetched with modified (M) data from an L2 or L3 on a distant module. Fetch groups can contain up to 8 instructions #81,v,g,n,n,n,PM_INST_FROM_L1,Instruction fetches from L1 ##4080 An instruction fetch group was fetched from L1. Fetch Groups can contain up to 8 instructions #82,v,g,n,n,n,PM_INST_FROM_L21_SHR,Instruction fetched from another L2 on same chip shared ##4046 Instruction fetched from another L2 on same chip shared #83,v,g,n,n,n,PM_INST_FROM_L2MISS,Instruction fetched missed L2 ##4048 An instruction fetch group was fetched from beyond the local L2. #84,v,g,n,n,n,PM_INST_FROM_LMEM,Instruction fetched from local memory ##4042 An instruction fetch group was fetched from memory attached to the same module this proccessor is located on. Fetch groups can contain up to 8 instructions #85,v,g,n,n,n,PM_INST_PTEG_FROM_DL2L3_MOD,Instruction PTEG loaded from distant L2 or L3 modified ##E054 Instruction PTEG loaded from distant L2 or L3 modified #86,v,g,n,n,n,PM_INST_PTEG_FROM_L21_SHR,Instruction PTEG loaded from another L2 on same chip shared ##E056 Instruction PTEG loaded from another L2 on same chip shared #87,v,g,n,n,n,PM_INST_PTEG_FROM_L2MISS,Instruction PTEG loaded from L2 miss ##E058 Instruction PTEG loaded from L2 miss #88,v,g,n,n,n,PM_INST_PTEG_FROM_LMEM,Instruction PTEG loaded from local memory ##E052 Instruction PTEG loaded from local memory #89,v,g,n,n,n,PM_ISEG,ISEG Exception ##20A4 ISEG Exception #90,v,g,n,n,n,PM_ISLB_MISS,Instruction SLB Miss - Tota of all segment sizes ##D092 A SLB miss for an instruction fetch as occurred #91,v,g,n,n,n,PM_ITLB_MISS,ITLB Reloaded (always zero on POWER6) ##00FC A TLB miss for an Instruction Fetch has occurred #92,v,g,n,n,n,PM_L1_DEMAND_WRITE,Instruction Demand sectors wriittent into IL1 ##408C Instruction Demand sectors wriittent into IL1 #93,v,g,n,n,n,PM_L1_PREF,L1 Prefetches ##D8B8 A request to prefetch data into the L1 was made #94,v,g,n,s,n,PM_L2_DISP_ALL,All successful LD/ST dispatches for this thread(i+d) ##6080 All successful LD/ST dispatches for this thread(i+d) #95,v,g,n,s,n,PM_L2_RCLD_BUSY_RC_FULL, L2 activated Busy to the core for loads due to all RC full ##6282 L2 activated Busy to the core for loads due to all RC full #96,v,g,n,s,n,PM_L2_RCST_DISP_FAIL_OTHER, L2 RC store dispatch attempt failed due to other reasons ##6280 L2 RC store dispatch attempt failed due to other reasons #97,v,g,n,s,n,PM_L2_SN_M_RD_DONE,SNP dispatched for a read and was M ##6380 SNP dispatched for a read and was M #98,v,g,n,s,n,PM_L2_SN_M_WR_DONE,SNP dispatched for a write and was M ##6382 SNP dispatched for a write and was M #99,v,g,n,s,n,PM_L2_ST_DISP,All successful store dispatches ##6180 All successful store dispatches #100,v,g,n,s,n,PM_L2_ST_HIT,All successful store dispatches that were L2Hits ##6182 A store request hit in the L2 directory. This event includes all requests to this L2 from all sources. Total for all slices. #101,v,g,n,s,n,PM_L3_CO_MEM,L3 Castouts to Memory ##F082 L3 Castouts to Memory #102,v,g,n,s,n,PM_L3_CO_L31,L3 Castouts to L3.1 ##F080 L3 Castouts to L3.1 #103,v,g,n,s,n,PM_L3_PREF_BUSY,Prefetch machines >= threshold (8,16,20,24) ##F080 Prefetch machines >= threshold (8,16,20,24) #104,v,g,n,n,n,PM_L3_PREF_LD,L3 cache LD prefetches ##D0AC L3 cache LD prefetches #105,v,g,n,n,n,PM_L3_PREF_LDST,L3 cache prefetches LD + ST ##D8AC L3 cache prefetches LD + ST #106,v,g,n,n,n,PM_L3_PREF_ST,L3 cache ST prefetches ##D0AE L3 cache ST prefetches #107,v,g,n,s,n,PM_L3_RD_BUSY,Rd machines busy >= threshold (2,4,6,8) ##F082 Rd machines busy >= threshold (2,4,6,8) #108,v,g,n,n,n,PM_LARX_LSU,Larx Finished ##C894 Larx Finished #109,v,g,n,n,n,PM_LARX_LSU0,ls0 Larx Finished ##C094 A larx (lwarx or ldarx) was executed on side 0 #110,v,g,n,n,n,PM_LARX_LSU1,ls1 Larx Finished ##C096 A larx (lwarx or ldarx) was executed on side 1 #111,v,g,n,n,n,PM_LD_MISS_L1,Load Missed L1 ##00F0 Load references that miss the Level 1 Data cache. Combined unit 0 + 1. #112,v,g,n,n,n,PM_LD_REF_L1, L1 D cache load references counted at finish ##C880 L1 D cache load references counted at finish #113,v,g,n,n,n,PM_LD_REF_L1_LSU0,LS0 L1 D cache load references counted at finish ##C080 Load references to Level 1 Data Cache, by unit 0. #114,v,g,n,n,n,PM_LD_REF_L1_LSU1,LS1 L1 D cache load references counted at finish ##C082 Load references to Level 1 Data Cache, by unit 1. #115,v,g,n,n,n,PM_LSU_DC_PREF_STREAM_ALLOC,D cache new prefetch stream allocated ##D8A8 D cache new prefetch stream allocated #116,v,g,n,n,n,PM_LSU_DC_PREF_STREAM_CONFIRM,Dcache new prefetch stream confirmed ##D8B4 Dcache new prefetch stream confirmed #117,v,g,n,n,n,PM_LSU_DC_PREF_STRIDED_STREAM_CONFIRM,Dcache Strided prefetch stream confirmed (software + hardware) ##D8BC Dcache Strided prefetch stream confirmed (software + hardware) #118,v,g,n,n,n,PM_LSU_DCACHE_RELOAD_VALID,count per sector of lines reloaded in L1 (demand + prefetch) ##D0A2 count per sector of lines reloaded in L1 (demand + prefetch) #119,v,g,n,n,n,PM_LSU_FLUSH,Flush initiated by LSU ##208E A flush was initiated by the Load Store Unit. #120,v,g,n,n,n,PM_LSU_FLUSH_LRQ,Flush: LRQ ##C8B8 Load Hit Load or Store Hit Load flush. A younger load was flushed because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. Combined Unit 0 + 1. #121,v,g,n,n,n,PM_LSU_FLUSH_SRQ,Flush: SRQ ##C8BC Load Hit Store flush. A younger load was flushed because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. Combined Unit 0 + 1. #122,v,g,n,n,n,PM_LSU_FLUSH_ULD,Flush: Unaligned Load ##C8B0 A load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1). Combined Unit 0 + 1. #123,v,g,n,n,n,PM_LSU_FLUSH_UST,Flush: Unaligned Store ##C8B4 A store was flushed because it was unaligned (crossed a 4K boundary). Combined Unit 0 + 1. #124,v,g,n,n,n,PM_LSU_LDF,All Scalar Loads ##C884 LSU executed Floating Point load instruction. Combined Unit 0 + 1. #125,v,g,n,n,n,PM_LSU_LDX,All Vector loads (vsx vector + vmx vector) ##C888 All Vector loads (vsx vector + vmx vector) #126,v,g,n,n,n,PM_LSU_LMQ_FULL_CYC,LMQ full ##D0A4 The Load Miss Queue was full. #127,v,g,n,n,n,PM_LSU_LMQ_S0_ALLOC,Slot 0 of LMQ valid ##D0A1 Slot 0 of LMQ valid #128,v,g,n,n,n,PM_LSU_LMQ_S0_VALID,Slot 0 of LMQ valid ##D0A0 This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the LRQ is split between the two threads (16 entries each). #129,v,g,n,n,n,PM_LSU_LRQ_S0_ALLOC,Slot 0 of LRQ valid ##D09F Slot 0 of LRQ valid #130,v,g,n,n,n,PM_LSU_LRQ_S0_VALID,Slot 0 of LRQ valid ##D09E This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the LRQ is split between the two threads (16 entries each). #131,v,g,n,n,n,PM_LSU_NCLD,Non-cachable Loads counted at finish ##C88C A non-cacheable load was executed. Combined Unit 0 + 1. #132,v,g,n,n,n,PM_LSU_NCST,Non-cachable Stores sent to nest ##C090 Non-cachable Stores sent to nest #133,v,g,n,n,n,PM_LSU_PARTIAL_CDF,A partial cacheline was returned from the L3 ##C0AA A partial cacheline was returned from the L3 #134,v,g,n,n,n,PM_LSU_REJECT_LHS,Reject: Load Hit Store ##C8AC The Load Store Unit rejected a load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully. Combined Unit 0 + 1 #135,v,g,n,n,n,PM_LSU_REJECT_LMQ_FULL,Reject: LMQ Full (LHR) ##C8A4 Total cycles the Load Store Unit is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all the eight entries are full, subsequent load instructions are rejected. Combined unit 0 + 1. #136,v,g,n,n,n,PM_LSU_REJECT_SET_MPRED,Reject: Set Predict Wrong ##C8A8 The Load Store Unit rejected an instruction because the cache set was improperly predicted. This is a fast reject and will be immediately redispatched. Combined Unit 0 + 1 #137,v,g,n,n,n,PM_LSU_SET_MPRED,Line already in cache at reload time ##C0A8 Line already in cache at reload time #138,v,g,n,n,n,PM_LSU_SRQ_EMPTY_CYC,ALL threads srq empty ##0008 The Store Request Queue is empty #139,v,g,n,n,n,PM_LSU_SRQ_S0_ALLOC,Slot 0 of SRQ valid ##D09D Slot 0 of SRQ valid #140,v,g,n,n,n,PM_LSU_SRQ_S0_VALID,Slot 0 of SRQ valid ##D09C This signal is asserted every cycle that the Store Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the SRQ is split between the two threads (16 entries each). #141,v,g,n,n,n,PM_LSU_SRQ_STFWD,Load got data from a store ##C8A0 Data from a store instruction was forwarded to a load. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss. Combined Unit 0 + 1. #142,v,g,n,n,n,PM_LSU_SRQ_SYNC_COUNT,SRQ sync count (edge of PM_LSU_SRQ_SYNC_CYC) ##D097 SRQ sync count (edge of PM_LSU_SRQ_SYNC_CYC) #143,v,g,n,n,n,PM_LSU_SRQ_SYNC_CYC,A sync is in the SRQ ##D096 Cycles that a sync instruction is active in the Store Request Queue. #144,v,g,n,n,n,PM_LSU_TWO_TABLEWALK_CYC,Cycles when two tablewalks pending on this thread ##D0A6 Cycles when two tablewalks pending on this thread #145,v,g,n,n,n,PM_LSU0_DC_PREF_STREAM_ALLOC,LS0 D cache new prefetch stream allocated ##D0A8 LS0 D cache new prefetch stream allocated #146,v,g,n,n,n,PM_LSU0_DC_PREF_STREAM_CONFIRM,LS0 Dcache prefetch stream confirmed ##D0B4 LS0 Dcache prefetch stream confirmed #147,v,g,n,n,n,PM_LSU0_DC_PREF_STREAM_CONFIRM_STRIDE,LS0 Dcache Strided prefetch stream confirmed ##D0BC LS0 Dcache Strided prefetch stream confirmed #148,v,g,n,n,n,PM_LSU0_FLUSH_LRQ,LS0 Flush: LRQ ##C0B8 Load Hit Load or Store Hit Load flush. A younger load was flushed from unit 0 because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. #149,v,g,n,n,n,PM_LSU0_FLUSH_SRQ,LS0 Flush: SRQ ##C0BC Load Hit Store flush. A younger load was flushed from unit 0 because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. #150,v,g,n,n,n,PM_LSU0_FLUSH_ULD,LS0 Flush: Unaligned Load ##C0B0 A load was flushed from unit 0 because it was unaligned (crossed a 64 byte boundary, or 32 byte if it missed the L1) #151,v,g,n,n,n,PM_LSU0_FLUSH_UST,LS0 Flush: Unaligned Store ##C0B4 A store was flushed from unit 0 because it was unaligned (crossed a 4K boundary). #152,v,g,n,n,n,PM_LSU0_L1_PREF, LS0 L1 cache data prefetches ##D0B8 LS0 L1 cache data prefetches #153,v,g,n,n,n,PM_LSU0_L1_SW_PREF,LSU0 Software L1 Prefetches, including SW Transient Prefetches ##C09C LSU0 Software L1 Prefetches, including SW Transient Prefetches #154,v,g,n,n,n,PM_LSU0_LDF,LS0 Scalar Loads ##C084 A floating point load was executed by LSU0 #155,v,g,n,n,n,PM_LSU0_LDX,LS0 Vector Loads ##C088 LS0 Vector Loads #156,v,g,n,n,n,PM_LSU0_LMQ_LHR_MERGE,LS0 Load Merged with another cacheline request ##D098 LS0 Load Merged with another cacheline request #157,v,g,n,n,n,PM_LSU0_NCLD,LS0 Non-cachable Loads counted at finish ##C08C A non-cacheable load was executed by unit 0. #158,v,g,n,n,n,PM_LSU0_REJECT_LHS,LS0 Reject: Load Hit Store ##C0AC Load Store Unit 0 rejected a load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully. #159,v,g,n,n,n,PM_LSU0_REJECT_LMQ_FULL,LS0 Reject: LMQ Full (LHR) ##C0A4 Total cycles the Load Store Unit 0 is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all eight entries are full, subsequent load instructions are rejected. #160,v,g,n,n,n,PM_LSU0_SRQ_STFWD,LS0 SRQ forwarded data to a load ##C0A0 Data from a store instruction was forwarded to a load on unit 0. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss. #161,v,g,n,n,n,PM_LSU1_DC_PREF_STREAM_ALLOC,LS 1 D cache new prefetch stream allocated ##D0AA LS 1 D cache new prefetch stream allocated #162,v,g,n,n,n,PM_LSU1_DC_PREF_STREAM_CONFIRM,LS1 'Dcache prefetch stream confirmed ##D0B6 LS1 'Dcache prefetch stream confirmed #163,v,g,n,n,n,PM_LSU1_DC_PREF_STREAM_CONFIRM_STRIDE,LS1 Dcache Strided prefetch stream confirmed ##D0BE LS1 Dcache Strided prefetch stream confirmed #164,v,g,n,n,n,PM_LSU1_FLUSH_LRQ,LS1 Flush: LRQ ##C0BA Load Hit Load or Store Hit Load flush. A younger load was flushed from unit 1 because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. #165,v,g,n,n,n,PM_LSU1_FLUSH_SRQ,LS1 Flush: SRQ ##C0BE Load Hit Store flush. A younger load was flushed from unit 1 because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. #166,v,g,n,n,n,PM_LSU1_FLUSH_ULD,LS 1 Flush: Unaligned Load ##C0B2 A load was flushed from unit 1 because it was unaligned (crossed a 64 byte boundary, or 32 byte if it missed the L1). #167,v,g,n,n,n,PM_LSU1_FLUSH_UST,LS1 Flush: Unaligned Store ##C0B6 A store was flushed from unit 1 because it was unaligned (crossed a 4K boundary) #168,v,g,n,n,n,PM_LSU1_L1_PREF, LS1 L1 cache data prefetches ##D0BA LS1 L1 cache data prefetches #169,v,g,n,n,n,PM_LSU1_L1_SW_PREF,LSU1 Software L1 Prefetches, including SW Transient Prefetches ##C09E LSU1 Software L1 Prefetches, including SW Transient Prefetches #170,v,g,n,n,n,PM_LSU1_LDF,LS1 Scalar Loads ##C086 A floating point load was executed by LSU1 #171,v,g,n,n,n,PM_LSU1_LDX,LS1 Vector Loads ##C08A LS1 Vector Loads #172,v,g,n,n,n,PM_LSU1_LMQ_LHR_MERGE,LS1 Load Merge with another cacheline request ##D09A LS1 Load Merge with another cacheline request #173,v,g,n,n,n,PM_LSU1_NCLD,LS1 Non-cachable Loads counted at finish ##C08E A non-cacheable load was executed by Unit 0. #174,v,g,n,n,n,PM_LSU1_REJECT_LHS,LS1 Reject: Load Hit Store ##C0AE Load Store Unit 1 rejected a load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully. #175,v,g,n,n,n,PM_LSU1_REJECT_LMQ_FULL,LS1 Reject: LMQ Full (LHR) ##C0A6 Total cycles the Load Store Unit 1 is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all eight entries are full, subsequent load instructions are rejected. #176,v,g,n,n,n,PM_LSU1_SRQ_STFWD,LS1 SRQ forwarded data to a load ##C0A2 Data from a store instruction was forwarded to a load on unit 1. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss. #177,v,g,n,n,n,PM_LWSYNC,lwsync count (easier to use than IMC) ##D094 lwsync count (easier to use than IMC) #178,v,g,n,n,n,PM_LWSYNC_HELD,LWSYNC held at dispatch ##209A Cycles a LWSYNC instruction was held at dispatch. LWSYNC instructions are held at dispatch until all previous loads are done and all previous stores have issued. LWSYNC enters the Store Request Queue and is sent to the storage subsystem but does not wait for a response. #179,v,g,n,n,m,PM_MRK_DATA_FROM_DL2L3_MOD,Marked data loaded from distant L2 or L3 modified ##D044 The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a distant module due to a marked load. #180,v,g,n,n,m,PM_MRK_DATA_FROM_DL2L3_MOD_CYC,Marked ld latency Data source 1011 (L2.75/L3.75 M different 4 chip node) ##002A Marked ld latency Data source 1011 (L2.75/L3.75 M different 4 chip node) #181,v,g,n,n,m,PM_MRK_DATA_FROM_L21_MOD_CYC,Marked ld latency Data source 0101 (L2.1 M same chip) ##0024 Marked ld latency Data source 0101 (L2.1 M same chip) #182,v,g,n,n,m,PM_MRK_DATA_FROM_L21_SHR,Marked data loaded from another L2 on same chip shared ##D046 Marked data loaded from another L2 on same chip shared #183,v,g,n,n,m,PM_MRK_DATA_FROM_L2MISS,Marked data loaded missed L2 ##D048 DL1 was reloaded from beyond L2 due to a marked demand load. #184,v,g,n,n,m,PM_MRK_DATA_FROM_L3_CYC,Marked ld latency Data source 0001 (L3) ##0020 Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level. #185,v,g,n,n,m,PM_MRK_DATA_FROM_L31_MOD_CYC,Marked ld latency Data source 0111 (L3.1 M same chip) ##0026 Marked ld latency Data source 0111 (L3.1 M same chip) #186,v,g,n,n,m,PM_MRK_DATA_FROM_LMEM,Marked data loaded from local memory ##D042 The processor’s Data Cache was reloaded due to a marked load from memory attached to the same module this proccessor is located on. #187,v,g,n,n,m,PM_MRK_DATA_FROM_RL2L3_MOD_CYC,Marked ld latency Data source 1001 (L2.5/L3.5 M same 4 chip node) ##0028 Marked ld latency Data source 1001 (L2.5/L3.5 M same 4 chip node) #188,v,g,n,n,m,PM_MRK_DATA_FROM_RMEM_CYC,Marked ld latency Data source 1101 (Memory same 4 chip node) ##002C Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level. #189,v,g,n,n,m,PM_MRK_DERAT_MISS_16G,Marked DERAT misses for 16G page ##D05C A marked data request (load or store) missed the ERAT for 16G page and resulted in an ERAT reload. #190,v,g,n,n,m,PM_MRK_DTLB_MISS_16M,Marked Data TLB misses for 16M page ##D05E Data TLB references to 16M pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time. #191,v,g,t,n,m,PM_MRK_GRP_CMPL,Marked group complete ##0030 A group containing a sampled instruction completed. Microcoded instructions that span multiple groups will generate this event once per group. #192,v,g,t,n,m,PM_MRK_GRP_IC_MISS,Marked group experienced I cache miss ##0038 A group containing a marked (sampled) instruction experienced an instruction cache miss. #193,v,g,n,n,m,PM_MRK_INST_TIMEO,marked Instruction finish timeout ##0034 The number of instructions finished since the last progress indicator from a marked instruction exceeded the threshold. The marked instruction was flushed. #194,v,g,n,n,m,PM_MRK_LD_MISS_L1_CYC,L1 data load miss cycles ##003E L1 data load miss cycles #195,v,g,n,n,m,PM_MRK_LSU_FIN,Marked LSU instruction finished ##0032 One of the Load/Store Units finished a marked instruction. Instructions that finish may not necessary complete #196,v,g,n,n,m,PM_MRK_LSU_FLUSH,Flush: (marked) : All Cases ##D08C Marked flush initiated by LSU #197,v,g,n,n,m,PM_MRK_LSU_FLUSH_LRQ,Flush: (marked) LRQ ##D088 Load Hit Load or Store Hit Load flush. A marked load was flushed because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. #198,v,g,n,n,m,PM_MRK_LSU_FLUSH_SRQ,Flush: (marked) SRQ ##D08A Load Hit Store flush. A marked load was flushed because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. #199,v,g,n,n,m,PM_MRK_LSU_FLUSH_ULD,Flush: (marked) Unaligned Load ##D084 A marked load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1) #200,v,g,n,n,m,PM_MRK_LSU_FLUSH_UST,Flush: (marked) Unaligned Store ##D086 A marked store was flushed because it was unaligned #201,v,g,n,n,m,PM_MRK_LSU_PARTIAL_CDF,A partial cacheline was returned from the L3 for a marked load ##D080 A partial cacheline was returned from the L3 for a marked load #202,v,g,n,n,m,PM_MRK_LSU_REJECT,LSU marked reject (up to 2 per cycle) ##0064 LSU marked reject (up to 2 per cycle) #203,v,g,n,n,m,PM_MRK_LSU_REJECT_LHS, Reject(marked): Load Hit Store ##D082 The Load Store Unit rejected a marked load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully #204,v,g,n,n,m,PM_MRK_PTEG_FROM_DL2L3_MOD,Marked PTEG loaded from distant L2 or L3 modified ##D054 A Page Table Entry was loaded into the ERAT with modified (M) data from an L2 or L3 on a distant module due to a marked load or store. #205,v,g,n,n,m,PM_MRK_PTEG_FROM_L21_SHR,Marked PTEG loaded from another L2 on same chip shared ##D056 Marked PTEG loaded from another L2 on same chip shared #206,v,g,n,n,m,PM_MRK_PTEG_FROM_L2MISS,Marked PTEG loaded from L2 miss ##D058 A Page Table Entry was loaded into the ERAT but not from the local L2 due to a marked load or store. #207,v,g,n,n,m,PM_MRK_PTEG_FROM_LMEM,Marked PTEG loaded from local memory ##D052 A Page Table Entry was loaded into the ERAT from memory attached to the same module this proccessor is located on due to a marked load or store. #208,v,g,n,n,m,PM_MRK_STCX_FAIL,Marked STCX failed ##D08E A marked stcx (stwcx or stdcx) failed #209,v,g,n,c,n,PM_PB_RETRY_SYS_PUMP, Nest events (MC0/MC1/PB/GX), Pair3 Bit0 ##0081 Nest events (MC0/MC1/PB/GX), Pair3 Bit0 #210,v,g,n,c,n,PM_MEM0_WQ_DISP, Nest events (MC0/MC1/PB/GX), Pair3 Bit1 ##0083 Nest events (MC0/MC1/PB/GX), Pair3 Bit1 #211,v,g,n,c,n,PM_NEST_PAIR3_ADD, Nest events (MC0/MC1/PB/GX), Pair3 ADD ##0881 Nest events (MC0/MC1/PB/GX), Pair3 ADD #212,v,g,n,c,n,PM_NEST_PAIR3_AND, Nest events (MC0/MC1/PB/GX), Pair3 AND ##0883 Nest events (MC0/MC1/PB/GX), Pair3 AND #213,v,g,n,n,n,PM_PMC3_OVERFLOW,Overflow from counter 3 ##0010 Overflows from PMC3 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow. #214,v,g,n,n,n,PM_POWER_EVENT4,Power Management Event 4 ##006E Power Management Event 4 #215,v,g,n,n,n,PM_PTEG_FROM_DL2L3_MOD,PTEG loaded from distant L2 or L3 modified ##C054 A Page Table Entry was loaded into the ERAT with modified (M) data from an L2 or L3 on a distant module due to a demand load or store. #216,v,g,n,n,n,PM_PTEG_FROM_L21_SHR,PTEG loaded from another L2 on same chip shared ##C056 PTEG loaded from another L2 on same chip shared #217,v,g,n,n,n,PM_PTEG_FROM_L2MISS,PTEG loaded from L2 miss ##C058 A Page Table Entry was loaded into the TLB but not from the local L2. #218,v,g,n,n,n,PM_PTEG_FROM_LMEM,PTEG loaded from local memory ##C052 A Page Table Entry was loaded into the TLB from memory attached to the same module this proccessor is located on. #219,v,g,n,n,n,PM_RUN_INST_CMPL,Run_Instructions ##00FA Number of run instructions completed. #220,v,g,n,c,n,PM_RUN_PURR,Run_PURR ##00F4 The Processor Utilization of Resources Register was incremented while the run latch was set. The PURR registers will be incremented roughly in the ratio in which the instructions are dispatched from the two threads. #221,v,g,n,n,n,PM_SEG_EXCEPTION,ISEG + DSEG Exception ##28A4 ISEG + DSEG Exception #222,v,g,n,n,n,PM_SHL_CREATED,SHL table entry Created ##5082 SHL table entry Created #223,v,g,n,n,n,PM_SHL_DEALLOCATED,SHL Table entry deallocated ##5080 SHL Table entry deallocated #224,v,g,n,n,n,PM_SHL_MATCH,SHL Table Match ##5086 SHL Table Match #225,v,g,n,n,n,PM_SHL_MERGED,SHL table entry merged with existing ##5084 SHL table entry merged with existing #226,v,g,n,n,n,PM_SLB_MISS,Data + Instruction SLB Miss - Total of all segment sizes ##D890 Total of all Segment Lookaside Buffer (SLB) misses, Instructions + Data. #227,v,g,n,c,n,PM_SNOOP_TLBIE,TLBIE snoop ##D0B2 A tlbie was snooped from another processor. #228,v,g,n,n,n,PM_STCX_CMPL,STCX executed ##C098 Conditional stores with reservation completed #229,v,g,n,n,n,PM_STCX_FAIL,STCX failed ##C09A A stcx (stwcx or stdcx) failed #230,v,g,n,n,n,PM_SUSPENDED,Counter OFF ##0000 The counter is suspended (does not count) #231,v,g,n,c,n,PM_THERMAL_MAX,Processor In Thermal MAX ##0006 The processor experienced a thermal overload condition. This bit is sticky, it remains set until cleared by software. #232,v,g,n,c,n,PM_THRD_2_CONC_RUN_INSTR,2 thread Concurrent Run Instructions ##0062 2 thread Concurrent Run Instructions #233,v,g,n,c,n,PM_THRD_4_RUN_CYC,4 thread in Run Cycles ##0060 4 thread in Run Cycles #234,v,g,n,n,n,PM_THRD_PRIO_0_1_CYC, Cycles thread running at priority level 0 or 1 ##40B0 Cycles thread running at priority level 0 or 1 #235,v,g,n,n,n,PM_THRD_PRIO_2_3_CYC, Cycles thread running at priority level 2 or 3 ##40B2 Cycles thread running at priority level 2 or 3 #236,v,g,n,n,n,PM_THRD_PRIO_4_5_CYC, Cycles thread running at priority level 4 or 5 ##40B4 Cycles thread running at priority level 4 or 5 #237,v,g,n,n,n,PM_THRD_PRIO_6_7_CYC, Cycles thread running at priority level 6 or 7 ##40B6 Cycles thread running at priority level 6 or 7 #238,v,g,n,n,n,PM_VMX_RESULT_SAT_1,Valid result with sat=1 ##B0A0 Valid result with sat=1 #239,v,g,n,n,n,PM_VSU_1FLOP,one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished ##A880 one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished #240,v,g,n,n,n,PM_VSU_2FLOP,two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) ##A898 two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) #241,v,g,n,n,n,PM_VSU_2FLOP_DOUBLE,DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg ##A88C DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg #242,v,g,n,n,n,PM_VSU_4FLOP,four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions) ##A89C four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions) #243,v,g,n,n,n,PM_VSU_8FLOP,eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) ##A8A0 eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) #244,v,g,n,n,n,PM_VSU_DENORM,Vector or Scalar denorm operand ##A8AC Vector or Scalar denorm operand #245,v,g,n,n,n,PM_VSU_FCONV,Convert instruction executed ##A8B0 Convert instruction executed #246,v,g,n,n,n,PM_VSU_FEST,Estimate instruction executed ##A8B8 Estimate instruction executed #247,v,g,n,n,n,PM_VSU_FIN,VSU0 Finished an instruction ##A8BC VSU0 Finished an instruction #248,v,g,n,n,n,PM_VSU_FMA,two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only! ##A884 two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only! #249,v,g,n,n,n,PM_VSU_FMA_DOUBLE,DP vector version of fmadd,fnmadd,fmsub,fnmsub ##A890 DP vector version of fmadd,fnmadd,fmsub,fnmsub #250,v,g,n,n,n,PM_VSU_FRSP,Round to single precision instruction executed ##A8B4 Round to single precision instruction executed #251,v,g,n,n,n,PM_VSU_FSQRT_FDIV,four flops operation (fdiv,fsqrt) Scalar Instructions only! ##A888 DP vector versions of fdiv,fsqrt #252,v,g,n,n,n,PM_VSU_FSQRT_FDIV_DOUBLE,DP vector versions of fdiv,fsqrt ##A894 DP vector versions of fdiv,fsqrt #253,v,g,n,n,n,PM_VSU_SCALAR_DOUBLE_ISSUED,Double Precision scalar instruction issued on Pipe0 ##B888 Double Precision scalar instruction issued on Pipe0 #254,v,g,n,n,n,PM_VSU_SCALAR_SINGLE_ISSUED,Single Precision scalar instruction issued on Pipe0 ##B884 Single Precision scalar instruction issued on Pipe0 #255,v,g,n,n,n,PM_VSU_SIMPLE_ISSUED,Simple VMX instruction issued ##B894 Simple VMX instruction issued #256,v,g,n,n,n,PM_VSU_SINGLE,Vector or Scalar single precision ##A8A8 Vector or Scalar single precision #257,v,g,n,n,n,PM_VSU_STF,FPU store (SP or DP) issued on Pipe0 ##B88C FPU store (SP or DP) issued on Pipe0 #258,v,g,n,n,n,PM_VSU_VECTOR_DOUBLE_ISSUED,Double Precision vector instruction issued on Pipe0 ##B880 Double Precision vector instruction issued on Pipe0 #259,v,g,n,n,n,PM_VSU_VECTOR_SINGLE_ISSUED,Single Precision vector instruction issued (executed) ##B890 Single Precision vector instruction issued (executed) #260,v,g,n,n,n,PM_VSU0_16FLOP,Sixteen flops operation (SP vector versions of fdiv,fsqrt) ##A0A4 Sixteen flops operation (SP vector versions of fdiv,fsqrt) #261,v,g,n,n,n,PM_VSU0_1FLOP,one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg, xsadd, xsmul, xssub, xscmp, xssel, xsabs, xsnabs, xsre, xssqrte, xsneg) operation finished ##A080 one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg, xsadd, xsmul, xssub, xscmp, xssel, xsabs, xsnabs, xsre, xssqrte, xsneg) operation finished #262,v,g,n,n,n,PM_VSU0_2FLOP,two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) ##A098 two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) #263,v,g,n,n,n,PM_VSU0_2FLOP_DOUBLE,two flop DP vector operation (xvadddp, xvmuldp, xvsubdp, xvcmpdp, xvseldp, xvabsdp, xvnabsdp, xvredp ,xvsqrtedp, vxnegdp) ##A08C two flop DP vector operation (xvadddp, xvmuldp, xvsubdp, xvcmpdp, xvseldp, xvabsdp, xvnabsdp, xvredp ,xvsqrtedp, vxnegdp) #264,v,g,n,n,n,PM_VSU0_4FLOP,four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions) ##A09C four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions) #265,v,g,n,n,n,PM_VSU0_8FLOP,eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) ##A0A0 eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) #266,v,g,n,n,n,PM_VSU0_COMPLEX_ISSUED,Complex VMX instruction issued ##B096 Complex VMX instruction issued #267,v,g,n,n,n,PM_VSU0_DENORM,FPU denorm operand ##A0AC VSU0 received denormalized data #268,v,g,n,n,n,PM_VSU0_FCONV,Convert instruction executed ##A0B0 Convert instruction executed #269,v,g,n,n,n,PM_VSU0_FEST,Estimate instruction executed ##A0B8 Estimate instruction executed #270,v,g,n,n,n,PM_VSU0_FIN,VSU0 Finished an instruction ##A0BC VSU0 Finished an instruction #271,v,g,n,n,n,PM_VSU0_FMA,two flops operation (fmadd, fnmadd, fmsub, fnmsub, xsmadd, xsnmadd, xsmsub, xsnmsub) Scalar instructions only! ##A084 two flops operation (fmadd, fnmadd, fmsub, fnmsub, xsmadd, xsnmadd, xsmsub, xsnmsub) Scalar instructions only! #272,v,g,n,n,n,PM_VSU0_FMA_DOUBLE,four flop DP vector operations (xvmadddp, xvnmadddp, xvmsubdp, xvmsubdp) ##A090 four flop DP vector operations (xvmadddp, xvnmadddp, xvmsubdp, xvmsubdp) #273,v,g,n,n,n,PM_VSU0_FPSCR,Move to/from FPSCR type instruction issued on Pipe 0 ##B09C Move to/from FPSCR type instruction issued on Pipe 0 #274,v,g,n,n,n,PM_VSU0_FRSP,Round to single precision instruction executed ##A0B4 Round to single precision instruction executed #275,v,g,n,n,n,PM_VSU0_FSQRT_FDIV,four flops operation (fdiv,fsqrt,xsdiv,xssqrt) Scalar Instructions only! ##A088 four flops operation (fdiv,fsqrt,xsdiv,xssqrt) Scalar Instructions only! #276,v,g,n,n,n,PM_VSU0_FSQRT_FDIV_DOUBLE,eight flop DP vector operations (xvfdivdp, xvsqrtdp ##A094 eight flop DP vector operations (xvfdivdp, xvsqrtdp #277,v,g,n,n,n,PM_VSU0_SCAL_DOUBLE_ISSUED,Double Precision scalar instruction issued on Pipe0 ##B088 Double Precision scalar instruction issued on Pipe0 #278,v,g,n,n,n,PM_VSU0_SCAL_SINGLE_ISSUED,Single Precision scalar instruction issued on Pipe0 ##B084 Single Precision scalar instruction issued on Pipe0 #279,v,g,n,n,n,PM_VSU0_SIMPLE_ISSUED,Simple VMX instruction issued ##B094 Simple VMX instruction issued #280,v,g,n,n,n,PM_VSU0_SINGLE,FPU single precision ##A0A8 VSU0 executed single precision instruction #281,v,g,n,n,n,PM_VSU0_STF,FPU store (SP or DP) issued on Pipe0 ##B08C FPU store (SP or DP) issued on Pipe0 #282,v,g,n,n,n,PM_VSU0_VECT_DOUBLE_ISSUED,Double Precision vector instruction issued on Pipe0 ##B080 Double Precision vector instruction issued on Pipe0 #283,v,g,n,n,n,PM_VSU0_VECTOR_SP_ISSUED,Single Precision vector instruction issued (executed) ##B090 Single Precision vector instruction issued (executed) #284,v,g,n,n,n,PM_VSU1_1FLOP,one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg, xsadd, xsmul, xssub, xscmp, xssel, xsabs, xsnabs, xsre, xssqrte, xsneg) operation finished ##A082 one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg, xsadd, xsmul, xssub, xscmp, xssel, xsabs, xsnabs, xsre, xssqrte, xsneg) operation finished #285,v,g,n,n,n,PM_VSU1_2FLOP,two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) ##A09A two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) #286,v,g,n,n,n,PM_VSU1_2FLOP_DOUBLE,two flop DP vector operation (xvadddp, xvmuldp, xvsubdp, xvcmpdp, xvseldp, xvabsdp, xvnabsdp, xvredp ,xvsqrtedp, vxnegdp) ##A08E two flop DP vector operation (xvadddp, xvmuldp, xvsubdp, xvcmpdp, xvseldp, xvabsdp, xvnabsdp, xvredp ,xvsqrtedp, vxnegdp) #287,v,g,n,n,n,PM_VSU1_4FLOP,four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions) ##A09E four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions) #288,v,g,n,n,n,PM_VSU1_8FLOP,eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) ##A0A2 eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) #289,v,g,n,n,n,PM_VSU1_DD_ISSUED,64BIT Decimal Issued on Pipe1 ##B098 64BIT Decimal Issued on Pipe1 #290,v,g,n,n,n,PM_VSU1_DENORM,FPU denorm operand ##A0AE VSU1 received denormalized data #291,v,g,n,n,n,PM_VSU1_DQ_ISSUED,128BIT Decimal Issued on Pipe1 ##B09A 128BIT Decimal Issued on Pipe1 #292,v,g,n,n,n,PM_VSU1_FCONV,Convert instruction executed ##A0B2 Convert instruction executed #293,v,g,n,n,n,PM_VSU1_FEST,Estimate instruction executed ##A0BA Estimate instruction executed #294,v,g,n,n,n,PM_VSU1_FIN,VSU1 Finished an instruction ##A0BE VSU1 Finished an instruction #295,v,g,n,n,n,PM_VSU1_FMA,two flops operation (fmadd, fnmadd, fmsub, fnmsub, xsmadd, xsnmadd, xsmsub, xsnmsub) Scalar instructions only! ##A086 two flops operation (fmadd, fnmadd, fmsub, fnmsub, xsmadd, xsnmadd, xsmsub, xsnmsub) Scalar instructions only! #296,v,g,n,n,n,PM_VSU1_FMA_DOUBLE,four flop DP vector operations (xvmadddp, xvnmadddp, xvmsubdp, xvmsubdp) ##A092 four flop DP vector operations (xvmadddp, xvnmadddp, xvmsubdp, xvmsubdp) #297,v,g,n,n,n,PM_VSU1_FRSP,Round to single precision instruction executed ##A0B6 Round to single precision instruction executed #298,v,g,n,n,n,PM_VSU1_FSQRT_FDIV,four flops operation (fdiv,fsqrt,xsdiv,xssqrt) Scalar Instructions only! ##A08A four flops operation (fdiv,fsqrt,xsdiv,xssqrt) Scalar Instructions only! #299,v,g,n,n,n,PM_VSU1_FSQRT_FDIV_DOUBLE,eight flop DP vector operations (xvfdivdp, xvsqrtdp ##A096 eight flop DP vector operations (xvfdivdp, xvsqrtdp #300,v,g,n,n,n,PM_VSU1_PERMUTE_ISSUED,Permute VMX Instruction Issued ##B092 Permute VMX Instruction Issued #301,v,g,n,n,n,PM_VSU1_SCAL_DOUBLE_ISSUED,Double Precision scalar instruction issued on Pipe1 ##B08A Double Precision scalar instruction issued on Pipe1 #302,v,g,n,n,n,PM_VSU1_SCAL_SINGLE_ISSUED,Single Precision scalar instruction issued on Pipe1 ##B086 Single Precision scalar instruction issued on Pipe1 #303,v,g,n,n,n,PM_VSU1_SINGLE,FPU single precision ##A0AA VSU1 executed single precision instruction #304,v,g,n,n,n,PM_VSU1_SQ,Store Vector Issued on Pipe1 ##B09E Store Vector Issued on Pipe1 #305,v,g,n,n,n,PM_VSU1_STF,FPU store (SP or DP) issued on Pipe1 ##B08E FPU store (SP or DP) issued on Pipe1 #306,v,g,n,n,n,PM_VSU1_VECT_DOUBLE_ISSUED,Double Precision vector instruction issued on Pipe1 ##B082 Double Precision vector instruction issued on Pipe1 $$$$$$$$ { counter 5 } #0,v,g,n,n,n,PM_RUN_INST_CMPL,Run_Instructions ##0009 Number of run instructions completed. $$$$$$$$ { counter 6 } #0,v,g,n,n,n,PM_RUN_CYC,Run_cycles ##0005 Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.