# IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # # bos720 src/bos/usr/sbin/perf/pmapi/events/POWER7.dms 1.3 # # Licensed Materials - Property of IBM # # Restricted Materials of IBM # # COPYRIGHT International Business Machines Corp. 2009 # All Rights Reserved # # US Government Users Restricted Rights - Use, duplication or # disclosure restricted by GSA ADP Schedule Contract with IBM Corp. # # IBM_PROLOG_END_TAG CACHE_LINE_SIZE = 128; MEM_LINE_SIZE = 128; @PMD_CYC_GRP_COMPLETED;Percentage Cycles a group completed;% @@PM_GRP_CMPL / PM_CYC * 100 @@@group=General @PMD_GRP_DISP_COMPLETION;Group dispatch-to-completion ratio @@PM_1PLUS_PPC_DISP / PM_1PLUS_PPC_CMPL @@@group=General @PMD_INST_DISP_COMPLETION;Instruction dispatch-to-completion ratio @@PM_INST_DISP / PM_INST_CMPL @@@group=General @PMD_GRP_SIZE;Average group size @@PM_INST_CMPL / PM_1PLUS_PPC_CMPL @@@group=General @PMD_DL1_MISS_RATE;Percentage of L1 load misses per L1 load ref;% @@PM_LD_MISS_L1 / PM_LD_REF_L1_BOTH * 100 @@@group=General @PMD_DL1_MISS_RATE;Percentage of L1 load misses per L1 load ref;% @@PM_LD_MISS_L1 * 100 / PM_INST_CMPL @@@group=General @PMD_L2_LD_MISS_RATE;L2 Load Miss Rate (per instruction)(%);% @@PM_DATA_FROM_L2MISS * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_L3_LD_MISS_RATE;L3 Load Miss Rate (per instruction)(%);% @@PM_DATA_FROM_L3MISS * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_DERAT_MISS_RATE;DERAT Miss Rate (per instruction)(%);% @@PM_LSU_DERAT_MISS * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_L2_PTEG_MISS_RATE;L2 PTEG Miss Rate (per instruction)(%);% @@PM_PTEG_FROM_L2MISS * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_L3_PTEG_MISS_RATE;L3 PTEG Miss Rate (per instruction)(%);% @@PM_PTEG_FROM_L3MISS * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_ICACHE_MISS_RATE;Instruction Cache Miss Rate (Per Instruction)(%);% @@PM_L1_ICACHE_MISS * 100 / PM_INST_CMPL @@@group=General @PMD_ICACHE_PREF;% of ICache reloads due to prefetch;% @@PM_IC_PREF_WRITE * 100 / PM_L1_ICACHE_MISS @@@group=General @PMD_L2_INST_MISS_RATE;L2 Instruction Miss Rate (per instruction)(%);% @@PM_INST_FROM_L2MISS * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_L3_INST_MISS_RATE;L3 Instruction Miss Rate (per instruction)(%);% @@PM_INST_FROM_L3MISS * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_CPI;Cycles per instruction @@PM_CYC / PM_INST_CMPL @@@group=General @PMD_AVG_SYNC_CYC;average service time for SYNC @@PM_LSU_SRQ_SYNC_CYC / PM_LSU_SRQ_SYNC_COUNT @@@group=General @PMD_IPC;Instructions per cycles @@PM_INST_CMPL / PM_CYC @@@group=General @PMD_RUN_CPI;Run cycles per run instruction @@PM_RUN_CYC / PM_RUN_INST_CMPL @@@group=General @PMD_CYC_PER_GRP;Cycles per group @@PM_CYC / PM_1PLUS_PPC_CMPL @@@group=General @PMD_INST_PER_GRP;Instructions per group @@PM_INST_CMPL / PM_1PLUS_PPC_CMPL @@@group=General @PMD_RUN_CYCLES;Run cycles per cycle;% @@PM_RUN_CYC / PM_CYC*100 @@@group=General @PMD_UTILIZATION_RATE;Utilization rate(%);% @@PM_CYC * 100 / proc_freq / total_time @@@group=General @PMD_MIPS;MIPS;MIPS @@(0.000001 * PM_INST_CMPL) / total_time @@@group=General @PMD_CPU_UTIL;CPU Utilization;% @@PM_RUN_CYC / PM_CYC * 100 @@@group=General @PMD_DEMAND_DISP_BW;Dispatch bandwidth demand @@PM_1PLUS_PPC_DISP / PM_CYC @@@group=General @PMD_CYC_GRP_DISP;Percentage Cycles a group dispatched;% @@PM_1PLUS_PPC_DISP / PM_CYC * 100 @@@group=General @PMD_DL1_ST_MISS_RATIO;Percentage of L1 store misses per L1 store ref;% @@PM_ST_MISS_L1 / (PM_ST_FIN - PM_ST_MISS_L1) * 100 @@@group=General @PMD_FLUSH_ALIGN_RATE;Alignment flush rate (%);% @@PM_LSU_FLUSH_ULD + PM_LSU_FLUSH_UST * 100 / PM_INST_CMPL @@@group=General @PMD_FLUSH_RATE;Flush rate (%);% @@PM_FLUSH * 100 / PM_INST_CMPL @@@group=General @PMD_VSU_STALL_SCALAR_CPI;Cycles stalled by VSU Scalar Operations @@PM_CMPLU_STALL_SCALAR / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_VSU_STALL_VECTOR_CPI;Cycles stalled by VSU Vector Operations @@PM_CMPLU_STALL_VECTOR / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_VSU_STALL_DFU_CPI;Cycles stalled by DFU @@PM_CMPLU_STALL_DFU / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_VSU_STALL_CPI;Cycles stalled by VSU @@PMD_VSU_STALL_SCALAR_CPI + PMD_VSU_STALL_VECTOR_CPI + PMD_VSU_STALL_DFU_CPI @@@group=CPI_Breakdown @PMD_VSU_STALL_SCALAR_LONG_CPI;Cycles stalled by VSU Scalar Long Operations @@PM_CMPLU_STALL_SCALAR_LONG / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_VSU_STALL_SCALAR_OTHER_CPI;Cycles stalled by Other VSU Scalar Operations @@PMD_VSU_STALL_SCALAR_CPI - PMD_VSU_STALL_SCALAR_LONG_CPI @@@group=CPI_Breakdown @PMD_LSU_STALL_CPI;Cycles stalled by LSU @@PM_CMPLU_STALL_LSU / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_LSU_STALL_REJECT_CPI;Cycles stalled by LSU Rejects @@PM_CMPLU_STALL_REJECT / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_LSU_STALL_ERAT_MISS_CPI;Cycles stalled by ERAT Translations @@PM_CMPLU_STALL_ERAT_MISS / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_LSU_STALL_REJECT_OTHER_CPI;Cycles stalled by Other LSU Rejects @@PMD_LSU_STALL_REJECT_CPI - PMD_LSU_STALL_ERAT_MISS_CPI @@@group=CPI_Breakdown @PMD_LSU_STALL_DCACHE_MISS_CPI;Cycles stalled by D-Cache Misses @@PM_CMPLU_STALL_DCACHE_MISS / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_LSU_STALL_OTHER_CPI;Cycles stalled by Other LSU Operations @@PMD_LSU_STALL_CPI - PMD_LSU_STALL_REJECT_CPI - PMD_LSU_STALL_DCACHE_MISS_CPI @@@group=CPI_Breakdown @PMD_SMT_STALL_CPI;Cycles stalled by SMT @@PM_CMPLU_STALL_THRD / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_STALL_CPI;Completion Stall Cycles @@PM_CMPLU_STALL / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_FXU_STALL_CPI;Cycles stalled by FXU @@PM_CMPLU_STALL_FXU / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_OTHER_STALL_CPI;Other stall cycles @@PMD_STALL_CPI - PMD_FXU_STALL_CPI - PMD_VSU_STALL_CPI - PMD_LSU_STALL_CPI - PMD_SMT_STALL_CPI @@@group=CPI_Breakdown @PMD_FXU_MULTI_CYC_CPI;Cycles stalled by FXU Multi-Cycle Instructions @@PM_CMPLU_STALL_DIV / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_FXU_STALL_OTHER_CPI;Other cycles stalled by FXU @@PMD_FXU_STALL_CPI - PMD_FXU_MULTI_CYC_CPI @@@group=CPI_Breakdown @PMD_GCT_EMPTY_CPI;GCT empty cycles @@PM_GCT_NOSLOT_CYC / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_GCT_EMPTY_IC_MISS_CPI;Cycles GCT empty due to I-Cache Misses @@PM_GCT_NOSLOT_IC_MISS / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_GCT_EMPTY_BR_MPRED_CPI;Cycles GCT empty due to Branch Mispredicts @@PM_GCT_NOSLOT_BR_MPRED / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_GCT_EMPTY_BR_MPRED_IC_MISS_CPI;Cycles GCT empty due to Branch Mispredicts and Icache Misses @@PM_GCT_NOSLOT_BR_MPRED_IC_MISS / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_GCT_EMPTY_OTHER_CPI;Other GCT empty cycles @@PMD_GCT_EMPTY_CPI - PMD_GCT_EMPTY_IC_MISS_CPI - PMD_GCT_EMPTY_BR_MPRED_CPI - PMD_GCT_EMPTY_BR_MPRED_IC_MISS_CPI @@@group=CPI_Breakdown @PMD_COMPLETION_CPI;Cycles in which a Group Completed @@PM_GRP_CMPL / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_BASE_COMPLETION_CPI;Base Completion Cycles @@PM_1PLUS_PPC_CMPL / PM_RUN_INST_CMPL @@@group=CPI_Breakdown @PMD_EXPANSION_OVERHEAD_CPI;Overhead of expansion cycles @@PMD_RUN_CPI - PMD_STALL_CPI - PMD_GCT_EMPTY_CPI - PMD_BASE_COMPLETION_CPI @@@group=CPI_Breakdown @PMD_FPU_FINISH;Fraction of cycles an FPU delivers a result assuming 1 cycle per op @@PM_VSU_FIN / PM_RUN_CYC @@@group=Instruction_Mix @PMD_FPU0_BALANCE;FPU0 balance @@PM_VSU0_FIN / PM_VSU_FIN @@@group=Instruction_Mix @PMD_FXU_BOTH_BUSY;Both FXU Busy @@PM_FXU_BUSY / PM_CYC @@@group=Instruction_Mix @PMD_FXU0_ONLY_BUSY;FXU0 only Busy @@PM_FXU0_BUSY_FXU1_IDLE / PM_CYC @@@group=Instruction_Mix @PMD_FXU1_ONLY_BUSY;FXU1 only Busy @@PM_FXU1_BUSY_FXU0_IDLE / PM_CYC @@@group=Instruction_Mix @PMD_FXU_BOTH_IDLE;Both FXU Idle @@PM_FXU_IDLE / PM_CYC @@@group=Instruction_Mix @PMD_FXU0_BALANCE;FXU0 balance @@PM_FXU0_FIN / (PM_FXU0_FIN + PM_FXU1_FIN) @@@group=Instruction_Mix @PMD_LD_PER_INST;PCT instruction loads @@PM_LD_REF_L1 / PM_INST_CMPL @@@group=Instruction_Mix @PMD_ST_PER_INST;PCT instruction stores @@(PM_ST_FIN - PM_ST_MISS_L1) / PM_INST_CMPL @@@group=Instruction_Mix @PMD_BR_PER_INST;% Branches per instruction @@PM_BRU_FIN / PM_INST_CMPL @@@group=Instruction_Mix @PMD_FXD_PER_INST;Total Fixed point operations @@(PM_FXU0_FIN + PM_FXU1_FIN)/PM_INST_CMPL @@@group=Instruction_Mix @PMD_FP_LOAD_STORE_PER_INST;Floating point load and store operations @@(PM_LSU_LDF + PM_VSU_STF) * 0.000001 @@@group=Instruction_Mix @PMD_FMA_PER_INST;FMA_perInst @@PM_VSU_FMA / PM_INST_CMPL @@@group=Instruction_Mix @PMD_FP_COMPUTATION_INTENSITY;Floating point Computation intensity @@(PM_VSU_1FLOP + PM_VSU_FMA) / (PM_LSU_LDF + PM_VSU_STF) @@@group=Instruction_Mix @PMD_FXU0_FIN;Fraction of cycles that FXU0 is in use @@PM_FXU0_FIN / PM_RUN_CYC @@@group=Instruction_Mix @PMD_FXU1_FIN;Fraction of cycles that FXU1 is in use @@PM_FXU1_FIN / PM_RUN_CYC @@@group=Instruction_Mix @PMD_MPRED_CR;Branch Misprediction for CR;% @@PM_BR_MPRED_CR / (PM_BR_PRED_CR + PM_BR_PRED_CCACHE + PM_BR_PRED_LSTACK) * 100 @@@group=Branch_Prediction @PMD_MPRED_TA;Branch Misprediction for TA;% @@PM_BR_MPRED_TA / (PM_BR_PRED_CR + PM_BR_PRED_CCACHE + PM_BR_PRED_LSTACK) * 100 @@@group=Branch_Prediction @PMD_TA_MPRED_CCACHE;% of Branch miss predictions that were due to Count cache mispredictions;% @@PM_BR_MPRED_CCACHE / (PM_BR_PRED_CR + PM_BR_PRED_CCACHE + PM_BR_PRED_LSTACK) * 100 @@@group=Branch_Prediction @PMD_TA_MPRED_LSTACK;% of Branch miss predictions that were due to Link stack mispredictions;% @@(PM_BR_MPRED_TA - PM_BR_MPRED_CCACHE) / (PM_BR_PRED_CR + PM_BR_PRED_CCACHE + PM_BR_PRED_LSTACK) * 100 @@@group=Branch_Prediction @PMD_TAKEN_BRANCHES;% Branches Taken;% @@PM_BR_TAKEN * 100 / PM_BRU_FIN @@@group=Branch_Prediction @PMD_BR_MPRED;% of BR Miss Prediction;% @@PM_BR_MPRED / PM_BR_PRED * 100 @@@group=Branch_Prediction @PMD_CR_MPRED;% of CR Miss Prediction;% @@PM_BR_MPRED_CR / PM_BR_PRED_CR * 100 @@@group=Branch_Prediction @PMD_CCACHE_MPRED;Count cache branch misprediction;% @@PM_BR_MPRED_CCACHE / PM_BR_PRED_CCACHE * 100 @@@group=Branch_Prediction @PMD_TA_MPRED;% of TA Miss Prediction;% @@PM_BR_MPRED_TA / (PM_BR_PRED_CCACHE + PM_BR_PRED_LSTACK) * 100 @@@group=Branch_Prediction @PMD_LSTACK_MPRED;Link stack branch misprediction;% @@(PM_BR_MPRED_TA - PM_BR_MPRED_CCACHE) / PM_BR_PRED_LSTACK * 100 @@@group=Branch_Prediction @PMD_DL1_RELOAD_FROM_L2_RATE;% of DL1 reloads from L2 per Inst;% @@PM_DATA_FROM_L2 * 100 / PM_INST_CMPL @@@group=dL1_Reloads_percentage_per_inst @PMD_DL1_RELOAD_FROM_L21_MOD_RATE;% of DL1 reloads from Private L2, other core per Inst;% @@PM_DATA_FROM_L21_MOD * 100 / PM_INST_CMPL @@@group=dL1_Reloads_percentage_per_inst @PMD_DL1_RELOAD_FROM_L21_SHR_RATE;% of DL1 reloads from Private L2, other core per Inst;% @@PM_DATA_FROM_L21_SHR * 100 / PM_INST_CMPL @@@group=dL1_Reloads_percentage_per_inst @PMD_DL1_RELOAD_FROM_L2_MISS_RATE;% of DL1 reloads from L2 per Inst;% @@PM_DATA_FROM_L2MISS * 100 / PM_INST_CMPL @@@group=dL1_Reloads_percentage_per_inst @PMD_DL1_RELOAD_FROM_L3_RATE;% of DL1 Reloads from L3 per Inst;% @@PM_DATA_FROM_L3 * 100 / PM_INST_CMPL @@@group=dL1_Reloads_percentage_per_inst @PMD_DL1_RELOAD_FROM_L3_MISS_RATE;% of DL1 reloads from L3 per Inst;% @@PM_DATA_FROM_L3MISS * 100 / PM_INST_CMPL @@@group=dL1_Reloads_percentage_per_inst @PMD_DL1_RELOAD_FROM_RL2L3_SHR_RATE;% of DL1 Reloads from Remote L2 or L3 (Shared) per Inst;% @@PM_DATA_FROM_RL2L3_SHR * 100 / PM_INST_CMPL @@@group=dL1_Reloads_percentage_per_inst @PMD_DL1_RELOAD_FROM_RL2L3_MOD_RATE;% of DL1 Reloads from Remote L2 or L3 (Modified) per Inst;% @@PM_DATA_FROM_RL2L3_MOD * 100 / PM_INST_CMPL @@@group=dL1_Reloads_percentage_per_inst @PMD_DL1_RELOAD_FROM_DL2L3_MOD_RATE;% of DL1 Reloads from Distant L2 or L3 (Modified) per Inst;% @@PM_DATA_FROM_DL2L3_MOD * 100 / PM_INST_CMPL @@@group=dL1_Reloads_percentage_per_inst @PMD_DL1_RELOAD_FROM_DL2L3_SHR_RATE;% of DL1 Reloads from Distant L2 or L3 (Shared) per Inst;% @@PM_DATA_FROM_DL2L3_SHR * 100 / PM_INST_CMPL @@@group=dL1_Reloads_percentage_per_inst @PMD_DL1_RELOAD_FROM_LMEM_RATE;% of DL1 Reloads from Local Memory per Inst;% @@PM_DATA_FROM_LMEM * 100 / PM_INST_CMPL @@@group=dL1_Reloads_percentage_per_inst @PMD_DL1_RELOAD_FROM_RMEM_RATE;% of DL1 Reloads from Remote Memory per Inst;% @@PM_DATA_FROM_RMEM * 100 / PM_INST_CMPL @@@group=dL1_Reloads_percentage_per_inst @PMD_DL1_RELOAD_FROM_DMEM_RATE;% of DL1 Reloads from Distant Memory per Inst;% @@PM_DATA_FROM_DMEM * 100 / PM_INST_CMPL @@@group=dL1_Reloads_percentage_per_inst @PMD_DL1_MISS_RELOADS;% of DL1 misses that result in a cache reload;% @@PM_L1_DCACHE_RELOAD_VALID * 100 / PM_LD_MISS_L1 @@@group=dL1_Reloads_percentage_per_ref @PMD_DL1_RELOAD_FROM_L2;% of DL1 reloads from L2;% @@PM_DATA_FROM_L2 * 100 / PM_L1_DCACHE_RELOAD_VALID @@@group=dL1_Reloads_percentage_per_ref @PMD_DL1_RELOAD_FROM_L21_MOD;% of DL1 reloads from Private L2, other core;% @@PM_DATA_FROM_L21_MOD * 100 / PM_L1_DCACHE_RELOAD_VALID @@@group=dL1_Reloads_percentage_per_ref @PMD_DL1_RELOAD_FROM_L21_SHR;% of DL1 reloads from Private L2, other core;% @@PM_DATA_FROM_L21_SHR * 100 / PM_L1_DCACHE_RELOAD_VALID @@@group=dL1_Reloads_percentage_per_ref @PMD_DL1_RELOAD_FROM_L3;% of DL1 dL1_Reloads from L3;% @@PM_DATA_FROM_L3 * 100 / PM_L1_DCACHE_RELOAD_VALID @@@group=dL1_Reloads_percentage_per_ref @PMD_DL1_RELOAD_FROM_RL2L3_SHR;% of DL1 dL1_Reloads from Remote L2 or L3 (Shared);% @@PM_DATA_FROM_RL2L3_SHR * 100 / PM_L1_DCACHE_RELOAD_VALID @@@group=dL1_Reloads_percentage_per_ref @PMD_DL1_RELOAD_FROM_RL2L3_MOD;% of DL1 dL1_Reloads from Remote L2 or L3 (Modified);% @@PM_DATA_FROM_RL2L3_MOD * 100 / PM_L1_DCACHE_RELOAD_VALID @@@group=dL1_Reloads_percentage_per_ref @PMD_DL1_RELOAD_FROM_DL2L3_MOD;% of DL1 dL1_Reloads from Distant L2 or L3 (Modified);% @@PM_DATA_FROM_DL2L3_MOD * 100 / PM_L1_DCACHE_RELOAD_VALID @@@group=dL1_Reloads_percentage_per_ref @PMD_DL1_RELOAD_FROM_DL2L3_SHR;% of DL1 dL1_Reloads from Distant L2 or L3 (Shared);% @@PM_DATA_FROM_DL2L3_SHR * 100 / PM_L1_DCACHE_RELOAD_VALID @@@group=dL1_Reloads_percentage_per_ref @PMD_DL1_RELOAD_FROM_LMEM;% of DL1 dL1_Reloads from Local Memory;% @@PM_DATA_FROM_LMEM * 100 / PM_L1_DCACHE_RELOAD_VALID @@@group=dL1_Reloads_percentage_per_ref @PMD_DL1_RELOAD_FROM_RMEM;% of DL1 dL1_Reloads from Remote Memory;% @@PM_DATA_FROM_RMEM * 100 / PM_L1_DCACHE_RELOAD_VALID @@@group=dL1_Reloads_percentage_per_ref @PMD_DL1_RELOAD_FROM_DMEM;% of DL1 dL1_Reloads from Distant Memory;% @@PM_DATA_FROM_DMEM * 100 / PM_L1_DCACHE_RELOAD_VALID @@@group=dL1_Reloads_percentage_per_ref @PMD_LD_BYTES;Load Bytes @@(PM_LD_REF_L1 - PM_LSU_LDF) * 4 + PM_LSU_LDF * 8 @@@group=Memory @PMD_ST_BYTES;Store Bytes @@((PM_ST_FIN - PM_ST_MISS_L1) - PM_VSU_STF) * 4 + PM_VSU_STF * 8 @@@group=Memory @PMD_MEM_LOCALITY;Memory locality @@PM_DATA_FROM_LMEM / (PM_DATA_FROM_LMEM + PM_DATA_FROM_RMEM + PM_DATA_FROM_DMEM) @@@group=Memory @PMD_MEM_LD_TRAF;Memory load traffic;MBytes @@(PM_DATA_FROM_LMEM + PM_DATA_FROM_RMEM + PM_DATA_FROM_DMEM) * MEM_LINE_SIZE * CACHE_LINE_SIZE / (1024 * 1024) @@@group=Memory @PMD_MEM_LD_BDW;Memory load bandwidth per processor;MBytes/s @@(PM_DATA_FROM_LMEM + PM_DATA_FROM_RMEM + PM_DATA_FROM_DMEM) * MEM_LINE_SIZE * CACHE_LINE_SIZE / (1024 * 1024) / total_time @@@group=Memory @PMD_LD_LMEM_PER_LD_RMEM;Number of loads from local memory per loads from remote memory @@PM_DATA_FROM_LMEM / PM_DATA_FROM_RMEM @@@group=Memory @PMD_LD_LMEM_PER_LD_DMEM;Number of loads from local memory per loads from distant memory @@PM_DATA_FROM_LMEM / PM_DATA_FROM_DMEM @@@group=Memory @PMD_LD_LMEM_PER_LD_MEM;Number of loads from local memory per loads from remote and distant memory @@PM_DATA_FROM_LMEM / (PM_DATA_FROM_DMEM + PM_DATA_FROM_RMEM) @@@group=Memory @PMD_LD_RMEM_PER_LD_DMEM;Number of loads from remote memory per loads from distant memory @@PM_DATA_FROM_RMEM / PM_DATA_FROM_DMEM @@@group=Memory @PMD_DSLB_MISS_RATE;% DSLB_Miss_Rate per inst;% @@PM_DSLB_MISS * 100 / PM_INST_CMPL @@@group=Translation @PMD_DERAT_MISS_RATIO;DERAT miss ratio @@PM_LSU_DERAT_MISS / PM_RUN_INST_CMPL @@@group=Translation @PMD_DERAT_4K_MISS_RATIO;DERAT miss ratio for 4K page @@PM_DERAT_MISS_4K / PM_LSU_DERAT_MISS @@@group=Translation @PMD_DERAT_64K_MISS_RATIO;DERAT miss ratio for 64K page @@PM_DERAT_MISS_64K / PM_LSU_DERAT_MISS @@@group=Translation @PMD_DERAT_16G_MISS_RATIO;DERAT miss ratio for 16G page @@PM_DERAT_MISS_16G / PM_LSU_DERAT_MISS @@@group=Translation @PMD_DERAT_16M_MISS_RATIO;DERAT miss ratio for 16M page @@PM_DERAT_MISS_16M / PM_LSU_DERAT_MISS @@@group=Translation @PMD_IERAT_MISS_RATE;IERAT miss rate (%);% @@PM_IERAT_MISS * 100 / PM_INST_CMPL @@@group=Translation @PMD_ISLB_MISS_RATE;% ISLB miss rate per inst;% @@PM_ISLB_MISS * 100 / PM_INST_CMPL @@@group=Translation @PMD_PTEG_FETCH;Page Table Entry fetches @@PM_PTEG_FROM_L2 + PM_PTEG_FROM_L2MISS @@@group=Translation @PMD_PTEG_PER_DERAT;Page Table Entry fetches per DERAT @@PMD_PTEG_FETCH / PM_LSU_DERAT_MISS @@@group=Translation @PMD_DERAT_4K_MISS_RATE;% DERAT miss rate for 4K page per inst;% @@PM_DERAT_MISS_4K * 100 / PM_INST_CMPL @@@group=Translation @PMD_DERAT_64K_MISS_RATE;% DERAT miss ratio for 64K page per inst;% @@PM_DERAT_MISS_64K * 100 / PM_INST_CMPL @@@group=Translation @PMD_DERAT_16M_MISS_RATE;% DERAT miss rate for 16M page per inst;% @@PM_DERAT_MISS_16M * 100 / PM_INST_CMPL @@@group=Translation @PMD_DERAT_16G_MISS_RATE;% DERAT miss ratio for 16G page per inst;% @@PM_DERAT_MISS_16G / PM_INST_CMPL @@@group=Translation #@PMD_DERAT_MISS_RELOAD;% of DERAT misses that result in an ERAT reload;% #@@PM_PTEG_RELOAD_VALID * 100 / PM_LSU_DERAT_MISS #@@@group=PTEG_Reloads_percentage_per_ref #@PMD_PTEG_FROM_L2;% of DERAT reloads from L2;% #@@PM_PTEG_FROM_L2 * 100 / PM_PTEG_RELOAD_VALID #@@@group=PTEG_Reloads_percentage_per_ref #@PMD_PTEG_FROM_RMEM;% of DERAT reloads from Remote Memory;% #@@PM_PTEG_FROM_RMEM * 100 / PM_PTEG_RELOAD_VALID #@@@group=PTEG_Reloads_percentage_per_ref #@PMD_PTEG_FROM_DMEM;% of DERAT reloads from Distant Memory;% #@@PM_PTEG_FROM_DMEM * 100 / PM_PTEG_RELOAD_VALID #@@@group=PTEG_Reloads_percentage_per_ref #@PMD_PTEG_FROM_L21_MOD;% of DERAT reloads from Private L2, other core;% #@@PM_PTEG_FROM_L21_MOD * 100 / PM_PTEG_RELOAD_VALID #@@@group=PTEG_Reloads_percentage_per_ref #@PMD_PTEG_FROM_L21_SHR;% of DERAT reloads from Private L2, other core;% #@@PM_PTEG_FROM_L21_SHR * 100 / PM_PTEG_RELOAD_VALID #@@@group=PTEG_Reloads_percentage_per_ref #@PMD_PTEG_FROM_L3;% of DERAT reloads from L3;% #@@PM_PTEG_FROM_L3 * 100 / PM_PTEG_RELOAD_VALID #@@@group=PTEG_Reloads_percentage_per_ref #@PMD_PTEG_FROM_RL2L3_SHR;% of DERAT reloads from Remote L2 or L3 (Shared);% #@@PM_PTEG_FROM_RL2L3_SHR * 100 / PM_PTEG_RELOAD_VALID #@@@group=PTEG_Reloads_percentage_per_ref #@PMD_PTEG_FROM_RL2L3_MOD;% of DERAT reloads from Remote L2 or L3 (Modified);% #@@PM_PTEG_FROM_RL2L3_MOD * 100 / PM_PTEG_RELOAD_VALID #@@@group=PTEG_Reloads_percentage_per_ref #@PMD_PTEG_FROM_DL2L3_MOD;% of DERAT reloads from Distant L2 or L3 (Modified);% #@@PM_PTEG_FROM_DL2L3_MOD * 100 / PM_PTEG_RELOAD_VALID #@@@group=PTEG_Reloads_percentage_per_ref #@PMD_PTEG_FROM_DL2L3_SHR;% of DERAT reloads from Distant L2 or L3 (Shared);% #@@PM_PTEG_FROM_DL2L3_SHR * 100 / PM_PTEG_RELOAD_VALID #@@@group=PTEG_Reloads_percentage_per_ref #@PMD_PTEG_FROM_LMEM;% of DERAT reloads from Local Memory;% #@@PM_PTEG_FROM_LMEM * 100 / PM_PTEG_RELOAD_VALID #@@@group=PTEG_Reloads_percentage_per_ref @PMD_PTEG_FROM_L2_RATE;% of DERAT reloads from L2 per inst;% @@PM_PTEG_FROM_L2 * 100 / PM_INST_CMPL @@@group=PTEG_Reloads_percentage_per_inst @PMD_PTEG_FROM_L21_MOD_RATE;% of DERAT reloads from Private L2, other core per inst;% @@PM_PTEG_FROM_L21_MOD * 100 / PM_INST_CMPL @@@group=PTEG_Reloads_percentage_per_inst @PMD_PTEG_FROM_L21_SHR_RATE;% of DERAT reloads from Private L2, other core per inst;% @@PM_PTEG_FROM_L21_SHR * 100 / PM_INST_CMPL @@@group=PTEG_Reloads_percentage_per_inst @PMD_PTEG_FROM_L3_RATE;% of DERAT reloads from L3 per inst;% @@PM_PTEG_FROM_L3 * 100 / PM_INST_CMPL @@@group=PTEG_Reloads_percentage_per_inst @PMD_PTEG_FROM_RL2L3_SHR_RATE;% of DERAT reloads from Remote L2 or L3 (Shared) per inst;% @@PM_PTEG_FROM_RL2L3_SHR * 100 / PM_INST_CMPL @@@group=PTEG_Reloads_percentage_per_inst @PMD_PTEG_FROM_RL2L3_MOD_RATE;% of DERAT reloads from Remote L2 or L3 (Modified) per inst;% @@PM_PTEG_FROM_RL2L3_MOD * 100 / PM_INST_CMPL @@@group=PTEG_Reloads_percentage_per_inst @PMD_PTEG_FROM_DL2L3_MOD_RATE;% of DERAT reloads from Distant L2 or L3 (Modified) per inst;% @@PM_PTEG_FROM_DL2L3_MOD * 100 / PM_INST_CMPL @@@group=PTEG_Reloads_percentage_per_inst #@PMD_PTEG_FROM_DL2L3_SHR_RATE;% of DERAT reloads from Distant L2 or L3 (Shared) per inst;% #@@PM_PTEG_FROM_DL2L3_SHR * 100 / PM_INST_CMPL #@@@group=PTEG_Reloads_percentage_per_inst @PMD_PTEG_FROM_LMEM_RATE;% of DERAT reloads from Local Memory per inst;% @@PM_PTEG_FROM_LMEM * 100 / PM_INST_CMPL @@@group=PTEG_Reloads_percentage_per_inst @PMD_PTEG_FROM_RMEM_RATE;% of DERAT reloads from Remote Memory per inst;% @@PM_PTEG_FROM_RMEM * 100 / PM_INST_CMPL @@@group=PTEG_Reloads_percentage_per_inst @PMD_PTEG_FROM_DMEM_RATE;% of DERAT reloads from Distant Memory per inst;% @@PM_PTEG_FROM_DMEM * 100 / PM_INST_CMPL @@@group=PTEG_Reloads_percentage_per_inst @PMD_FLOPS;FLOPs @@PM_VSU_1FLOP + 2 * PM_VSU_FMA + 4 * PM_VSU_FSQRT_FDIV @@@group=VSU_Stats @PMD_LSU_REJ_RATIO;LSU reject ratio @@PM_LSU_REJECT / (PM_LD_REF_L1 + (PM_ST_FIN - PM_ST_MISS_L1)) @@@group=LSU_Rejects @PMD_LHS_REJ_RATIO;LHS reject ratio @@PM_LSU_REJECT_LHS / PM_LD_REF_L1 @@@group=LSU_Rejects @PMD_INST_FROM_RL2L3_SHR;% of ICache reloads from Remote L2 or L3 (Shared);% @@PM_INST_FROM_RL2L3_SHR * 100 / PM_L1_ICACHE_MISS @@@group=Instruction_Stats_Percentage_per_ref @PMD_INST_FROM_RL2L3_MOD;% of ICache reloads from Remote L2 or L3 (Modified);% @@PM_INST_FROM_RL2L3_MOD * 100 / PM_L1_ICACHE_MISS @@@group=Instruction_Stats_Percentage_per_ref @PMD_ICACHE_MISS_RELOAD;Icache Fetchs per Icache Miss @@(PM_L1_ICACHE_MISS - PM_IC_PREF_WRITE) / PM_L1_ICACHE_MISS @@@group=Instruction_Stats_Percentage_per_ref @PMD_INST_FROM_L2;% of ICache reloads from L2;% @@PM_INST_FROM_L2 * 100 / PM_L1_ICACHE_MISS @@@group=Instruction_Stats_Percentage_per_ref @PMD_INST_FROM_L21_MOD;% of ICache reloads from Private L2, other core;% @@PM_INST_FROM_L21_MOD * 100 / PM_L1_ICACHE_MISS @@@group=Instruction_Stats_Percentage_per_ref @PMD_INST_FROM_L21_SHR;% of ICache reloads from Private L2, other core;% @@PM_INST_FROM_L21_SHR * 100 / PM_L1_ICACHE_MISS @@@group=Instruction_Stats_Percentage_per_ref @PMD_INST_FROM_L3;% of ICache reloads from L3;% @@PM_INST_FROM_L3 * 100 / PM_L1_ICACHE_MISS @@@group=Instruction_Stats_Percentage_per_ref @PMD_INST_FROM_DL2L3_MOD;% of ICache reloads from Distant L2 or L3 (Modified);% @@PM_INST_FROM_DL2L3_MOD * 100 / PM_L1_ICACHE_MISS @@@group=Instruction_Stats_Percentage_per_ref @PMD_INST_FROM_DL2L3_SHR;% of ICache reloads from Distant L2 or L3 (Shared);% @@PM_INST_FROM_DL2L3_SHR * 100 / PM_L1_ICACHE_MISS @@@group=Instruction_Stats_Percentage_per_ref @PMD_INST_FROM_LMEM;% of ICache reloads from Local Memory;% @@PM_INST_FROM_LMEM * 100 / PM_L1_ICACHE_MISS @@@group=Instruction_Stats_Percentage_per_ref @PMD_INST_FROM_RMEM;% of ICache reloads from Remote Memory;% @@PM_INST_FROM_RMEM * 100 / PM_L1_ICACHE_MISS @@@group=Instruction_Stats_Percentage_per_ref @PMD_INST_FROM_DMEM;% of ICache reloads from Distant Memory;% @@PM_INST_FROM_DMEM * 100 / PM_L1_ICACHE_MISS @@@group=Instruction_Stats_Percentage_per_ref @PMD_INST_FROM_L2_RATE;% of ICache reloads from L2 per Inst;% @@PM_INST_FROM_L2 * 100 / PM_INST_CMPL @@@group=Instruction_Stats_Percentage_per_inst @PMD_INST_FROM_L21_MOD_RATE;% of ICache reloads from Private L2, other core per Inst;% @@PM_INST_FROM_L21_MOD * 100 / PM_INST_CMPL @@@group=Instruction_Stats_Percentage_per_inst @PMD_INST_FROM_L21_SHR_RATE;% of ICache reloads from Private L2, other core per Inst;% @@PM_INST_FROM_L21_SHR * 100 / PM_INST_CMPL @@@group=Instruction_Stats_Percentage_per_inst @PMD_INST_FROM_L3_RATE;% of ICache reloads from L3 per Inst;% @@PM_INST_FROM_L3 * 100 / PM_INST_CMPL @@@group=Instruction_Stats_Percentage_per_inst @PMD_INST_FROM_RL2L3_SHR_RATE;% of ICache reloads from Remote L2 or L3 (Shared) per Inst;% @@PM_INST_FROM_RL2L3_SHR * 100 / PM_INST_CMPL @@@group=Instruction_Stats_Percentage_per_inst @PMD_INST_FROM_RL2L3_MOD_RATE;% of ICache reloads from Remote L2 or L3 (Modified) per Inst;% @@PM_INST_FROM_RL2L3_MOD * 100 / PM_INST_CMPL @@@group=Instruction_Stats_Percentage_per_inst @PMD_INST_FROM_DL2L3_MOD_RATE;% of ICache reloads from Distant L2 or L3 (Modified) per Inst;% @@PM_INST_FROM_DL2L3_MOD * 100 / PM_INST_CMPL @@@group=Instruction_Stats_Percentage_per_inst @PMD_INST_FROM_DL2L3_SHR_RATE;% of ICache reloads from Distant L2 or L3 (Shared) per Inst;% @@PM_INST_FROM_DL2L3_SHR * 100 / PM_INST_CMPL @@@group=Instruction_Stats_Percentage_per_inst @PMD_INST_FROM_LMEM_RATE;% of ICache reloads from Local Memory per Inst;% @@PM_INST_FROM_LMEM * 100 / PM_INST_CMPL @@@group=Instruction_Stats_Percentage_per_inst @PMD_INST_FROM_RMEM_RATE;% of ICache reloads from Remote Memory per Inst;% @@PM_INST_FROM_RMEM * 100 / PM_INST_CMPL @@@group=Instruction_Stats_Percentage_per_inst @PMD_INST_FROM_DMEM_RATE;% of ICache reloads from Distant Memory per Inst;% @@PM_INST_FROM_DMEM * 100 / PM_INST_CMPL @@@group=Instruction_Stats_Percentage_per_inst