{ @(#)M		1.1.1.9  src/bos/usr/sbin/perf/pmapi/events/POWER6.evs, pmapi, bos720 6/29/07 10:18:29
{ IBM_PROLOG_BEGIN_TAG 
{ This is an automatically generated prolog. 
{  
{ bos720 src/bos/usr/sbin/perf/pmapi/events/POWER6.evs 1.1.1.9 
{  
{ Licensed Materials - Property of IBM 
{  
{ COPYRIGHT International Business Machines Corp. 2005,2007 
{ All Rights Reserved 
{  
{ US Government Users Restricted Rights - Use, duplication or 
{ disclosure restricted by GSA ADP Schedule Contract with IBM Corp. 
{  
{ IBM_PROLOG_END_TAG 

355,365,347,348,1,1

{ counter 1 }
#0,v,g,n,n,n,PM_0INST_FETCH,No instructions fetched
##40080
No instructions were fetched this cycles (due to IFU hold, redirect, or icache miss)
#1,v,g,n,n,n,PM_1PLUS_PPC_CMPL,One or more PPC instruction completed
##00004,000F2
A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once.
#2,v,g,n,n,n,PM_1PLUS_PPC_DISP,Cycles at least one instruction dispatched
##00012
A group containing at least one PPC instruction was dispatched. For microcoded instructions that span multiple groups, this will only occur once.
#3,v,g,n,n,n,PM_BRU_FIN,BRU produced a result
##430E6
The Branch execution unit finished an instruction
#4,v,g,n,n,n,PM_BR_MPRED_CCACHE,Branch misprediction due to count cache prediction
##410AE
A branch instruction target was incorrectly predicted by the ccount cache. This will result in a branch redirect flush if not overfidden by a flush of an older instruction.
#5,v,g,n,n,n,PM_BR_MPRED_COUNT,Branch misprediction due to count prediction
##410AA
A branch instruction count value was incorrectly predicted. This will result in a branch mispredict flush unless a flush is detected from an older instruction.
#6,v,g,n,n,n,PM_BR_MPRED_CR,Branch mispredictions due to CR bit setting
##410A8
A conditional branch instruction was incorrectly predicted as taken or not taken. The branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This will result in a branch redirect flush if not overfidden by a flush of an older instruction.
#7,v,g,n,n,n,PM_BR_MPRED_TA,Branch mispredictions due to target address
##410AC
A branch instruction target was incorrectly predicted. This will result in a branch mispredict flush unless a flush is detected from an older instruction.
#8,v,g,n,n,n,PM_BR_PRED,A conditional branch was predicted
##410A0
A branch prediction was made. This could have been a target prediction, a condition prediction, or both
#9,v,g,n,n,n,PM_BR_PRED_CCACHE,Branch count cache prediction
##410A4
The count value of a Branch and Count instruction was predicted
#10,v,g,n,n,n,PM_BR_PRED_CR,A conditional branch was predicted, CR prediction
##410A2
A conditional branch instruction was predicted as taken or not taken.
#11,v,g,n,n,n,PM_BR_PRED_LSTACK,A conditional branch was predicted, link stack
##410A6
The target address of a Branch to Link instruction was predicted by the link stack.
#12,v,g,n,c,n,PM_CYC,Processor cycles
##0001E
Processor cycles
#13,v,g,n,n,n,PM_DATA_FROM_L2,Data loaded from L2
##00058
The processor's Data Cache was reloaded from the local L2 due to a demand load.
#14,v,g,n,n,n,PM_DATA_FROM_L35_MOD,Data loaded from L3.5 modified
##0005A
The processor's Data Cache was reloaded with modified (M) data from the L3 of a chip on the same module as this processor is located due to a demand load.
#15,v,g,n,n,n,PM_DATA_FROM_MEM_DP,Data loaded from double pump memory
##0005E
This event should have been removed from the documentation by now. The core will never see this data sources as it is used by the L2
#16,v,g,n,n,n,PM_DATA_FROM_RL2L3_MOD,Data loaded from remote L2 or L3 modified
##0005C
The processor's Data Cache was reloaded with modified (M) data from an L2  or L3 on a remote module due to a demand load
#17,v,g,n,n,n,PM_DATA_PTEG_1ST_HALF,Data table walk matched in first half primary PTEG
##910A0
A translation request for a data address was satisfied using the primary page table hash. The matching Page Table Entry is one of the first four PTE entries of the primary PTEG
#18,v,g,n,n,n,PM_DATA_PTEG_2ND_HALF,Data table walk matched in second half primary PTEG
##910A2
A translation request for a data address was satisfied using the primary page table hash. The matching Page Table Entry is one of the second four PTE entries of the primary PTEG
#19,v,g,n,n,n,PM_DATA_PTEG_SECONDARY,Data table walk matched in secondary PTEG
##910A4
A translation request for a data address was satisfied using the secondary page table hash. 
#20,u,g,n,c,n,PM_DC_INV_L2,L1 D cache entries invalidated from L2
##50632
A dcache invalidated was received from the L2 because a line in L2 was castout.
#21,u,g,n,n,n,PM_DC_PREF_OUT_OF_STREAMS,D cache out of streams
##810A0
A new prefetch stream was detected but no more stream entries were available.
#22,v,g,n,n,n,PM_DC_PREF_STREAM_ALLOC,D cache new prefetch stream allocated
##810A2
A new Prefetch Stream was allocated.
#23,v,g,n,n,n,PM_DFU_ADD,DFU add type instruction
##E008C
The Decimal Floating Point Unit executed an add type instruction. This could be dadd, dsub, dcmpo, or dcmpu
#24,v,g,n,n,n,PM_DFU_ADD_SHIFTED_BOTH,DFU add type with both operands shifted
##E0088
The Decimal Floating Point Unit executed an add type instruction and both operands required shifting. This could be dadd, dsub, dcmpo, or dcmpu
#25,v,g,n,n,n,PM_DFU_BACK2BACK,DFU back to back operations executed
##E0082
The Decimal Floating Point Unit executed two instructions back to back.
#26,v,g,n,n,n,PM_DFU_CONV,DFU convert from fixed op
##E008E
The Decimal Floating Point Unit executed a convert from fixed point operation. This could be a dcffix or dcffixq instruction. The fixed point operand was converted to a Decimal Floating Point number
#27,v,g,n,n,n,PM_DFU_ENC_BCD_DPD,DFU Encode BCD to DPD
##E008A
The Decimal Floating Point Unit executed an encode to fixed point operation. This could have been a denbcd or denbcdq instruction. The binary coded decimal operand is convered to a binary floating point number.
#28,v,g,n,n,n,PM_DFU_EXP_EQ,DFU operand exponents are equal for add type
##E0084
The Decimal Floating Point Unit executed an add type instruction and the exponents of both operand are equal
#29,v,g,n,n,n,PM_DFU_FIN,DFU instruction finish
##E0080
The Decimal Floating Point Unit finished an operation.
#30,v,g,n,n,n,PM_DFU_SUBNORM,DFU result is a subnormal
##E0086
The result of a Decimal Floating Point operation was subnormal.
#31,v,g,n,n,n,PM_DPU_HELD_COMPLETION,DISP unit held due to completion holding dispatch 
##210AC
Cycles that Instruction Dispatch was held because of the completion unit. More than one hold condition can exist at the same time
#32,v,g,n,n,n,PM_DPU_HELD_CR_LOGICAL,DISP unit held due to CR, LR or CTR updated by CR logical, MTCRF, MTLR or MTCTR
##3008E
Cycles that Instruction Dispatch was held because the CR, LR, or CTR SPRs were being updated by a CR logical, MTCRF, MTLR or MTCTR instruction. More than one hold condition can exist at the same time
#33,v,g,n,n,n,PM_DPU_HELD_CW,DISP unit held due to cache writes 
##20084
Cycles that Load Store Unit is performing a cache write. The LSU blocks dispatch to avoid contention for the cache during a write. More than one hold condition can exist at the same time
#34,v,g,n,n,n,PM_DPU_HELD_FPQ,DISP unit held due to FPU issue queue full
##20086
Cycles that Instruction Dispatch was held because the Floating Point Issue Queue was full. More than one hold condition can exist at the same time
#35,v,g,n,n,n,PM_DPU_HELD_FPU_CR,DISP unit held due to FPU updating CR
##210A0
Cycles that Instruction Dispatch was held because a Floating Point operation was updating a condition register. Younger instruction are blocked to avoid Write after Write conflicts. More than one hold condition can exist at the same time
#36,v,g,n,n,n,PM_DPU_HELD_FP_FX_MULT,DISP unit held due to non fixed multiple/divide after fixed multiply/divide
##210A8
Cycles that Instruction Dispatch was held due to fixed point multiply/divides. After dispatching a FXU Multiply/Divide instruction, the dispatcher must block all non FXU/Divide instruction from dispatch (same thread)  More than one hold condition can exist at the same time
#37,v,g,n,n,n,PM_DPU_HELD_FXU_MULTI,DISP unit held due to FXU multicycle
##210A6
Cycles that Instruction Dispatch was held due to multi-cycle fixed operation. More than one hold condition can exist at the same time
#38,v,g,n,n,n,PM_DPU_HELD_FXU_SOPS,DISP unit held due to FXU slow ops (mtmsr, scv, rfscv)
##30088
Cycles that Instruction Dispatch was held due to a slow operation executing on a fixed point unit. Instructions such as mtmsr, scv, rfscv require that dispatch be held until all units are idle. More than one hold condition can exist at the same time
#39,v,g,n,n,n,PM_DPU_HELD_GPR,DISP unit held due to GPR dependencies
##20080
Cycles that Instruction Dispatch was held due to a GPR dependency. The dependent instruction is held until the GPR is written. More than one hold condition can exist at the same time
#40,v,g,n,n,n,PM_DPU_HELD_INT,DISP unit held due to exception
##310A8
Cycles that Instruction Dispatch was held due to an exception. Dispatch is  held until all units are idle. More than one hold condition can exist at the same time
#41,v,g,n,n,n,PM_DPU_HELD_ISYNC,DISP unit held due to ISYNC 
##2008A
Cycles that Instruction Dispatch was held due to an isync instruction. If an previous instruction requires a context serializing instruction (CSI), dispatch will be held until the FPU is empty and a completion flush has been received. More than one hold condition can exist at the same time
#42,v,g,n,n,n,PM_DPU_HELD_ITLB_ISLB,DISP unit held due to SLB or TLB invalidates 
##210A4
Cycles that Instruction Dispatch was held due to a islb or itlb instruction. Dispatch is held for three cycles after an islb or itlb instruction is dispatched. More than one hold condition can exist at the same time
#43,v,g,n,n,n,PM_DPU_HELD_LLA_END,DISP unit held due to load look ahead ended
##30084
Cycles that Instruction Dispatch was held due to load look ahead ending. More than one hold condition can exist at the same time
#44,v,g,n,n,n,PM_DPU_HELD_LSU,DISP unit held due to LSU move or invalidate SLB and SR
##210A2
Cycles that Instruction Dispatch was held due to a move to or invalidate of the Segment Lookaside Buffer. Dispatch is held until all units are idle. More than one hold condition can exist at the same time
#45,v,g,n,n,n,PM_DPU_HELD_LSU_SOPS,DISP unit held due to LSU slow ops (sync, tlbie, stcx)
##30080
Cycles that Instruction Dispatch was held due to a slow operation executing on a Load Store Unit. Instructions such as sync, tlbie, stcx require that dispatch be held until all units are idle. More than one hold condition can exist at the same time
#46,v,g,n,n,n,PM_DPU_HELD_MULT_GPR,DISP unit held due to multiple/divide multiply/divide GPR dependencies
##210AA
Cycles that Instruction Dispatch was held due to a GPR dependency caused by a fixed point multiple or divide that is dependent on the results of another fixed point multiple or divide. More than one hold condition can exist at the same time
#47,v,g,n,n,n,PM_DPU_HELD_RESTART,DISP unit held after restart coming
##30086
Cycles that Instruction Dispatch was held waiting on a restart signal from the LSU. Dispatch has dispatched all available instructions in load look ahead mode and is waiting for the demand load to be returned. 
#48,v,g,n,n,n,PM_DPU_HELD_RU_WQ,DISP unit held due to RU FXU write queue full
##2008E
Cycles that Instruction Dispatch was held because the recovery unit's fixed point write cycle was full. More than one hold condition can exist at the same time
#49,v,g,n,n,n,PM_DPU_HELD_SMT,DISP unit held due to SMT conflicts 
##20082
Cycles that Instruction Dispatch was held due to conflicts with the other thread. There are not enough execution units available to dispatch. More than one hold condition can exist at the same time
#50,v,g,n,n,n,PM_DPU_HELD_SPR,DISP unit held due to MTSPR/MFSPR
##3008C
Cycles that Instruction Dispatch was held because of a move to or move from SPR instruction. More than one hold condition can exist at the same time
#51,v,g,n,n,n,PM_DPU_HELD_STCX_CR,DISP unit held due to STCX updating CR 
##2008C
Cycles that Instruction Dispatch was held due to a stcx instruction updating the CR. Instructions dependant on the CR are held until the stcx finishes. This hold condition is a subset of LSO Slow Operations. More than one hold condition can exist at the same time
#52,v,g,n,n,n,PM_DPU_HELD_THERMAL,DISP unit held due to thermal condition
##0002A
Cycles that Instruction Dispatch was held due to a thermal condition. More than one hold condition can exist at the same time
#53,v,g,n,n,n,PM_DPU_HELD_THRD_PRIO,DISP unit held due to lower priority thread
##3008A
Cycles that Instruction Dispatch was held due to a lower priority thread. More than one hold condition can exist at the same time
#54,v,g,n,n,n,PM_DPU_HELD_XER,DISP unit held due to XER dependency
##20088
Cycles that Instruction Dispatch was held due to a XER dependency. More than one hold condition can exist at the same time
#55,v,g,n,n,n,PM_DPU_HELD_XTHRD,DISP unit held due to cross thread resource conflicts
##30082
Cycles that Instruction Dispatch was held due to a resource conflict with the other thread. This could be caused by a mtspr, mfspr, or a multi-cycle fixed point operation. More than one hold condition can exist at the same time
#56,v,g,n,n,n,PM_DSLB_MISS,Data SLB misses
##830E8
A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve
#57,u,g,n,n,n,PM_EE_OFF_EXT_INT,Cycles MSR(EE) bit off and external interrupt pending
##230EE
Cycles when an interrupt due to an external exception is pending but external exceptions were masked.
#58,v,g,n,c,n,PM_FAB_ADDR_COLLISION,local node launch collision with off-node address   
##5018E
A command from the local node hadd an address collision with a command for a system address. The local node competes with system pump addresses from remote nodes for address slots, this event is an indication of how badly local requests are affected by system wide requests
#59,v,g,n,c,n,PM_FAB_CMD_ISSUED,Fabric command issued
##50130
Incremented when a chip issues a command on its SnoopA address bus. Each of the two address busses (SnoopA and SnoopB) is capable of one transaction per fabric cycle (one fabric cycle = 2 cpu cycles in normal 2:1 mode), but each chip can only drive the SnoopA bus, and can only drive one transaction every two fabric cycles (i.e., every four cpu cycles). In MCM-based systems, two chips interleave their accesses to each of the two fabric busses (SnoopA, Snoop
#60,v,g,n,c,n,PM_FAB_DCLAIM,Dclaim operation, locally mastered
##50184
A DCLAIM command was issued. Each chip reports its own counts. The signal is delivered at FBC speed and the count must be scaled accordingly.
#61,v,g,n,c,n,PM_FAB_DMA,DMA operation, locally mastered
##5018C
A DMA operation was issued. Each chip reports its own counts. The signal is delivered at FBC speed and the count must be scaled accordingly.
#62,v,g,n,c,n,PM_FAB_MMIO,MMIO operation, locally mastered
##50186
A MMIO operation was issued. Each chip reports its own counts. The signal is delivered at FBC speed and the count must be scaled accordingly.
#63,v,g,n,c,n,PM_FAB_NODE_PUMP,Node pump operation, locally mastered
##50188
A request from this chip was send out on the XYZ (intra-node) link. Each chip reports its own counts. The signal is delivered at FBC speed and the count must be scaled accordingly.
#64,v,g,n,c,n,PM_FAB_RETRY_NODE_PUMP,Retry of a node pump, locally mastered
##5018A
A snoop operation for a node pump address originated from a master on this chip and the result was a retry.
#65,v,g,n,c,n,PM_FAB_RETRY_SYS_PUMP,Retry of a system pump, locally mastered  
##50182
A snoop operation for a system pump address originated from a master on this chip and the result was a retry.
#66,v,g,n,c,n,PM_FAB_SYS_PUMP,System pump operation, locally mastered
##50180
An request from this chip was send out on the AB (inter-node) link. Each chip reports its own counts. The signal is delivered at FBC speed and the count must be scaled accordingly.
#67,v,g,n,n,n,PM_FLUSH,Flushes
##00010
Flushes occurred including LSU and Branch flushes.
#68,v,g,n,n,n,PM_FLUSH_ASYNC,Flush caused by asynchronous exception
##220CA
A flush was caused by an asyncronous exception. 
#69,v,g,n,n,n,PM_FLUSH_FPU,Flush caused by FPU exception
##230EC
A flush was caused by a floating point exception.
#70,v,g,n,n,n,PM_FLUSH_FXU,Flush caused by FXU exception
##230EA
A flush was caused by a fixed point exception.
#71,v,g,n,n,n,PM_FPU0_1FLOP,FPU0 executed add, mult, sub, cmp or sel instruction
##C0080
The floating point unit has executed an add, mult, sub, compare, fsel, fneg, fabs, fnabs, fres, or frsqrte kind of instruction. These are single FLOP operations.
#72,v,g,n,n,n,PM_FPU0_DENORM,FPU0 received denormalized data
##C10A2
FPU0 has encountered a denormalized operand. 
#73,v,g,n,n,n,PM_FPU0_FCONV,FPU0 executed FCONV instruction
##D10A0
FPU0 has executed a convert kind of instruction. This could be fcfid* or fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.
#74,v,g,n,n,n,PM_FPU0_FEST,FPU0 executed FEST instruction
##D10A6
FPU0 has executed an estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. 
#75,v,g,n,n,n,PM_FPU0_FIN,FPU0 produced a result
##D0080
FPU0 finished, produced a result. This only indicates finish,  not completion. Floating Point Stores are included in this count but not Floating Point Loads.
#76,v,g,n,n,n,PM_FPU0_FLOP,FPU0 executed 1FLOP, FMA, FSQRT or FDIV instruction
##C0086
FPU0 has executed a one flop, multiply-add, square root, or divide kind of instruction.
#77,v,g,n,n,n,PM_FPU0_FMA,FPU0 executed multiply-add instruction
##C0082
FPU0 has executed a multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.
#78,v,g,n,n,n,PM_FPU0_FPSCR,FPU0 executed FPSCR instruction
##D0084
FPU0 has executed FPSCR move related instruction. This could be mtfsfi*, mtfsb0*, mtfsb1*, mffs*, mtfsf*, mcrsf* where XYZ* means XYZ, XYZs, XYZ., XYZs.
#79,v,g,n,n,n,PM_FPU0_FRSP,FPU0 executed FRSP instruction
##D10A2
FPU0 has executed a frsp kind of instruction. This could be frsp* where XYZ* means XYZ, XYZs, XYZ., XYZs.
#80,v,g,n,n,n,PM_FPU0_FSQRT_FDIV,FPU0 executed FSQRT or FDIV instruction
##C0084
FPU0 has executed a square root or divide instruction. This could be fsqrt* or fdiv* where XYZ* means XYZ, XYZs, XYZ., XYZs
#81,v,g,n,n,n,PM_FPU0_FXDIV,FPU0 executed fixed point division
##C10A0
FPU0 has executed a fixed point divide instruction.
#82,v,g,n,n,n,PM_FPU0_FXMULT,FPU0 executed fixed point multiplication
##D0086
FPU0 has executed a fixed point multiply instruction.
#83,v,g,n,n,n,PM_FPU0_SINGLE,FPU0 executed single precision instruction
##C10A6
FPU0 has executed a single precision instruction.
#84,v,g,n,n,n,PM_FPU0_STF,FPU0 executed store instruction
##C10A4
FPU0 has executed a Floating Point Store instruction.
#85,v,g,n,n,n,PM_FPU0_ST_FOLDED,FPU0 folded store
##D10A4
FPU0 executed a store that was dependant on the result of a previous instruction. The result it folded into the store allowing the store to execute earlier.
#86,v,g,n,n,n,PM_FPU1_1FLOP,FPU1 executed add, mult, sub, cmp or sel instruction
##C0088
FPU1 has executed an add, mult, sub, compare, fsel, fneg, fabs, fnabs, fres, or frsqrte kind of instruction. These are single FLOP operations.
#87,v,g,n,n,n,PM_FPU1_DENORM,FPU1 received denormalized data
##C10AA
FPU1 has encountered a denormalized operand.
#88,v,g,n,n,n,PM_FPU1_FCONV,FPU1 executed FCONV instruction
##D10A8
FPU1 has executed a convert kind of instruction. This could be fcfid* or fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.
#89,v,g,n,n,n,PM_FPU1_FEST,FPU1 executed FEST instruction
##D10AE
FPU1 has executed an estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ.
#90,v,g,n,n,n,PM_FPU1_FIN,FPU1 produced a result
##D0088
FPU1 finished, produced a result. This only indicates finish,  not completion. Floating Point Stores are included in this count but not Floating Point Loads. 
#91,v,g,n,n,n,PM_FPU1_FLOP,FPU1 executed 1FLOP, FMA, FSQRT or FDIV instruction
##C008E
FPU1 has executed a one flop, multiply-add, square root, or divide kind of instruction.
#92,v,g,n,n,n,PM_FPU1_FMA,FPU1 executed multiply-add instruction
##C008A
FPU1 has executed a multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.
#93,v,g,n,n,n,PM_FPU1_FPSCR,FPU1 executed FPSCR instruction
##D008C
FPU1 has executed FPSCR move related instruction. This could be mtfsfi*, mtfsb0*, mtfsb1*, mffs*, mtfsf*, mcrsf* where XYZ* means XYZ, XYZs, XYZ., XYZs.
#94,v,g,n,n,n,PM_FPU1_FRSP,FPU1 executed FRSP instruction
##D10AA
FPU1 has executed a frsp kind of instruction. This could be frsp* where XYZ* means XYZ, XYZs, XYZ., XYZs.
#95,v,g,n,n,n,PM_FPU1_FSQRT_FDIV,FPU1 executed FSQRT or FDIV instruction
##C008C
FPU1 has executed a square root or divide instruction. This could be fsqrt* or fdiv* where XYZ* means XYZ, XYZs, XYZ., XYZs
#96,v,g,n,n,n,PM_FPU1_FXDIV,FPU1 executed fixed point division
##C10A8
FPU1 has executed a fixed point divide instruction.
#97,v,g,n,n,n,PM_FPU1_FXMULT,FPU1 executed fixed point multiplication
##D008E
FPU1 has executed a fixed point multiply instruction.
#98,v,g,n,n,n,PM_FPU1_SINGLE,FPU1 executed single precision instruction
##C10AE
FPU1 has executed a single precision instruction.
#99,v,g,n,n,n,PM_FPU1_STF,FPU1 executed store instruction
##C10AC
FPU1 has executed a Floating Point Store instruction.
#100,v,g,n,n,n,PM_FPU1_ST_FOLDED,FPU1 folded store
##D10AC
FPU1 executed a store that was dependant on the result of a previous instruction. The result it folded into the store allowing the store to execute earlier.
#101,v,g,n,n,n,PM_FPU_1FLOP,FPU executed one flop instruction 
##C0030
The floating point unit has executed an add, mult, sub, compare, fsel, fneg, fabs, fnabs, fres, or frsqrte kind of instruction. These are single FLOP operations.
#102,v,g,n,n,n,PM_FPU_FCONV,FPU executed FCONV instruction
##D1034
The floating point unit has executed a convert kind of instruction. This could be fcfid* or fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1.
#103,v,g,n,n,n,PM_FPU_FIN,FPU produced a result
##D0030
FPU finished, produced a result This only indicates finish, not completion. Combined Unit 0 + Unit 1
#104,v,g,n,n,n,PM_FPU_FLOP,FPU executed 1FLOP, FMA, FSQRT or FDIV instruction
##C0032
The floating point unit has executed a one flop, multiply-add, square root, or divide kind of instruction. Combined Unit 0 + Unit 1.
#105,v,g,n,n,n,PM_FPU_FXDIV,FPU executed fixed point division
##C1034
The floating point unit has executed a fixed point divide instruction. Combined Unit 0 + 1.
#106,v,g,n,n,n,PM_FPU_FXMULT,FPU executed fixed point multiplication
##D0032
The floating point unit has executed a fixed point multiply instruction. Combined Unit 0 + 1.
#107,v,g,n,n,n,PM_FPU_ISSUE_0,FPU issue 0 per cycle
##320C6
Cycles when no instructions were issued to the floating point units.
#108,v,g,n,n,n,PM_FPU_ISSUE_1,FPU issue 1 per cycle
##320C8
Cycles when one instruction was issued to the floating point units.
#109,v,g,n,n,n,PM_FPU_ISSUE_2,FPU issue 2 per cycle
##320CA
Cycles when two instruction were issued to the floating point units.
#110,v,g,n,n,n,PM_FPU_ISSUE_DIV_SQRT_OVERLAP,FPU divide/sqrt overlapped with other divide/sqrt
##320CC
The floating point unit was issued a divide or square root instruction that overlapped execution with another divide or square root instruction. These instructions are not pipelined but they can execute in parallel on separate units.
#111,v,g,n,n,n,PM_FPU_ISSUE_OOO,FPU issue out-of-order
##320C0
Instructions were issued to the floating point unit of of order with respect to program order. The floating point unit has limited ability to execute instructions out of order.
#112,v,g,n,n,n,PM_FPU_ISSUE_STALL_FPR,FPU issue stalled due to FPR dependencies
##330E2
Instruction issue to the floating point unit was stalled waiting on the results of a previous instruction.
#113,v,g,n,n,n,PM_FPU_ISSUE_STALL_ST,FPU issue stalled due to store
##320CE
Instruction issue to the floating point unit was stalled due to store. Only one store per cycle can be issued to the floating point unit.
#114,v,g,n,n,n,PM_FPU_ISSUE_STALL_THRD,FPU issue stalled due to thread resource conflict
##330E0
Instruction issue to the floating point unit was stalled because a critical resource was in use by the other thread.
#115,v,g,n,n,n,PM_FPU_ISSUE_STEERING,FPU issue steering
##320C4
An instruction was steered to a specific execution unit at issue time. Some instructions are limited to execution on a specific unit. The issue logic will attempt to steer dependent floating-point instructions to the unit that is producing the result it is dependent upon.
#116,v,g,n,n,n,PM_FPU_ISSUE_ST_FOLDED,FPU issue a folded store
##320C2
A store was issued to the floating point unit that was dependant on the result of a previous instruction. The result it folded into the store allowing the store to execute earlier.
#117,u,g,n,n,n,PM_FXU_IDLE,FXU idle
##00050
FXU0 and FXU1 are both idle
#118,v,g,n,n,n,PM_FXU_PIPELINED_MULT_DIV,Fix point multiply/divide pipelined
##210AE
A fixed point multiple or divide was dispatched while another one was in progress. A sequence of fixed point multiplies or divides can be pipelined, one every other cycle, but any other instruction will stall until the multiply or divide  instructions are finished.
#119,v,g,n,s,n,PM_GCT_EMPTY_CYC,Cycles GCT empty
##000F8
Cycles when the Global Completion Table was completely empty. No thread had an entry allocated.
#120,v,g,n,n,n,PM_GCT_FULL_CYC,Cycles GCT full
##40086
The Global Completion Table is completely full.
#121,v,g,n,n,n,PM_GCT_NOSLOT_CYC,Cycles no GCT slot allocated
##00008
Cycles this thread does not have any slots allocated in the GCT.
#122,v,g,n,c,n,PM_GXI_ADDR_CYC_BUSY,Inbound GX address utilization (# of cycle address is in valid)
##50388
Number of bus cycles the inbound GX bus is receiving an address. The signal is delivered at GX Controller speed and the count must be scaled accordingly
#123,v,g,n,c,n,PM_GXI_CYC_BUSY,Inbound GX bus utilizations (# of cycles in use)
##50386
Number of bus cycles the inbound GX bus is in use. The signal is delivered at GX Controller speed and the count must be scaled accordingly
#124,v,g,n,c,n,PM_GXI_DATA_CYC_BUSY,Inbound GX Data utilization (# of cycle data in is valid)
##5038A
Number of bus cycles the inbound GX bus is receiving data. The signal is delivered at GX Controller speed and the count must be scaled accordingly
#125,v,g,n,c,n,PM_GXO_ADDR_CYC_BUSY,Outbound GX address utilization (# of cycles address out is valid)
##50382
Number of bus cycles the outbound GX bus is receiving an address. The signal is delivered at GX Controller speed and the count must be scaled accordingly
#126,v,g,n,c,n,PM_GXO_CYC_BUSY,Outbound GX bus utilizations (# of cycles in use)
##50380
Number of bus cycles the outbound GX bus is in use. The signal is delivered at GX Controller speed and the count must be scaled accordingly
#127,v,g,n,c,n,PM_GXO_DATA_CYC_BUSY,Outbound GX Data utilization (# of cycles data out is valid)
##50384
Number of bus cycles the outbound GX bus is receiving data. The signal is delivered at GX Controller speed and the count must be scaled accordingly
#128,v,g,n,c,n,PM_GX_DMA_READ,DMA Read Request
##5038C
The GX Bus Controller processed a DMA read request. The signal is delivered at GX Controller speed and the count must be scaled accordingly
#129,v,g,n,c,n,PM_GX_DMA_WRITE,All DMA Write Requests (including dma wrt lgcy)
##5038E
The GX Bus Controller processed a DMA write request. The signal is delivered at GX Controller speed and the count must be scaled accordingly
#130,v,g,n,n,n,PM_IBUF_FULL_CYC,Cycles instruction buffer full
##40084
Cycles with the Instruction Buffer was full. The Instruction Buffer is a circular queue of 64 instructions per thread, organized as 16 groups of 4 instructions.
#131,v,g,n,n,n,PM_IC_DEMAND_L2_BHT_REDIRECT,L2 I cache demand request due to BHT redirect
##420CA
A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (CR mispredict).
#132,v,g,n,n,n,PM_IC_DEMAND_L2_BR_REDIRECT,L2 I cache demand request due to branch redirect
##420CC
A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (either ALL mispredicted or Target).
#133,v,g,n,n,n,PM_IC_PREF_REQ,Instruction prefetch requests
##4008C
An instruction prefetch request has been made.
#134,v,g,n,n,n,PM_IC_PREF_WRITE,Instruction prefetch written into I cache
##430E0
Number of Instruction Cache entries written because of prefetch. Prefetch entries are marked least recently used and are candidates for eviction if they are not needed to satify a demand fetch.
#135,v,g,n,n,n,PM_IC_RELOAD_SHR,I cache line reloading to be shared by threads
##4008E
An Instruction Cache request was made by this thread and the cache line was already in the cache for the other thread. The line is marked valid for both threads.
#136,v,g,n,n,n,PM_IC_REQ,I cache demand of prefetch request
##4008A
An instruction fetch request was made. The request may have been a prefetch request or a demand request.
#137,v,g,n,n,n,PM_IERAT_MISS,IERAT miss count
##420CE
A translation request missed the Instruction Effective to Real Address Translation (ERAT) table
#138,v,g,n,n,n,PM_IFU_FIN,IFU finished an instruction
##430E4
The Instruction Fetch Unit finished an instruction
#139,v,g,n,n,n,PM_INST_CMPL,Instructions completed
##00002
Number of PPC instructions completed. 
#140,v,g,n,n,n,PM_INST_DISP_LLA,Instruction dispatched under load look ahead
##310A2
Instructions dispatched while Load Look ahead is active.
#141,v,g,n,n,n,PM_INST_FETCH_CYC,Cycles at least 1 instruction fetched
##420C8
Cycles when at least one instruction was sent from the fetch unit to the decode unit.
#142,v,g,n,n,n,PM_INST_FROM_L1,Instruction fetched from L1
##40082
An instruction fetch group was fetched from L1. Fetch Groups can contain up to 8 instructions
#143,v,g,n,n,n,PM_INST_FROM_L2,Instructions fetched from L2
##42040
An instruction fetch group was fetched from L2. Fetch Groups can contain up to 8 instructions
#144,v,g,n,n,n,PM_INST_FROM_L35_MOD,Instruction fetched from L3.5 modified
##42046
An instruction fetch group was fetched with modified (M) data from the L3 of a chip on the same module as this processor is located. Fetch groups can contain up to 8 instructions
#145,v,g,n,n,n,PM_INST_FROM_MEM_DP,Instruction fetched from double pump memory
##42042
Instruction fetched from double pump memory
#146,v,g,n,n,n,PM_INST_FROM_RL2L3_MOD,Instruction fetched from remote L2 or L3 modified
##42044
An instruction fetch group was fetched with modified  (M) data from an L2 or L3 on a remote module. Fetch groups can contain up to 8 instructions
#147,v,g,n,n,n,PM_INST_IMC_MATCH_CMPL,IMC matched instructions completed
##000F0
Number of instructions resulting from the marked instructions expansion that completed.
#148,v,g,n,n,n,PM_INST_PTEG_1ST_HALF,Instruction table walk matched in first half primary PTEG
##910A8
A translation request for a instruction address was satisfied using the primary page table hash. The matching Page Table Entry is one of the first four PTE entries of the primary PTEG
#149,v,g,n,n,n,PM_INST_PTEG_2ND_HALF,Instruction table walk matched in second half primary PTEG
##910AA
A translation request for a instruction address was satisfied using the primary page table hash. The matching Page Table Entry is one of the second four PTE entries of the primary PTEG
#150,v,g,n,n,n,PM_INST_PTEG_SECONDARY,Instruction table walk matched in secondary PTEG
##910AC
A translation request for a instruction address was satisfied using the secondary page table hash. 
#151,v,g,n,n,n,PM_INST_TABLEWALK_CYC,Cycles doing instruction tablewalks
##920CA
Cycles an Instruction Tablewalk is active. 
#152,u,g,n,n,n,PM_ISLB_MISS,Instruction SLB misses
##830E0
A SLB miss for an instruction fetch as occurred
#153,v,g,n,n,n,PM_ITLB_REF,Instruction TLB reference
##920C2
Number of Instruction Translation requests from the ERAT. 
#154,v,g,n,n,n,PM_L1_ICACHE_MISS,L1 I cache miss count
##00056,00056
An instruction fetch request missed the L1 cache.
#155,v,g,n,n,n,PM_L1_PREF,L1 cache data prefetches
##810A4
A request to prefetch data into the L1 was made
#156,v,g,n,n,n,PM_L1_WRITE_CYC,Cycles writing to instruction L1
##430E2
Cycles that a cache line was written to the instruction cache.
#157,v,g,n,c,n,PM_L2SA_CASTOUT_MOD,L2 slice A castouts - Modified
##50680
An L2 line in the Modified state was castout. Reported per slice.
#158,v,g,n,c,n,PM_L2SA_CASTOUT_SHR,L2 slice A castouts - Shared
##50682
An L2 line in the Shared state was castout. Reported per slice.
#159,v,g,n,c,n,PM_L2SA_DC_INV,L2 slice A D cache invalidate
##50686
The L2 invalidated a line in processor's data cache. This is caused by the L2 line being cast out or invalidated. Reported per slice.
#160,v,g,n,c,n,PM_L2SA_IC_INV,L2 slice A I cache invalidate
##50684
The L2 invalidated a line in processor's instruction cache. This is caused by the L2 line being cast out or invalidated. Reported per slice.
#161,v,g,n,c,n,PM_L2SA_LD_HIT,L2 slice A load hits
##50782
A load request (data or instruction) hit in the L2 directory. Includes speculative, prefetched, and demand requests. This event includes all requests to this L2 from all sources. Reported per slice.
#162,v,g,n,n,n,PM_L2SA_LD_MISS_DATA,L2 slice A data load misses
##50482
A data load request from this thread hit in the L2 directory. Includes speculative, prefetched, and demand requests. Reported per slice.
#163,v,g,n,n,n,PM_L2SA_LD_MISS_INST,L2 slice A instruction load misses
##50582
An instruction load request from this thread hit in the L2 directory. Includes speculative, prefetched, and demand requests. Reported per slice.
#164,v,g,n,c,n,PM_L2SA_LD_REQ,L2 slice A load requests 
##50780
A load request (data or instruction) was received by the L2 directory. Includes speculative, prefetched, and demand requests. This event includes all requests to this L2 from all sources. Reported per slice.
#165,v,g,n,n,n,PM_L2SA_LD_REQ_DATA,L2 slice A data load requests
##50480
A data load request from this thread was received by the L2 directory. Includes speculative, prefetched, and demand requests. Reported per slice.
#166,v,g,n,n,n,PM_L2SA_LD_REQ_INST,L2 slice A instruction load requests
##50580
An instruction load request from this thread was received by the L2 directory. Includes speculative, prefetched, and demand requests. Reported per slice.
#167,v,g,n,n,n,PM_L2SA_MISS,L2 slice A misses
##50584
Total L2 misses (loads and stores) from this thread. Includes speculative, prefetched, and demand requests. Reported per slice.
#168,v,g,n,c,n,PM_L2SA_ST_HIT,L2 slice A store hits
##50786
A store request hit in the L2 directory. This event includes all requests to this L2 from all sources. Reported per slice.
#169,v,g,n,n,n,PM_L2SA_ST_MISS,L2 slice A store misses
##50486
A store request from this thread missed in the L2 directory. Reported per slice.
#170,v,g,n,n,n,PM_L2SA_ST_REQ,L2 slice A store requests
##50484,50784
A store request  was received by the L2 directory. This event includes all requests to this L2 from all sources. Stores are counted after gathering in the L2 store queues. Reported per slice.
#171,v,g,n,c,n,PM_L2SB_CASTOUT_MOD,L2 slice B castouts - Modified
##50688
An L2 line in the Modified state was castout. Reported per slice.
#172,v,g,n,c,n,PM_L2SB_CASTOUT_SHR,L2 slice B castouts - Shared
##5068A
An L2 line in the Shared state was castout. Reported per slice.
#173,v,g,n,c,n,PM_L2SB_DC_INV,L2 slice B D cache invalidate
##5068E
The L2 invalidated a line in processor's data cache. This is caused by the L2 line being cast out or invalidated. Reported per slice.
#174,v,g,n,c,n,PM_L2SB_IC_INV,L2 slice B I cache invalidate
##5068C
The L2 invalidated a line in processor's instruction cache. This is caused by the L2 line being cast out or invalidated. Reported per slice.
#175,v,g,n,c,n,PM_L2SB_LD_HIT,L2 slice B load hits
##5078A
A load request (data or instruction) hit in the L2 directory. Includes speculative, prefetched, and demand requests. This event includes all requests to this L2 from all sources. Reported per slice.
#176,v,g,n,n,n,PM_L2SB_LD_MISS_DATA,L2 slice B data load misses
##5048A
A data load request from this thread hit in the L2 directory. Includes speculative, prefetched, and demand requests. Reported per slice.
#177,v,g,n,n,n,PM_L2SB_LD_MISS_INST,L2 slice B instruction load misses
##5058A
An instruction load request from this thread hit in the L2 directory. Includes speculative, prefetched, and demand requests. Reported per slice.
#178,v,g,n,c,n,PM_L2SB_LD_REQ,L2 slice B load requests 
##50788
A load request (data or instruction) was received by the L2 directory. Includes speculative, prefetched, and demand requests. This event includes all requests to this L2 from all sources. Reported per slice.
#179,v,g,n,n,n,PM_L2SB_LD_REQ_DATA,L2 slice B data load requests
##50488
A data load request from this thread was received by the L2 directory. Includes speculative, prefetched, and demand requests. Reported per slice.
#180,v,g,n,n,n,PM_L2SB_LD_REQ_INST,L2 slice B instruction load requests
##50588
An instruction load request from this thread was received by the L2 directory. Includes speculative, prefetched, and demand requests. Reported per slice.
#181,v,g,n,n,n,PM_L2SB_MISS,L2 slice B misses
##5058C
Total L2 misses (loads and stores) from this thread. Includes speculative, prefetched, and demand requests. Reported per slice.
#182,v,g,n,c,n,PM_L2SB_ST_HIT,L2 slice B store hits
##5078E
A store request hit in the L2 directory. This event includes all requests to this L2 from all sources. Reported per slice.
#183,v,g,n,n,n,PM_L2SB_ST_MISS,L2 slice B store misses
##5048E
A store request from this thread missed in the L2 directory. Reported per slice.
#184,v,g,n,n,n,PM_L2SB_ST_REQ,L2 slice B store requests
##5048C,5078C
A store request  was received by the L2 directory. This event includes all requests to this L2 from all sources. Stores are counted after gathering in the L2 store queues. Reported per slice.
#185,v,g,n,c,n,PM_L2_CASTOUT_MOD,L2 castouts - Modified (M, Mu, Me)
##50630
An L2 line in the Modified state was castout. Total for all slices.
#186,v,g,n,n,n,PM_L2_LD_REQ_DATA,L2 data load requests
##50430
A data load request from this thread was received by the L2 directory. Includes speculative, prefetched, and demand requests. Total for all slices.
#187,v,g,n,n,n,PM_L2_LD_REQ_INST,L2 instruction load requests
##50530
An instruction load request from this thread was received by the L2 directory. Includes speculative, prefetched, and demand requests. Total for all slices.
#188,v,g,n,n,n,PM_L2_PREF_LD,L2 cache prefetches
##810A6
A request to prefetch load data into L2 was made
#189,v,g,n,n,n,PM_L2_PREF_ST,L2 cache prefetches
##810A8
A request to prefetch the target of a store into L2 was made
#190,v,g,n,n,n,PM_L2_ST_MISS_DATA,L2 data store misses
##50432
A store request from this thread missed in the L2 directory. Total for all slices.
#191,v,g,n,c,n,PM_L3SA_HIT,L3 slice A hits
##50082
Number of attempts made by this chip cores that resulted in an L3 hit. Reported per L3 slice
#192,v,g,n,c,n,PM_L3SA_MISS,L3 slice A misses
##50084
Number of attempts made by this chip cores that resulted in an L3 miss. Reported per L3 slice
#193,v,g,n,c,n,PM_L3SA_REF,L3 slice A references
##50030,50080
Number of attempts made by this chip cores to find data in the L3. Reported per L3 slice 
#194,v,g,n,c,n,PM_L3SB_HIT,L3 slice B hits
##5008A
Number of attempts made by this chip cores that resulted in an L3 hit. Reported per L3 slice
#195,v,g,n,n,n,PM_L3SB_MISS,L3 slice B misses
##5008C
Number of attempts made by this chip cores that resulted in an L3 miss. Reported per L3 slice
#196,v,g,n,c,n,PM_L3SB_REF,L3 slice B references
##50088
Number of attempts made by this chip cores to find data in the L3. Reported per L3 slice 
#197,v,g,n,n,n,PM_LARX,Larx executed
##830EA
A larx (lwarx or ldarx) was sent to the nest
#198,v,g,n,n,n,PM_LARX_L1HIT,larx hits in L1
##830E2
A larxa was sent to the nest
#199,v,g,n,n,n,PM_LD_MISS_L1,L1 D cache load misses
##0000D,80080
Load references that miss the Level 1 Data cache. Combined unit 0 + 1.
#200,v,g,n,n,n,PM_LD_MISS_L1_CYC,L1 data load miss cycles
##0000C
Cycles waiting on a demand miss to the level 1 Data cache. On POWER6 there can only be one demand miss outstanding at a time. Dividing cycles waiting on a demand miss by the number of demand misses gives the average latency to satisfy a demand miss
#201,v,g,n,n,n,PM_LD_REF_L1,L1 D cache load references
##80082,8008A
Load references to the Level 1 Data Cache. Combined unit 0 + 1.
#202,v,g,n,n,n,PM_LD_REF_L1_BOTH,Both units L1 D cache load reference
##80036
Both Load Store Units were servicing a load reference at the same time.
#203,v,g,n,c,n,PM_LD_REQ_L2,L2 load requests 
##50730
L2 load requests 
#204,v,g,n,n,n,PM_LSU0_DERAT_MISS,LSU0 DERAT misses
##910A6
A data request (load or store) from LSU Unit 0 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.
#205,v,g,n,n,n,PM_LSU0_LDF,LSU0 executed Floating Point load instruction
##80084
A floating point load was executed from LSU unit 0
#206,v,g,n,n,n,PM_LSU0_NCLD,LSU0 non-cacheable loads
##820CA
A non-cacheable load was executed by unit 0.
#207,v,g,n,n,n,PM_LSU0_NCST,LSU0 non-cachable stores
##820CC
A non-cacheable store was executed by unit 0.
#208,v,g,n,n,n,PM_LSU0_REJECT,LSU0 reject
##A10A6
Load Store Unit 0 rejected an instruction.
#209,v,g,n,n,n,PM_LSU0_REJECT_DERAT_MPRED,LSU0 reject due to mispredicted DERAT
##A0082
Load Store Unit 0 rejected an instruction because the Effective Address was improperly predicted. This is a fast reject and will be immediately redispatched. On the redispatch, the scratch register is used to provide the correct effective address for the D-ERAT access to resolve the incorrect guess.
#210,v,g,n,n,n,PM_LSU0_REJECT_EXTERN,LSU0 external reject request 
##A10A4
Load Store Unit 0 rejected an instruction due to a request from the decode unit or the fixed point unit.
#211,v,g,n,n,n,PM_LSU0_REJECT_L2MISS,LSU0 L2 miss reject
##90084
Load Store Unit 0 rejected a load due to a correctable error in the L2. This is a fast reject and will be immediately redispatched. 
#212,v,g,n,n,n,PM_LSU0_REJECT_L2_CORR,LSU0 reject due to L2 correctable error
##A10A0
Load Store Unit 0 rejected an instruction. The reject was a collision type reject. The IDU immediately redispatches the rejected instruction. The result is eleven (11) cycles, dispatch-to-dispatch, in the best case. 
#213,v,g,n,n,n,PM_LSU0_REJECT_LHS,LSU0 load hit store reject
##90086
Load Store Unit 0 rejected a load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully.
#214,v,g,n,n,n,PM_LSU0_REJECT_NO_SCRATCH,LSU0 reject due to scratch register not available
##A10A2
Load Store Unit 0 rejected an instruction because the internal scratch register was not available. This is a fast reject and will be immediately redispatched. 
#215,v,g,n,n,n,PM_LSU0_REJECT_PARTIAL_SECTOR,LSU0 reject due to partial sector valid
##A0086
Load Store Unit 0 rejected an instruction that had a L1 Data Cache line hit but the critical sector was not valid. Since the cache line is partially validated, a reload of that cache line is in progress. This is a fast reject and will be immediately redispatched. 
#216,v,g,n,n,n,PM_LSU0_REJECT_SET_MPRED,LSU0 reject due to mispredicted set
##A0084
Load Store Unit 0 rejected an instruction because the cache set was improperly predicted. This is a fast reject and will be immediately redispatched. 
#217,v,g,n,n,n,PM_LSU0_REJECT_STQ_FULL,LSU0 reject due to store queue full
##A0080
Load Store Unit 0 rejected a store because the store request queue was full. This is a fast reject and will be immediately redispatched.
#218,v,g,n,n,n,PM_LSU0_REJECT_ULD,LSU0 unaligned load reject
##90080
Load Store Unit 0 rejected a load instruction that spans a cache line boundary (128B). The LSU will pass the incremented address information to the FXU via the scratch register so that the subsequent address generation will access the next line.
#219,v,g,n,n,n,PM_LSU0_REJECT_UST,LSU0 unaligned store reject
##90082
Load Store Unit 0 rejected a store instruction that spans a cache line boundary (128B). The LSU will pass the incremented address information to the FXU via the scratch register so that the subsequent address generation will access the next line.
#220,v,g,n,n,n,PM_LSU1_DERAT_MISS,LSU1 DERAT misses
##910AE
A data request (load or store) from LSU Unit 1 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.
#221,v,g,n,n,n,PM_LSU1_LDF,LSU1 executed Floating Point load instruction
##8008C
A floating point load was executed from LSU unit 1
#222,v,g,n,n,n,PM_LSU1_REJECT,LSU1 reject
##A10AE
Load Store Unit 1 rejected an instruction.
#223,v,g,n,n,n,PM_LSU1_REJECT_DERAT_MPRED,LSU1 reject due to mispredicted DERAT
##A008A
Load Store Unit 1 rejected an instruction because the Effective Address was improperly predicted. This is a fast reject and will be immediately redispatched. On the redispatch, the scratch register is used to provide the correct effective address for the D-ERAT access to resolve the incorrect guess.
#224,v,g,n,n,n,PM_LSU1_REJECT_EXTERN,LSU1 external reject request 
##A10AC
Load Store Unit 1 rejected an instruction due to a request from the decode unit or the fixed point unit.
#225,v,g,n,n,n,PM_LSU1_REJECT_L2_CORR,LSU1 reject due to L2 correctable error
##A10A8
Load Store Unit 1 rejected an instruction. The reject was a collision type reject. The IDU immediately redispatches the rejected instruction. The result is eleven (11) cycles, dispatch-to-dispatch, in the best case. 
#226,v,g,n,n,n,PM_LSU1_REJECT_LHS,LSU1 load hit store reject
##9008E
Load Store Unit 1 rejected a load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully.
#227,v,g,n,n,n,PM_LSU1_REJECT_NO_SCRATCH,LSU1 reject due to scratch register not available
##A10AA
Load Store Unit 1 rejected an instruction because the internal scratch register was not available. This is a fast reject and will be immediately redispatched. 
#228,v,g,n,n,n,PM_LSU1_REJECT_PARTIAL_SECTOR,LSU1 reject due to partial sector valid
##A008E
Load Store Unit 1 rejected an instruction that had a L1 Data Cache line hit but the critical sector was not valid. Since the cache line is partially validated, a reload of that cache line is in progress. This is a fast reject and will be immediately redispatched. 
#229,v,g,n,n,n,PM_LSU1_REJECT_SET_MPRED,LSU1 reject due to mispredicted set
##A008C
Load Store Unit 1 rejected an instruction because the cache set was improperly predicted. This is a fast reject and will be immediately redispatched. 
#230,v,g,n,n,n,PM_LSU1_REJECT_STQ_FULL,LSU1 reject due to store queue full
##A0088
Load Store Unit 1 rejected a store because the store request queue was full. This is a fast reject and will be immediately redispatched.
#231,v,g,n,n,n,PM_LSU1_REJECT_ULD,LSU1 unaligned load reject
##90088
Load Store Unit 1 rejected a load instruction that spans a cache line boundary (128B). The LSU will pass the incremented address information to the FXU via the scratch register so that the subsequent address generation will access the next line.
#232,v,g,n,n,n,PM_LSU1_REJECT_UST,LSU1 unaligned store reject
##9008A
Load Store Unit 1 rejected a store instruction that spans a cache line boundary (128B). The LSU will pass the incremented address information to the FXU via the scratch register so that the subsequent address generation will access the next line.
#233,v,g,n,n,n,PM_LSU_BOTH_BUS,Both data return buses busy simultaneously
##810AA
Data was returned on both data buses
#234,v,g,n,n,n,PM_LSU_DERAT_MISS_CYC,DERAT miss latency
##000FC
Cycles waiting on a demand D-ERAT miss. On POWER6 there can only be one demand miss outstanding at a time. Dividing cycles waiting on a demand miss by the number of demand misses gives the average latency to satisfy a demand miss
#235,v,g,n,n,n,PM_LSU_FLUSH_ALIGN,Flush caused by alignement exception
##220CC
A flush was initiated by the Load Store Unit in response to an unaligned operand
#236,v,g,n,n,n,PM_LSU_FLUSH_DSI,Flush caused by DSI
##220CE
A flush was initiated by the Load Store Unit in response to a Data Storage Interrupt
#237,v,g,n,n,n,PM_LSU_LDF_BOTH,Both LSU units executed Floating Point load instruction
##80038
Both Load Store Units were executing a Floating Point Load instruction at the same time.
#238,u,g,n,s,n,PM_LSU_LMQ_FULL_CYC,Cycles LMQ full
##810AC
The Load Miss Queue was full.
#239,v,g,n,n,n,PM_LSU_REJECT_L2_CORR,LSU reject due to L2 correctable error
##A1034
The Load Store Unit rejected a load due to a correctable error in the L2. This is a fast reject and will be immediately redispatched. Combined Unit 0 + 1
#240,v,g,n,n,n,PM_LSU_REJECT_LHS,Load hit store reject
##90032
The Load Store Unit rejected a load load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully. Combined Unit 0 + 1
#241,v,g,n,n,n,PM_LSU_REJECT_PARTIAL_SECTOR,LSU reject due to partial sector valid
##A0032
The Load Store Unit rejected an instruction that had a L1 Data Cache line hit but the critical sector was not valid. Since the cache line is partially validated, a reload of that cache line is in progress. This is a fast reject and will be immediately redispatched. Combined Unit 0 + 1
#242,v,g,n,n,n,PM_LSU_REJECT_STEAL,LSU reject due to steal
##9008C
The Load Store Unit rejected an instruction because a cache or cache directory was being updated. This is a fast reject and will be immediately redispatched. Combined Unit 0 + 1
#243,v,g,n,n,n,PM_LSU_REJECT_STQ_FULL,LSU reject due to store queue full
##A0030
The Load Store Unit rejected a store because the store request queue was full. This is a fast reject and will be immediately redispatched. Combined Unit 0 + 1
#244,v,g,n,n,n,PM_LSU_REJECT_ULD,Unaligned load reject
##90030
The Load Store Unit rejected a load instruction that spans a cache line boundary (128B). The LSU will pass the incremented address information to the FXU via the scratch register so that the subsequent address generation will access the next line. Combined Unit 0 + 1
#245,v,g,n,n,n,PM_LSU_REJECT_UST_BOTH,Unaligned store reject both units
##90036
Both Load Store Units are rejecting an unaligned store at the same time
#246,v,g,n,n,n,PM_LSU_ST_CHAINED,number of chained stores
##820CE
The Load Store Unit chained two store requests together and sent them as one to the L2
#247,v,g,n,n,n,PM_LWSYNC,Isync instruction completed
##810AE
A lightweight sync instruction completed.
#248,v,g,n,c,n,PM_MEM0_DP_CL_WR_GLOB,cacheline write setting dp to global side 0
##50284
A memory cacheline write on memory controller 0 from a remote node. This event is sent from the Memory Controller clock domain and must be scaled accordingly.
#249,v,g,n,c,n,PM_MEM0_DP_CL_WR_LOC,cacheline write setting dp to local side 0
##50286
A memory cacheline write on memory controller 0 from a local node. This event is sent from the Memory Controller clock domain and must be scaled accordingly.
#250,v,g,n,c,n,PM_MEM0_DP_RQ_GLOB_LOC,Memory read queue marking cache line double pump state from global to local side 0
##50280
A memory cacheline read on memory controller 0 changed the double pump state from global to local. This event is sent from the Memory Controller clock domain and must be scaled accordingly.
#251,v,g,n,c,n,PM_MEM0_DP_RQ_LOC_GLOB,Memory read queue marking cache line double pump state from local to global side 0
##50282
A memory cacheline read on memory controller 0 changed the double pump state from local to global. This event is sent from the Memory Controller clock domain and must be scaled accordingly.
#252,v,g,n,c,n,PM_MEM1_DP_CL_WR_GLOB,cacheline write setting dp to global side 1
##5028C
A memory cacheline write on memory controller 1 from a remote node. This event is sent from the Memory Controller clock domain and must be scaled accordingly.
#253,v,g,n,c,n,PM_MEM1_DP_CL_WR_LOC,cacheline write setting dp to local side 1
##5028E
A memory cacheline write on memory controller 1 from a local node. This event is sent from the Memory Controller clock domain and must be scaled accordingly.
#254,v,g,n,c,n,PM_MEM1_DP_RQ_GLOB_LOC,Memory read queue marking cache line double pump state from global to local side 1
##50288
A memory cacheline read on memory controller 1 changed the double pump state from global to local. This event is sent from the Memory Controller clock domain and must be scaled accordingly.
#255,v,g,n,c,n,PM_MEM1_DP_RQ_LOC_GLOB,Memory read queue marking cache line double pump state from local to global side 1
##5028A
A memory cacheline read on memory controller 1 changed the double pump state from local to global. This event is sent from the Memory Controller clock domain and must be scaled accordingly.
#256,v,g,n,c,n,PM_MEM_DP_CL_WR_LOC,cache line write setting double pump state to local
##50232
A memory cacheline write from a local node. This event is sent from the Memory Controller clock domain and must be scaled accordingly. Combined unit 0 + 1.
#257,v,g,n,c,n,PM_MEM_DP_RQ_GLOB_LOC,Memory read queue marking cache line double pump state from global to local
##50230
A memory cacheline read changed the double pump state from global to local. This event is sent from the Memory Controller clock domain and must be scaled accordingly. Combined unit 0 + 1.
#258,v,g,n,n,m,PM_MRK_BR_TAKEN,Marked branch taken
##00052
A marked branch was taken
#259,v,g,n,n,m,PM_MRK_DATA_FROM_L2,Marked data loaded from L2
##03048
The processor's Data Cache was reloaded from the local L2 due to a marked load.
#260,v,g,n,n,m,PM_MRK_DATA_FROM_L2MISS,Marked data loaded missed L2
##03028
DL1 was reloaded from beyond L2 due to a marked demand load.
#261,v,g,n,n,m,PM_MRK_DATA_FROM_L35_MOD,Marked data loaded from L3.5 modified
##0304E
The processor's Data Cache was reloaded with modified (M) data from the L3 of a chip on the same module as this processor is located due to a marked load.
#262,v,g,n,n,m,PM_MRK_DATA_FROM_MEM_DP,Marked data loaded from double pump memory
##0304A
Marked data loaded from double pump memory
#263,v,g,n,n,m,PM_MRK_DATA_FROM_RL2L3_MOD,Marked data loaded from remote L2 or L3 modified
##0304C
The processor's Data Cache was reloaded with modified (M) data from an L2  or L3 on a remote module due to a marked load.
#264,v,g,n,n,m,PM_MRK_DTLB_REF,Marked Data TLB reference
##920C0
Total number of Data TLB references by a marked instruction for all page sizes. Page size is determined at TLB reload time.
#265,v,g,n,n,m,PM_MRK_FPU0_FIN,Marked instruction FPU0 processing finished
##D0082
Floating Point Unit 0 finished a marked instruction.
#266,v,g,n,n,m,PM_MRK_FPU1_FIN,Marked instruction FPU1 processing finished
##D008A
Floating Point Unit 1 finished a marked instruction.
#267,v,g,n,n,m,PM_MRK_INST_DISP,Marked instruction dispatched
##0001A
A marked instruction was dispatched
#268,v,g,n,n,m,PM_MRK_INST_ISSUED,Marked instruction issued
##0001C
A marked instruction was issued to an execution unit.
#269,b,g,n,n,m,PM_MRK_LSU0_REJECT_L2MISS,LSU0 marked L2 miss reject
##930E4
This event never worked and was replaced by marked DERAT guess wrong
#270,v,g,n,n,m,PM_MRK_LSU0_REJECT_LHS,LSU0 marked load hit store reject
##930E6
Load Store Unit 0 rejected a marked load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully.
#271,v,g,n,n,m,PM_MRK_LSU0_REJECT_ULD,LSU0 marked unaligned load reject
##930E0
Load Store Unit 0 rejected a marked load instruction that spans a cache line boundary (128B). The LSU will pass the incremented address information to the FXU via the scratch register so that the subsequent address generation will access the next line.
#272,v,g,n,n,m,PM_MRK_LSU0_REJECT_UST,LSU0 marked unaligned store reject
##930E2
Load Store Unit 0 rejected a marked store instruction that spans a cache line boundary (128B). The LSU will pass the incremented address information to the FXU via the scratch register so that the subsequent address generation will access the next line.
#273,v,g,n,n,m,PM_MRK_LSU1_REJECT_LHS,LSU1 marked load hit store reject
##930EE
Load Store Unit 1 rejected a marked load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully.
#274,v,g,n,n,m,PM_MRK_LSU1_REJECT_ULD,LSU1 marked unaligned load reject
##930E8
Load Store Unit 1 rejected a marked load instruction that spans a cache line boundary (128B). The LSU will pass the incremented address information to the FXU via the scratch register so that the subsequent address generation will access the next line.
#275,v,g,n,n,m,PM_MRK_LSU1_REJECT_UST,LSU1 marked unaligned store reject
##930EA
Load Store Unit 1 rejected a marked store instruction that spans a cache line boundary (128B). The LSU will pass the incremented address information to the FXU via the scratch register so that the subsequent address generation will access the next line.
#276,v,g,n,n,m,PM_MRK_LSU_REJECT_ULD,Marked unaligned load reject
##93034
The Load Store Unit rejected a marked load instruction that spans a cache line boundary (128B). The LSU will pass the incremented address information to the FXU via the scratch register so that the subsequent address generation will access the next line.
#277,v,g,n,n,m,PM_MRK_PTEG_FROM_L2,Marked PTEG loaded from L2
##12040
A Page Table Entry was loaded into the ERAT from the local L2 due to a marked load or store.
#278,v,g,n,n,m,PM_MRK_PTEG_FROM_L35_MOD,Marked PTEG loaded from L3.5 modified
##12046
A Page Table Entry was loaded into the ERAT with modified (M) data from the L3 of a chip on the same module as this processor is located, due to a marked load or store.
#279,v,g,n,n,m,PM_MRK_PTEG_FROM_MEM_DP,Marked PTEG loaded from double pump memory
##12042
A Page Table Entry was loaded into the ERAT with modified (M) data from an L2  or L3 on a remote module due to a marked load or store.
#280,v,g,n,n,m,PM_MRK_PTEG_FROM_RL2L3_MOD,Marked PTEG loaded from remote L2 or L3 modified
##12044
A Page Table Entry was loaded into the ERAT with shared (T or SL) data from an L2 or L3 on a remote module due to a marked load or store.
#281,v,g,n,n,m,PM_MRK_STCX_FAIL,Marked STCX failed
##830E4
A marked stcx (stwcx or stdcx) failed
#282,v,g,n,n,m,PM_MRK_ST_CMPL,Marked store instruction completed
##00006
A sampled store has completed (data home)
#283,v,g,n,n,m,PM_MRK_VMX0_LD_WRBACK,Marked VMX0 load writeback valid
##60086
A marked load returned data on VMX unit 0
#284,v,g,n,n,m,PM_MRK_VMX1_LD_WRBACK,Marked VMX1 load writeback valid
##6008E
A marked load returned data on VMX unit 1
#285,v,g,n,n,m,PM_MRK_VMX_COMPLEX_ISSUED,Marked VMX instruction issued to complex
##7008C
A marked instruction was issued to the VMX Complex pipeline.
#286,v,g,n,n,m,PM_MRK_VMX_FLOAT_ISSUED,Marked VMX instruction issued to float
##70088
A marked instruction was issued to the VMX Float pipeline.
#287,v,g,n,n,m,PM_MRK_VMX_PERMUTE_ISSUED,Marked VMX instruction issued to permute
##7008E
A marked instruction was issued to the VMX Permute pipeline.
#288,v,g,n,n,m,PM_MRK_VMX_SIMPLE_ISSUED,Marked VMX instruction issued to simple
##7008A
A marked instruction was issued to the VMX Simple pipeline.
#289,v,g,n,n,m,PM_MRK_VMX_ST_ISSUED,Marked VMX store issued
##B0088
A marked VMX Store was issued
#290,v,g,n,n,n,PM_NO_ITAG_CYC,Cyles no ITAG available
##40088
Cycles when no ITAGS are available. This condition will block instruction fetch.
#291,v,g,n,n,n,PM_PMC2_SAVED,PMC2 rewind value saved
##00022
PMC2 was counting speculatively. The speculative condition was met and the counter value was committed by copying it to the backup register.
#292,v,g,n,n,n,PM_PMC4_OVERFLOW,PMC4 Overflow
##00014
Overflows from PMC4 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.
#293,v,g,n,n,n,PM_PMC4_REWIND,PMC4 rewind event
##00020
PMC4 was counting speculatively. The speculative condition was not met and the counter was restored to its previous value.
#294,v,g,n,n,n,PM_PMC5_OVERFLOW,PMC5 Overflow
##00024
Overflows from PMC5 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.
#295,v,g,n,n,n,PM_PTEG_FROM_L2,PTEG loaded from L2
##13048
A Page Table Entry was loaded into the ERAT from the local L2 due to a demand load or store.
#296,v,g,n,n,n,PM_PTEG_FROM_L2MISS,PTEG loaded from L2 miss
##13028
A Page Table Entry was loaded into the ERAT but not from the local L2  due to a demand load or store.
#297,v,g,n,n,n,PM_PTEG_FROM_L35_MOD,PTEG loaded from L3.5 modified
##1304E
A Page Table Entry was loaded into the ERAT with modified (M) data from the L3 of a chip on the same module as this processor is located, due to a demand load or store.
#298,v,g,n,n,n,PM_PTEG_FROM_MEM_DP,PTEG loaded from double pump memory
##1304A
PTEG loaded from double pump memory
#299,v,g,n,n,n,PM_PTEG_FROM_RL2L3_MOD,PTEG loaded from remote L2 or L3 modified
##1304C
A Page Table Entry was loaded into the ERAT with modified (M) data from an L2  or L3 on a remote module due to a demand load or store.
#300,v,g,n,n,n,PM_PTEG_RELOAD_VALID,PTEG reload valid
##130E8
A Page Table Entry was loaded into the ERAT. POWER6 does not have a TLB
#301,v,g,n,n,n,PM_PURR,PURR Event
##0000E
The Processor Utilization of Resources Register was incremented. The PURR registers will be incremented roughly in the ratio in which the instructions are dispatched from the two threads. 
#302,v,g,n,n,n,PM_RUN_CYC,Run cycles
##0000A
Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
#303,v,g,n,n,n,PM_SLB_MISS,SLB misses
##83034
Total of all Segment Lookaside Buffer (SLB) misses, Instructions + Data.
#304,v,g,n,n,n,PM_STCX,STCX executed
##830E6
STCX executed
#305,v,g,n,n,n,PM_STCX_CANCEL,stcx cancel by core
##830EC
A conditional store request to the nest was canceled by the core
#306,v,g,n,n,n,PM_STCX_FAIL,STCX failed
##830EE
A stcx (stwcx or stdcx) failed
#307,v,g,n,n,n,PM_ST_FIN,Store instructions finished
##00054
Store requests sent to the nest.
#308,v,g,n,c,n,PM_ST_HIT_L2,L2 D cache store hits
##50732
L2 D cache store hits
#309,v,g,n,n,n,PM_ST_MISS_L1,L1 D cache store misses
##80088
A store missed the dcache. Combined Unit 0 + 1.
#310,v,g,n,n,n,PM_ST_REF_L1,L1 D cache store references
##80032,80086,8008E
Store references to the Data Cache. Combined Unit 0 + 1.
#311,v,g,n,n,n,PM_SUSPENDED,Suspended
##00000
The counter is suspended (does not count).
#312,v,g,n,n,n,PM_SYNC_CYC,Sync duration
##920CC
Cycles a SYNC instruction is pending. Starts counting when the request is sent to the nest until the nest responds.
#313,u,g,n,s,n,PM_TB_BIT_TRANS,Time Base bit transition
##00026
When the selected time base bit (as specified in MMCR0[TBSEL])transitions from 0 to 1 
#314,v,g,n,n,n,PM_THRD_L2MISS,Thread in L2 miss
##310A0
This thread has a L2 miss pending.
#315,v,g,n,s,n,PM_THRD_ONE_RUN_CYC,One of the threads in run cycles
##00016,000FA
At least one thread has set its run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. This event does not respect FCWAIT.
#316,v,g,n,n,n,PM_THRD_PRIO_0_CYC,Cycles thread running at priority level 0
##22040
Cycles this thread was running at priority level 0. Priority level 0 is the lowest and indicates the thread is sleeping.
#317,v,g,n,n,n,PM_THRD_PRIO_7_CYC,Cycles thread running at priority level 7
##22046
Cycles this thread was running at priority level 7.
#318,v,g,n,n,n,PM_THRD_PRIO_DIFF_0_CYC,Cycles no thread priority difference
##23040
Cycles when this thread's priority is equal to the other thread's priority.
#319,v,g,n,c,n,PM_THRD_SEL_T0,Decode selected thread 0
##310A6
Thread selection picked thread 0 for decode.
#320,v,g,n,n,n,PM_TLB_REF,TLB reference
##920C8
Number of Data Translation requests from the ERAT. 
#321,v,g,n,n,n,PM_VMX0_INST_ISSUED,VMX0 instruction issued
##60080
An instruction was issued to VMX unit 0
#322,v,g,n,n,n,PM_VMX0_LD_ISSUED,VMX0 load issued
##60082
A load instruction was issued to VMX unit 0
#323,v,g,n,n,n,PM_VMX0_LD_WRBACK,VMX0 load writeback valid
##60084
A load returned data on VMX unit 0
#324,v,g,n,n,n,PM_VMX0_STALL,VMX0 stall
##B0084
Cycles the VMX unit 0 was stalled
#325,v,g,n,n,n,PM_VMX1_INST_ISSUED,VMX1 instruction issued
##60088
An instruction was issued to VMX unit 1
#326,v,g,n,n,n,PM_VMX1_LD_ISSUED,VMX1 load issued
##6008A
A load instruction was issued to VMX unit 1
#327,v,g,n,n,n,PM_VMX1_LD_WRBACK,VMX1 load writeback valid
##6008C
A load returned data on VMX unit 1
#328,v,g,n,n,n,PM_VMX1_STALL,VMX1 stall
##B008C
Cycles the VMX unit 1 was stalled
#329,v,g,n,n,n,PM_VMX_COMPLEX_ISSUED,VMX instruction issued to complex
##70084
An instruction was issued to the VMX Complex pipeline.
#330,v,g,n,n,n,PM_VMX_FLOAT_ISSUED,VMX instruction issued to float
##70080
An instruction was issued to the VMX Float pipeline.
#331,v,g,n,n,n,PM_VMX_FLOAT_MULTICYCLE,VMX multi-cycle floating point instruction issued
##B0082
A multi-cycle instruction was issued to the VMX Float pipeline.
#332,v,g,n,n,n,PM_VMX_PERMUTE_ISSUED,VMX instruction issued to permute
##70086
An instruction was issued to the VMX Permute pipeline.
#333,v,g,n,n,n,PM_VMX_RESULT_SAT_0_1,VMX valid result with sat bit is set (0->1)
##B008E
An instruction finished on the VMX unit that set the saturation bit. This bit is sticky, once set to 1 it remains set to 1 until it is set to 0 by an mtvscr instruction.
#334,v,g,n,n,n,PM_VMX_RESULT_SAT_1,VMX valid result with sat=1
##B0086
An instruction finished on the VMX unit with the saturation bit on. This bit is sticky, once set to 1 it remains set to 1 until it is set to 0 by an mtvscr instruction.
#335,v,g,n,n,n,PM_VMX_SIMPLE_ISSUED,VMX instruction issued to simple
##70082
An instruction was issued to the VMX Simple pipeline.
#336,v,g,n,n,n,PM_VMX_ST_ISSUED,VMX store issued
##B0080
A VMX Store was issued
#337,v,g,n,n,n,PM_0INST_FETCH_COUNT,Periods with no instructions fetched
##40081
No instructions were fetched this periods (due to IFU hold, redirect, or icache miss)
#338,v,g,n,n,n,PM_IBUF_FULL_COUNT,Periods instruction buffer full
##40085
Number of times the Instruction Buffer was full. The Instruction Buffer is a circular queue of 64 instructions per thread, organized as 16 groups of 4 instructions.
#339,v,g,n,n,n,PM_GCT_FULL_COUNT,Periods GCT full
##40087
The Global Completion Table is completely full.
#340,v,g,n,n,n,PM_NO_ITAG_COUNT,Periods no ITAG available
##40089
Number of periods when no ITAGS are available. This condition will block instruction fetch.
#341,v,g,n,n,n,PM_INST_TABLEWALK_COUNT,Periods doing instruction tablewalks
##920CB
Number of Instruction Tablewalks
#342,v,g,n,n,n,PM_SYNC_COUNT,SYNC instructions completed
##920CD
Number of SYNC instructions executed.
#343,v,g,n,n,n,PM_RUN_COUNT,Run Periods
##0000B
Processor Periods gated by the run latch
#344,v,g,n,s,n,PM_THRD_ONE_RUN_COUNT,Periods one of the threads in run cycles
##000FB
Number of times at least one thread has set its run latch.
#345,v,g,n,c,n,PM_LLA_CYC,Load Look Ahead Active
##0C01E
Load Look Ahead Active. When a demand cache or ERAT miss is encountered, the processor continues dispatching instructions but inhibits the results from writing registers (i.e. the architected state of the machine is not changed), executing subsequent load instructions such that independent cache line miss requests maybe started.
#346,v,g,n,c,n,PM_NOT_LLA_CYC,Load Look Ahead not Active
##0401E
Load Look Ahead not Active
#347,v,g,n,c,n,PM_LLA_COUNT,Transitions into Load Look Ahead mode
##0C01F
Transitions into Load Look Ahead mode
#348,v,g,n,n,n,PM_DPU_HELD_THERMAL_COUNT,Periods DISP unit held due to thermal condition
##0002B
Number of times Instruction Dispatch was held due to a thermal condition.
#349,v,g,n,n,n,PM_GCT_NOSLOT_COUNT,Periods no GCT slot allocated
##00009
Periods this thread does not have any slots allocated in the GCT.
#350,v,g,n,n,n,PM_DERAT_REF_4K,DERAT reference for 4K page
##82070
A data request (load or store) referenced (accessed)  the ERAT for 4K page
#351,v,g,n,n,n,PM_DERAT_MISS_4K,DERAT misses for 4K page
##92070
A data request (load or store) missed the ERAT for 4K page and resulted in an ERAT reload.
#352,v,g,n,n,n,PM_IERAT_MISS_16G,IERAT misses for 16G page
##92076
A translation request for a 16GB page missed the Instruction Effective to Real Address Translation (ERAT) table
#353,v,g,n,n,m,PM_MRK_DERAT_REF_64K,Marked DERAT reference for 64K page
##82044
A marked data request (load or store) referenced (accessed)  the ERAT for 64K page
#354,v,g,n,n,m,PM_MRK_DERAT_MISS_64K,Marked DERAT misses for 64K page
##92044
A marked data request (load or store) missed the ERAT for 64K page and resulted in an ERAT reload.

$$$$$$$$

{ counter 2 }
#0,v,g,n,n,n,PM_0INST_FETCH,No instructions fetched
##40080
No instructions were fetched this cycles (due to IFU hold, redirect, or icache miss)
#1,v,g,n,n,n,PM_BRU_FIN,BRU produced a result
##430E6
The Branch execution unit finished an instruction
#2,v,g,n,n,n,PM_BR_MPRED_CCACHE,Branch misprediction due to count cache prediction
##410AE
A branch instruction target was incorrectly predicted by the ccount cache. This will result in a branch redirect flush if not overfidden by a flush of an older instruction.
#3,v,g,n,n,n,PM_BR_MPRED_COUNT,Branch misprediction due to count prediction
##410AA
A branch instruction count value was incorrectly predicted. This will result in a branch mispredict flush unless a flush is detected from an older instruction.
#4,v,g,n,n,n,PM_BR_MPRED_CR,Branch mispredictions due to CR bit setting
##410A8
A conditional branch instruction was incorrectly predicted as taken or not taken. The branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This will result in a branch redirect flush if not overfidden by a flush of an older instruction.
#5,v,g,n,n,n,PM_BR_MPRED_TA,Branch mispredictions due to target address
##410AC
A branch instruction target was incorrectly predicted. This will result in a branch mispredict flush unless a flush is detected from an older instruction.
#6,v,g,n,n,n,PM_BR_PRED,A conditional branch was predicted
##410A0
A branch prediction was made. This could have been a target prediction, a condition prediction, or both
#7,v,g,n,n,n,PM_BR_PRED_CCACHE,Branch count cache prediction
##410A4
The count value of a Branch and Count instruction was predicted
#8,v,g,n,n,n,PM_BR_PRED_CR,A conditional branch was predicted, CR prediction
##410A2
A conditional branch instruction was predicted as taken or not taken.
#9,v,g,n,n,n,PM_BR_PRED_LSTACK,A conditional branch was predicted, link stack
##410A6
The target address of a Branch to Link instruction was predicted by the link stack.
#10,v,g,n,n,n,PM_BR_TAKEN,Branches taken
##00052
A branch instruction was taken. This could have been a conditional branch or an unconditional branch
#11,v,g,n,c,n,PM_CYC,Processor cycles
##0001E
Processor cycles
#12,v,g,n,n,n,PM_DATA_FROM_DL2L3_SHR_CYC,Load latency from distant L2 or L3 shared
##0002A
Cycles waiting for a Data Cache reload of shared (T or SL) data from a distant L2 or L3
#13,v,g,n,n,n,PM_DATA_FROM_DMEM,Data loaded from distant memory
##0005E
The processor's Data Cache was reloaded with data from memory attached to a distant module due to a demand load
#14,v,g,n,n,n,PM_DATA_FROM_DMEM_CYC,Load latency from distant memory
##0002E
Cycles waiting for a Data Cache reload  of data from memory attached to a distant module
#15,v,g,n,n,n,PM_DATA_FROM_L21,Data loaded from private L2 other core
##00058
The processor's Data Cache was reloaded from the private L2 of the other core on this chip
#16,v,g,n,n,n,PM_DATA_FROM_L25_SHR_CYC,Load latency from L2.5 shared
##00024
Cycles waiting for a Data Cache reload of shared (T or SL) data from the L2 of a chip on the same module as this processor is located
#17,v,g,n,n,n,PM_DATA_FROM_L2MISS,Data loaded missed L2
##000FE
The processor's Data Cache was reloaded but not from the local L2.
#18,v,g,n,n,n,PM_DATA_FROM_L2_CYC,Load latency from L2
##00020
Cycles waiting for a Data Cache reload of data from from the local L2
#19,v,g,n,n,n,PM_DATA_FROM_L35_SHR,Data loaded from L3.5 shared
##0005A
The processor's Data Cache was reloaded with shared (S) data from the L3 of a chip on the same module as this processor is located due to a demand load.
#20,v,g,n,n,n,PM_DATA_FROM_L35_SHR_CYC,Load latency from L3.5 shared
##00026
Cycles waiting for a Data Cache reload of shared (T or SL) data from the L3 of a chip on this MCM
#21,v,g,n,n,n,PM_DATA_FROM_L3_CYC,Load latency from L3
##00022
Cycles waiting for a Data Cache reload of data from from the local L3
#22,v,g,n,n,n,PM_DATA_FROM_LMEM_CYC,Load latency from local memory
##0002C
Cycles waiting for a Data Cache reload of data from local memory
#23,v,g,n,n,n,PM_DATA_FROM_RL2L3_SHR,Data loaded from remote L2 or L3 shared
##0005C
The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load
#24,v,g,n,n,n,PM_DATA_FROM_RL2L3_SHR_CYC,Load latency from remote L2 or L3 shared
##00028
Cycles waiting for a Data Cache reload of shared (T or SL) data from a remote L2 or L3
#25,v,g,n,n,n,PM_DATA_PTEG_1ST_HALF,Data table walk matched in first half primary PTEG
##910A0
A translation request for a data address was satisfied using the primary page table hash. The matching Page Table Entry is one of the first four PTE entries of the primary PTEG
#26,v,g,n,n,n,PM_DATA_PTEG_2ND_HALF,Data table walk matched in second half primary PTEG
##910A2
A translation request for a data address was satisfied using the primary page table hash. The matching Page Table Entry is one of the second four PTE entries of the primary PTEG
#27,v,g,n,n,n,PM_DATA_PTEG_SECONDARY,Data table walk matched in secondary PTEG
##910A4
A translation request for a data address was satisfied using the secondary page table hash. 
#28,u,g,n,n,n,PM_DC_PREF_OUT_OF_STREAMS,D cache out of streams
##810A0
A new prefetch stream was detected but no more stream entries were available.
#29,v,g,n,n,n,PM_DC_PREF_STREAM_ALLOC,D cache new prefetch stream allocated
##810A2
A new Prefetch Stream was allocated.
#30,v,g,n,n,n,PM_DFU_ADD,DFU add type instruction
##E008C
The Decimal Floating Point Unit executed an add type instruction. This could be dadd, dsub, dcmpo, or dcmpu
#31,v,g,n,n,n,PM_DFU_ADD_SHIFTED_BOTH,DFU add type with both operands shifted
##E0088
The Decimal Floating Point Unit executed an add type instruction and both operands required shifting. This could be dadd, dsub, dcmpo, or dcmpu
#32,v,g,n,n,n,PM_DFU_BACK2BACK,DFU back to back operations executed
##E0082
The Decimal Floating Point Unit executed two instructions back to back.
#33,v,g,n,n,n,PM_DFU_CONV,DFU convert from fixed op
##E008E
The Decimal Floating Point Unit executed a convert from fixed point operation. This could be a dcffix or dcffixq instruction. The fixed point operand was converted to a Decimal Floating Point number
#34,v,g,n,n,n,PM_DFU_ENC_BCD_DPD,DFU Encode BCD to DPD
##E008A
The Decimal Floating Point Unit executed an encode to fixed point operation. This could have been a denbcd or denbcdq instruction. The binary coded decimal operand is convered to a binary floating point number.
#35,v,g,n,n,n,PM_DFU_EXP_EQ,DFU operand exponents are equal for add type
##E0084
The Decimal Floating Point Unit executed an add type instruction and the exponents of both operand are equal
#36,v,g,n,n,n,PM_DFU_FIN,DFU instruction finish
##E0080
The Decimal Floating Point Unit finished an operation.
#37,v,g,n,n,n,PM_DFU_SUBNORM,DFU result is a subnormal
##E0086
The result of a Decimal Floating Point operation was subnormal.
#38,v,g,n,n,n,PM_DPU_HELD,DISP unit held
##00004
Cycles that Instruction Dispatch was held. Instruction Dispatch is held to handle resource conflicts, resource dependencies, resources not available and syncronization requirements. More than one hold condition can exist at the same time.
#39,v,g,n,n,n,PM_DPU_HELD_COMPLETION,DISP unit held due to completion holding dispatch 
##210AC
Cycles that Instruction Dispatch was held because of the completion unit. More than one hold condition can exist at the same time
#40,v,g,n,n,n,PM_DPU_HELD_CR_LOGICAL,DISP unit held due to CR, LR or CTR updated by CR logical, MTCRF, MTLR or MTCTR
##3008E
Cycles that Instruction Dispatch was held because the CR, LR, or CTR SPRs were being updated by a CR logical, MTCRF, MTLR or MTCTR instruction. More than one hold condition can exist at the same time
#41,v,g,n,n,n,PM_DPU_HELD_CW,DISP unit held due to cache writes 
##20084
Cycles that Load Store Unit is performing a cache write. The LSU blocks dispatch to avoid contention for the cache during a write. More than one hold condition can exist at the same time
#42,v,g,n,n,n,PM_DPU_HELD_FPQ,DISP unit held due to FPU issue queue full
##20086
Cycles that Instruction Dispatch was held because the Floating Point Issue Queue was full. More than one hold condition can exist at the same time
#43,v,g,n,n,n,PM_DPU_HELD_FPU_CR,DISP unit held due to FPU updating CR
##210A0
Cycles that Instruction Dispatch was held because a Floating Point operation was updating a condition register. Younger instruction are blocked to avoid Write after Write conflicts. More than one hold condition can exist at the same time
#44,v,g,n,n,n,PM_DPU_HELD_FP_FX_MULT,DISP unit held due to non fixed multiple/divide after fixed multiply/divide
##210A8
Cycles that Instruction Dispatch was held due to fixed point multiply/divides. After dispatching a FXU Multiply/Divide instruction, the dispatcher must block all non FXU/Divide instruction from dispatch (same thread)  More than one hold condition can exist at the same time
#45,v,g,n,n,n,PM_DPU_HELD_FXU_MULTI,DISP unit held due to FXU multicycle
##210A6
Cycles that Instruction Dispatch was held due to multi-cycle fixed operation. More than one hold condition can exist at the same time
#46,v,g,n,n,n,PM_DPU_HELD_FXU_SOPS,DISP unit held due to FXU slow ops (mtmsr, scv, rfscv)
##30088
Cycles that Instruction Dispatch was held due to a slow operation executing on a fixed point unit. Instructions such as mtmsr, scv, rfscv require that dispatch be held until all units are idle. More than one hold condition can exist at the same time
#47,v,g,n,n,n,PM_DPU_HELD_GPR,DISP unit held due to GPR dependencies
##20080
Cycles that Instruction Dispatch was held due to a GPR dependency. The dependent instruction is held until the GPR is written. More than one hold condition can exist at the same time
#48,v,g,n,n,n,PM_DPU_HELD_INT,DISP unit held due to exception
##310A8
Cycles that Instruction Dispatch was held due to an exception. Dispatch is  held until all units are idle. More than one hold condition can exist at the same time
#49,v,g,n,n,n,PM_DPU_HELD_ISYNC,DISP unit held due to ISYNC 
##2008A
Cycles that Instruction Dispatch was held due to an isync instruction. If an previous instruction requires a context serializing instruction (CSI), dispatch will be held until the FPU is empty and a completion flush has been received. More than one hold condition can exist at the same time
#50,v,g,n,n,n,PM_DPU_HELD_ITLB_ISLB,DISP unit held due to SLB or TLB invalidates 
##210A4
Cycles that Instruction Dispatch was held due to a islb or itlb instruction. Dispatch is held for three cycles after an islb or itlb instruction is dispatched. More than one hold condition can exist at the same time
#51,v,g,n,n,n,PM_DPU_HELD_LLA_END,DISP unit held due to load look ahead ended
##30084
Cycles that Instruction Dispatch was held due to load look ahead ending. More than one hold condition can exist at the same time
#52,v,g,n,n,n,PM_DPU_HELD_LSU,DISP unit held due to LSU move or invalidate SLB and SR
##210A2
Cycles that Instruction Dispatch was held due to a move to or invalidate of the Segment Lookaside Buffer. Dispatch is held until all units are idle. More than one hold condition can exist at the same time
#53,v,g,n,n,n,PM_DPU_HELD_LSU_SOPS,DISP unit held due to LSU slow ops (sync, tlbie, stcx)
##30080
Cycles that Instruction Dispatch was held due to a slow operation executing on a Load Store Unit. Instructions such as sync, tlbie, stcx require that dispatch be held until all units are idle. More than one hold condition can exist at the same time
#54,v,g,n,n,n,PM_DPU_HELD_MULT_GPR,DISP unit held due to multiple/divide multiply/divide GPR dependencies
##210AA
Cycles that Instruction Dispatch was held due to a GPR dependency caused by a fixed point multiple or divide that is dependent on the results of another fixed point multiple or divide. More than one hold condition can exist at the same time
#55,v,g,n,n,n,PM_DPU_HELD_POWER,DISP unit held due to Power Management
##0003C
Cycles that Instruction Dispatch was held due to power management. More than one hold condition can exist at the same time
#56,v,g,n,n,n,PM_DPU_HELD_RESTART,DISP unit held after restart coming
##30086
Cycles that Instruction Dispatch was held waiting on a restart signal from the LSU. Dispatch has dispatched all available instructions in load look ahead mode and is waiting for the demand load to be returned. 
#57,v,g,n,n,n,PM_DPU_HELD_RU_WQ,DISP unit held due to RU FXU write queue full
##2008E
Cycles that Instruction Dispatch was held because the recovery unit's fixed point write cycle was full. More than one hold condition can exist at the same time
#58,v,g,n,n,n,PM_DPU_HELD_SMT,DISP unit held due to SMT conflicts 
##20082
Cycles that Instruction Dispatch was held due to conflicts with the other thread. There are not enough execution units available to dispatch. More than one hold condition can exist at the same time
#59,v,g,n,n,n,PM_DPU_HELD_SPR,DISP unit held due to MTSPR/MFSPR
##3008C
Cycles that Instruction Dispatch was held because of a move to or move from SPR instruction. More than one hold condition can exist at the same time
#60,v,g,n,n,n,PM_DPU_HELD_STCX_CR,DISP unit held due to STCX updating CR 
##2008C
Cycles that Instruction Dispatch was held due to a stcx instruction updating the CR. Instructions dependant on the CR are held until the stcx finishes. This hold condition is a subset of LSO Slow Operations. More than one hold condition can exist at the same time
#61,v,g,n,n,n,PM_DPU_HELD_THRD_PRIO,DISP unit held due to lower priority thread
##3008A
Cycles that Instruction Dispatch was held due to a lower priority thread. More than one hold condition can exist at the same time
#62,v,g,n,n,n,PM_DPU_HELD_XER,DISP unit held due to XER dependency
##20088
Cycles that Instruction Dispatch was held due to a XER dependency. More than one hold condition can exist at the same time
#63,v,g,n,n,n,PM_DPU_HELD_XTHRD,DISP unit held due to cross thread resource conflicts
##30082
Cycles that Instruction Dispatch was held due to a resource conflict with the other thread. This could be caused by a mtspr, mfspr, or a multi-cycle fixed point operation. More than one hold condition can exist at the same time
#64,v,g,n,n,n,PM_DPU_WT_IC_MISS,Cycles DISP unit is stalled due to I cache miss
##0000C
Cycles that Instruction Dispatch had no instructions available to dispatch because of an instruction cache misst.
#65,v,g,n,n,n,PM_DSLB_MISS,Data SLB misses
##830E8
A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve
#66,u,g,n,n,n,PM_EE_OFF_EXT_INT,Cycles MSR(EE) bit off and external interrupt pending
##230EE
Cycles when an interrupt due to an external exception is pending but external exceptions were masked.
#67,v,g,n,n,n,PM_EXT_INT,External interrupts
##000F8
An interrupt due to an external exception occurred
#68,v,g,n,c,n,PM_FAB_ADDR_COLLISION,local node launch collision with off-node address   
##5018E
A command from the local node hadd an address collision with a command for a system address. The local node competes with system pump addresses from remote nodes for address slots, this event is an indication of how badly local requests are affected by system wide requests
#69,v,g,n,c,n,PM_FAB_CMD_RETRIED,Fabric command retried
##50130
Incremented when a command issued by a chip on its SnoopA address bus is retried for any reason. The overwhelming majority of retries are due to running out of memory controller queues but retries can also be caused by trying to reference addresses that are in a transient cache state -- e.g. a line is transient after issuing a DCLAIM instruction to a shared line but before the associated store completes. Each chip reports its own counts. The signal is 
#70,v,g,n,c,n,PM_FAB_DCLAIM,Dclaim operation, locally mastered
##50184
A DCLAIM command was issued. Each chip reports its own counts. The signal is delivered at FBC speed and the count must be scaled accordingly.
#71,v,g,n,c,n,PM_FAB_DMA,DMA operation, locally mastered
##5018C
A DMA operation was issued. Each chip reports its own counts. The signal is delivered at FBC speed and the count must be scaled accordingly.
#72,v,g,n,c,n,PM_FAB_MMIO,MMIO operation, locally mastered
##50186
A MMIO operation was issued. Each chip reports its own counts. The signal is delivered at FBC speed and the count must be scaled accordingly.
#73,v,g,n,c,n,PM_FAB_NODE_PUMP,Node pump operation, locally mastered
##50188
A request from this chip was send out on the XYZ (intra-node) link. Each chip reports its own counts. The signal is delivered at FBC speed and the count must be scaled accordingly.
#74,v,g,n,c,n,PM_FAB_RETRY_NODE_PUMP,Retry of a node pump, locally mastered
##5018A
A snoop operation for a node pump address originated from a master on this chip and the result was a retry.
#75,v,g,n,c,n,PM_FAB_RETRY_SYS_PUMP,Retry of a system pump, locally mastered  
##50182
A snoop operation for a system pump address originated from a master on this chip and the result was a retry.
#76,v,g,n,c,n,PM_FAB_SYS_PUMP,System pump operation, locally mastered
##50180
An request from this chip was send out on the AB (inter-node) link. Each chip reports its own counts. The signal is delivered at FBC speed and the count must be scaled accordingly.
#77,v,g,n,n,n,PM_FLUSH_ASYNC,Flush caused by asynchronous exception
##220CA
A flush was caused by an asyncronous exception. 
#78,v,g,n,n,n,PM_FLUSH_FPU,Flush caused by FPU exception
##230EC
A flush was caused by a floating point exception.
#79,v,g,n,n,n,PM_FLUSH_FXU,Flush caused by FXU exception
##230EA
A flush was caused by a fixed point exception.
#80,v,g,n,n,n,PM_FPU0_1FLOP,FPU0 executed add, mult, sub, cmp or sel instruction
##C0080
The floating point unit has executed an add, mult, sub, compare, fsel, fneg, fabs, fnabs, fres, or frsqrte kind of instruction. These are single FLOP operations.
#81,v,g,n,n,n,PM_FPU0_DENORM,FPU0 received denormalized data
##C10A2
FPU0 has encountered a denormalized operand. 
#82,v,g,n,n,n,PM_FPU0_FCONV,FPU0 executed FCONV instruction
##D10A0
FPU0 has executed a convert kind of instruction. This could be fcfid* or fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.
#83,v,g,n,n,n,PM_FPU0_FEST,FPU0 executed FEST instruction
##D10A6
FPU0 has executed an estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. 
#84,v,g,n,n,n,PM_FPU0_FIN,FPU0 produced a result
##D0080
FPU0 finished, produced a result. This only indicates finish,  not completion. Floating Point Stores are included in this count but not Floating Point Loads.
#85,v,g,n,n,n,PM_FPU0_FLOP,FPU0 executed 1FLOP, FMA, FSQRT or FDIV instruction
##C0086
FPU0 has executed a one flop, multiply-add, square root, or divide kind of instruction.
#86,v,g,n,n,n,PM_FPU0_FMA,FPU0 executed multiply-add instruction
##C0082
FPU0 has executed a multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.
#87,v,g,n,n,n,PM_FPU0_FPSCR,FPU0 executed FPSCR instruction
##D0084
FPU0 has executed FPSCR move related instruction. This could be mtfsfi*, mtfsb0*, mtfsb1*, mffs*, mtfsf*, mcrsf* where XYZ* means XYZ, XYZs, XYZ., XYZs.
#88,v,g,n,n,n,PM_FPU0_FRSP,FPU0 executed FRSP instruction
##D10A2
FPU0 has executed a frsp kind of instruction. This could be frsp* where XYZ* means XYZ, XYZs, XYZ., XYZs.
#89,v,g,n,n,n,PM_FPU0_FSQRT_FDIV,FPU0 executed FSQRT or FDIV instruction
##C0084
FPU0 has executed a square root or divide instruction. This could be fsqrt* or fdiv* where XYZ* means XYZ, XYZs, XYZ., XYZs
#90,v,g,n,n,n,PM_FPU0_FXDIV,FPU0 executed fixed point division
##C10A0
FPU0 has executed a fixed point divide instruction.
#91,v,g,n,n,n,PM_FPU0_FXMULT,FPU0 executed fixed point multiplication
##D0086
FPU0 has executed a fixed point multiply instruction.
#92,v,g,n,n,n,PM_FPU0_SINGLE,FPU0 executed single precision instruction
##C10A6
FPU0 has executed a single precision instruction.
#93,v,g,n,n,n,PM_FPU0_STF,FPU0 executed store instruction
##C10A4
FPU0 has executed a Floating Point Store instruction.
#94,v,g,n,n,n,PM_FPU0_ST_FOLDED,FPU0 folded store
##D10A4
FPU0 executed a store that was dependant on the result of a previous instruction. The result it folded into the store allowing the store to execute earlier.
#95,v,g,n,n,n,PM_FPU1_1FLOP,FPU1 executed add, mult, sub, cmp or sel instruction
##C0088
FPU1 has executed an add, mult, sub, compare, fsel, fneg, fabs, fnabs, fres, or frsqrte kind of instruction. These are single FLOP operations.
#96,v,g,n,n,n,PM_FPU1_DENORM,FPU1 received denormalized data
##C10AA
FPU1 has encountered a denormalized operand.
#97,v,g,n,n,n,PM_FPU1_FCONV,FPU1 executed FCONV instruction
##D10A8
FPU1 has executed a convert kind of instruction. This could be fcfid* or fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.
#98,v,g,n,n,n,PM_FPU1_FEST,FPU1 executed FEST instruction
##D10AE
FPU1 has executed an estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ.
#99,v,g,n,n,n,PM_FPU1_FIN,FPU1 produced a result
##D0088
FPU1 finished, produced a result. This only indicates finish,  not completion. Floating Point Stores are included in this count but not Floating Point Loads. 
#100,v,g,n,n,n,PM_FPU1_FLOP,FPU1 executed 1FLOP, FMA, FSQRT or FDIV instruction
##C008E
FPU1 has executed a one flop, multiply-add, square root, or divide kind of instruction.
#101,v,g,n,n,n,PM_FPU1_FMA,FPU1 executed multiply-add instruction
##C008A
FPU1 has executed a multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.
#102,v,g,n,n,n,PM_FPU1_FPSCR,FPU1 executed FPSCR instruction
##D008C
FPU1 has executed FPSCR move related instruction. This could be mtfsfi*, mtfsb0*, mtfsb1*, mffs*, mtfsf*, mcrsf* where XYZ* means XYZ, XYZs, XYZ., XYZs.
#103,v,g,n,n,n,PM_FPU1_FRSP,FPU1 executed FRSP instruction
##D10AA
FPU1 has executed a frsp kind of instruction. This could be frsp* where XYZ* means XYZ, XYZs, XYZ., XYZs.
#104,v,g,n,n,n,PM_FPU1_FSQRT_FDIV,FPU1 executed FSQRT or FDIV instruction
##C008C
FPU1 has executed a square root or divide instruction. This could be fsqrt* or fdiv* where XYZ* means XYZ, XYZs, XYZ., XYZs
#105,v,g,n,n,n,PM_FPU1_FXDIV,FPU1 executed fixed point division
##C10A8
FPU1 has executed a fixed point divide instruction.
#106,v,g,n,n,n,PM_FPU1_FXMULT,FPU1 executed fixed point multiplication
##D008E
FPU1 has executed a fixed point multiply instruction.
#107,v,g,n,n,n,PM_FPU1_SINGLE,FPU1 executed single precision instruction
##C10AE
FPU1 has executed a single precision instruction.
#108,v,g,n,n,n,PM_FPU1_STF,FPU1 executed store instruction
##C10AC
FPU1 has executed a Floating Point Store instruction.
#109,v,g,n,n,n,PM_FPU1_ST_FOLDED,FPU1 folded store
##D10AC
FPU1 executed a store that was dependant on the result of a previous instruction. The result it folded into the store allowing the store to execute earlier.
#110,v,g,n,n,n,PM_FPU_DENORM,FPU received denormalized data
##C1034
The floating point unit has encountered a denormalized operand. Combined Unit 0 + Unit 1.
#111,v,g,n,n,n,PM_FPU_FMA,FPU executed multiply-add instruction
##C0030
The floating point unit has executed a multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.
#112,v,g,n,n,n,PM_FPU_FPSCR,FPU executed FPSCR instruction
##D0032
The floating point unit has executed a FPSCR move related instruction. This could be mtfsfi*, mtfsb0*, mtfsb1*, mffs*, mtfsf*, mcrsf* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1.
#113,v,g,n,n,n,PM_FPU_FRSP,FPU executed FRSP instruction
##D1034
The floating point unit has executed a frsp or convert kind of instruction. This could be frsp*  where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1.
#114,v,g,n,n,n,PM_FPU_FSQRT_FDIV,FPU executed FSQRT or FDIV instruction
##C0032
The floating point unit has executed a square root or divide instruction. This could be fsqrt* or fdiv* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1.
#115,v,g,n,n,n,PM_FPU_ISSUE_0,FPU issue 0 per cycle
##320C6
Cycles when no instructions were issued to the floating point units.
#116,v,g,n,n,n,PM_FPU_ISSUE_1,FPU issue 1 per cycle
##320C8
Cycles when one instruction was issued to the floating point units.
#117,v,g,n,n,n,PM_FPU_ISSUE_2,FPU issue 2 per cycle
##320CA
Cycles when two instruction were issued to the floating point units.
#118,v,g,n,n,n,PM_FPU_ISSUE_DIV_SQRT_OVERLAP,FPU divide/sqrt overlapped with other divide/sqrt
##320CC
The floating point unit was issued a divide or square root instruction that overlapped execution with another divide or square root instruction. These instructions are not pipelined but they can execute in parallel on separate units.
#119,v,g,n,n,n,PM_FPU_ISSUE_OOO,FPU issue out-of-order
##320C0
Instructions were issued to the floating point unit of of order with respect to program order. The floating point unit has limited ability to execute instructions out of order.
#120,v,g,n,n,n,PM_FPU_ISSUE_STALL_FPR,FPU issue stalled due to FPR dependencies
##330E2
Instruction issue to the floating point unit was stalled waiting on the results of a previous instruction.
#121,v,g,n,n,n,PM_FPU_ISSUE_STALL_ST,FPU issue stalled due to store
##320CE
Instruction issue to the floating point unit was stalled due to store. Only one store per cycle can be issued to the floating point unit.
#122,v,g,n,n,n,PM_FPU_ISSUE_STALL_THRD,FPU issue stalled due to thread resource conflict
##330E0
Instruction issue to the floating point unit was stalled because a critical resource was in use by the other thread.
#123,v,g,n,n,n,PM_FPU_ISSUE_STEERING,FPU issue steering
##320C4
An instruction was steered to a specific execution unit at issue time. Some instructions are limited to execution on a specific unit. The issue logic will attempt to steer dependent floating-point instructions to the unit that is producing the result it is dependent upon.
#124,v,g,n,n,n,PM_FPU_ISSUE_ST_FOLDED,FPU issue a folded store
##320C2
A store was issued to the floating point unit that was dependant on the result of a previous instruction. The result it folded into the store allowing the store to execute earlier.
#125,u,g,n,n,n,PM_FXU_BUSY,FXU busy
##00050
Cycles when both FXU0 and FXU1 are busy.
#126,v,g,n,n,n,PM_FXU_PIPELINED_MULT_DIV,Fix point multiply/divide pipelined
##210AE
A fixed point multiple or divide was dispatched while another one was in progress. A sequence of fixed point multiplies or divides can be pipelined, one every other cycle, but any other instruction will stall until the multiply or divide  instructions are finished.
#127,v,g,n,s,n,PM_GCT_EMPTY_CYC,Cycles GCT empty
##00008
Cycles when the Global Completion Table was completely empty. No thread had an entry allocated.
#128,v,g,n,n,n,PM_GCT_FULL_CYC,Cycles GCT full
##40086
The Global Completion Table is completely full.
#129,v,g,n,c,n,PM_GXI_ADDR_CYC_BUSY,Inbound GX address utilization (# of cycle address is in valid)
##50388
Number of bus cycles the inbound GX bus is receiving an address. The signal is delivered at GX Controller speed and the count must be scaled accordingly
#130,v,g,n,c,n,PM_GXI_CYC_BUSY,Inbound GX bus utilizations (# of cycles in use)
##50386
Number of bus cycles the inbound GX bus is in use. The signal is delivered at GX Controller speed and the count must be scaled accordingly
#131,v,g,n,c,n,PM_GXI_DATA_CYC_BUSY,Inbound GX Data utilization (# of cycle data in is valid)
##5038A
Number of bus cycles the inbound GX bus is receiving data. The signal is delivered at GX Controller speed and the count must be scaled accordingly
#132,v,g,n,c,n,PM_GXO_ADDR_CYC_BUSY,Outbound GX address utilization (# of cycles address out is valid)
##50382
Number of bus cycles the outbound GX bus is receiving an address. The signal is delivered at GX Controller speed and the count must be scaled accordingly
#133,v,g,n,c,n,PM_GXO_CYC_BUSY,Outbound GX bus utilizations (# of cycles in use)
##50380
Number of bus cycles the outbound GX bus is in use. The signal is delivered at GX Controller speed and the count must be scaled accordingly
#134,v,g,n,c,n,PM_GXO_DATA_CYC_BUSY,Outbound GX Data utilization (# of cycles data out is valid)
##50384
Number of bus cycles the outbound GX bus is receiving data. The signal is delivered at GX Controller speed and the count must be scaled accordingly
#135,v,g,n,c,n,PM_GX_DMA_READ,DMA Read Request
##5038C
The GX Bus Controller processed a DMA read request. The signal is delivered at GX Controller speed and the count must be scaled accordingly
#136,v,g,n,c,n,PM_GX_DMA_WRITE,All DMA Write Requests (including dma wrt lgcy)
##5038E
The GX Bus Controller processed a DMA write request. The signal is delivered at GX Controller speed and the count must be scaled accordingly
#137,v,g,n,n,n,PM_HV_CYC,Hypervisor Cycles
##00016
Cycles when the processor is executing in Hypervisor (MSR[HV] = 1 and MSR[PR]=0)
#138,v,g,n,n,n,PM_IBUF_FULL_CYC,Cycles instruction buffer full
##40084
Cycles with the Instruction Buffer was full. The Instruction Buffer is a circular queue of 64 instructions per thread, organized as 16 groups of 4 instructions.
#139,v,g,n,n,n,PM_IC_DEMAND_L2_BHT_REDIRECT,L2 I cache demand request due to BHT redirect
##420CA
A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (CR mispredict).
#140,v,g,n,n,n,PM_IC_DEMAND_L2_BR_REDIRECT,L2 I cache demand request due to branch redirect
##420CC
A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (either ALL mispredicted or Target).
#141,v,g,n,c,n,PM_IC_INV_L2,L1 I cache entries invalidated from L2
##50632
L1 I cache entries invalidated from L2
#142,v,g,n,n,n,PM_IC_PREF_REQ,Instruction prefetch requests
##4008C
An instruction prefetch request has been made.
#143,v,g,n,n,n,PM_IC_PREF_WRITE,Instruction prefetch written into I cache
##430E0
Number of Instruction Cache entries written because of prefetch. Prefetch entries are marked least recently used and are candidates for eviction if they are not needed to satify a demand fetch.
#144,v,g,n,n,n,PM_IC_RELOAD_SHR,I cache line reloading to be shared by threads
##4008E
An Instruction Cache request was made by this thread and the cache line was already in the cache for the other thread. The line is marked valid for both threads.
#145,v,g,n,n,n,PM_IC_REQ,I cache demand of prefetch request
##4008A
An instruction fetch request was made. The request may have been a prefetch request or a demand request.
#146,v,g,n,n,n,PM_IERAT_MISS,IERAT miss count
##420CE
A translation request missed the Instruction Effective to Real Address Translation (ERAT) table
#147,v,g,n,n,n,PM_IFU_FIN,IFU finished an instruction
##430E4
The Instruction Fetch Unit finished an instruction
#148,v,g,n,n,n,PM_INST_CMPL,Instructions completed
##00002
Number of PPC instructions completed. 
#149,v,g,n,n,n,PM_INST_DISP,Instructions dispatched
##00012,000F2
Number of PowerPC instructions successfully dispatched.
#150,v,g,n,n,n,PM_INST_DISP_LLA,Instruction dispatched under load look ahead
##310A2
Instructions dispatched while Load Look ahead is active.
#151,v,g,n,n,n,PM_INST_FETCH_CYC,Cycles at least 1 instruction fetched
##420C8
Cycles when at least one instruction was sent from the fetch unit to the decode unit.
#152,v,g,n,n,n,PM_INST_FROM_DMEM,Instruction fetched from distant memory
##42042
An instruction fetch group was fetched from memory attached to a distant module. Fetch groups can contain up to 8 instructions
#153,v,g,n,n,n,PM_INST_FROM_L1,Instruction fetched from L1
##40082
An instruction fetch group was fetched from L1. Fetch Groups can contain up to 8 instructions
#154,v,g,n,n,n,PM_INST_FROM_L21,Instruction fetched from private L2 other core
##42040
An instruction fetch group was fetched from the private L2 of the other processor on this chip. Fetch groups can contain up to 8 instructions.
#155,v,g,n,n,n,PM_INST_FROM_L35_SHR,Instruction fetched from L3.5 shared
##42046
An instruction fetch group was fetched with shared (S) data from the L3 of a chip on the same module as this processor is located. Fetch groups can contain up to 8 instructions
#156,v,g,n,n,n,PM_INST_FROM_RL2L3_SHR,Instruction fetched from remote L2 or L3 shared
##42044
An instruction fetch group was fetched with shared  (S) data from the L2 or L3 on a remote module. Fetch groups can contain up to 8 instructions
#157,v,g,n,n,n,PM_INST_PTEG_1ST_HALF,Instruction table walk matched in first half primary PTEG
##910A8
A translation request for a instruction address was satisfied using the primary page table hash. The matching Page Table Entry is one of the first four PTE entries of the primary PTEG
#158,v,g,n,n,n,PM_INST_PTEG_2ND_HALF,Instruction table walk matched in second half primary PTEG
##910AA
A translation request for a instruction address was satisfied using the primary page table hash. The matching Page Table Entry is one of the second four PTE entries of the primary PTEG
#159,v,g,n,n,n,PM_INST_PTEG_SECONDARY,Instruction table walk matched in secondary PTEG
##910AC
A translation request for a instruction address was satisfied using the secondary page table hash. 
#160,v,g,n,n,n,PM_INST_TABLEWALK_CYC,Cycles doing instruction tablewalks
##920CA
Cycles an Instruction Tablewalk is active. 
#161,u,g,n,n,n,PM_ISLB_MISS,Instruction SLB misses
##830E0
A SLB miss for an instruction fetch as occurred
#162,v,g,n,n,n,PM_ITLB_REF,Instruction TLB reference
##920C2
Number of Instruction Translation requests from the ERAT. 
#163,v,g,n,n,n,PM_L1_ICACHE_MISS,L1 I cache miss count
##000FC
An instruction fetch request missed the L1 cache.
#164,v,g,n,n,n,PM_L1_PREF,L1 cache data prefetches
##810A4
A request to prefetch data into the L1 was made
#165,v,g,n,n,n,PM_L1_WRITE_CYC,Cycles writing to instruction L1
##430E2
Cycles that a cache line was written to the instruction cache.
#166,v,g,n,c,n,PM_L2SA_CASTOUT_MOD,L2 slice A castouts - Modified
##50680
An L2 line in the Modified state was castout. Reported per slice.
#167,v,g,n,c,n,PM_L2SA_CASTOUT_SHR,L2 slice A castouts - Shared
##50682
An L2 line in the Shared state was castout. Reported per slice.
#168,v,g,n,c,n,PM_L2SA_DC_INV,L2 slice A D cache invalidate
##50686
The L2 invalidated a line in processor's data cache. This is caused by the L2 line being cast out or invalidated. Reported per slice.
#169,v,g,n,c,n,PM_L2SA_IC_INV,L2 slice A I cache invalidate
##50684
The L2 invalidated a line in processor's instruction cache. This is caused by the L2 line being cast out or invalidated. Reported per slice.
#170,v,g,n,c,n,PM_L2SA_LD_HIT,L2 slice A load hits
##50782
A load request (data or instruction) hit in the L2 directory. Includes speculative, prefetched, and demand requests. This event includes all requests to this L2 from all sources. Reported per slice.
#171,v,g,n,n,n,PM_L2SA_LD_MISS_DATA,L2 slice A data load misses
##50482
A data load request from this thread hit in the L2 directory. Includes speculative, prefetched, and demand requests. Reported per slice.
#172,v,g,n,n,n,PM_L2SA_LD_MISS_INST,L2 slice A instruction load misses
##50582
An instruction load request from this thread hit in the L2 directory. Includes speculative, prefetched, and demand requests. Reported per slice.
#173,v,g,n,c,n,PM_L2SA_LD_REQ,L2 slice A load requests 
##50780
A load request (data or instruction) was received by the L2 directory. Includes speculative, prefetched, and demand requests. This event includes all requests to this L2 from all sources. Reported per slice.
#174,v,g,n,n,n,PM_L2SA_LD_REQ_DATA,L2 slice A data load requests
##50480
A data load request from this thread was received by the L2 directory. Includes speculative, prefetched, and demand requests. Reported per slice.
#175,v,g,n,n,n,PM_L2SA_LD_REQ_INST,L2 slice A instruction load requests
##50580
An instruction load request from this thread was received by the L2 directory. Includes speculative, prefetched, and demand requests. Reported per slice.
#176,v,g,n,n,n,PM_L2SA_MISS,L2 slice A misses
##50584
Total L2 misses (loads and stores) from this thread. Includes speculative, prefetched, and demand requests. Reported per slice.
#177,v,g,n,c,n,PM_L2SA_ST_HIT,L2 slice A store hits
##50786
A store request hit in the L2 directory. This event includes all requests to this L2 from all sources. Reported per slice.
#178,v,g,n,n,n,PM_L2SA_ST_MISS,L2 slice A store misses
##50486
A store request from this thread missed in the L2 directory. Reported per slice.
#179,v,g,n,n,n,PM_L2SA_ST_REQ,L2 slice A store requests
##50484,50784
A store request  was received by the L2 directory. This event includes all requests to this L2 from all sources. Stores are counted after gathering in the L2 store queues. Reported per slice.
#180,v,g,n,c,n,PM_L2SB_CASTOUT_MOD,L2 slice B castouts - Modified
##50688
An L2 line in the Modified state was castout. Reported per slice.
#181,v,g,n,c,n,PM_L2SB_CASTOUT_SHR,L2 slice B castouts - Shared
##5068A
An L2 line in the Shared state was castout. Reported per slice.
#182,v,g,n,c,n,PM_L2SB_DC_INV,L2 slice B D cache invalidate
##5068E
The L2 invalidated a line in processor's data cache. This is caused by the L2 line being cast out or invalidated. Reported per slice.
#183,v,g,n,c,n,PM_L2SB_IC_INV,L2 slice B I cache invalidate
##5068C
The L2 invalidated a line in processor's instruction cache. This is caused by the L2 line being cast out or invalidated. Reported per slice.
#184,v,g,n,c,n,PM_L2SB_LD_HIT,L2 slice B load hits
##5078A
A load request (data or instruction) hit in the L2 directory. Includes speculative, prefetched, and demand requests. This event includes all requests to this L2 from all sources. Reported per slice.
#185,v,g,n,n,n,PM_L2SB_LD_MISS_DATA,L2 slice B data load misses
##5048A
A data load request from this thread hit in the L2 directory. Includes speculative, prefetched, and demand requests. Reported per slice.
#186,v,g,n,n,n,PM_L2SB_LD_MISS_INST,L2 slice B instruction load misses
##5058A
An instruction load request from this thread hit in the L2 directory. Includes speculative, prefetched, and demand requests. Reported per slice.
#187,v,g,n,c,n,PM_L2SB_LD_REQ,L2 slice B load requests 
##50788
A load request (data or instruction) was received by the L2 directory. Includes speculative, prefetched, and demand requests. This event includes all requests to this L2 from all sources. Reported per slice.
#188,v,g,n,n,n,PM_L2SB_LD_REQ_DATA,L2 slice B data load requests
##50488
A data load request from this thread was received by the L2 directory. Includes speculative, prefetched, and demand requests. Reported per slice.
#189,v,g,n,n,n,PM_L2SB_LD_REQ_INST,L2 slice B instruction load requests
##50588
An instruction load request from this thread was received by the L2 directory. Includes speculative, prefetched, and demand requests. Reported per slice.
#190,v,g,n,n,n,PM_L2SB_MISS,L2 slice B misses
##5058C
Total L2 misses (loads and stores) from this thread. Includes speculative, prefetched, and demand requests. Reported per slice.
#191,v,g,n,c,n,PM_L2SB_ST_HIT,L2 slice B store hits
##5078E
A store request hit in the L2 directory. This event includes all requests to this L2 from all sources. Reported per slice.
#192,v,g,n,n,n,PM_L2SB_ST_MISS,L2 slice B store misses
##5048E
A store request from this thread missed in the L2 directory. Reported per slice.
#193,v,g,n,n,n,PM_L2SB_ST_REQ,L2 slice B store requests
##5048C,5078C
A store request  was received by the L2 directory. This event includes all requests to this L2 from all sources. Stores are counted after gathering in the L2 store queues. Reported per slice.
#194,v,g,n,c,n,PM_L2_CASTOUT_SHR,L2 castouts - Shared (T, Te, Si, S)
##50630
An L2 line in the Shared state was castout. Total for all slices.
#195,v,g,n,n,n,PM_L2_LD_MISS_DATA,L2 data load misses
##50430
A data load request from this thread hit in the L2 directory. Includes speculative, prefetched, and demand requests. Total for all slices.
#196,v,g,n,n,n,PM_L2_LD_MISS_INST,L2 instruction load misses
##50530
An instruction load request from this thread hit in the L2 directory. Includes speculative, prefetched, and demand requests. Total for all slices.
#197,v,g,n,n,n,PM_L2_MISS,L2 cache misses
##50532
Total L2 misses (loads and stores) from this thread. Includes speculative, prefetched, and demand requests. Total for all slices.
#198,v,g,n,n,n,PM_L2_PREF_LD,L2 cache prefetches
##810A6
A request to prefetch load data into L2 was made
#199,v,g,n,n,n,PM_L2_PREF_ST,L2 cache prefetches
##810A8
A request to prefetch the target of a store into L2 was made
#200,v,g,n,n,n,PM_L2_ST_REQ_DATA,L2 data store requests
##50432
A store request  from this thread was received by the L2 directory. Stores are counted after gathering in the L2 store queues. Reported per slice.
#201,v,g,n,c,n,PM_L3SA_HIT,L3 slice A hits
##50030,50082
Number of attempts made by this chip cores that resulted in an L3 hit. Reported per L3 slice
#202,v,g,n,c,n,PM_L3SA_MISS,L3 slice A misses
##50032,50084
Number of attempts made by this chip cores that resulted in an L3 miss. Reported per L3 slice
#203,v,g,n,c,n,PM_L3SA_REF,L3 slice A references
##50080
Number of attempts made by this chip cores to find data in the L3. Reported per L3 slice 
#204,v,g,n,c,n,PM_L3SB_HIT,L3 slice B hits
##5008A
Number of attempts made by this chip cores that resulted in an L3 hit. Reported per L3 slice
#205,v,g,n,n,n,PM_L3SB_MISS,L3 slice B misses
##5008C
Number of attempts made by this chip cores that resulted in an L3 miss. Reported per L3 slice
#206,v,g,n,c,n,PM_L3SB_REF,L3 slice B references
##50088
Number of attempts made by this chip cores to find data in the L3. Reported per L3 slice 
#207,v,g,n,n,n,PM_LARX,Larx executed
##830EA
A larx (lwarx or ldarx) was sent to the nest
#208,v,g,n,n,n,PM_LARX_L1HIT,larx hits in L1
##830E2
A larxa was sent to the nest
#209,v,g,n,c,n,PM_LD_HIT_L2,L2 D cache load hits
##50730
L2 D cache load hits
#210,v,g,n,n,n,PM_LD_MISS_L1,L1 D cache load misses
##80080
Load references that miss the Level 1 Data cache. Combined unit 0 + 1.
#211,v,g,n,n,n,PM_LD_MISS_L1_CYC,L1 data load miss cycles
##0000C
Cycles waiting on a demand miss to the level 1 Data cache. On POWER6 there can only be one demand miss outstanding at a time. Dividing cycles waiting on a demand miss by the number of demand misses gives the average latency to satisfy a demand miss
#212,v,g,n,n,n,PM_LD_REF_L1,L1 D cache load references
##80030,80082,8008A
Load references to the Level 1 Data Cache. Combined unit 0 + 1.
#213,v,g,n,n,n,PM_LSU0_DERAT_MISS,LSU0 DERAT misses
##910A6
A data request (load or store) from LSU Unit 0 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.
#214,v,g,n,n,n,PM_LSU0_LDF,LSU0 executed Floating Point load instruction
##80084
A floating point load was executed from LSU unit 0
#215,v,g,n,n,n,PM_LSU0_NCLD,LSU0 non-cacheable loads
##820CA
A non-cacheable load was executed by unit 0.
#216,v,g,n,n,n,PM_LSU0_NCST,LSU0 non-cachable stores
##820CC
A non-cacheable store was executed by unit 0.
#217,v,g,n,n,n,PM_LSU0_REJECT,LSU0 reject
##A10A6
Load Store Unit 0 rejected an instruction.
#218,v,g,n,n,n,PM_LSU0_REJECT_DERAT_MPRED,LSU0 reject due to mispredicted DERAT
##A0082
Load Store Unit 0 rejected an instruction because the Effective Address was improperly predicted. This is a fast reject and will be immediately redispatched. On the redispatch, the scratch register is used to provide the correct effective address for the D-ERAT access to resolve the incorrect guess.
#219,v,g,n,n,n,PM_LSU0_REJECT_EXTERN,LSU0 external reject request 
##A10A4
Load Store Unit 0 rejected an instruction due to a request from the decode unit or the fixed point unit.
#220,v,g,n,n,n,PM_LSU0_REJECT_L2MISS,LSU0 L2 miss reject
##90084
Load Store Unit 0 rejected a load due to a correctable error in the L2. This is a fast reject and will be immediately redispatched. 
#221,v,g,n,n,n,PM_LSU0_REJECT_L2_CORR,LSU0 reject due to L2 correctable error
##A10A0
Load Store Unit 0 rejected an instruction. The reject was a collision type reject. The IDU immediately redispatches the rejected instruction. The result is eleven (11) cycles, dispatch-to-dispatch, in the best case. 
#222,v,g,n,n,n,PM_LSU0_REJECT_LHS,LSU0 load hit store reject
##90086
Load Store Unit 0 rejected a load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully.
#223,v,g,n,n,n,PM_LSU0_REJECT_NO_SCRATCH,LSU0 reject due to scratch register not available
##A10A2
Load Store Unit 0 rejected an instruction because the internal scratch register was not available. This is a fast reject and will be immediately redispatched. 
#224,v,g,n,n,n,PM_LSU0_REJECT_PARTIAL_SECTOR,LSU0 reject due to partial sector valid
##A0086
Load Store Unit 0 rejected an instruction that had a L1 Data Cache line hit but the critical sector was not valid. Since the cache line is partially validated, a reload of that cache line is in progress. This is a fast reject and will be immediately redispatched. 
#225,v,g,n,n,n,PM_LSU0_REJECT_SET_MPRED,LSU0 reject due to mispredicted set
##A0084
Load Store Unit 0 rejected an instruction because the cache set was improperly predicted. This is a fast reject and will be immediately redispatched. 
#226,v,g,n,n,n,PM_LSU0_REJECT_STQ_FULL,LSU0 reject due to store queue full
##A0080
Load Store Unit 0 rejected a store because the store request queue was full. This is a fast reject and will be immediately redispatched.
#227,v,g,n,n,n,PM_LSU0_REJECT_ULD,LSU0 unaligned load reject
##90080
Load Store Unit 0 rejected a load instruction that spans a cache line boundary (128B). The LSU will pass the incremented address information to the FXU via the scratch register so that the subsequent address generation will access the next line.
#228,v,g,n,n,n,PM_LSU0_REJECT_UST,LSU0 unaligned store reject
##90082
Load Store Unit 0 rejected a store instruction that spans a cache line boundary (128B). The LSU will pass the incremented address information to the FXU via the scratch register so that the subsequent address generation will access the next line.
#229,v,g,n,n,n,PM_LSU1_DERAT_MISS,LSU1 DERAT misses
##910AE
A data request (load or store) from LSU Unit 1 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.
#230,v,g,n,n,n,PM_LSU1_LDF,LSU1 executed Floating Point load instruction
##8008C
A floating point load was executed from LSU unit 1
#231,v,g,n,n,n,PM_LSU1_REJECT,LSU1 reject
##A10AE
Load Store Unit 1 rejected an instruction.
#232,v,g,n,n,n,PM_LSU1_REJECT_DERAT_MPRED,LSU1 reject due to mispredicted DERAT
##A008A
Load Store Unit 1 rejected an instruction because the Effective Address was improperly predicted. This is a fast reject and will be immediately redispatched. On the redispatch, the scratch register is used to provide the correct effective address for the D-ERAT access to resolve the incorrect guess.
#233,v,g,n,n,n,PM_LSU1_REJECT_EXTERN,LSU1 external reject request 
##A10AC
Load Store Unit 1 rejected an instruction due to a request from the decode unit or the fixed point unit.
#234,v,g,n,n,n,PM_LSU1_REJECT_L2_CORR,LSU1 reject due to L2 correctable error
##A10A8
Load Store Unit 1 rejected an instruction. The reject was a collision type reject. The IDU immediately redispatches the rejected instruction. The result is eleven (11) cycles, dispatch-to-dispatch, in the best case. 
#235,v,g,n,n,n,PM_LSU1_REJECT_LHS,LSU1 load hit store reject
##9008E
Load Store Unit 1 rejected a load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully.
#236,v,g,n,n,n,PM_LSU1_REJECT_NO_SCRATCH,LSU1 reject due to scratch register not available
##A10AA
Load Store Unit 1 rejected an instruction because the internal scratch register was not available. This is a fast reject and will be immediately redispatched. 
#237,v,g,n,n,n,PM_LSU1_REJECT_PARTIAL_SECTOR,LSU1 reject due to partial sector valid
##A008E
Load Store Unit 1 rejected an instruction that had a L1 Data Cache line hit but the critical sector was not valid. Since the cache line is partially validated, a reload of that cache line is in progress. This is a fast reject and will be immediately redispatched. 
#238,v,g,n,n,n,PM_LSU1_REJECT_SET_MPRED,LSU1 reject due to mispredicted set
##A008C
Load Store Unit 1 rejected an instruction because the cache set was improperly predicted. This is a fast reject and will be immediately redispatched. 
#239,v,g,n,n,n,PM_LSU1_REJECT_STQ_FULL,LSU1 reject due to store queue full
##A0088
Load Store Unit 1 rejected a store because the store request queue was full. This is a fast reject and will be immediately redispatched.
#240,v,g,n,n,n,PM_LSU1_REJECT_ULD,LSU1 unaligned load reject
##90088
Load Store Unit 1 rejected a load instruction that spans a cache line boundary (128B). The LSU will pass the incremented address information to the FXU via the scratch register so that the subsequent address generation will access the next line.
#241,v,g,n,n,n,PM_LSU1_REJECT_UST,LSU1 unaligned store reject
##9008A
Load Store Unit 1 rejected a store instruction that spans a cache line boundary (128B). The LSU will pass the incremented address information to the FXU via the scratch register so that the subsequent address generation will access the next line.
#242,v,g,n,n,n,PM_LSU_BOTH_BUS,Both data return buses busy simultaneously
##810AA
Data was returned on both data buses
#243,v,g,n,n,n,PM_LSU_DERAT_MISS,DERAT misses
##0000E
Total D-ERAT Misses. On POWER6 only one demand D-ERAT miss can be pending at a time. The processor may continue to execute instructions in Load Look Ahead mode while the miss is serviced.
#244,v,g,n,n,n,PM_LSU_FLUSH_ALIGN,Flush caused by alignement exception
##220CC
A flush was initiated by the Load Store Unit in response to an unaligned operand
#245,v,g,n,n,n,PM_LSU_FLUSH_DSI,Flush caused by DSI
##220CE
A flush was initiated by the Load Store Unit in response to a Data Storage Interrupt
#246,v,g,n,n,n,PM_LSU_LDF,LSU executed Floating Point load instruction
##80032
LSU executed Floating Point load instruction. Combined Unit 0 + 1.
#247,u,g,n,s,n,PM_LSU_LMQ_FULL_CYC,Cycles LMQ full
##810AC
The Load Miss Queue was full.
#248,u,g,n,n,n,PM_LSU_LMQ_SRQ_EMPTY_CYC,Cycles LMQ and SRQ empty
##0001C
This thread had no entries in the Load Miss Queue and Store Request Queue (Load Store Units are idle)
#249,v,g,n,n,n,PM_LSU_REJECT_DERAT_MPRED,LSU reject due to mispredicted DERAT
##A0030
The Load Store Unit rejected an instruction because the Effective Address was improperly predicted. This is a fast reject and will be immediately redispatched. On the redispatch, the scratch register is used to provide the correct effective address for the D-ERAT access to resolve the incorrect guess. Combined Unit 0 + 1
#250,v,g,n,n,n,PM_LSU_REJECT_LHS_BOTH,Load hit store reject both units
##90038
Both Load Store Units were rejecting a load instruction that had an address overlap with an older store in the store queue.
#251,v,g,n,n,n,PM_LSU_REJECT_NO_SCRATCH,LSU reject due to scratch register not available
##A1034
The Load Store Unit rejected an instruction because the internal scratch register was not available. This is a fast reject and will be immediately redispatched. Combined Unit 0 + 1
#252,v,g,n,n,n,PM_LSU_REJECT_SET_MPRED,LSU reject due to mispredicted set
##A0032
The Load Store Unit rejected an instruction because the cache set was improperly predicted. This is a fast reject and will be immediately redispatched. Combined Unit 0 + 1
#253,v,g,n,n,n,PM_LSU_REJECT_SLOW,LSU slow reject
##0003E
The Load Store Unit rejected an instruction. The reject was a restart type reject. The IDU may continue to dispatch instructions in load look ahead mode. The Load Store Unit will notify the IDU when the rejected instruction can be restarted. Combined Unit 0 + 1
#254,v,g,n,n,n,PM_LSU_REJECT_STEAL,LSU reject due to steal
##9008C
The Load Store Unit rejected an instruction because a cache or cache directory was being updated. This is a fast reject and will be immediately redispatched. Combined Unit 0 + 1
#255,v,g,n,n,n,PM_LSU_REJECT_ULD_BOTH,Unaligned load reject both units
##90036
Both Load Store Units are rejecting an unaligned load at the same time
#256,v,g,n,n,n,PM_LSU_REJECT_UST,Unaligned store reject
##90030
The Load Store Unit rejected a store instruction that spans a cache line boundary (128B). The LSU will pass the incremented address information to the FXU via the scratch register so that the subsequent address generation will access the next line. Combined Unit 0 + 1
#257,v,g,n,n,n,PM_LSU_ST_CHAINED,number of chained stores
##820CE
The Load Store Unit chained two store requests together and sent them as one to the L2
#258,v,g,n,n,n,PM_LWSYNC,Isync instruction completed
##810AE
A lightweight sync instruction completed.
#259,v,g,n,c,n,PM_MEM0_DP_CL_WR_GLOB,cacheline write setting dp to global side 0
##50284
A memory cacheline write on memory controller 0 from a remote node. This event is sent from the Memory Controller clock domain and must be scaled accordingly.
#260,v,g,n,c,n,PM_MEM0_DP_CL_WR_LOC,cacheline write setting dp to local side 0
##50286
A memory cacheline write on memory controller 0 from a local node. This event is sent from the Memory Controller clock domain and must be scaled accordingly.
#261,v,g,n,c,n,PM_MEM0_DP_RQ_GLOB_LOC,Memory read queue marking cache line double pump state from global to local side 0
##50280
A memory cacheline read on memory controller 0 changed the double pump state from global to local. This event is sent from the Memory Controller clock domain and must be scaled accordingly.
#262,v,g,n,c,n,PM_MEM0_DP_RQ_LOC_GLOB,Memory read queue marking cache line double pump state from local to global side 0
##50282
A memory cacheline read on memory controller 0 changed the double pump state from local to global. This event is sent from the Memory Controller clock domain and must be scaled accordingly.
#263,v,g,n,c,n,PM_MEM1_DP_CL_WR_GLOB,cacheline write setting dp to global side 1
##5028C
A memory cacheline write on memory controller 1 from a remote node. This event is sent from the Memory Controller clock domain and must be scaled accordingly.
#264,v,g,n,c,n,PM_MEM1_DP_CL_WR_LOC,cacheline write setting dp to local side 1
##5028E
A memory cacheline write on memory controller 1 from a local node. This event is sent from the Memory Controller clock domain and must be scaled accordingly.
#265,v,g,n,c,n,PM_MEM1_DP_RQ_GLOB_LOC,Memory read queue marking cache line double pump state from global to local side 1
##50288
A memory cacheline read on memory controller 1 changed the double pump state from global to local. This event is sent from the Memory Controller clock domain and must be scaled accordingly.
#266,v,g,n,c,n,PM_MEM1_DP_RQ_LOC_GLOB,Memory read queue marking cache line double pump state from local to global side 1
##5028A
A memory cacheline read on memory controller 1 changed the double pump state from local to global. This event is sent from the Memory Controller clock domain and must be scaled accordingly.
#267,v,g,n,c,n,PM_MEM_DP_CL_WR_GLOB,cache line write setting double pump state to global
##50232
A memory cacheline write from a remote node. This event is sent from the Memory Controller clock domain and must be scaled accordingly. Combined unit 0 + 1.
#268,v,g,n,c,n,PM_MEM_DP_RQ_LOC_GLOB,Memory read queue marking cache line double pump state from local to global
##50230
A memory cacheline read changed the double pump state from local to global. This event is sent from the Memory Controller clock domain and must be scaled accordingly. Combined unit 0 + 1.
#269,v,g,n,n,m,PM_MRK_DATA_FROM_DMEM,Marked data loaded from distant memory
##0304A
The processor's Data Cache was reloaded with data from memory attached to a distant module due to a marked load.
#270,v,g,n,n,m,PM_MRK_DATA_FROM_L21,Marked data loaded from private L2 other core
##03048
The processor's Data Cache was reloaded from the private L2 of the other core on this chip due to a marked load.
#271,v,g,n,n,m,PM_MRK_DATA_FROM_L35_SHR,Marked data loaded from L3.5 shared
##0304E
The processor's Data Cache was reloaded with shared (S) data from the L3 of a chip on the same module as this processor is located due to a marked load.
#272,v,g,n,n,m,PM_MRK_DATA_FROM_RL2L3_SHR,Marked data loaded from remote L2 or L3 shared
##0304C
The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a remote module due to a marked load.
#273,v,g,n,n,m,PM_MRK_DTLB_REF,Marked Data TLB reference
##920C0
Total number of Data TLB references by a marked instruction for all page sizes. Page size is determined at TLB reload time.
#274,v,g,n,n,m,PM_MRK_FPU0_FIN,Marked instruction FPU0 processing finished
##D0082
Floating Point Unit 0 finished a marked instruction.
#275,v,g,n,n,m,PM_MRK_FPU1_FIN,Marked instruction FPU1 processing finished
##D008A
Floating Point Unit 1 finished a marked instruction.
#276,v,g,n,n,m,PM_MRK_FPU_FIN,Marked instruction FPU processing finished
##D0030
One of the Floating Point Units finished a marked instruction. Instructions that finish may not necessary complete
#277,v,g,n,n,m,PM_MRK_FXU_FIN,Marked instruction FXU processing finished
##0001A
One of the Fixed Point Units finished a marked instruction. Instructions that finish may not necessary complete.
#278,v,g,n,n,m,PM_MRK_IFU_FIN,Marked instruction IFU processing finished
##0000A
The Instruction Fetch Unit finished a marked instruction.
#279,v,g,n,n,m,PM_MRK_INST_DISP,Marked instruction dispatched
##00010
A marked instruction was dispatched
#280,v,g,n,n,m,PM_MRK_LD_MISS_L1,Marked L1 D cache load misses
##00056
Marked L1 D cache load misses
#281,b,g,n,n,m,PM_MRK_LSU0_REJECT_L2MISS,LSU0 marked L2 miss reject
##930E4
This event never worked and was replaced by marked DERAT guess wrong
#282,v,g,n,n,m,PM_MRK_LSU0_REJECT_LHS,LSU0 marked load hit store reject
##930E6
Load Store Unit 0 rejected a marked load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully.
#283,v,g,n,n,m,PM_MRK_LSU0_REJECT_ULD,LSU0 marked unaligned load reject
##930E0
Load Store Unit 0 rejected a marked load instruction that spans a cache line boundary (128B). The LSU will pass the incremented address information to the FXU via the scratch register so that the subsequent address generation will access the next line.
#284,v,g,n,n,m,PM_MRK_LSU0_REJECT_UST,LSU0 marked unaligned store reject
##930E2
Load Store Unit 0 rejected a marked store instruction that spans a cache line boundary (128B). The LSU will pass the incremented address information to the FXU via the scratch register so that the subsequent address generation will access the next line.
#285,v,g,n,n,m,PM_MRK_LSU1_REJECT_LHS,LSU1 marked load hit store reject
##930EE
Load Store Unit 1 rejected a marked load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully.
#286,v,g,n,n,m,PM_MRK_LSU1_REJECT_ULD,LSU1 marked unaligned load reject
##930E8
Load Store Unit 1 rejected a marked load instruction that spans a cache line boundary (128B). The LSU will pass the incremented address information to the FXU via the scratch register so that the subsequent address generation will access the next line.
#287,v,g,n,n,m,PM_MRK_LSU1_REJECT_UST,LSU1 marked unaligned store reject
##930EA
Load Store Unit 1 rejected a marked store instruction that spans a cache line boundary (128B). The LSU will pass the incremented address information to the FXU via the scratch register so that the subsequent address generation will access the next line.
#288,v,g,n,n,m,PM_MRK_LSU_REJECT_UST,Marked unaligned store reject
##93034
The Load Store Unit rejected a marked store instruction that spans a cache line boundary (128B). The LSU will pass the incremented address information to the FXU via the scratch register so that the subsequent address generation will access the next line.
#289,v,g,n,n,m,PM_MRK_PTEG_FROM_DMEM,Marked PTEG loaded from distant memory
##12042
A Page Table Entry was loaded into the ERAT with data from memory attached to a distant module due to a marked load or store.
#290,v,g,n,n,m,PM_MRK_PTEG_FROM_L21,Marked PTEG loaded from private L2 other core
##12040
A Page Table Entry was loaded into the ERAT from the private L2 of the other core on this chip due to a marked load or store.
#291,v,g,n,n,m,PM_MRK_PTEG_FROM_L35_SHR,Marked PTEG loaded from L3.5 shared
##12046
A Page Table Entry was loaded into the ERAT with shared (S) data from the L3 of a chip on the same module as this processor is located, due to a marked load or store.
#292,v,g,n,n,m,PM_MRK_PTEG_FROM_RL2L3_SHR,Marked PTEG loaded from remote L2 or L3 shared
##12044
A Page Table Entry was loaded into the ERAT from memory attached to a different module than this proccessor is located on due to a marked load or store.
#293,v,g,n,n,m,PM_MRK_STCX_FAIL,Marked STCX failed
##830E4
A marked stcx (stwcx or stdcx) failed
#294,v,g,n,n,m,PM_MRK_ST_GPS,Marked store sent to GPS
##00006
A sampled store has been sent to the memory subsystem
#295,v,g,n,n,m,PM_MRK_VMX0_LD_WRBACK,Marked VMX0 load writeback valid
##60086
A marked load returned data on VMX unit 0
#296,v,g,n,n,m,PM_MRK_VMX1_LD_WRBACK,Marked VMX1 load writeback valid
##6008E
A marked load returned data on VMX unit 1
#297,v,g,n,n,m,PM_MRK_VMX_COMPLEX_ISSUED,Marked VMX instruction issued to complex
##7008C
A marked instruction was issued to the VMX Complex pipeline.
#298,v,g,n,n,m,PM_MRK_VMX_FLOAT_ISSUED,Marked VMX instruction issued to float
##70088
A marked instruction was issued to the VMX Float pipeline.
#299,v,g,n,n,m,PM_MRK_VMX_PERMUTE_ISSUED,Marked VMX instruction issued to permute
##7008E
A marked instruction was issued to the VMX Permute pipeline.
#300,v,g,n,n,m,PM_MRK_VMX_SIMPLE_ISSUED,Marked VMX instruction issued to simple
##7008A
A marked instruction was issued to the VMX Simple pipeline.
#301,v,g,n,n,m,PM_MRK_VMX_ST_ISSUED,Marked VMX store issued
##B0088
A marked VMX Store was issued
#302,v,g,n,n,n,PM_NO_ITAG_CYC,Cyles no ITAG available
##40088
Cycles when no ITAGS are available. This condition will block instruction fetch.
#303,v,g,n,n,n,PM_PMC1_OVERFLOW,PMC1 Overflow
##00014
Overflows from PMC1 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.
#304,v,g,n,n,n,PM_PTEG_FROM_DMEM,PTEG loaded from distant memory
##1304A
A Page Table Entry was loaded into the ERAT with data from memory attached to a distant module due to a demand load or store.
#305,v,g,n,n,n,PM_PTEG_FROM_L21,PTEG loaded from private L2 other core
##13048
A Page Table Entry was loaded into the ERAT from the private L2 of the other core on this chip  due to a demand load or store.
#306,v,g,n,n,n,PM_PTEG_FROM_L35_SHR,PTEG loaded from L3.5 shared
##1304E
A Page Table Entry was loaded into the ERAT with shared (S) data from the L3 of a chip on the same module as this processor is located, due to a demand load or store.
#307,v,g,n,n,n,PM_PTEG_FROM_RL2L3_SHR,PTEG loaded from remote L2 or L3 shared
##1304C
A Page Table Entry was loaded into the ERAT with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load or store.
#308,v,g,n,n,n,PM_PTEG_RELOAD_VALID,PTEG reload valid
##130E8
A Page Table Entry was loaded into the ERAT. POWER6 does not have a TLB
#309,v,g,n,n,n,PM_RUN_CYC,Run cycles
##000F4
Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
#310,v,g,n,n,n,PM_STCX,STCX executed
##830E6
STCX executed
#311,v,g,n,n,n,PM_STCX_CANCEL,stcx cancel by core
##830EC
A conditional store request to the nest was canceled by the core
#312,v,g,n,n,n,PM_STCX_FAIL,STCX failed
##830EE
A stcx (stwcx or stdcx) failed
#313,v,g,n,n,n,PM_ST_FIN,Store instructions finished
##000F0
Store requests sent to the nest.
#314,v,g,n,n,n,PM_ST_MISS_L1,L1 D cache store misses
##00054,80088
A store missed the dcache. Combined Unit 0 + 1.
#315,v,g,n,n,n,PM_ST_REF_L1,L1 D cache store references
##80086,8008E
Store references to the Data Cache. Combined Unit 0 + 1.
#316,v,g,n,n,n,PM_ST_REF_L1_BOTH,Both units L1 D cache store reference
##80038
Both Load Store Units executed store references to the Data Cache at the same time.
#317,v,g,n,c,n,PM_ST_REQ_L2,L2 store requests
##50732
L2 store requests
#318,v,g,n,n,n,PM_SUSPENDED,Suspended
##00000
The counter is suspended (does not count).
#319,v,g,n,n,n,PM_SYNC_CYC,Sync duration
##920CC
Cycles a SYNC instruction is pending. Starts counting when the request is sent to the nest until the nest responds.
#320,v,g,n,s,n,PM_THRD_GRP_CMPL_BOTH_CYC,Cycles group completed by both threads
##00018
Cycles that both threads completed.
#321,v,g,n,n,n,PM_THRD_L2MISS,Thread in L2 miss
##310A0
This thread has a L2 miss pending.
#322,v,g,n,n,n,PM_THRD_PRIO_1_CYC,Cycles thread running at priority level 1
##22040
Cycles this thread was running at priority level 1
#323,v,g,n,n,n,PM_THRD_PRIO_6_CYC,Cycles thread running at priority level 6
##22046
Cycles this thread was running at priority level 6.
#324,v,g,n,n,n,PM_THRD_PRIO_DIFF_1or2_CYC,Cycles thread priority difference is 1 or 2
##23040
Cycles when this thread's priority is higher than the other thread's priority by 1 or 2.
#325,v,g,n,n,n,PM_THRD_PRIO_DIFF_minus1or2_CYC,Cycles thread priority difference is -1 or -2
##23046
Cycles when this thread's priority is lower than the other thread's priority by 1 or 2.
#326,v,g,n,c,n,PM_THRD_SEL_T0,Decode selected thread 0
##310A6
Thread selection picked thread 0 for decode.
#327,v,g,n,n,n,PM_TLB_REF,TLB reference
##920C8
Number of Data Translation requests from the ERAT. 
#328,v,g,n,n,n,PM_VMX0_INST_ISSUED,VMX0 instruction issued
##60080
An instruction was issued to VMX unit 0
#329,v,g,n,n,n,PM_VMX0_LD_ISSUED,VMX0 load issued
##60082
A load instruction was issued to VMX unit 0
#330,v,g,n,n,n,PM_VMX0_LD_WRBACK,VMX0 load writeback valid
##60084
A load returned data on VMX unit 0
#331,v,g,n,n,n,PM_VMX0_STALL,VMX0 stall
##B0084
Cycles the VMX unit 0 was stalled
#332,v,g,n,n,n,PM_VMX1_INST_ISSUED,VMX1 instruction issued
##60088
An instruction was issued to VMX unit 1
#333,v,g,n,n,n,PM_VMX1_LD_ISSUED,VMX1 load issued
##6008A
A load instruction was issued to VMX unit 1
#334,v,g,n,n,n,PM_VMX1_LD_WRBACK,VMX1 load writeback valid
##6008C
A load returned data on VMX unit 1
#335,v,g,n,n,n,PM_VMX1_STALL,VMX1 stall
##B008C
Cycles the VMX unit 1 was stalled
#336,v,g,n,n,n,PM_VMX_COMPLEX_ISSUED,VMX instruction issued to complex
##70084
An instruction was issued to the VMX Complex pipeline.
#337,v,g,n,n,n,PM_VMX_FLOAT_ISSUED,VMX instruction issued to float
##70080
An instruction was issued to the VMX Float pipeline.
#338,v,g,n,n,n,PM_VMX_FLOAT_MULTICYCLE,VMX multi-cycle floating point instruction issued
##B0082
A multi-cycle instruction was issued to the VMX Float pipeline.
#339,v,g,n,n,n,PM_VMX_PERMUTE_ISSUED,VMX instruction issued to permute
##70086
An instruction was issued to the VMX Permute pipeline.
#340,v,g,n,n,n,PM_VMX_RESULT_SAT_0_1,VMX valid result with sat bit is set (0->1)
##B008E
An instruction finished on the VMX unit that set the saturation bit. This bit is sticky, once set to 1 it remains set to 1 until it is set to 0 by an mtvscr instruction.
#341,v,g,n,n,n,PM_VMX_RESULT_SAT_1,VMX valid result with sat=1
##B0086
An instruction finished on the VMX unit with the saturation bit on. This bit is sticky, once set to 1 it remains set to 1 until it is set to 0 by an mtvscr instruction.
#342,v,g,n,n,n,PM_VMX_SIMPLE_ISSUED,VMX instruction issued to simple
##70082
An instruction was issued to the VMX Simple pipeline.
#343,v,g,n,n,n,PM_VMX_ST_ISSUED,VMX store issued
##B0080
A VMX Store was issued
#344,v,g,n,n,n,PM_0INST_FETCH_COUNT,Periods with no instructions fetched
##40081
No instructions were fetched this periods (due to IFU hold, redirect, or icache miss)
#345,v,g,n,n,n,PM_IBUF_FULL_COUNT,Periods instruction buffer full
##40085
Number of times the Instruction Buffer was full. The Instruction Buffer is a circular queue of 64 instructions per thread, organized as 16 groups of 4 instructions.
#346,v,g,n,n,n,PM_GCT_FULL_COUNT,Periods GCT full
##40087
The Global Completion Table is completely full.
#347,v,g,n,n,n,PM_NO_ITAG_COUNT,Periods no ITAG available
##40089
Number of periods when no ITAGS are available. This condition will block instruction fetch.
#348,v,g,n,n,n,PM_INST_TABLEWALK_COUNT,Periods doing instruction tablewalks
##920CB
Number of Instruction Tablewalks
#349,v,g,n,n,n,PM_SYNC_COUNT,SYNC instructions completed
##920CD
Number of SYNC instructions executed.
#350,v,g,n,n,n,PM_RUN_COUNT,Run Periods
##000F5
Processor Periods gated by the run latch
#351,v,g,n,n,n,PM_HV_COUNT,Hypervisor Periods
##00017
Periods when the processor is executing in Hypervisor (MSR[HV] = 1 and MSR[PR]=0)
#352,v,g,n,c,n,PM_LLA_CYC,Load Look Ahead Active
##0C01E
Load Look Ahead Active. When a demand cache or ERAT miss is encountered, the processor continues dispatching instructions but inhibits the results from writing registers (i.e. the architected state of the machine is not changed), executing subsequent load instructions such that independent cache line miss requests maybe started.
#353,v,g,n,c,n,PM_NOT_LLA_CYC,Load Look Ahead not Active
##0401E
Load Look Ahead not Active
#354,v,g,n,c,n,PM_LLA_COUNT,Transitions into Load Look Ahead mode
##0C01F
Transitions into Load Look Ahead mode
#355,v,g,n,n,n,PM_DPU_HELD_COUNT,Periods DISP unit held
##00005
Dispatch unit held
#356,v,g,n,n,n,PM_DPU_HELD_POWER_COUNT,Periods DISP unit held due to Power Management
##0003D
Number of times Instruction Dispatch was held due to power management.
#357,v,g,n,n,n,PM_DPU_WT_IC_MISS_COUNT,Periods DISP unit is stalled due to I cache miss
##0000D
Number of times that Instruction Dispatch had no instructions available to dispatch because of an instruction cache misst.
#358,v,g,n,s,n,PM_GCT_EMPTY_COUNT,Periods GCT empty
##00009
Number of times the Global Completion Table was completely empty. No thread had an entry allocated.
#359,u,g,n,n,n,PM_LSU_LMQ_SRQ_EMPTY_COUNT,Periods LMQ and SRQ empty
##0001D
This thread had no entries in the Load Miss Queue and Store Request Queue (Load Store Units are idle)
#360,v,g,n,n,n,PM_DERAT_REF_64K,DERAT reference for 64K page
##82070
A data request (load or store) referenced (accessed)  the ERAT for 64K page
#361,v,g,n,n,n,PM_DERAT_MISS_64K,DERAT misses for 64K page
##92070
A data request (load or store) missed the ERAT for 64K page and resulted in an ERAT reload.
#362,v,g,n,n,n,PM_IERAT_MISS_16M,IERAT misses for 16M page
##92076
A translation request for a 16MB page missed the Instruction Effective to Real Address Translation (ERAT) table
#363,v,g,n,n,m,PM_MRK_DERAT_REF_4K,Marked DERAT reference for 4K page
##82044
A marked data request (load or store) referenced (accessed)  the ERAT for 4K page
#364,v,g,n,n,m,PM_MRK_DERAT_MISS_4K,Marked DERAT misses for 4K page
##92044
A marked data request (load or store) missed the ERAT for 4K page and resulted in an ERAT reload.

$$$$$$$$

{ counter 3 }
#0,v,g,n,n,n,PM_0INST_FETCH,No instructions fetched
##400A0
No instructions were fetched this cycles (due to IFU hold, redirect, or icache miss)
#1,v,g,n,n,n,PM_BRU_FIN,BRU produced a result
##430C6
The Branch execution unit finished an instruction
#2,v,g,n,n,n,PM_BR_MPRED_CCACHE,Branch misprediction due to count cache prediction
##4108E
A branch instruction target was incorrectly predicted by the ccount cache. This will result in a branch redirect flush if not overfidden by a flush of an older instruction.
#3,v,g,n,n,n,PM_BR_MPRED_COUNT,Branch misprediction due to count prediction
##4108A
A branch instruction count value was incorrectly predicted. This will result in a branch mispredict flush unless a flush is detected from an older instruction.
#4,v,g,n,n,n,PM_BR_MPRED_CR,Branch mispredictions due to CR bit setting
##41088
A conditional branch instruction was incorrectly predicted as taken or not taken. The branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This will result in a branch redirect flush if not overfidden by a flush of an older instruction.
#5,v,g,n,n,n,PM_BR_MPRED_TA,Branch mispredictions due to target address
##4108C
A branch instruction target was incorrectly predicted. This will result in a branch mispredict flush unless a flush is detected from an older instruction.
#6,v,g,n,n,n,PM_BR_PRED,A conditional branch was predicted
##41080
A branch prediction was made. This could have been a target prediction, a condition prediction, or both
#7,v,g,n,n,n,PM_BR_PRED_CCACHE,Branch count cache prediction
##41084
The count value of a Branch and Count instruction was predicted
#8,v,g,n,n,n,PM_BR_PRED_CR,A conditional branch was predicted, CR prediction
##41082
A conditional branch instruction was predicted as taken or not taken.
#9,v,g,n,n,n,PM_BR_PRED_LSTACK,A conditional branch was predicted, link stack
##41086
The target address of a Branch to Link instruction was predicted by the link stack.
#10,v,g,n,c,n,PM_CYC,Processor cycles
##0001E
Processor cycles
#11,v,g,n,n,n,PM_DATA_FROM_DL2L3_SHR,Data loaded from distant L2 or L3 shared
##0005C
The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a distant module due to a demand load
#12,v,g,n,n,n,PM_DATA_FROM_L25_MOD,Data loaded from L2.5 modified
##0005A
The processor's Data Cache was reloaded with modified (M) data from the L2 of a chip on the same module as this processor is located due to a demand load.
#13,v,g,n,n,n,PM_DATA_FROM_L2MISS,Data loaded missed L2
##00056
The processor's Data Cache was reloaded but not from the local L2.
#14,v,g,n,n,n,PM_DATA_FROM_L3,Data loaded from L3
##00058
The processor's Data Cache was reloaded from the local L3 due to a demand load.
#15,v,g,n,n,n,PM_DATA_FROM_L3MISS,Data loaded from private L3 miss
##000FE
The processor's Data Cache was reloaded from beyond L3 due to a demand load
#16,v,g,n,n,n,PM_DATA_FROM_RMEM,Data loaded from remote memory
##0005E
The processor's Data Cache was reloaded from memory attached to a different module than this proccessor is located on.
#17,v,g,n,n,n,PM_DATA_PTEG_1ST_HALF,Data table walk matched in first half primary PTEG
##91080
A translation request for a data address was satisfied using the primary page table hash. The matching Page Table Entry is one of the first four PTE entries of the primary PTEG
#18,v,g,n,n,n,PM_DATA_PTEG_2ND_HALF,Data table walk matched in second half primary PTEG
##91082
A translation request for a data address was satisfied using the primary page table hash. The matching Page Table Entry is one of the second four PTE entries of the primary PTEG
#19,v,g,n,n,n,PM_DATA_PTEG_SECONDARY,Data table walk matched in secondary PTEG
##91084
A translation request for a data address was satisfied using the secondary page table hash. 
#20,u,g,n,n,n,PM_DC_PREF_OUT_OF_STREAMS,D cache out of streams
##81080
A new prefetch stream was detected but no more stream entries were available.
#21,v,g,n,n,n,PM_DC_PREF_STREAM_ALLOC,D cache new prefetch stream allocated
##81082
A new Prefetch Stream was allocated.
#22,v,g,n,n,n,PM_DFU_ADD,DFU add type instruction
##E00AC
The Decimal Floating Point Unit executed an add type instruction. This could be dadd, dsub, dcmpo, or dcmpu
#23,v,g,n,n,n,PM_DFU_ADD_SHIFTED_BOTH,DFU add type with both operands shifted
##E00A8
The Decimal Floating Point Unit executed an add type instruction and both operands required shifting. This could be dadd, dsub, dcmpo, or dcmpu
#24,v,g,n,n,n,PM_DFU_BACK2BACK,DFU back to back operations executed
##E00A2
The Decimal Floating Point Unit executed two instructions back to back.
#25,v,g,n,n,n,PM_DFU_CONV,DFU convert from fixed op
##E00AE
The Decimal Floating Point Unit executed a convert from fixed point operation. This could be a dcffix or dcffixq instruction. The fixed point operand was converted to a Decimal Floating Point number
#26,v,g,n,n,n,PM_DFU_ENC_BCD_DPD,DFU Encode BCD to DPD
##E00AA
The Decimal Floating Point Unit executed an encode to fixed point operation. This could have been a denbcd or denbcdq instruction. The binary coded decimal operand is convered to a binary floating point number.
#27,v,g,n,n,n,PM_DFU_EXP_EQ,DFU operand exponents are equal for add type
##E00A4
The Decimal Floating Point Unit executed an add type instruction and the exponents of both operand are equal
#28,v,g,n,n,n,PM_DFU_FIN,DFU instruction finish
##E00A0
The Decimal Floating Point Unit finished an operation.
#29,v,g,n,n,n,PM_DFU_SUBNORM,DFU result is a subnormal
##E00A6
The result of a Decimal Floating Point operation was subnormal.
#30,v,g,n,n,n,PM_DPU_HELD_COMPLETION,DISP unit held due to completion holding dispatch 
##2108C
Cycles that Instruction Dispatch was held because of the completion unit. More than one hold condition can exist at the same time
#31,v,g,n,n,n,PM_DPU_HELD_CR_LOGICAL,DISP unit held due to CR, LR or CTR updated by CR logical, MTCRF, MTLR or MTCTR
##300AE
Cycles that Instruction Dispatch was held because the CR, LR, or CTR SPRs were being updated by a CR logical, MTCRF, MTLR or MTCTR instruction. More than one hold condition can exist at the same time
#32,v,g,n,n,n,PM_DPU_HELD_CW,DISP unit held due to cache writes 
##200A4
Cycles that Load Store Unit is performing a cache write. The LSU blocks dispatch to avoid contention for the cache during a write. More than one hold condition can exist at the same time
#33,v,g,n,n,n,PM_DPU_HELD_FPQ,DISP unit held due to FPU issue queue full
##200A6
Cycles that Instruction Dispatch was held because the Floating Point Issue Queue was full. More than one hold condition can exist at the same time
#34,v,g,n,n,n,PM_DPU_HELD_FPU_CR,DISP unit held due to FPU updating CR
##21080
Cycles that Instruction Dispatch was held because a Floating Point operation was updating a condition register. Younger instruction are blocked to avoid Write after Write conflicts. More than one hold condition can exist at the same time
#35,v,g,n,n,n,PM_DPU_HELD_FP_FX_MULT,DISP unit held due to non fixed multiple/divide after fixed multiply/divide
##21088
Cycles that Instruction Dispatch was held due to fixed point multiply/divides. After dispatching a FXU Multiply/Divide instruction, the dispatcher must block all non FXU/Divide instruction from dispatch (same thread)  More than one hold condition can exist at the same time
#36,v,g,n,n,n,PM_DPU_HELD_FXU_MULTI,DISP unit held due to FXU multicycle
##21086
Cycles that Instruction Dispatch was held due to multi-cycle fixed operation. More than one hold condition can exist at the same time
#37,v,g,n,n,n,PM_DPU_HELD_FXU_SOPS,DISP unit held due to FXU slow ops (mtmsr, scv, rfscv)
##300A8
Cycles that Instruction Dispatch was held due to a slow operation executing on a fixed point unit. Instructions such as mtmsr, scv, rfscv require that dispatch be held until all units are idle. More than one hold condition can exist at the same time
#38,v,g,n,n,n,PM_DPU_HELD_GPR,DISP unit held due to GPR dependencies
##200A0
Cycles that Instruction Dispatch was held due to a GPR dependency. The dependent instruction is held until the GPR is written. More than one hold condition can exist at the same time
#39,v,g,n,n,n,PM_DPU_HELD_INT,DISP unit held due to exception
##31088
Cycles that Instruction Dispatch was held due to an exception. Dispatch is  held until all units are idle. More than one hold condition can exist at the same time
#40,v,g,n,n,n,PM_DPU_HELD_ISYNC,DISP unit held due to ISYNC 
##200AA
Cycles that Instruction Dispatch was held due to an isync instruction. If an previous instruction requires a context serializing instruction (CSI), dispatch will be held until the FPU is empty and a completion flush has been received. More than one hold condition can exist at the same time
#41,v,g,n,n,n,PM_DPU_HELD_ITLB_ISLB,DISP unit held due to SLB or TLB invalidates 
##21084
Cycles that Instruction Dispatch was held due to a islb or itlb instruction. Dispatch is held for three cycles after an islb or itlb instruction is dispatched. More than one hold condition can exist at the same time
#42,v,g,n,n,n,PM_DPU_HELD_LLA_END,DISP unit held due to load look ahead ended
##300A4
Cycles that Instruction Dispatch was held due to load look ahead ending. More than one hold condition can exist at the same time
#43,v,g,n,n,n,PM_DPU_HELD_LSU,DISP unit held due to LSU move or invalidate SLB and SR
##21082
Cycles that Instruction Dispatch was held due to a move to or invalidate of the Segment Lookaside Buffer. Dispatch is held until all units are idle. More than one hold condition can exist at the same time
#44,v,g,n,n,n,PM_DPU_HELD_LSU_SOPS,DISP unit held due to LSU slow ops (sync, tlbie, stcx)
##300A0
Cycles that Instruction Dispatch was held due to a slow operation executing on a Load Store Unit. Instructions such as sync, tlbie, stcx require that dispatch be held until all units are idle. More than one hold condition can exist at the same time
#45,v,g,n,n,n,PM_DPU_HELD_MULT_GPR,DISP unit held due to multiple/divide multiply/divide GPR dependencies
##2108A
Cycles that Instruction Dispatch was held due to a GPR dependency caused by a fixed point multiple or divide that is dependent on the results of another fixed point multiple or divide. More than one hold condition can exist at the same time
#46,v,g,n,n,n,PM_DPU_HELD_RESTART,DISP unit held after restart coming
##300A6
Cycles that Instruction Dispatch was held waiting on a restart signal from the LSU. Dispatch has dispatched all available instructions in load look ahead mode and is waiting for the demand load to be returned. 
#47,v,g,n,n,n,PM_DPU_HELD_RU_WQ,DISP unit held due to RU FXU write queue full
##200AE
Cycles that Instruction Dispatch was held because the recovery unit's fixed point write cycle was full. More than one hold condition can exist at the same time
#48,v,g,n,n,n,PM_DPU_HELD_SMT,DISP unit held due to SMT conflicts 
##200A2
Cycles that Instruction Dispatch was held due to conflicts with the other thread. There are not enough execution units available to dispatch. More than one hold condition can exist at the same time
#49,v,g,n,n,n,PM_DPU_HELD_SPR,DISP unit held due to MTSPR/MFSPR
##300AC
Cycles that Instruction Dispatch was held because of a move to or move from SPR instruction. More than one hold condition can exist at the same time
#50,v,g,n,n,n,PM_DPU_HELD_STCX_CR,DISP unit held due to STCX updating CR 
##200AC
Cycles that Instruction Dispatch was held due to a stcx instruction updating the CR. Instructions dependant on the CR are held until the stcx finishes. This hold condition is a subset of LSO Slow Operations. More than one hold condition can exist at the same time
#51,v,g,n,n,n,PM_DPU_HELD_THRD_PRIO,DISP unit held due to lower priority thread
##300AA
Cycles that Instruction Dispatch was held due to a lower priority thread. More than one hold condition can exist at the same time
#52,v,g,n,n,n,PM_DPU_HELD_XER,DISP unit held due to XER dependency
##200A8
Cycles that Instruction Dispatch was held due to a XER dependency. More than one hold condition can exist at the same time
#53,v,g,n,n,n,PM_DPU_HELD_XTHRD,DISP unit held due to cross thread resource conflicts
##300A2
Cycles that Instruction Dispatch was held due to a resource conflict with the other thread. This could be caused by a mtspr, mfspr, or a multi-cycle fixed point operation. More than one hold condition can exist at the same time
#54,v,g,n,n,n,PM_DPU_WT,Cycles DISP unit is stalled waiting for instructions
##00004
Cycles that Instruction Dispatch had no instructions available to dispatch and was not held for any reason.
#55,v,g,n,n,n,PM_DSLB_MISS,Data SLB misses
##830C8
A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve
#56,u,g,n,n,n,PM_EE_OFF_EXT_INT,Cycles MSR(EE) bit off and external interrupt pending
##230CE
Cycles when an interrupt due to an external exception is pending but external exceptions were masked.
#57,v,g,n,n,n,PM_EXT_INT,External interrupts
##00010
An interrupt due to an external exception occurred
#58,v,g,n,c,n,PM_FAB_ADDR_COLLISION,local node launch collision with off-node address   
##501AE
A command from the local node hadd an address collision with a command for a system address. The local node competes with system pump addresses from remote nodes for address slots, this event is an indication of how badly local requests are affected by system wide requests
#59,v,g,n,c,n,PM_FAB_DCLAIM,Dclaim operation, locally mastered
##501A4
A DCLAIM command was issued. Each chip reports its own counts. The signal is delivered at FBC speed and the count must be scaled accordingly.
#60,v,g,n,c,n,PM_FAB_DMA,DMA operation, locally mastered
##501AC
A DMA operation was issued. Each chip reports its own counts. The signal is delivered at FBC speed and the count must be scaled accordingly.
#61,v,g,n,c,n,PM_FAB_MMIO,MMIO operation, locally mastered
##501A6
A MMIO operation was issued. Each chip reports its own counts. The signal is delivered at FBC speed and the count must be scaled accordingly.
#62,v,g,n,c,n,PM_FAB_NODE_PUMP,Node pump operation, locally mastered
##501A8
A request from this chip was send out on the XYZ (intra-node) link. Each chip reports its own counts. The signal is delivered at FBC speed and the count must be scaled accordingly.
#63,v,g,n,c,n,PM_FAB_RETRY_NODE_PUMP,Retry of a node pump, locally mastered
##501AA
A snoop operation for a node pump address originated from a master on this chip and the result was a retry.
#64,v,g,n,c,n,PM_FAB_RETRY_SYS_PUMP,Retry of a system pump, locally mastered  
##501A2
A snoop operation for a system pump address originated from a master on this chip and the result was a retry.
#65,v,g,n,c,n,PM_FAB_SYS_PUMP,System pump operation, locally mastered
##501A0
An request from this chip was send out on the AB (inter-node) link. Each chip reports its own counts. The signal is delivered at FBC speed and the count must be scaled accordingly.
#66,v,g,n,n,n,PM_FLUSH_ASYNC,Flush caused by asynchronous exception
##220EA
A flush was caused by an asyncronous exception. 
#67,v,g,n,n,n,PM_FLUSH_FPU,Flush caused by FPU exception
##230CC
A flush was caused by a floating point exception.
#68,v,g,n,n,n,PM_FLUSH_FXU,Flush caused by FXU exception
##230CA
A flush was caused by a fixed point exception.
#69,v,g,n,n,n,PM_FPU0_1FLOP,FPU0 executed add, mult, sub, cmp or sel instruction
##C00A0
The floating point unit has executed an add, mult, sub, compare, fsel, fneg, fabs, fnabs, fres, or frsqrte kind of instruction. These are single FLOP operations.
#70,v,g,n,n,n,PM_FPU0_DENORM,FPU0 received denormalized data
##C1082
FPU0 has encountered a denormalized operand. 
#71,v,g,n,n,n,PM_FPU0_FCONV,FPU0 executed FCONV instruction
##D1080
FPU0 has executed a convert kind of instruction. This could be fcfid* or fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.
#72,v,g,n,n,n,PM_FPU0_FEST,FPU0 executed FEST instruction
##D1086
FPU0 has executed an estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. 
#73,v,g,n,n,n,PM_FPU0_FIN,FPU0 produced a result
##D00A0
FPU0 finished, produced a result. This only indicates finish,  not completion. Floating Point Stores are included in this count but not Floating Point Loads.
#74,v,g,n,n,n,PM_FPU0_FLOP,FPU0 executed 1FLOP, FMA, FSQRT or FDIV instruction
##C00A6
FPU0 has executed a one flop, multiply-add, square root, or divide kind of instruction.
#75,v,g,n,n,n,PM_FPU0_FMA,FPU0 executed multiply-add instruction
##C00A2
FPU0 has executed a multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.
#76,v,g,n,n,n,PM_FPU0_FPSCR,FPU0 executed FPSCR instruction
##D00A4
FPU0 has executed FPSCR move related instruction. This could be mtfsfi*, mtfsb0*, mtfsb1*, mffs*, mtfsf*, mcrsf* where XYZ* means XYZ, XYZs, XYZ., XYZs.
#77,v,g,n,n,n,PM_FPU0_FRSP,FPU0 executed FRSP instruction
##D1082
FPU0 has executed a frsp kind of instruction. This could be frsp* where XYZ* means XYZ, XYZs, XYZ., XYZs.
#78,v,g,n,n,n,PM_FPU0_FSQRT_FDIV,FPU0 executed FSQRT or FDIV instruction
##C00A4
FPU0 has executed a square root or divide instruction. This could be fsqrt* or fdiv* where XYZ* means XYZ, XYZs, XYZ., XYZs
#79,v,g,n,n,n,PM_FPU0_FXDIV,FPU0 executed fixed point division
##C1080
FPU0 has executed a fixed point divide instruction.
#80,v,g,n,n,n,PM_FPU0_FXMULT,FPU0 executed fixed point multiplication
##D00A6
FPU0 has executed a fixed point multiply instruction.
#81,v,g,n,n,n,PM_FPU0_SINGLE,FPU0 executed single precision instruction
##C1086
FPU0 has executed a single precision instruction.
#82,v,g,n,n,n,PM_FPU0_STF,FPU0 executed store instruction
##C1084
FPU0 has executed a Floating Point Store instruction.
#83,v,g,n,n,n,PM_FPU0_ST_FOLDED,FPU0 folded store
##D1084
FPU0 executed a store that was dependant on the result of a previous instruction. The result it folded into the store allowing the store to execute earlier.
#84,v,g,n,n,n,PM_FPU1_1FLOP,FPU1 executed add, mult, sub, cmp or sel instruction
##C00A8
FPU1 has executed an add, mult, sub, compare, fsel, fneg, fabs, fnabs, fres, or frsqrte kind of instruction. These are single FLOP operations.
#85,v,g,n,n,n,PM_FPU1_DENORM,FPU1 received denormalized data
##C108A
FPU1 has encountered a denormalized operand.
#86,v,g,n,n,n,PM_FPU1_FCONV,FPU1 executed FCONV instruction
##D1088
FPU1 has executed a convert kind of instruction. This could be fcfid* or fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.
#87,v,g,n,n,n,PM_FPU1_FEST,FPU1 executed FEST instruction
##D108E
FPU1 has executed an estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ.
#88,v,g,n,n,n,PM_FPU1_FIN,FPU1 produced a result
##D00A8
FPU1 finished, produced a result. This only indicates finish,  not completion. Floating Point Stores are included in this count but not Floating Point Loads. 
#89,v,g,n,n,n,PM_FPU1_FLOP,FPU1 executed 1FLOP, FMA, FSQRT or FDIV instruction
##C00AE
FPU1 has executed a one flop, multiply-add, square root, or divide kind of instruction.
#90,v,g,n,n,n,PM_FPU1_FMA,FPU1 executed multiply-add instruction
##C00AA
FPU1 has executed a multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.
#91,v,g,n,n,n,PM_FPU1_FPSCR,FPU1 executed FPSCR instruction
##D00AC
FPU1 has executed FPSCR move related instruction. This could be mtfsfi*, mtfsb0*, mtfsb1*, mffs*, mtfsf*, mcrsf* where XYZ* means XYZ, XYZs, XYZ., XYZs.
#92,v,g,n,n,n,PM_FPU1_FRSP,FPU1 executed FRSP instruction
##D108A
FPU1 has executed a frsp kind of instruction. This could be frsp* where XYZ* means XYZ, XYZs, XYZ., XYZs.
#93,v,g,n,n,n,PM_FPU1_FSQRT_FDIV,FPU1 executed FSQRT or FDIV instruction
##C00AC
FPU1 has executed a square root or divide instruction. This could be fsqrt* or fdiv* where XYZ* means XYZ, XYZs, XYZ., XYZs
#94,v,g,n,n,n,PM_FPU1_FXDIV,FPU1 executed fixed point division
##C1088
FPU1 has executed a fixed point divide instruction.
#95,v,g,n,n,n,PM_FPU1_FXMULT,FPU1 executed fixed point multiplication
##D00AE
FPU1 has executed a fixed point multiply instruction.
#96,v,g,n,n,n,PM_FPU1_SINGLE,FPU1 executed single precision instruction
##C108E
FPU1 has executed a single precision instruction.
#97,v,g,n,n,n,PM_FPU1_STF,FPU1 executed store instruction
##C108C
FPU1 has executed a Floating Point Store instruction.
#98,v,g,n,n,n,PM_FPU1_ST_FOLDED,FPU1 folded store
##D108C
FPU1 executed a store that was dependant on the result of a previous instruction. The result it folded into the store allowing the store to execute earlier.
#99,v,g,n,n,n,PM_FPU_DENORM,FPU received denormalized data
##C1032
The floating point unit has encountered a denormalized operand. Combined Unit 0 + Unit 1.
#100,v,g,n,n,n,PM_FPU_FPSCR,FPU executed FPSCR instruction
##D0034
The floating point unit has executed a FPSCR move related instruction. This could be mtfsfi*, mtfsb0*, mtfsb1*, mffs*, mtfsf*, mcrsf* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1.
#101,v,g,n,n,n,PM_FPU_FRSP,FPU executed FRSP instruction
##D1032
The floating point unit has executed a frsp or convert kind of instruction. This could be frsp*  where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1.
#102,v,g,n,n,n,PM_FPU_FSQRT_FDIV,FPU executed FSQRT or FDIV instruction
##C0034
The floating point unit has executed a square root or divide instruction. This could be fsqrt* or fdiv* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1.
#103,v,g,n,n,n,PM_FPU_ISSUE_0,FPU issue 0 per cycle
##320E6
Cycles when no instructions were issued to the floating point units.
#104,v,g,n,n,n,PM_FPU_ISSUE_1,FPU issue 1 per cycle
##320E8
Cycles when one instruction was issued to the floating point units.
#105,v,g,n,n,n,PM_FPU_ISSUE_2,FPU issue 2 per cycle
##320EA
Cycles when two instruction were issued to the floating point units.
#106,v,g,n,n,n,PM_FPU_ISSUE_DIV_SQRT_OVERLAP,FPU divide/sqrt overlapped with other divide/sqrt
##320EC
The floating point unit was issued a divide or square root instruction that overlapped execution with another divide or square root instruction. These instructions are not pipelined but they can execute in parallel on separate units.
#107,v,g,n,n,n,PM_FPU_ISSUE_OOO,FPU issue out-of-order
##320E0
Instructions were issued to the floating point unit of of order with respect to program order. The floating point unit has limited ability to execute instructions out of order.
#108,v,g,n,n,n,PM_FPU_ISSUE_STALL_FPR,FPU issue stalled due to FPR dependencies
##330C2
Instruction issue to the floating point unit was stalled waiting on the results of a previous instruction.
#109,v,g,n,n,n,PM_FPU_ISSUE_STALL_ST,FPU issue stalled due to store
##320EE
Instruction issue to the floating point unit was stalled due to store. Only one store per cycle can be issued to the floating point unit.
#110,v,g,n,n,n,PM_FPU_ISSUE_STALL_THRD,FPU issue stalled due to thread resource conflict
##330C0
Instruction issue to the floating point unit was stalled because a critical resource was in use by the other thread.
#111,v,g,n,n,n,PM_FPU_ISSUE_STEERING,FPU issue steering
##320E4
An instruction was steered to a specific execution unit at issue time. Some instructions are limited to execution on a specific unit. The issue logic will attempt to steer dependent floating-point instructions to the unit that is producing the result it is dependent upon.
#112,v,g,n,n,n,PM_FPU_ISSUE_ST_FOLDED,FPU issue a folded store
##320E2
A store was issued to the floating point unit that was dependant on the result of a previous instruction. The result it folded into the store allowing the store to execute earlier.
#113,v,g,n,n,n,PM_FPU_STF,FPU executed store instruction
##C1030
FPU is executing a store instruction. Combined Unit 0 + Unit 1
#114,v,g,n,n,n,PM_FPU_ST_FOLDED,FPU folded store
##D1030
The floating point unit executed a store that was dependant on the result of a previous instruction. The result it folded into the store allowing the store to execute earlier. Combined Unit 0 + Unit 1.
#115,v,g,n,s,n,PM_FREQ_DOWN,Frequency is being slewed down due to Power Management
##0003C
Processor frequency was slowed down due to power management
#116,u,g,n,n,n,PM_FXU0_BUSY_FXU1_IDLE,FXU0 busy FXU1 idle
##00050
FXU0 is busy while FXU1 was idle
#117,v,g,n,n,n,PM_FXU0_FIN,FXU0 produced a result
##00016
The Fixed Point unit 0 finished an instruction and produced a result. Instructions that finish may not necessary complete.
#118,v,g,n,n,n,PM_FXU_PIPELINED_MULT_DIV,Fix point multiply/divide pipelined
##2108E
A fixed point multiple or divide was dispatched while another one was in progress. A sequence of fixed point multiplies or divides can be pipelined, one every other cycle, but any other instruction will stall until the multiply or divide  instructions are finished.
#119,v,g,n,n,n,PM_GCT_FULL_CYC,Cycles GCT full
##400A6
The Global Completion Table is completely full.
#120,v,g,n,c,n,PM_GXI_ADDR_CYC_BUSY,Inbound GX address utilization (# of cycle address is in valid)
##503A8
Number of bus cycles the inbound GX bus is receiving an address. The signal is delivered at GX Controller speed and the count must be scaled accordingly
#121,v,g,n,c,n,PM_GXI_CYC_BUSY,Inbound GX bus utilizations (# of cycles in use)
##503A6
Number of bus cycles the inbound GX bus is in use. The signal is delivered at GX Controller speed and the count must be scaled accordingly
#122,v,g,n,c,n,PM_GXI_DATA_CYC_BUSY,Inbound GX Data utilization (# of cycle data in is valid)
##503AA
Number of bus cycles the inbound GX bus is receiving data. The signal is delivered at GX Controller speed and the count must be scaled accordingly
#123,v,g,n,c,n,PM_GXO_ADDR_CYC_BUSY,Outbound GX address utilization (# of cycles address out is valid)
##503A2
Number of bus cycles the outbound GX bus is receiving an address. The signal is delivered at GX Controller speed and the count must be scaled accordingly
#124,v,g,n,c,n,PM_GXO_CYC_BUSY,Outbound GX bus utilizations (# of cycles in use)
##503A0
Number of bus cycles the outbound GX bus is in use. The signal is delivered at GX Controller speed and the count must be scaled accordingly
#125,v,g,n,c,n,PM_GXO_DATA_CYC_BUSY,Outbound GX Data utilization (# of cycles data out is valid)
##503A4
Number of bus cycles the outbound GX bus is receiving data. The signal is delivered at GX Controller speed and the count must be scaled accordingly
#126,v,g,n,c,n,PM_GX_DMA_READ,DMA Read Request
##503AC
The GX Bus Controller processed a DMA read request. The signal is delivered at GX Controller speed and the count must be scaled accordingly
#127,v,g,n,c,n,PM_GX_DMA_WRITE,All DMA Write Requests (including dma wrt lgcy)
##503AE
The GX Bus Controller processed a DMA write request. The signal is delivered at GX Controller speed and the count must be scaled accordingly
#128,v,g,n,n,n,PM_IBUF_FULL_CYC,Cycles instruction buffer full
##400A4
Cycles with the Instruction Buffer was full. The Instruction Buffer is a circular queue of 64 instructions per thread, organized as 16 groups of 4 instructions.
#129,v,g,n,n,n,PM_IC_DEMAND_L2_BHT_REDIRECT,L2 I cache demand request due to BHT redirect
##420EA
A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (CR mispredict).
#130,v,g,n,n,n,PM_IC_DEMAND_L2_BR_REDIRECT,L2 I cache demand request due to branch redirect
##420EC
A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (either ALL mispredicted or Target).
#131,v,g,n,c,n,PM_IC_INV_L2,L1 I cache entries invalidated from L2
##50634
L1 I cache entries invalidated from L2
#132,v,g,n,n,n,PM_IC_PREF_REQ,Instruction prefetch requests
##400AC
An instruction prefetch request has been made.
#133,v,g,n,n,n,PM_IC_PREF_WRITE,Instruction prefetch written into I cache
##430C0
Number of Instruction Cache entries written because of prefetch. Prefetch entries are marked least recently used and are candidates for eviction if they are not needed to satify a demand fetch.
#134,v,g,n,n,n,PM_IC_RELOAD_SHR,I cache line reloading to be shared by threads
##400AE
An Instruction Cache request was made by this thread and the cache line was already in the cache for the other thread. The line is marked valid for both threads.
#135,v,g,n,n,n,PM_IC_REQ,I cache demand of prefetch request
##400AA
An instruction fetch request was made. The request may have been a prefetch request or a demand request.
#136,v,g,n,n,n,PM_IERAT_MISS,IERAT miss count
##420EE
A translation request missed the Instruction Effective to Real Address Translation (ERAT) table
#137,v,g,n,n,n,PM_IFU_FIN,IFU finished an instruction
##430C4
The Instruction Fetch Unit finished an instruction
#138,v,g,n,n,n,PM_INST_CMPL,Instructions completed
##00002
Number of PPC instructions completed. 
#139,v,g,n,n,n,PM_INST_DISP,Instructions dispatched
##00012,000F2
Number of PowerPC instructions successfully dispatched.
#140,v,g,n,n,n,PM_INST_DISP_LLA,Instruction dispatched under load look ahead
##31082
Instructions dispatched while Load Look ahead is active.
#141,v,g,n,n,n,PM_INST_FETCH_CYC,Cycles at least 1 instruction fetched
##420E8
Cycles when at least one instruction was sent from the fetch unit to the decode unit.
#142,v,g,n,n,n,PM_INST_FROM_DL2L3_SHR,Instruction fetched from distant L2 or L3 shared
##42044
An instruction fetch group was fetched with shared  (S) data from the L2 or L3 on a distant module. Fetch groups can contain up to 8 instructions
#143,v,g,n,n,n,PM_INST_FROM_L1,Instruction fetched from L1
##400A2
An instruction fetch group was fetched from L1. Fetch Groups can contain up to 8 instructions
#144,v,g,n,n,n,PM_INST_FROM_L25_MOD,Instruction fetched from L2.5 modified
##42046
An instruction fetch group was fetched with modified (M) data from the L2 of a chip on the same module as this processor is located. Fetch groups can contain up to 8 instructions.
#145,v,g,n,n,n,PM_INST_FROM_L3,Instruction fetched from L3
##42040
An instruction fetch group was fetched from L3. Fetch Groups can contain up to 8 instructions
#146,v,g,n,n,n,PM_INST_FROM_L3MISS,Instruction fetched missed L3
##42054
An instruction fetch group was fetched from beyond L3. Fetch groups can contain up to 8 instructions.
#147,v,g,n,n,n,PM_INST_FROM_RMEM,Instruction fetched from remote memory
##42042
An instruction fetch group was fetched from memory attached to a different module than this proccessor is located on. Fetch groups can contain up to 8 instructions
#148,v,g,n,n,n,PM_INST_PTEG_1ST_HALF,Instruction table walk matched in first half primary PTEG
##91088
A translation request for a instruction address was satisfied using the primary page table hash. The matching Page Table Entry is one of the first four PTE entries of the primary PTEG
#149,v,g,n,n,n,PM_INST_PTEG_2ND_HALF,Instruction table walk matched in second half primary PTEG
##9108A
A translation request for a instruction address was satisfied using the primary page table hash. The matching Page Table Entry is one of the second four PTE entries of the primary PTEG
#150,v,g,n,n,n,PM_INST_PTEG_SECONDARY,Instruction table walk matched in secondary PTEG
##9108C
A translation request for a instruction address was satisfied using the secondary page table hash. 
#151,v,g,n,n,n,PM_INST_TABLEWALK_CYC,Cycles doing instruction tablewalks
##920EA
Cycles an Instruction Tablewalk is active. 
#152,u,g,n,n,n,PM_ISLB_MISS,Instruction SLB misses
##830C0
A SLB miss for an instruction fetch as occurred
#153,v,g,n,n,n,PM_ITLB_REF,Instruction TLB reference
##920E2
Number of Instruction Translation requests from the ERAT. 
#154,v,g,n,n,n,PM_L1_DCACHE_RELOAD_VALID,L1 reload data source valid
##000F6
The data source information is valid,the data cache has been reloaded. Prior to POWER5+ this included data cache reloads due to prefetch activity. With POWER5+ this now only includes reloads due to demand loads.
#155,v,g,n,n,n,PM_L1_PREF,L1 cache data prefetches
##81084
A request to prefetch data into the L1 was made
#156,v,g,n,n,n,PM_L1_WRITE_CYC,Cycles writing to instruction L1
##430C2
Cycles that a cache line was written to the instruction cache.
#157,v,g,n,c,n,PM_L2SA_CASTOUT_MOD,L2 slice A castouts - Modified
##506A0
An L2 line in the Modified state was castout. Reported per slice.
#158,v,g,n,c,n,PM_L2SA_CASTOUT_SHR,L2 slice A castouts - Shared
##506A2
An L2 line in the Shared state was castout. Reported per slice.
#159,v,g,n,c,n,PM_L2SA_DC_INV,L2 slice A D cache invalidate
##506A6
The L2 invalidated a line in processor's data cache. This is caused by the L2 line being cast out or invalidated. Reported per slice.
#160,v,g,n,c,n,PM_L2SA_IC_INV,L2 slice A I cache invalidate
##506A4
The L2 invalidated a line in processor's instruction cache. This is caused by the L2 line being cast out or invalidated. Reported per slice.
#161,v,g,n,c,n,PM_L2SA_LD_HIT,L2 slice A load hits
##507A2
A load request (data or instruction) hit in the L2 directory. Includes speculative, prefetched, and demand requests. This event includes all requests to this L2 from all sources. Reported per slice.
#162,v,g,n,n,n,PM_L2SA_LD_MISS_DATA,L2 slice A data load misses
##504A2
A data load request from this thread hit in the L2 directory. Includes speculative, prefetched, and demand requests. Reported per slice.
#163,v,g,n,n,n,PM_L2SA_LD_MISS_INST,L2 slice A instruction load misses
##505A2
An instruction load request from this thread hit in the L2 directory. Includes speculative, prefetched, and demand requests. Reported per slice.
#164,v,g,n,c,n,PM_L2SA_LD_REQ,L2 slice A load requests 
##507A0
A load request (data or instruction) was received by the L2 directory. Includes speculative, prefetched, and demand requests. This event includes all requests to this L2 from all sources. Reported per slice.
#165,v,g,n,n,n,PM_L2SA_LD_REQ_DATA,L2 slice A data load requests
##504A0
A data load request from this thread was received by the L2 directory. Includes speculative, prefetched, and demand requests. Reported per slice.
#166,v,g,n,n,n,PM_L2SA_LD_REQ_INST,L2 slice A instruction load requests
##505A0
An instruction load request from this thread was received by the L2 directory. Includes speculative, prefetched, and demand requests. Reported per slice.
#167,v,g,n,n,n,PM_L2SA_MISS,L2 slice A misses
##505A4
Total L2 misses (loads and stores) from this thread. Includes speculative, prefetched, and demand requests. Reported per slice.
#168,v,g,n,c,n,PM_L2SA_ST_HIT,L2 slice A store hits
##507A6
A store request hit in the L2 directory. This event includes all requests to this L2 from all sources. Reported per slice.
#169,v,g,n,n,n,PM_L2SA_ST_MISS,L2 slice A store misses
##504A6
A store request from this thread missed in the L2 directory. Reported per slice.
#170,v,g,n,n,n,PM_L2SA_ST_REQ,L2 slice A store requests
##504A4,507A4
A store request  was received by the L2 directory. This event includes all requests to this L2 from all sources. Stores are counted after gathering in the L2 store queues. Reported per slice.
#171,v,g,n,c,n,PM_L2SB_CASTOUT_MOD,L2 slice B castouts - Modified
##506A8
An L2 line in the Modified state was castout. Reported per slice.
#172,v,g,n,c,n,PM_L2SB_CASTOUT_SHR,L2 slice B castouts - Shared
##506AA
An L2 line in the Shared state was castout. Reported per slice.
#173,v,g,n,c,n,PM_L2SB_DC_INV,L2 slice B D cache invalidate
##506AE
The L2 invalidated a line in processor's data cache. This is caused by the L2 line being cast out or invalidated. Reported per slice.
#174,v,g,n,c,n,PM_L2SB_IC_INV,L2 slice B I cache invalidate
##506AC
The L2 invalidated a line in processor's instruction cache. This is caused by the L2 line being cast out or invalidated. Reported per slice.
#175,v,g,n,c,n,PM_L2SB_LD_HIT,L2 slice B load hits
##507AA
A load request (data or instruction) hit in the L2 directory. Includes speculative, prefetched, and demand requests. This event includes all requests to this L2 from all sources. Reported per slice.
#176,v,g,n,n,n,PM_L2SB_LD_MISS_DATA,L2 slice B data load misses
##504AA
A data load request from this thread hit in the L2 directory. Includes speculative, prefetched, and demand requests. Reported per slice.
#177,v,g,n,n,n,PM_L2SB_LD_MISS_INST,L2 slice B instruction load misses
##505AA
An instruction load request from this thread hit in the L2 directory. Includes speculative, prefetched, and demand requests. Reported per slice.
#178,v,g,n,c,n,PM_L2SB_LD_REQ,L2 slice B load requests 
##507A8
A load request (data or instruction) was received by the L2 directory. Includes speculative, prefetched, and demand requests. This event includes all requests to this L2 from all sources. Reported per slice.
#179,v,g,n,n,n,PM_L2SB_LD_REQ_DATA,L2 slice B data load requests
##504A8
A data load request from this thread was received by the L2 directory. Includes speculative, prefetched, and demand requests. Reported per slice.
#180,v,g,n,n,n,PM_L2SB_LD_REQ_INST,L2 slice B instruction load requests
##505A8
An instruction load request from this thread was received by the L2 directory. Includes speculative, prefetched, and demand requests. Reported per slice.
#181,v,g,n,n,n,PM_L2SB_MISS,L2 slice B misses
##505AC
Total L2 misses (loads and stores) from this thread. Includes speculative, prefetched, and demand requests. Reported per slice.
#182,v,g,n,c,n,PM_L2SB_ST_HIT,L2 slice B store hits
##507AE
A store request hit in the L2 directory. This event includes all requests to this L2 from all sources. Reported per slice.
#183,v,g,n,n,n,PM_L2SB_ST_MISS,L2 slice B store misses
##504AE
A store request from this thread missed in the L2 directory. Reported per slice.
#184,v,g,n,n,n,PM_L2SB_ST_REQ,L2 slice B store requests
##504AC,507AC
A store request  was received by the L2 directory. This event includes all requests to this L2 from all sources. Stores are counted after gathering in the L2 store queues. Reported per slice.
#185,v,g,n,n,n,PM_L2_MISS,L2 cache misses
##50534
Total L2 misses (loads and stores) from this thread. Includes speculative, prefetched, and demand requests. Total for all slices.
#186,v,g,n,n,n,PM_L2_PREF_LD,L2 cache prefetches
##81086
A request to prefetch load data into L2 was made
#187,v,g,n,n,n,PM_L2_PREF_ST,L2 cache prefetches
##81088
A request to prefetch the target of a store into L2 was made
#188,v,g,n,n,n,PM_L2_ST_REQ_DATA,L2 data store requests
##50434
A store request  from this thread was received by the L2 directory. Stores are counted after gathering in the L2 store queues. Reported per slice.
#189,v,g,n,c,n,PM_L3SA_HIT,L3 slice A hits
##500A2
Number of attempts made by this chip cores that resulted in an L3 hit. Reported per L3 slice
#190,v,g,n,c,n,PM_L3SA_MISS,L3 slice A misses
##50034,500A4
Number of attempts made by this chip cores that resulted in an L3 miss. Reported per L3 slice
#191,v,g,n,c,n,PM_L3SA_REF,L3 slice A references
##500A0
Number of attempts made by this chip cores to find data in the L3. Reported per L3 slice 
#192,v,g,n,c,n,PM_L3SB_HIT,L3 slice B hits
##500AA
Number of attempts made by this chip cores that resulted in an L3 hit. Reported per L3 slice
#193,v,g,n,n,n,PM_L3SB_MISS,L3 slice B misses
##500AC
Number of attempts made by this chip cores that resulted in an L3 miss. Reported per L3 slice
#194,v,g,n,c,n,PM_L3SB_REF,L3 slice B references
##500A8
Number of attempts made by this chip cores to find data in the L3. Reported per L3 slice 
#195,v,g,n,n,n,PM_LARX,Larx executed
##830CA
A larx (lwarx or ldarx) was sent to the nest
#196,v,g,n,n,n,PM_LARX_L1HIT,larx hits in L1
##830C2
A larxa was sent to the nest
#197,v,g,n,n,n,PM_LD_MISS_L1,L1 D cache load misses
##0000C,800A0
Load references that miss the Level 1 Data cache. Combined unit 0 + 1.
#198,v,g,n,n,n,PM_LD_REF_L1,L1 D cache load references
##800A2,800AA
Load references to the Level 1 Data Cache. Combined unit 0 + 1.
#199,v,g,n,n,n,PM_LSU0_DERAT_MISS,LSU0 DERAT misses
##91086
A data request (load or store) from LSU Unit 0 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.
#200,v,g,n,n,n,PM_LSU0_LDF,LSU0 executed Floating Point load instruction
##800A4
A floating point load was executed from LSU unit 0
#201,v,g,n,n,n,PM_LSU0_NCLD,LSU0 non-cacheable loads
##820EA
A non-cacheable load was executed by unit 0.
#202,v,g,n,n,n,PM_LSU0_NCST,LSU0 non-cachable stores
##820EC
A non-cacheable store was executed by unit 0.
#203,v,g,n,n,n,PM_LSU0_REJECT,LSU0 reject
##A1086
Load Store Unit 0 rejected an instruction.
#204,v,g,n,n,n,PM_LSU0_REJECT_DERAT_MPRED,LSU0 reject due to mispredicted DERAT
##A00A2
Load Store Unit 0 rejected an instruction because the Effective Address was improperly predicted. This is a fast reject and will be immediately redispatched. On the redispatch, the scratch register is used to provide the correct effective address for the D-ERAT access to resolve the incorrect guess.
#205,v,g,n,n,n,PM_LSU0_REJECT_EXTERN,LSU0 external reject request 
##A1084
Load Store Unit 0 rejected an instruction due to a request from the decode unit or the fixed point unit.
#206,v,g,n,n,n,PM_LSU0_REJECT_L2MISS,LSU0 L2 miss reject
##900A4
Load Store Unit 0 rejected a load due to a correctable error in the L2. This is a fast reject and will be immediately redispatched. 
#207,v,g,n,n,n,PM_LSU0_REJECT_L2_CORR,LSU0 reject due to L2 correctable error
##A1080
Load Store Unit 0 rejected an instruction. The reject was a collision type reject. The IDU immediately redispatches the rejected instruction. The result is eleven (11) cycles, dispatch-to-dispatch, in the best case. 
#208,v,g,n,n,n,PM_LSU0_REJECT_LHS,LSU0 load hit store reject
##900A6
Load Store Unit 0 rejected a load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully.
#209,v,g,n,n,n,PM_LSU0_REJECT_NO_SCRATCH,LSU0 reject due to scratch register not available
##A1082
Load Store Unit 0 rejected an instruction because the internal scratch register was not available. This is a fast reject and will be immediately redispatched. 
#210,v,g,n,n,n,PM_LSU0_REJECT_PARTIAL_SECTOR,LSU0 reject due to partial sector valid
##A00A6
Load Store Unit 0 rejected an instruction that had a L1 Data Cache line hit but the critical sector was not valid. Since the cache line is partially validated, a reload of that cache line is in progress. This is a fast reject and will be immediately redispatched. 
#211,v,g,n,n,n,PM_LSU0_REJECT_SET_MPRED,LSU0 reject due to mispredicted set
##A00A4
Load Store Unit 0 rejected an instruction because the cache set was improperly predicted. This is a fast reject and will be immediately redispatched. 
#212,v,g,n,n,n,PM_LSU0_REJECT_STQ_FULL,LSU0 reject due to store queue full
##A00A0
Load Store Unit 0 rejected a store because the store request queue was full. This is a fast reject and will be immediately redispatched.
#213,v,g,n,n,n,PM_LSU0_REJECT_ULD,LSU0 unaligned load reject
##900A0
Load Store Unit 0 rejected a load instruction that spans a cache line boundary (128B). The LSU will pass the incremented address information to the FXU via the scratch register so that the subsequent address generation will access the next line.
#214,v,g,n,n,n,PM_LSU0_REJECT_UST,LSU0 unaligned store reject
##900A2
Load Store Unit 0 rejected a store instruction that spans a cache line boundary (128B). The LSU will pass the incremented address information to the FXU via the scratch register so that the subsequent address generation will access the next line.
#215,v,g,n,n,n,PM_LSU1_DERAT_MISS,LSU1 DERAT misses
##9108E
A data request (load or store) from LSU Unit 1 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.
#216,v,g,n,n,n,PM_LSU1_LDF,LSU1 executed Floating Point load instruction
##800AC
A floating point load was executed from LSU unit 1
#217,v,g,n,n,n,PM_LSU1_REJECT,LSU1 reject
##A108E
Load Store Unit 1 rejected an instruction.
#218,v,g,n,n,n,PM_LSU1_REJECT_DERAT_MPRED,LSU1 reject due to mispredicted DERAT
##A00AA
Load Store Unit 1 rejected an instruction because the Effective Address was improperly predicted. This is a fast reject and will be immediately redispatched. On the redispatch, the scratch register is used to provide the correct effective address for the D-ERAT access to resolve the incorrect guess.
#219,v,g,n,n,n,PM_LSU1_REJECT_EXTERN,LSU1 external reject request 
##A108C
Load Store Unit 1 rejected an instruction due to a request from the decode unit or the fixed point unit.
#220,v,g,n,n,n,PM_LSU1_REJECT_L2_CORR,LSU1 reject due to L2 correctable error
##A1088
Load Store Unit 1 rejected an instruction. The reject was a collision type reject. The IDU immediately redispatches the rejected instruction. The result is eleven (11) cycles, dispatch-to-dispatch, in the best case. 
#221,v,g,n,n,n,PM_LSU1_REJECT_LHS,LSU1 load hit store reject
##900AE
Load Store Unit 1 rejected a load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully.
#222,v,g,n,n,n,PM_LSU1_REJECT_NO_SCRATCH,LSU1 reject due to scratch register not available
##A108A
Load Store Unit 1 rejected an instruction because the internal scratch register was not available. This is a fast reject and will be immediately redispatched. 
#223,v,g,n,n,n,PM_LSU1_REJECT_PARTIAL_SECTOR,LSU1 reject due to partial sector valid
##A00AE
Load Store Unit 1 rejected an instruction that had a L1 Data Cache line hit but the critical sector was not valid. Since the cache line is partially validated, a reload of that cache line is in progress. This is a fast reject and will be immediately redispatched. 
#224,v,g,n,n,n,PM_LSU1_REJECT_SET_MPRED,LSU1 reject due to mispredicted set
##A00AC
Load Store Unit 1 rejected an instruction because the cache set was improperly predicted. This is a fast reject and will be immediately redispatched. 
#225,v,g,n,n,n,PM_LSU1_REJECT_STQ_FULL,LSU1 reject due to store queue full
##A00A8
Load Store Unit 1 rejected a store because the store request queue was full. This is a fast reject and will be immediately redispatched.
#226,v,g,n,n,n,PM_LSU1_REJECT_ULD,LSU1 unaligned load reject
##900A8
Load Store Unit 1 rejected a load instruction that spans a cache line boundary (128B). The LSU will pass the incremented address information to the FXU via the scratch register so that the subsequent address generation will access the next line.
#227,v,g,n,n,n,PM_LSU1_REJECT_UST,LSU1 unaligned store reject
##900AA
Load Store Unit 1 rejected a store instruction that spans a cache line boundary (128B). The LSU will pass the incremented address information to the FXU via the scratch register so that the subsequent address generation will access the next line.
#228,v,g,n,n,n,PM_LSU_BOTH_BUS,Both data return buses busy simultaneously
##8108A
Data was returned on both data buses
#229,v,g,n,n,n,PM_LSU_FLUSH_ALIGN,Flush caused by alignement exception
##220EC
A flush was initiated by the Load Store Unit in response to an unaligned operand
#230,v,g,n,n,n,PM_LSU_FLUSH_DSI,Flush caused by DSI
##220EE
A flush was initiated by the Load Store Unit in response to a Data Storage Interrupt
#231,v,g,n,n,n,PM_LSU_LDF,LSU executed Floating Point load instruction
##80034
LSU executed Floating Point load instruction. Combined Unit 0 + 1.
#232,v,g,n,n,n,PM_LSU_LDF_BOTH,Both LSU units executed Floating Point load instruction
##8003A
Both Load Store Units were executing a Floating Point Load instruction at the same time.
#233,u,g,n,s,n,PM_LSU_LMQ_FULL_CYC,Cycles LMQ full
##8108C
The Load Miss Queue was full.
#234,v,g,n,s,n,PM_LSU_LMQ_SRQ_EMPTY_BOTH_CYC,Cycles both threads LMQ and SRQ empty
##0001C
The Load Miss Queue and Store Request Queue were empty for both threads (Load Store Units are idle)
#235,v,g,n,n,n,PM_LSU_REJECT_EXTERN,LSU external reject request 
##A1030
The Load Store Unit rejected an instruction due to a request from the decode unit or the fixed point unit. Combined Unit 0 + 1
#236,v,g,n,n,n,PM_LSU_REJECT_FAST,LSU fast reject
##0003E
The Load Store Unit rejected an instruction. The reject was a collision type reject. The IDU immediately redispatches the rejected instruction. The result is eleven (11) cycles, dispatch-to-dispatch, in the best case. Combined Unit 0 + 1
#237,v,g,n,n,n,PM_LSU_REJECT_NO_SCRATCH,LSU reject due to scratch register not available
##A1032
The Load Store Unit rejected an instruction because the internal scratch register was not available. This is a fast reject and will be immediately redispatched. Combined Unit 0 + 1
#238,v,g,n,n,n,PM_LSU_REJECT_SET_MPRED,LSU reject due to mispredicted set
##A0034
The Load Store Unit rejected an instruction because the cache set was improperly predicted. This is a fast reject and will be immediately redispatched. Combined Unit 0 + 1
#239,v,g,n,n,n,PM_LSU_REJECT_STEAL,LSU reject due to steal
##900AC
The Load Store Unit rejected an instruction because a cache or cache directory was being updated. This is a fast reject and will be immediately redispatched. Combined Unit 0 + 1
#240,v,g,n,n,n,PM_LSU_ST_CHAINED,number of chained stores
##820EE
The Load Store Unit chained two store requests together and sent them as one to the L2
#241,v,g,n,n,n,PM_LWSYNC,Isync instruction completed
##8108E
A lightweight sync instruction completed.
#242,v,g,n,c,n,PM_MEM0_DP_CL_WR_GLOB,cacheline write setting dp to global side 0
##502A4
A memory cacheline write on memory controller 0 from a remote node. This event is sent from the Memory Controller clock domain and must be scaled accordingly.
#243,v,g,n,c,n,PM_MEM0_DP_CL_WR_LOC,cacheline write setting dp to local side 0
##502A6
A memory cacheline write on memory controller 0 from a local node. This event is sent from the Memory Controller clock domain and must be scaled accordingly.
#244,v,g,n,c,n,PM_MEM0_DP_RQ_GLOB_LOC,Memory read queue marking cache line double pump state from global to local side 0
##502A0
A memory cacheline read on memory controller 0 changed the double pump state from global to local. This event is sent from the Memory Controller clock domain and must be scaled accordingly.
#245,v,g,n,c,n,PM_MEM0_DP_RQ_LOC_GLOB,Memory read queue marking cache line double pump state from local to global side 0
##502A2
A memory cacheline read on memory controller 0 changed the double pump state from local to global. This event is sent from the Memory Controller clock domain and must be scaled accordingly.
#246,v,g,n,c,n,PM_MEM1_DP_CL_WR_GLOB,cacheline write setting dp to global side 1
##502AC
A memory cacheline write on memory controller 1 from a remote node. This event is sent from the Memory Controller clock domain and must be scaled accordingly.
#247,v,g,n,c,n,PM_MEM1_DP_CL_WR_LOC,cacheline write setting dp to local side 1
##502AE
A memory cacheline write on memory controller 1 from a local node. This event is sent from the Memory Controller clock domain and must be scaled accordingly.
#248,v,g,n,c,n,PM_MEM1_DP_RQ_GLOB_LOC,Memory read queue marking cache line double pump state from global to local side 1
##502A8
A memory cacheline read on memory controller 1 changed the double pump state from global to local. This event is sent from the Memory Controller clock domain and must be scaled accordingly.
#249,v,g,n,c,n,PM_MEM1_DP_RQ_LOC_GLOB,Memory read queue marking cache line double pump state from local to global side 1
##502AA
A memory cacheline read on memory controller 1 changed the double pump state from local to global. This event is sent from the Memory Controller clock domain and must be scaled accordingly.
#250,v,g,n,c,n,PM_MEM_DP_CL_WR_GLOB,cache line write setting double pump state to global
##50234
A memory cacheline write from a remote node. This event is sent from the Memory Controller clock domain and must be scaled accordingly. Combined unit 0 + 1.
#251,v,g,n,n,m,PM_MRK_BR_MPRED,Marked branch mispredicted
##00052
A marked branch was mispredicted
#252,v,g,n,n,m,PM_MRK_DATA_FROM_DL2L3_SHR,Marked data loaded from distant L2 or L3 shared
##0304C
The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a distant module due to a marked load.
#253,v,g,n,n,m,PM_MRK_DATA_FROM_L25_MOD,Marked data loaded from L2.5 modified
##0304E
The processor's Data Cache was reloaded with modified (M) data from the L2 of a chip on the same module as this processor is located due to a marked load.
#254,v,g,n,n,m,PM_MRK_DATA_FROM_L3,Marked data loaded from L3
##03048
The processor's Data Cache was reloaded from the local L3 due to a marked load.
#255,v,g,n,n,m,PM_MRK_DATA_FROM_L3MISS,Marked data loaded from L3 miss
##03028
DL1 was reloaded from beyond L3 due to a marked load.
#256,v,g,n,n,m,PM_MRK_DATA_FROM_RMEM,Marked data loaded from remote memory
##0304A
The processor's Data Cache was reloaded due to a marked load from memory attached to a different module than this proccessor is located on.
#257,v,g,n,n,m,PM_MRK_DFU_FIN,DFU marked instruction finish
##00008
The Decimal Floating Point Unit finished a marked instruction.
#258,v,g,n,n,m,PM_MRK_DTLB_REF,Marked Data TLB reference
##920E0
Total number of Data TLB references by a marked instruction for all page sizes. Page size is determined at TLB reload time.
#259,v,g,n,n,m,PM_MRK_FPU0_FIN,Marked instruction FPU0 processing finished
##D00A2
Floating Point Unit 0 finished a marked instruction.
#260,v,g,n,n,m,PM_MRK_FPU1_FIN,Marked instruction FPU1 processing finished
##D00AA
Floating Point Unit 1 finished a marked instruction.
#261,v,g,n,n,m,PM_MRK_FPU_FIN,Marked instruction FPU processing finished
##0001A
One of the Floating Point Units finished a marked instruction. Instructions that finish may not necessary complete
#262,v,g,n,n,m,PM_MRK_INST_FIN,Marked instruction finished
##0000A
One of the execution units finished a marked instruction. Instructions that finish may not necessary complete
#263,b,g,n,n,m,PM_MRK_LSU0_REJECT_L2MISS,LSU0 marked L2 miss reject
##930C4
This event never worked and was replaced by marked DERAT guess wrong
#264,v,g,n,n,m,PM_MRK_LSU0_REJECT_LHS,LSU0 marked load hit store reject
##930C6
Load Store Unit 0 rejected a marked load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully.
#265,v,g,n,n,m,PM_MRK_LSU0_REJECT_ULD,LSU0 marked unaligned load reject
##930C0
Load Store Unit 0 rejected a marked load instruction that spans a cache line boundary (128B). The LSU will pass the incremented address information to the FXU via the scratch register so that the subsequent address generation will access the next line.
#266,v,g,n,n,m,PM_MRK_LSU0_REJECT_UST,LSU0 marked unaligned store reject
##930C2
Load Store Unit 0 rejected a marked store instruction that spans a cache line boundary (128B). The LSU will pass the incremented address information to the FXU via the scratch register so that the subsequent address generation will access the next line.
#267,v,g,n,n,m,PM_MRK_LSU1_REJECT_LHS,LSU1 marked load hit store reject
##930CE
Load Store Unit 1 rejected a marked load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully.
#268,v,g,n,n,m,PM_MRK_LSU1_REJECT_ULD,LSU1 marked unaligned load reject
##930C8
Load Store Unit 1 rejected a marked load instruction that spans a cache line boundary (128B). The LSU will pass the incremented address information to the FXU via the scratch register so that the subsequent address generation will access the next line.
#269,v,g,n,n,m,PM_MRK_LSU1_REJECT_UST,LSU1 marked unaligned store reject
##930CA
Load Store Unit 1 rejected a marked store instruction that spans a cache line boundary (128B). The LSU will pass the incremented address information to the FXU via the scratch register so that the subsequent address generation will access the next line.
#270,v,g,n,n,m,PM_MRK_LSU_REJECT_UST,Marked unaligned store reject
##93032
The Load Store Unit rejected a marked store instruction that spans a cache line boundary (128B). The LSU will pass the incremented address information to the FXU via the scratch register so that the subsequent address generation will access the next line.
#271,v,g,n,n,m,PM_MRK_PTEG_FROM_DL2L3_SHR,Marked PTEG loaded from distant L2 or L3 shared
##12044
A Page Table Entry was loaded into the ERAT with shared (T or SL) data from an L2 or L3 on a distant module due to a marked load or store.
#272,v,g,n,n,m,PM_MRK_PTEG_FROM_L25_MOD,Marked PTEG loaded from L2.5 modified
##12046
A Page Table Entry was loaded into the ERAT with modified (M) data from the L2 of a chip on the same module as this processor is located due to a marked load or store.
#273,v,g,n,n,m,PM_MRK_PTEG_FROM_L3,Marked PTEG loaded from L3
##12040
A Page Table Entry was loaded into the ERAT from the local L3 due to a marked load or store.
#274,v,g,n,n,m,PM_MRK_PTEG_FROM_L3MISS,Marked PTEG loaded from L3 miss
##12054
A Page Table Entry was loaded into the ERAT from beyond the L3 due to a marked load or store
#275,v,g,n,n,m,PM_MRK_PTEG_FROM_RMEM,Marked PTEG loaded from remote memory
##12042
A Page Table Entry was loaded into the ERAT. POWER6 does not have a TLB
#276,v,g,n,n,m,PM_MRK_STCX_FAIL,Marked STCX failed
##830C4
A marked stcx (stwcx or stdcx) failed
#277,v,g,n,n,m,PM_MRK_ST_CMPL_INT,Marked store completed with intervention
##00006
A marked store previously sent to the memory subsystem completed (data home) after requiring intervention
#278,v,g,n,n,m,PM_MRK_VMX0_LD_WRBACK,Marked VMX0 load writeback valid
##600A6
A marked load returned data on VMX unit 0
#279,v,g,n,n,m,PM_MRK_VMX1_LD_WRBACK,Marked VMX1 load writeback valid
##600AE
A marked load returned data on VMX unit 1
#280,v,g,n,n,m,PM_MRK_VMX_COMPLEX_ISSUED,Marked VMX instruction issued to complex
##700AC
A marked instruction was issued to the VMX Complex pipeline.
#281,v,g,n,n,m,PM_MRK_VMX_FLOAT_ISSUED,Marked VMX instruction issued to float
##700A8
A marked instruction was issued to the VMX Float pipeline.
#282,v,g,n,n,m,PM_MRK_VMX_PERMUTE_ISSUED,Marked VMX instruction issued to permute
##700AE
A marked instruction was issued to the VMX Permute pipeline.
#283,v,g,n,n,m,PM_MRK_VMX_SIMPLE_ISSUED,Marked VMX instruction issued to simple
##700AA
A marked instruction was issued to the VMX Simple pipeline.
#284,v,g,n,n,m,PM_MRK_VMX_ST_ISSUED,Marked VMX store issued
##B00A8
A marked VMX Store was issued
#285,v,g,n,n,n,PM_NO_ITAG_CYC,Cyles no ITAG available
##400A8
Cycles when no ITAGS are available. This condition will block instruction fetch.
#286,v,g,n,n,n,PM_PMC2_OVERFLOW,PMC2 Overflow
##00014
Overflows from PMC2 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.
#287,v,g,n,n,n,PM_PMC2_REWIND,PMC2 rewind event
##00020
PMC2 was counting speculatively. The speculative condition was not met and the counter was restored to its previous value.
#288,v,g,n,n,n,PM_PMC4_SAVED,PMC4 rewind value saved
##00022
PMC4 was counting speculatively. The speculative condition was met and the counter value was committed by copying it to the backup register.
#289,v,g,n,n,n,PM_PMC6_OVERFLOW,PMC6 Overflow
##00024
Overflows from PMC6 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.
#290,v,g,n,n,n,PM_PTEG_FROM_DL2L3_SHR,PTEG loaded from distant L2 or L3 shared
##1304C
A Page Table Entry was loaded into the ERAT with shared (T or SL) data from an L2 or L3 on a distant module due to a demand load or store.
#291,v,g,n,n,n,PM_PTEG_FROM_L25_MOD,PTEG loaded from L2.5 modified
##1304E
A Page Table Entry was loaded into the ERAT with modified (M) data from the L2 of a chip on the same module as this processor is located due to a demand load or store.
#292,v,g,n,n,n,PM_PTEG_FROM_L3,PTEG loaded from L3
##13048
A Page Table Entry was loaded into the ERAT from the local L3 due to a demand load or store.
#293,v,g,n,n,n,PM_PTEG_FROM_L3MISS,PTEG loaded from L3 miss
##13028
A Page Table Entry was loaded into the ERAT from beyond the L3 due to a demand load or store.
#294,v,g,n,n,n,PM_PTEG_FROM_RMEM,PTEG loaded from remote memory
##1304A
A Page Table Entry was loaded into the ERAT from memory attached to a different module than this proccessor is located on due to a demand load or store.
#295,v,g,n,n,n,PM_PTEG_RELOAD_VALID,PTEG reload valid
##000FC,130C8
A Page Table Entry was loaded into the ERAT. POWER6 does not have a TLB
#296,v,g,n,n,n,PM_STCX,STCX executed
##830C6
STCX executed
#297,v,g,n,n,n,PM_STCX_CANCEL,stcx cancel by core
##830CC
A conditional store request to the nest was canceled by the core
#298,v,g,n,n,n,PM_STCX_FAIL,STCX failed
##830CE
A stcx (stwcx or stdcx) failed
#299,v,g,n,n,n,PM_ST_MISS_L1,L1 D cache store misses
##000F0,800A8
A store missed the dcache. Combined Unit 0 + 1.
#300,v,g,n,n,n,PM_ST_REF_L1,L1 D cache store references
##800A6,800AE
Store references to the Data Cache. Combined Unit 0 + 1.
#301,v,g,n,c,n,PM_ST_REQ_L2,L2 store requests
##50734
L2 store requests
#302,v,g,n,n,n,PM_SUSPENDED,Suspended
##00000
The counter is suspended (does not count).
#303,v,g,n,n,n,PM_SYNC_CYC,Sync duration
##920EC
Cycles a SYNC instruction is pending. Starts counting when the request is sent to the nest until the nest responds.
#304,u,g,n,s,n,PM_TB_BIT_TRANS,Time Base bit transition
##000F8
When the selected time base bit (as specified in MMCR0[TBSEL])transitions from 0 to 1 
#305,v,g,n,s,n,PM_THERMAL_MAX,Processor in thermal MAX
##0002A
The processor experienced a thermal overload condition. This bit is sticky, it remains set until cleared by software.
#306,v,g,n,n,n,PM_THRD_CONC_RUN_INST,Concurrent run instructions
##00026,000F4
Instructions completed by this thread when both threads had their run latches set.
#307,v,g,n,n,n,PM_THRD_L2MISS,Thread in L2 miss
##31080
This thread has a L2 miss pending.
#308,v,g,n,n,n,PM_THRD_PRIO_2_CYC,Cycles thread running at priority level 2
##22040
Cycles this thread was running at priority level 2.
#309,v,g,n,n,n,PM_THRD_PRIO_5_CYC,Cycles thread running at priority level 5
##22046
Cycles this thread was running at priority level 5.
#310,v,g,n,n,n,PM_THRD_PRIO_DIFF_3or4_CYC,Cycles thread priority difference is 3 or 4
##23040
Cycles when this thread's priority is higher than the other thread's priority by 3 or 4.
#311,v,g,n,n,n,PM_THRD_PRIO_DIFF_minus3or4_CYC,Cycles thread priority difference is -3 or -4
##23046
Cycles when this thread's priority is lower than the other thread's priority by 3 or 4.
#312,v,g,n,c,n,PM_THRD_SEL_T0,Decode selected thread 0
##31086
Thread selection picked thread 0 for decode.
#313,v,g,t,n,n,PM_THRESH_TIMEO,Threshold timeout
##00018
The threshold timer expired
#314,v,g,n,n,n,PM_TLB_REF,TLB reference
##920E8
Number of Data Translation requests from the ERAT. 
#315,v,g,n,n,n,PM_VMX0_INST_ISSUED,VMX0 instruction issued
##600A0
An instruction was issued to VMX unit 0
#316,v,g,n,n,n,PM_VMX0_LD_ISSUED,VMX0 load issued
##600A2
A load instruction was issued to VMX unit 0
#317,v,g,n,n,n,PM_VMX0_LD_WRBACK,VMX0 load writeback valid
##600A4
A load returned data on VMX unit 0
#318,v,g,n,n,n,PM_VMX0_STALL,VMX0 stall
##B00A4
Cycles the VMX unit 0 was stalled
#319,v,g,n,n,n,PM_VMX1_INST_ISSUED,VMX1 instruction issued
##600A8
An instruction was issued to VMX unit 1
#320,v,g,n,n,n,PM_VMX1_LD_ISSUED,VMX1 load issued
##600AA
A load instruction was issued to VMX unit 1
#321,v,g,n,n,n,PM_VMX1_LD_WRBACK,VMX1 load writeback valid
##600AC
A load returned data on VMX unit 1
#322,v,g,n,n,n,PM_VMX1_STALL,VMX1 stall
##B00AC
Cycles the VMX unit 1 was stalled
#323,v,g,n,n,n,PM_VMX_COMPLEX_ISSUED,VMX instruction issued to complex
##700A4
An instruction was issued to the VMX Complex pipeline.
#324,v,g,n,n,n,PM_VMX_FLOAT_ISSUED,VMX instruction issued to float
##700A0
An instruction was issued to the VMX Float pipeline.
#325,v,g,n,n,n,PM_VMX_FLOAT_MULTICYCLE,VMX multi-cycle floating point instruction issued
##B00A2
A multi-cycle instruction was issued to the VMX Float pipeline.
#326,v,g,n,n,n,PM_VMX_PERMUTE_ISSUED,VMX instruction issued to permute
##700A6
An instruction was issued to the VMX Permute pipeline.
#327,v,g,n,n,n,PM_VMX_RESULT_SAT_0_1,VMX valid result with sat bit is set (0->1)
##B00AE
An instruction finished on the VMX unit that set the saturation bit. This bit is sticky, once set to 1 it remains set to 1 until it is set to 0 by an mtvscr instruction.
#328,v,g,n,n,n,PM_VMX_RESULT_SAT_1,VMX valid result with sat=1
##B00A6
An instruction finished on the VMX unit with the saturation bit on. This bit is sticky, once set to 1 it remains set to 1 until it is set to 0 by an mtvscr instruction.
#329,v,g,n,n,n,PM_VMX_SIMPLE_ISSUED,VMX instruction issued to simple
##700A2
An instruction was issued to the VMX Simple pipeline.
#330,v,g,n,n,n,PM_VMX_ST_ISSUED,VMX store issued
##B00A0
A VMX Store was issued
#331,v,g,n,n,n,PM_0INST_FETCH_COUNT,Periods with no instructions fetched
##400A1
No instructions were fetched this periods (due to IFU hold, redirect, or icache miss)
#332,v,g,n,n,n,PM_IBUF_FULL_COUNT,Periods instruction buffer full
##400A5
Number of times the Instruction Buffer was full. The Instruction Buffer is a circular queue of 64 instructions per thread, organized as 16 groups of 4 instructions.
#333,v,g,n,n,n,PM_GCT_FULL_COUNT,Periods GCT full
##400A7
The Global Completion Table is completely full.
#334,v,g,n,n,n,PM_NO_ITAG_COUNT,Periods no ITAG available
##400A9
Number of periods when no ITAGS are available. This condition will block instruction fetch.
#335,v,g,n,n,n,PM_INST_TABLEWALK_COUNT,Periods doing instruction tablewalks
##920EB
Number of Instruction Tablewalks
#336,v,g,n,n,n,PM_SYNC_COUNT,SYNC instructions completed
##920ED
Number of SYNC instructions executed.
#337,v,g,n,c,n,PM_LLA_CYC,Load Look Ahead Active
##0C01E
Load Look Ahead Active. When a demand cache or ERAT miss is encountered, the processor continues dispatching instructions but inhibits the results from writing registers (i.e. the architected state of the machine is not changed), executing subsequent load instructions such that independent cache line miss requests maybe started.
#338,v,g,n,c,n,PM_NOT_LLA_CYC,Load Look Ahead not Active
##0401E
Load Look Ahead not Active
#339,v,g,n,c,n,PM_LLA_COUNT,Transitions into Load Look Ahead mode
##0C01F
Transitions into Load Look Ahead mode
#340,v,g,n,n,n,PM_DPU_WT_COUNT,Periods DISP unit is stalled waiting for instructions
##00005
Number of times that Instruction Dispatch had no instructions available to dispatch and was not held for any reason.
#341,v,g,n,s,n,PM_LSU_LMQ_SRQ_EMPTY_BOTH_COUNT,Periods both threads LMQ and SRQ empty
##0001D
The Load Miss Queue and Store Request Queue were empty for both threads (Load Store Units are idle)
#342,v,g,n,n,n,PM_DERAT_REF_16M,DERAT reference for 16M page
##82070
A data request (load or store) referenced (accessed)  the ERAT for 16M page
#343,v,g,n,n,n,PM_DERAT_MISS_16M,DERAT misses for 16M page
##92070
A data request (load or store) missed the ERAT for 16M page and resulted in an ERAT reload.
#344,v,g,n,n,n,PM_IERAT_MISS_64K,IERAT misses for 64K page
##92076
A translation request for a 64KB page missed the Instruction Effective to Real Address Translation (ERAT) table
#345,v,g,n,n,m,PM_MRK_DERAT_REF_16M,Marked DERAT reference for 16M page
##82044
A marked data request (load or store) referenced (accessed)  the ERAT for 16M page
#346,v,g,n,n,m,PM_MRK_DERAT_MISS_16M,Marked DERAT misses for 16M page
##92044
A marked data request (load or store) missed the ERAT for 16M page and resulted in an ERAT reload.

$$$$$$$$

{ counter 4 }
#0,v,g,n,n,n,PM_0INST_FETCH,No instructions fetched
##400A0
No instructions were fetched this cycles (due to IFU hold, redirect, or icache miss)
#1,v,g,n,n,n,PM_1PLUS_PPC_DISP,Cycles at least one instruction dispatched
##000F2
A group containing at least one PPC instruction was dispatched. For microcoded instructions that span multiple groups, this will only occur once.
#2,v,g,n,n,n,PM_BRU_FIN,BRU produced a result
##430C6
The Branch execution unit finished an instruction
#3,v,g,n,n,n,PM_BR_MPRED,Branches incorrectly predicted
##00052
A branch instruction was incorrectly predicted. This could have been a target prediction, a condition prediction, or both
#4,v,g,n,n,n,PM_BR_MPRED_CCACHE,Branch misprediction due to count cache prediction
##4108E
A branch instruction target was incorrectly predicted by the ccount cache. This will result in a branch redirect flush if not overfidden by a flush of an older instruction.
#5,v,g,n,n,n,PM_BR_MPRED_COUNT,Branch misprediction due to count prediction
##4108A
A branch instruction count value was incorrectly predicted. This will result in a branch mispredict flush unless a flush is detected from an older instruction.
#6,v,g,n,n,n,PM_BR_MPRED_CR,Branch mispredictions due to CR bit setting
##41088
A conditional branch instruction was incorrectly predicted as taken or not taken. The branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This will result in a branch redirect flush if not overfidden by a flush of an older instruction.
#7,v,g,n,n,n,PM_BR_MPRED_TA,Branch mispredictions due to target address
##4108C
A branch instruction target was incorrectly predicted. This will result in a branch mispredict flush unless a flush is detected from an older instruction.
#8,v,g,n,n,n,PM_BR_PRED,A conditional branch was predicted
##41080
A branch prediction was made. This could have been a target prediction, a condition prediction, or both
#9,v,g,n,n,n,PM_BR_PRED_CCACHE,Branch count cache prediction
##41084
The count value of a Branch and Count instruction was predicted
#10,v,g,n,n,n,PM_BR_PRED_CR,A conditional branch was predicted, CR prediction
##41082
A conditional branch instruction was predicted as taken or not taken.
#11,v,g,n,n,n,PM_BR_PRED_LSTACK,A conditional branch was predicted, link stack
##41086
The target address of a Branch to Link instruction was predicted by the link stack.
#12,v,g,n,c,n,PM_CYC,Processor cycles
##0001E
Processor cycles
#13,v,g,n,n,n,PM_DATA_FROM_DL2L3_MOD,Data loaded from distant L2 or L3 modified
##0005C
The processor's Data Cache was reloaded with modified (M) data from an L2  or L3 on a distant module due to a demand load
#14,v,g,n,n,n,PM_DATA_FROM_DL2L3_MOD_CYC,Load latency from distant L2 or L3 modified
##0002A
Cycles waiting for a Data Cache reload of modified (M) data from a distant L2  or L3
#15,v,g,n,n,n,PM_DATA_FROM_L21_CYC,Load latency from private L2 other core
##00020
Cycles waiting for a Data Cache reload of data from the private L2 of the other core on this chip
#16,v,g,n,n,n,PM_DATA_FROM_L25_SHR,Data loaded from L2.5 shared
##0005A
The processor's Data Cache was reloaded with shared (T or SL) data from the L2 of a chip on the same module as this processor is located due to a demand load.
#17,v,g,n,n,n,PM_DATA_FROM_L25_MOD_CYC,Load latency from L2.5 modified
##00024
Cycles waiting for a Data Cache reload of modified (M) data from the L2 of a chip on the same module as this processor is located
#18,v,g,n,n,n,PM_DATA_FROM_L35_MOD_CYC,Load latency from L3.5 modified
##00026
Cycles waiting for a Data Cache reload of modified (M) data from the L3 of a chip on this MCM
#19,v,g,n,n,n,PM_DATA_FROM_L3MISS,Data loaded from private L3 miss
##00056
The processor's Data Cache was reloaded from beyond L3 due to a demand load
#20,v,g,n,n,n,PM_DATA_FROM_LMEM,Data loaded from local memory
##0005E
The processor's Data Cache was reloaded with data from local memory due to a demand load
#21,v,g,n,n,n,PM_DATA_FROM_MEM_DP_CYC,Load latency from double pump memory
##0002E
This event should have been removed from the documentation by now. The core will never see this data sources as it is used by the L2
#22,v,g,n,n,n,PM_DATA_FROM_RL2L3_MOD_CYC,Load latency from remote L2 or L3 modified
##00028
Cycles waiting for a Data Cache reload of modified (M) data from a remote L2  or L3
#23,v,g,n,n,n,PM_DATA_FROM_RMEM_CYC,Load latency from remote memory
##0002C
Cycles waiting for a Data Cache reload  of data from memory on a remote module
#24,v,g,n,n,n,PM_DATA_PTEG_1ST_HALF,Data table walk matched in first half primary PTEG
##91080
A translation request for a data address was satisfied using the primary page table hash. The matching Page Table Entry is one of the first four PTE entries of the primary PTEG
#25,v,g,n,n,n,PM_DATA_PTEG_2ND_HALF,Data table walk matched in second half primary PTEG
##91082
A translation request for a data address was satisfied using the primary page table hash. The matching Page Table Entry is one of the second four PTE entries of the primary PTEG
#26,v,g,n,n,n,PM_DATA_PTEG_SECONDARY,Data table walk matched in secondary PTEG
##91084
A translation request for a data address was satisfied using the secondary page table hash. 
#27,u,g,n,c,n,PM_DC_INV_L2,L1 D cache entries invalidated from L2
##50634
A dcache invalidated was received from the L2 because a line in L2 was castout.
#28,u,g,n,n,n,PM_DC_PREF_OUT_OF_STREAMS,D cache out of streams
##81080
A new prefetch stream was detected but no more stream entries were available.
#29,v,g,n,n,n,PM_DC_PREF_STREAM_ALLOC,D cache new prefetch stream allocated
##81082
A new Prefetch Stream was allocated.
#30,v,g,n,n,n,PM_DFU_ADD,DFU add type instruction
##E00AC
The Decimal Floating Point Unit executed an add type instruction. This could be dadd, dsub, dcmpo, or dcmpu
#31,v,g,n,n,n,PM_DFU_ADD_SHIFTED_BOTH,DFU add type with both operands shifted
##E00A8
The Decimal Floating Point Unit executed an add type instruction and both operands required shifting. This could be dadd, dsub, dcmpo, or dcmpu
#32,v,g,n,n,n,PM_DFU_BACK2BACK,DFU back to back operations executed
##E00A2
The Decimal Floating Point Unit executed two instructions back to back.
#33,v,g,n,n,n,PM_DFU_CONV,DFU convert from fixed op
##E00AE
The Decimal Floating Point Unit executed a convert from fixed point operation. This could be a dcffix or dcffixq instruction. The fixed point operand was converted to a Decimal Floating Point number
#34,v,g,n,n,n,PM_DFU_ENC_BCD_DPD,DFU Encode BCD to DPD
##E00AA
The Decimal Floating Point Unit executed an encode to fixed point operation. This could have been a denbcd or denbcdq instruction. The binary coded decimal operand is convered to a binary floating point number.
#35,v,g,n,n,n,PM_DFU_EXP_EQ,DFU operand exponents are equal for add type
##E00A4
The Decimal Floating Point Unit executed an add type instruction and the exponents of both operand are equal
#36,v,g,n,n,n,PM_DFU_FIN,DFU instruction finish
##E00A0
The Decimal Floating Point Unit finished an operation.
#37,v,g,n,n,n,PM_DFU_SUBNORM,DFU result is a subnormal
##E00A6
The result of a Decimal Floating Point operation was subnormal.
#38,v,g,n,n,n,PM_DPU_HELD_COMPLETION,DISP unit held due to completion holding dispatch 
##2108C
Cycles that Instruction Dispatch was held because of the completion unit. More than one hold condition can exist at the same time
#39,v,g,n,n,n,PM_DPU_HELD_CR_LOGICAL,DISP unit held due to CR, LR or CTR updated by CR logical, MTCRF, MTLR or MTCTR
##300AE
Cycles that Instruction Dispatch was held because the CR, LR, or CTR SPRs were being updated by a CR logical, MTCRF, MTLR or MTCTR instruction. More than one hold condition can exist at the same time
#40,v,g,n,n,n,PM_DPU_HELD_CW,DISP unit held due to cache writes 
##200A4
Cycles that Load Store Unit is performing a cache write. The LSU blocks dispatch to avoid contention for the cache during a write. More than one hold condition can exist at the same time
#41,v,g,n,n,n,PM_DPU_HELD_FPQ,DISP unit held due to FPU issue queue full
##200A6
Cycles that Instruction Dispatch was held because the Floating Point Issue Queue was full. More than one hold condition can exist at the same time
#42,v,g,n,n,n,PM_DPU_HELD_FPU_CR,DISP unit held due to FPU updating CR
##21080
Cycles that Instruction Dispatch was held because a Floating Point operation was updating a condition register. Younger instruction are blocked to avoid Write after Write conflicts. More than one hold condition can exist at the same time
#43,v,g,n,n,n,PM_DPU_HELD_FP_FX_MULT,DISP unit held due to non fixed multiple/divide after fixed multiply/divide
##21088
Cycles that Instruction Dispatch was held due to fixed point multiply/divides. After dispatching a FXU Multiply/Divide instruction, the dispatcher must block all non FXU/Divide instruction from dispatch (same thread)  More than one hold condition can exist at the same time
#44,v,g,n,n,n,PM_DPU_HELD_FXU_MULTI,DISP unit held due to FXU multicycle
##21086
Cycles that Instruction Dispatch was held due to multi-cycle fixed operation. More than one hold condition can exist at the same time
#45,v,g,n,n,n,PM_DPU_HELD_FXU_SOPS,DISP unit held due to FXU slow ops (mtmsr, scv, rfscv)
##300A8
Cycles that Instruction Dispatch was held due to a slow operation executing on a fixed point unit. Instructions such as mtmsr, scv, rfscv require that dispatch be held until all units are idle. More than one hold condition can exist at the same time
#46,v,g,n,n,n,PM_DPU_HELD_GPR,DISP unit held due to GPR dependencies
##200A0
Cycles that Instruction Dispatch was held due to a GPR dependency. The dependent instruction is held until the GPR is written. More than one hold condition can exist at the same time
#47,v,g,n,n,n,PM_DPU_HELD_INT,DISP unit held due to exception
##31088
Cycles that Instruction Dispatch was held due to an exception. Dispatch is  held until all units are idle. More than one hold condition can exist at the same time
#48,v,g,n,n,n,PM_DPU_HELD_ISYNC,DISP unit held due to ISYNC 
##200AA
Cycles that Instruction Dispatch was held due to an isync instruction. If an previous instruction requires a context serializing instruction (CSI), dispatch will be held until the FPU is empty and a completion flush has been received. More than one hold condition can exist at the same time
#49,v,g,n,n,n,PM_DPU_HELD_ITLB_ISLB,DISP unit held due to SLB or TLB invalidates 
##21084
Cycles that Instruction Dispatch was held due to a islb or itlb instruction. Dispatch is held for three cycles after an islb or itlb instruction is dispatched. More than one hold condition can exist at the same time
#50,v,g,n,n,n,PM_DPU_HELD_LLA_END,DISP unit held due to load look ahead ended
##300A4
Cycles that Instruction Dispatch was held due to load look ahead ending. More than one hold condition can exist at the same time
#51,v,g,n,n,n,PM_DPU_HELD_LSU,DISP unit held due to LSU move or invalidate SLB and SR
##21082
Cycles that Instruction Dispatch was held due to a move to or invalidate of the Segment Lookaside Buffer. Dispatch is held until all units are idle. More than one hold condition can exist at the same time
#52,v,g,n,n,n,PM_DPU_HELD_LSU_SOPS,DISP unit held due to LSU slow ops (sync, tlbie, stcx)
##300A0
Cycles that Instruction Dispatch was held due to a slow operation executing on a Load Store Unit. Instructions such as sync, tlbie, stcx require that dispatch be held until all units are idle. More than one hold condition can exist at the same time
#53,v,g,n,n,n,PM_DPU_HELD_MULT_GPR,DISP unit held due to multiple/divide multiply/divide GPR dependencies
##2108A
Cycles that Instruction Dispatch was held due to a GPR dependency caused by a fixed point multiple or divide that is dependent on the results of another fixed point multiple or divide. More than one hold condition can exist at the same time
#54,v,g,n,n,n,PM_DPU_HELD_RESTART,DISP unit held after restart coming
##300A6
Cycles that Instruction Dispatch was held waiting on a restart signal from the LSU. Dispatch has dispatched all available instructions in load look ahead mode and is waiting for the demand load to be returned. 
#55,v,g,n,n,n,PM_DPU_HELD_RU_WQ,DISP unit held due to RU FXU write queue full
##200AE
Cycles that Instruction Dispatch was held because the recovery unit's fixed point write cycle was full. More than one hold condition can exist at the same time
#56,v,g,n,n,n,PM_DPU_HELD_SMT,DISP unit held due to SMT conflicts 
##200A2
Cycles that Instruction Dispatch was held due to conflicts with the other thread. There are not enough execution units available to dispatch. More than one hold condition can exist at the same time
#57,v,g,n,n,n,PM_DPU_HELD_SPR,DISP unit held due to MTSPR/MFSPR
##300AC
Cycles that Instruction Dispatch was held because of a move to or move from SPR instruction. More than one hold condition can exist at the same time
#58,v,g,n,n,n,PM_DPU_HELD_STCX_CR,DISP unit held due to STCX updating CR 
##200AC
Cycles that Instruction Dispatch was held due to a stcx instruction updating the CR. Instructions dependant on the CR are held until the stcx finishes. This hold condition is a subset of LSO Slow Operations. More than one hold condition can exist at the same time
#59,v,g,n,n,n,PM_DPU_HELD_THRD_PRIO,DISP unit held due to lower priority thread
##300AA
Cycles that Instruction Dispatch was held due to a lower priority thread. More than one hold condition can exist at the same time
#60,v,g,n,n,n,PM_DPU_HELD_XER,DISP unit held due to XER dependency
##200A8
Cycles that Instruction Dispatch was held due to a XER dependency. More than one hold condition can exist at the same time
#61,v,g,n,n,n,PM_DPU_HELD_XTHRD,DISP unit held due to cross thread resource conflicts
##300A2
Cycles that Instruction Dispatch was held due to a resource conflict with the other thread. This could be caused by a mtspr, mfspr, or a multi-cycle fixed point operation. More than one hold condition can exist at the same time
#62,v,g,n,n,n,PM_DPU_WT_BR_MPRED,Cycles DISP unit is stalled due to branch misprediction
##0000C
Cycles that Instruction Dispatch had no instructions available to dispatch because of a branch mispredict.
#63,v,g,n,n,n,PM_DSLB_MISS,Data SLB misses
##830C8
A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve
#64,u,g,n,n,n,PM_EE_OFF_EXT_INT,Cycles MSR(EE) bit off and external interrupt pending
##230CE
Cycles when an interrupt due to an external exception is pending but external exceptions were masked.
#65,v,g,n,c,n,PM_FAB_ADDR_COLLISION,local node launch collision with off-node address   
##501AE
A command from the local node hadd an address collision with a command for a system address. The local node competes with system pump addresses from remote nodes for address slots, this event is an indication of how badly local requests are affected by system wide requests
#66,v,g,n,c,n,PM_FAB_DCLAIM,Dclaim operation, locally mastered
##501A4
A DCLAIM command was issued. Each chip reports its own counts. The signal is delivered at FBC speed and the count must be scaled accordingly.
#67,v,g,n,c,n,PM_FAB_DMA,DMA operation, locally mastered
##501AC
A DMA operation was issued. Each chip reports its own counts. The signal is delivered at FBC speed and the count must be scaled accordingly.
#68,v,g,n,c,n,PM_FAB_MMIO,MMIO operation, locally mastered
##501A6
A MMIO operation was issued. Each chip reports its own counts. The signal is delivered at FBC speed and the count must be scaled accordingly.
#69,v,g,n,c,n,PM_FAB_NODE_PUMP,Node pump operation, locally mastered
##501A8
A request from this chip was send out on the XYZ (intra-node) link. Each chip reports its own counts. The signal is delivered at FBC speed and the count must be scaled accordingly.
#70,v,g,n,c,n,PM_FAB_RETRY_NODE_PUMP,Retry of a node pump, locally mastered
##501AA
A snoop operation for a node pump address originated from a master on this chip and the result was a retry.
#71,v,g,n,c,n,PM_FAB_RETRY_SYS_PUMP,Retry of a system pump, locally mastered  
##501A2
A snoop operation for a system pump address originated from a master on this chip and the result was a retry.
#72,v,g,n,c,n,PM_FAB_SYS_PUMP,System pump operation, locally mastered
##501A0
An request from this chip was send out on the AB (inter-node) link. Each chip reports its own counts. The signal is delivered at FBC speed and the count must be scaled accordingly.
#73,v,g,n,n,n,PM_FLUSH,Flushes
##000F8
Flushes occurred including LSU and Branch flushes.
#74,v,g,n,n,n,PM_FLUSH_ASYNC,Flush caused by asynchronous exception
##220EA
A flush was caused by an asyncronous exception. 
#75,v,g,n,n,n,PM_FLUSH_FPU,Flush caused by FPU exception
##230CC
A flush was caused by a floating point exception.
#76,v,g,n,n,n,PM_FLUSH_FXU,Flush caused by FXU exception
##230CA
A flush was caused by a fixed point exception.
#77,v,g,n,n,n,PM_FPU0_1FLOP,FPU0 executed add, mult, sub, cmp or sel instruction
##C00A0
The floating point unit has executed an add, mult, sub, compare, fsel, fneg, fabs, fnabs, fres, or frsqrte kind of instruction. These are single FLOP operations.
#78,v,g,n,n,n,PM_FPU0_DENORM,FPU0 received denormalized data
##C1082
FPU0 has encountered a denormalized operand. 
#79,v,g,n,n,n,PM_FPU0_FCONV,FPU0 executed FCONV instruction
##D1080
FPU0 has executed a convert kind of instruction. This could be fcfid* or fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.
#80,v,g,n,n,n,PM_FPU0_FEST,FPU0 executed FEST instruction
##D1086
FPU0 has executed an estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. 
#81,v,g,n,n,n,PM_FPU0_FIN,FPU0 produced a result
##D00A0
FPU0 finished, produced a result. This only indicates finish,  not completion. Floating Point Stores are included in this count but not Floating Point Loads.
#82,v,g,n,n,n,PM_FPU0_FLOP,FPU0 executed 1FLOP, FMA, FSQRT or FDIV instruction
##C00A6
FPU0 has executed a one flop, multiply-add, square root, or divide kind of instruction.
#83,v,g,n,n,n,PM_FPU0_FMA,FPU0 executed multiply-add instruction
##C00A2
FPU0 has executed a multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.
#84,v,g,n,n,n,PM_FPU0_FPSCR,FPU0 executed FPSCR instruction
##D00A4
FPU0 has executed FPSCR move related instruction. This could be mtfsfi*, mtfsb0*, mtfsb1*, mffs*, mtfsf*, mcrsf* where XYZ* means XYZ, XYZs, XYZ., XYZs.
#85,v,g,n,n,n,PM_FPU0_FRSP,FPU0 executed FRSP instruction
##D1082
FPU0 has executed a frsp kind of instruction. This could be frsp* where XYZ* means XYZ, XYZs, XYZ., XYZs.
#86,v,g,n,n,n,PM_FPU0_FSQRT_FDIV,FPU0 executed FSQRT or FDIV instruction
##C00A4
FPU0 has executed a square root or divide instruction. This could be fsqrt* or fdiv* where XYZ* means XYZ, XYZs, XYZ., XYZs
#87,v,g,n,n,n,PM_FPU0_FXDIV,FPU0 executed fixed point division
##C1080
FPU0 has executed a fixed point divide instruction.
#88,v,g,n,n,n,PM_FPU0_FXMULT,FPU0 executed fixed point multiplication
##D00A6
FPU0 has executed a fixed point multiply instruction.
#89,v,g,n,n,n,PM_FPU0_SINGLE,FPU0 executed single precision instruction
##C1086
FPU0 has executed a single precision instruction.
#90,v,g,n,n,n,PM_FPU0_STF,FPU0 executed store instruction
##C1084
FPU0 has executed a Floating Point Store instruction.
#91,v,g,n,n,n,PM_FPU0_ST_FOLDED,FPU0 folded store
##D1084
FPU0 executed a store that was dependant on the result of a previous instruction. The result it folded into the store allowing the store to execute earlier.
#92,v,g,n,n,n,PM_FPU1_1FLOP,FPU1 executed add, mult, sub, cmp or sel instruction
##C00A8
FPU1 has executed an add, mult, sub, compare, fsel, fneg, fabs, fnabs, fres, or frsqrte kind of instruction. These are single FLOP operations.
#93,v,g,n,n,n,PM_FPU1_DENORM,FPU1 received denormalized data
##C108A
FPU1 has encountered a denormalized operand.
#94,v,g,n,n,n,PM_FPU1_FCONV,FPU1 executed FCONV instruction
##D1088
FPU1 has executed a convert kind of instruction. This could be fcfid* or fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.
#95,v,g,n,n,n,PM_FPU1_FEST,FPU1 executed FEST instruction
##D108E
FPU1 has executed an estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ.
#96,v,g,n,n,n,PM_FPU1_FIN,FPU1 produced a result
##D00A8
FPU1 finished, produced a result. This only indicates finish,  not completion. Floating Point Stores are included in this count but not Floating Point Loads. 
#97,v,g,n,n,n,PM_FPU1_FLOP,FPU1 executed 1FLOP, FMA, FSQRT or FDIV instruction
##C00AE
FPU1 has executed a one flop, multiply-add, square root, or divide kind of instruction.
#98,v,g,n,n,n,PM_FPU1_FMA,FPU1 executed multiply-add instruction
##C00AA
FPU1 has executed a multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.
#99,v,g,n,n,n,PM_FPU1_FPSCR,FPU1 executed FPSCR instruction
##D00AC
FPU1 has executed FPSCR move related instruction. This could be mtfsfi*, mtfsb0*, mtfsb1*, mffs*, mtfsf*, mcrsf* where XYZ* means XYZ, XYZs, XYZ., XYZs.
#100,v,g,n,n,n,PM_FPU1_FRSP,FPU1 executed FRSP instruction
##D108A
FPU1 has executed a frsp kind of instruction. This could be frsp* where XYZ* means XYZ, XYZs, XYZ., XYZs.
#101,v,g,n,n,n,PM_FPU1_FSQRT_FDIV,FPU1 executed FSQRT or FDIV instruction
##C00AC
FPU1 has executed a square root or divide instruction. This could be fsqrt* or fdiv* where XYZ* means XYZ, XYZs, XYZ., XYZs
#102,v,g,n,n,n,PM_FPU1_FXDIV,FPU1 executed fixed point division
##C1088
FPU1 has executed a fixed point divide instruction.
#103,v,g,n,n,n,PM_FPU1_FXMULT,FPU1 executed fixed point multiplication
##D00AE
FPU1 has executed a fixed point multiply instruction.
#104,v,g,n,n,n,PM_FPU1_SINGLE,FPU1 executed single precision instruction
##C108E
FPU1 has executed a single precision instruction.
#105,v,g,n,n,n,PM_FPU1_STF,FPU1 executed store instruction
##C108C
FPU1 has executed a Floating Point Store instruction.
#106,v,g,n,n,n,PM_FPU1_ST_FOLDED,FPU1 folded store
##D108C
FPU1 executed a store that was dependant on the result of a previous instruction. The result it folded into the store allowing the store to execute earlier.
#107,v,g,n,n,n,PM_FPU_FCONV,FPU executed FCONV instruction
##D1032
The floating point unit has executed a convert kind of instruction. This could be fcfid* or fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1.
#108,v,g,n,n,n,PM_FPU_FEST,FPU executed FEST instruction
##D1030
The floating point unit has executed an estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or  XYZ. Combined Unit 0 + Unit 1.
#109,v,g,n,n,n,PM_FPU_FLOP,FPU executed 1FLOP, FMA, FSQRT or FDIV instruction
##C0034
The floating point unit has executed a one flop, multiply-add, square root, or divide kind of instruction. Combined Unit 0 + Unit 1.
#110,v,g,n,n,n,PM_FPU_FXDIV,FPU executed fixed point division
##C1032
The floating point unit has executed a fixed point divide instruction. Combined Unit 0 + 1.
#111,v,g,n,n,n,PM_FPU_FXMULT,FPU executed fixed point multiplication
##D0034
The floating point unit has executed a fixed point multiply instruction. Combined Unit 0 + 1.
#112,v,g,n,n,n,PM_FPU_ISSUE_0,FPU issue 0 per cycle
##320E6
Cycles when no instructions were issued to the floating point units.
#113,v,g,n,n,n,PM_FPU_ISSUE_1,FPU issue 1 per cycle
##320E8
Cycles when one instruction was issued to the floating point units.
#114,v,g,n,n,n,PM_FPU_ISSUE_2,FPU issue 2 per cycle
##320EA
Cycles when two instruction were issued to the floating point units.
#115,v,g,n,n,n,PM_FPU_ISSUE_DIV_SQRT_OVERLAP,FPU divide/sqrt overlapped with other divide/sqrt
##320EC
The floating point unit was issued a divide or square root instruction that overlapped execution with another divide or square root instruction. These instructions are not pipelined but they can execute in parallel on separate units.
#116,v,g,n,n,n,PM_FPU_ISSUE_OOO,FPU issue out-of-order
##320E0
Instructions were issued to the floating point unit of of order with respect to program order. The floating point unit has limited ability to execute instructions out of order.
#117,v,g,n,n,n,PM_FPU_ISSUE_STALL_FPR,FPU issue stalled due to FPR dependencies
##330C2
Instruction issue to the floating point unit was stalled waiting on the results of a previous instruction.
#118,v,g,n,n,n,PM_FPU_ISSUE_STALL_ST,FPU issue stalled due to store
##320EE
Instruction issue to the floating point unit was stalled due to store. Only one store per cycle can be issued to the floating point unit.
#119,v,g,n,n,n,PM_FPU_ISSUE_STALL_THRD,FPU issue stalled due to thread resource conflict
##330C0
Instruction issue to the floating point unit was stalled because a critical resource was in use by the other thread.
#120,v,g,n,n,n,PM_FPU_ISSUE_STEERING,FPU issue steering
##320E4
An instruction was steered to a specific execution unit at issue time. Some instructions are limited to execution on a specific unit. The issue logic will attempt to steer dependent floating-point instructions to the unit that is producing the result it is dependent upon.
#121,v,g,n,n,n,PM_FPU_ISSUE_ST_FOLDED,FPU issue a folded store
##320E2
A store was issued to the floating point unit that was dependant on the result of a previous instruction. The result it folded into the store allowing the store to execute earlier.
#122,v,g,n,n,n,PM_FPU_SINGLE,FPU executed single precision instruction
##C1030
FPU is executing single precision instruction. Combined Unit 0 + Unit 1
#123,v,g,n,s,n,PM_FREQ_UP,Frequency is being slewed up due to Power Management
##0003C
Processor frequency was sped up due to power management
#124,u,g,n,n,n,PM_FXU1_BUSY_FXU0_IDLE,FXU1 busy FXU0 idle
##00050
FXU0 was idle while FXU1 was busy
#125,v,g,n,n,n,PM_FXU1_FIN,FXU1 produced a result
##00016
The Fixed Point unit 1 finished an instruction and produced a result. Instructions that finish may not necessary complete.
#126,v,g,n,n,n,PM_FXU_PIPELINED_MULT_DIV,Fix point multiply/divide pipelined
##2108E
A fixed point multiple or divide was dispatched while another one was in progress. A sequence of fixed point multiplies or divides can be pipelined, one every other cycle, but any other instruction will stall until the multiply or divide  instructions are finished.
#127,v,g,n,n,n,PM_GCT_FULL_CYC,Cycles GCT full
##400A6
The Global Completion Table is completely full.
#128,v,g,n,c,n,PM_GXI_ADDR_CYC_BUSY,Inbound GX address utilization (# of cycle address is in valid)
##503A8
Number of bus cycles the inbound GX bus is receiving an address. The signal is delivered at GX Controller speed and the count must be scaled accordingly
#129,v,g,n,c,n,PM_GXI_CYC_BUSY,Inbound GX bus utilizations (# of cycles in use)
##503A6
Number of bus cycles the inbound GX bus is in use. The signal is delivered at GX Controller speed and the count must be scaled accordingly
#130,v,g,n,c,n,PM_GXI_DATA_CYC_BUSY,Inbound GX Data utilization (# of cycle data in is valid)
##503AA
Number of bus cycles the inbound GX bus is receiving data. The signal is delivered at GX Controller speed and the count must be scaled accordingly
#131,v,g,n,c,n,PM_GXO_ADDR_CYC_BUSY,Outbound GX address utilization (# of cycles address out is valid)
##503A2
Number of bus cycles the outbound GX bus is receiving an address. The signal is delivered at GX Controller speed and the count must be scaled accordingly
#132,v,g,n,c,n,PM_GXO_CYC_BUSY,Outbound GX bus utilizations (# of cycles in use)
##503A0
Number of bus cycles the outbound GX bus is in use. The signal is delivered at GX Controller speed and the count must be scaled accordingly
#133,v,g,n,c,n,PM_GXO_DATA_CYC_BUSY,Outbound GX Data utilization (# of cycles data out is valid)
##503A4
Number of bus cycles the outbound GX bus is receiving data. The signal is delivered at GX Controller speed and the count must be scaled accordingly
#134,v,g,n,c,n,PM_GX_DMA_READ,DMA Read Request
##503AC
The GX Bus Controller processed a DMA read request. The signal is delivered at GX Controller speed and the count must be scaled accordingly
#135,v,g,n,c,n,PM_GX_DMA_WRITE,All DMA Write Requests (including dma wrt lgcy)
##503AE
The GX Bus Controller processed a DMA write request. The signal is delivered at GX Controller speed and the count must be scaled accordingly
#136,v,g,n,n,n,PM_IBUF_FULL_CYC,Cycles instruction buffer full
##400A4
Cycles with the Instruction Buffer was full. The Instruction Buffer is a circular queue of 64 instructions per thread, organized as 16 groups of 4 instructions.
#137,v,g,n,n,n,PM_IC_DEMAND_L2_BHT_REDIRECT,L2 I cache demand request due to BHT redirect
##420EA
A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (CR mispredict).
#138,v,g,n,n,n,PM_IC_DEMAND_L2_BR_REDIRECT,L2 I cache demand request due to branch redirect
##420EC
A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (either ALL mispredicted or Target).
#139,v,g,n,n,n,PM_IC_PREF_REQ,Instruction prefetch requests
##400AC
An instruction prefetch request has been made.
#140,v,g,n,n,n,PM_IC_PREF_WRITE,Instruction prefetch written into I cache
##430C0
Number of Instruction Cache entries written because of prefetch. Prefetch entries are marked least recently used and are candidates for eviction if they are not needed to satify a demand fetch.
#141,v,g,n,n,n,PM_IC_RELOAD_SHR,I cache line reloading to be shared by threads
##400AE
An Instruction Cache request was made by this thread and the cache line was already in the cache for the other thread. The line is marked valid for both threads.
#142,v,g,n,n,n,PM_IC_REQ,I cache demand of prefetch request
##400AA
An instruction fetch request was made. The request may have been a prefetch request or a demand request.
#143,v,g,n,n,n,PM_IERAT_MISS,IERAT miss count
##420EE
A translation request missed the Instruction Effective to Real Address Translation (ERAT) table
#144,v,g,n,n,n,PM_IFU_FIN,IFU finished an instruction
##430C4
The Instruction Fetch Unit finished an instruction
#145,v,g,n,n,n,PM_INST_CMPL,Instructions completed
##00002
Number of PPC instructions completed. 
#146,v,g,n,n,n,PM_INST_DISP_LLA,Instruction dispatched under load look ahead
##31082
Instructions dispatched while Load Look ahead is active.
#147,v,g,n,n,n,PM_INST_FETCH_CYC,Cycles at least 1 instruction fetched
##420E8
Cycles when at least one instruction was sent from the fetch unit to the decode unit.
#148,v,g,n,n,n,PM_INST_FROM_DL2L3_MOD,Instruction fetched from distant L2 or L3 modified
##42044
An instruction fetch group was fetched with modified  (M) data from an L2 or L3 on a distant module. Fetch groups can contain up to 8 instructions
#149,v,g,n,n,n,PM_INST_FROM_L1,Instruction fetched from L1
##400A2
An instruction fetch group was fetched from L1. Fetch Groups can contain up to 8 instructions
#150,v,g,n,n,n,PM_INST_FROM_L25_SHR,Instruction fetched from L2.5 shared
##42046
An instruction fetch group was fetched with shared  (T or SL) data from the L2 of a chip on the same module as this processor is located. Fetch groups can contain up to 8 instructions.
#151,v,g,n,n,n,PM_INST_FROM_L2MISS,Instructions fetched missed L2
##42054
An instruction fetch group was fetched from beyond L2.
#152,v,g,n,n,n,PM_INST_FROM_LMEM,Instruction fetched from local memory
##42042
An instruction fetch group was fetched from memory attached to the same module this proccessor is located on. Fetch groups can contain up to 8 instructions
#153,v,g,n,n,n,PM_INST_IMC_MATCH_CMPL,IMC matched instructions completed
##0000A
Number of instructions resulting from the marked instructions expansion that completed.
#154,v,g,n,n,n,PM_INST_PTEG_1ST_HALF,Instruction table walk matched in first half primary PTEG
##91088
A translation request for a instruction address was satisfied using the primary page table hash. The matching Page Table Entry is one of the first four PTE entries of the primary PTEG
#155,v,g,n,n,n,PM_INST_PTEG_2ND_HALF,Instruction table walk matched in second half primary PTEG
##9108A
A translation request for a instruction address was satisfied using the primary page table hash. The matching Page Table Entry is one of the second four PTE entries of the primary PTEG
#156,v,g,n,n,n,PM_INST_PTEG_SECONDARY,Instruction table walk matched in secondary PTEG
##9108C
A translation request for a instruction address was satisfied using the secondary page table hash. 
#157,v,g,n,n,n,PM_INST_TABLEWALK_CYC,Cycles doing instruction tablewalks
##920EA
Cycles an Instruction Tablewalk is active. 
#158,u,g,n,n,n,PM_ISLB_MISS,Instruction SLB misses
##830C0
A SLB miss for an instruction fetch as occurred
#159,v,g,n,n,n,PM_ITLB_REF,Instruction TLB reference
##920E2
Number of Instruction Translation requests from the ERAT. 
#160,v,g,n,n,n,PM_L1_DCACHE_RELOAD_VALID,L1 reload data source valid
##0000E
The data source information is valid,the data cache has been reloaded. Prior to POWER5+ this included data cache reloads due to prefetch activity. With POWER5+ this now only includes reloads due to demand loads.
#161,v,g,n,n,n,PM_L1_PREF,L1 cache data prefetches
##81084
A request to prefetch data into the L1 was made
#162,v,g,n,n,n,PM_L1_WRITE_CYC,Cycles writing to instruction L1
##430C2
Cycles that a cache line was written to the instruction cache.
#163,v,g,n,c,n,PM_L2SA_CASTOUT_MOD,L2 slice A castouts - Modified
##506A0
An L2 line in the Modified state was castout. Reported per slice.
#164,v,g,n,c,n,PM_L2SA_CASTOUT_SHR,L2 slice A castouts - Shared
##506A2
An L2 line in the Shared state was castout. Reported per slice.
#165,v,g,n,c,n,PM_L2SA_DC_INV,L2 slice A D cache invalidate
##506A6
The L2 invalidated a line in processor's data cache. This is caused by the L2 line being cast out or invalidated. Reported per slice.
#166,v,g,n,c,n,PM_L2SA_IC_INV,L2 slice A I cache invalidate
##506A4
The L2 invalidated a line in processor's instruction cache. This is caused by the L2 line being cast out or invalidated. Reported per slice.
#167,v,g,n,c,n,PM_L2SA_LD_HIT,L2 slice A load hits
##507A2
A load request (data or instruction) hit in the L2 directory. Includes speculative, prefetched, and demand requests. This event includes all requests to this L2 from all sources. Reported per slice.
#168,v,g,n,n,n,PM_L2SA_LD_MISS_DATA,L2 slice A data load misses
##504A2
A data load request from this thread hit in the L2 directory. Includes speculative, prefetched, and demand requests. Reported per slice.
#169,v,g,n,n,n,PM_L2SA_LD_MISS_INST,L2 slice A instruction load misses
##505A2
An instruction load request from this thread hit in the L2 directory. Includes speculative, prefetched, and demand requests. Reported per slice.
#170,v,g,n,c,n,PM_L2SA_LD_REQ,L2 slice A load requests 
##507A0
A load request (data or instruction) was received by the L2 directory. Includes speculative, prefetched, and demand requests. This event includes all requests to this L2 from all sources. Reported per slice.
#171,v,g,n,n,n,PM_L2SA_LD_REQ_DATA,L2 slice A data load requests
##504A0
A data load request from this thread was received by the L2 directory. Includes speculative, prefetched, and demand requests. Reported per slice.
#172,v,g,n,n,n,PM_L2SA_LD_REQ_INST,L2 slice A instruction load requests
##505A0
An instruction load request from this thread was received by the L2 directory. Includes speculative, prefetched, and demand requests. Reported per slice.
#173,v,g,n,n,n,PM_L2SA_MISS,L2 slice A misses
##505A4
Total L2 misses (loads and stores) from this thread. Includes speculative, prefetched, and demand requests. Reported per slice.
#174,v,g,n,c,n,PM_L2SA_ST_HIT,L2 slice A store hits
##507A6
A store request hit in the L2 directory. This event includes all requests to this L2 from all sources. Reported per slice.
#175,v,g,n,n,n,PM_L2SA_ST_MISS,L2 slice A store misses
##504A6
A store request from this thread missed in the L2 directory. Reported per slice.
#176,v,g,n,n,n,PM_L2SA_ST_REQ,L2 slice A store requests
##504A4,507A4
A store request  was received by the L2 directory. This event includes all requests to this L2 from all sources. Stores are counted after gathering in the L2 store queues. Reported per slice.
#177,v,g,n,c,n,PM_L2SB_CASTOUT_MOD,L2 slice B castouts - Modified
##506A8
An L2 line in the Modified state was castout. Reported per slice.
#178,v,g,n,c,n,PM_L2SB_CASTOUT_SHR,L2 slice B castouts - Shared
##506AA
An L2 line in the Shared state was castout. Reported per slice.
#179,v,g,n,c,n,PM_L2SB_DC_INV,L2 slice B D cache invalidate
##506AE
The L2 invalidated a line in processor's data cache. This is caused by the L2 line being cast out or invalidated. Reported per slice.
#180,v,g,n,c,n,PM_L2SB_IC_INV,L2 slice B I cache invalidate
##506AC
The L2 invalidated a line in processor's instruction cache. This is caused by the L2 line being cast out or invalidated. Reported per slice.
#181,v,g,n,c,n,PM_L2SB_LD_HIT,L2 slice B load hits
##507AA
A load request (data or instruction) hit in the L2 directory. Includes speculative, prefetched, and demand requests. This event includes all requests to this L2 from all sources. Reported per slice.
#182,v,g,n,n,n,PM_L2SB_LD_MISS_DATA,L2 slice B data load misses
##504AA
A data load request from this thread hit in the L2 directory. Includes speculative, prefetched, and demand requests. Reported per slice.
#183,v,g,n,n,n,PM_L2SB_LD_MISS_INST,L2 slice B instruction load misses
##505AA
An instruction load request from this thread hit in the L2 directory. Includes speculative, prefetched, and demand requests. Reported per slice.
#184,v,g,n,c,n,PM_L2SB_LD_REQ,L2 slice B load requests 
##507A8
A load request (data or instruction) was received by the L2 directory. Includes speculative, prefetched, and demand requests. This event includes all requests to this L2 from all sources. Reported per slice.
#185,v,g,n,n,n,PM_L2SB_LD_REQ_DATA,L2 slice B data load requests
##504A8
A data load request from this thread was received by the L2 directory. Includes speculative, prefetched, and demand requests. Reported per slice.
#186,v,g,n,n,n,PM_L2SB_LD_REQ_INST,L2 slice B instruction load requests
##505A8
An instruction load request from this thread was received by the L2 directory. Includes speculative, prefetched, and demand requests. Reported per slice.
#187,v,g,n,n,n,PM_L2SB_MISS,L2 slice B misses
##505AC
Total L2 misses (loads and stores) from this thread. Includes speculative, prefetched, and demand requests. Reported per slice.
#188,v,g,n,c,n,PM_L2SB_ST_HIT,L2 slice B store hits
##507AE
A store request hit in the L2 directory. This event includes all requests to this L2 from all sources. Reported per slice.
#189,v,g,n,n,n,PM_L2SB_ST_MISS,L2 slice B store misses
##504AE
A store request from this thread missed in the L2 directory. Reported per slice.
#190,v,g,n,n,n,PM_L2SB_ST_REQ,L2 slice B store requests
##504AC,507AC
A store request  was received by the L2 directory. This event includes all requests to this L2 from all sources. Stores are counted after gathering in the L2 store queues. Reported per slice.
#191,v,g,n,n,n,PM_L2_PREF_LD,L2 cache prefetches
##81086
A request to prefetch load data into L2 was made
#192,v,g,n,n,n,PM_L2_PREF_ST,L2 cache prefetches
##81088
A request to prefetch the target of a store into L2 was made
#193,v,g,n,n,n,PM_L2_ST_MISS_DATA,L2 data store misses
##50434
A store request from this thread missed in the L2 directory. Total for all slices.
#194,v,g,n,c,n,PM_L3SA_HIT,L3 slice A hits
##500A2
Number of attempts made by this chip cores that resulted in an L3 hit. Reported per L3 slice
#195,v,g,n,c,n,PM_L3SA_MISS,L3 slice A misses
##500A4
Number of attempts made by this chip cores that resulted in an L3 miss. Reported per L3 slice
#196,v,g,n,c,n,PM_L3SA_REF,L3 slice A references
##500A0
Number of attempts made by this chip cores to find data in the L3. Reported per L3 slice 
#197,v,g,n,c,n,PM_L3SB_HIT,L3 slice B hits
##500AA
Number of attempts made by this chip cores that resulted in an L3 hit. Reported per L3 slice
#198,v,g,n,n,n,PM_L3SB_MISS,L3 slice B misses
##500AC
Number of attempts made by this chip cores that resulted in an L3 miss. Reported per L3 slice
#199,v,g,n,c,n,PM_L3SB_REF,L3 slice B references
##500A8
Number of attempts made by this chip cores to find data in the L3. Reported per L3 slice 
#200,v,g,n,n,n,PM_LARX,Larx executed
##830CA
A larx (lwarx or ldarx) was sent to the nest
#201,v,g,n,n,n,PM_LARX_L1HIT,larx hits in L1
##830C2
A larxa was sent to the nest
#202,v,g,n,n,n,PM_LD_MISS_L1,L1 D cache load misses
##000F0,800A0
Load references that miss the Level 1 Data cache. Combined unit 0 + 1.
#203,v,g,n,n,n,PM_LD_REF_L1,L1 D cache load references
##800A2,800AA
Load references to the Level 1 Data Cache. Combined unit 0 + 1.
#204,v,g,n,n,n,PM_LSU0_DERAT_MISS,LSU0 DERAT misses
##91086
A data request (load or store) from LSU Unit 0 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.
#205,v,g,n,n,n,PM_LSU0_LDF,LSU0 executed Floating Point load instruction
##800A4
A floating point load was executed from LSU unit 0
#206,v,g,n,n,n,PM_LSU0_NCLD,LSU0 non-cacheable loads
##820EA
A non-cacheable load was executed by unit 0.
#207,v,g,n,n,n,PM_LSU0_NCST,LSU0 non-cachable stores
##820EC
A non-cacheable store was executed by unit 0.
#208,v,g,n,n,n,PM_LSU0_REJECT,LSU0 reject
##A1086
Load Store Unit 0 rejected an instruction.
#209,v,g,n,n,n,PM_LSU0_REJECT_DERAT_MPRED,LSU0 reject due to mispredicted DERAT
##A00A2
Load Store Unit 0 rejected an instruction because the Effective Address was improperly predicted. This is a fast reject and will be immediately redispatched. On the redispatch, the scratch register is used to provide the correct effective address for the D-ERAT access to resolve the incorrect guess.
#210,v,g,n,n,n,PM_LSU0_REJECT_EXTERN,LSU0 external reject request 
##A1084
Load Store Unit 0 rejected an instruction due to a request from the decode unit or the fixed point unit.
#211,v,g,n,n,n,PM_LSU0_REJECT_L2MISS,LSU0 L2 miss reject
##900A4
Load Store Unit 0 rejected a load due to a correctable error in the L2. This is a fast reject and will be immediately redispatched. 
#212,v,g,n,n,n,PM_LSU0_REJECT_L2_CORR,LSU0 reject due to L2 correctable error
##A1080
Load Store Unit 0 rejected an instruction. The reject was a collision type reject. The IDU immediately redispatches the rejected instruction. The result is eleven (11) cycles, dispatch-to-dispatch, in the best case. 
#213,v,g,n,n,n,PM_LSU0_REJECT_LHS,LSU0 load hit store reject
##900A6
Load Store Unit 0 rejected a load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully.
#214,v,g,n,n,n,PM_LSU0_REJECT_NO_SCRATCH,LSU0 reject due to scratch register not available
##A1082
Load Store Unit 0 rejected an instruction because the internal scratch register was not available. This is a fast reject and will be immediately redispatched. 
#215,v,g,n,n,n,PM_LSU0_REJECT_PARTIAL_SECTOR,LSU0 reject due to partial sector valid
##A00A6
Load Store Unit 0 rejected an instruction that had a L1 Data Cache line hit but the critical sector was not valid. Since the cache line is partially validated, a reload of that cache line is in progress. This is a fast reject and will be immediately redispatched. 
#216,v,g,n,n,n,PM_LSU0_REJECT_SET_MPRED,LSU0 reject due to mispredicted set
##A00A4
Load Store Unit 0 rejected an instruction because the cache set was improperly predicted. This is a fast reject and will be immediately redispatched. 
#217,v,g,n,n,n,PM_LSU0_REJECT_STQ_FULL,LSU0 reject due to store queue full
##A00A0
Load Store Unit 0 rejected a store because the store request queue was full. This is a fast reject and will be immediately redispatched.
#218,v,g,n,n,n,PM_LSU0_REJECT_ULD,LSU0 unaligned load reject
##900A0
Load Store Unit 0 rejected a load instruction that spans a cache line boundary (128B). The LSU will pass the incremented address information to the FXU via the scratch register so that the subsequent address generation will access the next line.
#219,v,g,n,n,n,PM_LSU0_REJECT_UST,LSU0 unaligned store reject
##900A2
Load Store Unit 0 rejected a store instruction that spans a cache line boundary (128B). The LSU will pass the incremented address information to the FXU via the scratch register so that the subsequent address generation will access the next line.
#220,v,g,n,n,n,PM_LSU1_DERAT_MISS,LSU1 DERAT misses
##9108E
A data request (load or store) from LSU Unit 1 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.
#221,v,g,n,n,n,PM_LSU1_LDF,LSU1 executed Floating Point load instruction
##800AC
A floating point load was executed from LSU unit 1
#222,v,g,n,n,n,PM_LSU1_REJECT,LSU1 reject
##A108E
Load Store Unit 1 rejected an instruction.
#223,v,g,n,n,n,PM_LSU1_REJECT_DERAT_MPRED,LSU1 reject due to mispredicted DERAT
##A00AA
Load Store Unit 1 rejected an instruction because the Effective Address was improperly predicted. This is a fast reject and will be immediately redispatched. On the redispatch, the scratch register is used to provide the correct effective address for the D-ERAT access to resolve the incorrect guess.
#224,v,g,n,n,n,PM_LSU1_REJECT_EXTERN,LSU1 external reject request 
##A108C
Load Store Unit 1 rejected an instruction due to a request from the decode unit or the fixed point unit.
#225,v,g,n,n,n,PM_LSU1_REJECT_L2_CORR,LSU1 reject due to L2 correctable error
##A1088
Load Store Unit 1 rejected an instruction. The reject was a collision type reject. The IDU immediately redispatches the rejected instruction. The result is eleven (11) cycles, dispatch-to-dispatch, in the best case. 
#226,v,g,n,n,n,PM_LSU1_REJECT_LHS,LSU1 load hit store reject
##900AE
Load Store Unit 1 rejected a load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully.
#227,v,g,n,n,n,PM_LSU1_REJECT_NO_SCRATCH,LSU1 reject due to scratch register not available
##A108A
Load Store Unit 1 rejected an instruction because the internal scratch register was not available. This is a fast reject and will be immediately redispatched. 
#228,v,g,n,n,n,PM_LSU1_REJECT_PARTIAL_SECTOR,LSU1 reject due to partial sector valid
##A00AE
Load Store Unit 1 rejected an instruction that had a L1 Data Cache line hit but the critical sector was not valid. Since the cache line is partially validated, a reload of that cache line is in progress. This is a fast reject and will be immediately redispatched. 
#229,v,g,n,n,n,PM_LSU1_REJECT_SET_MPRED,LSU1 reject due to mispredicted set
##A00AC
Load Store Unit 1 rejected an instruction because the cache set was improperly predicted. This is a fast reject and will be immediately redispatched. 
#230,v,g,n,n,n,PM_LSU1_REJECT_STQ_FULL,LSU1 reject due to store queue full
##A00A8
Load Store Unit 1 rejected a store because the store request queue was full. This is a fast reject and will be immediately redispatched.
#231,v,g,n,n,n,PM_LSU1_REJECT_ULD,LSU1 unaligned load reject
##900A8
Load Store Unit 1 rejected a load instruction that spans a cache line boundary (128B). The LSU will pass the incremented address information to the FXU via the scratch register so that the subsequent address generation will access the next line.
#232,v,g,n,n,n,PM_LSU1_REJECT_UST,LSU1 unaligned store reject
##900AA
Load Store Unit 1 rejected a store instruction that spans a cache line boundary (128B). The LSU will pass the incremented address information to the FXU via the scratch register so that the subsequent address generation will access the next line.
#233,v,g,n,n,n,PM_LSU_BOTH_BUS,Both data return buses busy simultaneously
##8108A
Data was returned on both data buses
#234,v,g,n,n,n,PM_LSU_DERAT_MISS_CYC,DERAT miss latency
##00006
Cycles waiting on a demand D-ERAT miss. On POWER6 there can only be one demand miss outstanding at a time. Dividing cycles waiting on a demand miss by the number of demand misses gives the average latency to satisfy a demand miss
#235,v,g,n,n,n,PM_LSU_FLUSH_ALIGN,Flush caused by alignement exception
##220EC
A flush was initiated by the Load Store Unit in response to an unaligned operand
#236,v,g,n,n,n,PM_LSU_FLUSH_DSI,Flush caused by DSI
##220EE
A flush was initiated by the Load Store Unit in response to a Data Storage Interrupt
#237,u,g,n,s,n,PM_LSU_LMQ_FULL_CYC,Cycles LMQ full
##8108C
The Load Miss Queue was full.
#238,v,g,n,n,n,PM_LSU_REJECT,LSU reject
##A1030
The Load Store Unit rejected an instruction. Combined Unit 0 + 1
#239,v,g,n,n,n,PM_LSU_REJECT_L2_CORR,LSU reject due to L2 correctable error
##A1032
The Load Store Unit rejected a load due to a correctable error in the L2. This is a fast reject and will be immediately redispatched. Combined Unit 0 + 1
#240,v,g,n,n,n,PM_LSU_REJECT_LHS,Load hit store reject
##90034
The Load Store Unit rejected a load load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully. Combined Unit 0 + 1
#241,v,g,n,n,n,PM_LSU_REJECT_LHS_BOTH,Load hit store reject both units
##9003A
Both Load Store Units were rejecting a load instruction that had an address overlap with an older store in the store queue.
#242,v,g,n,n,n,PM_LSU_REJECT_PARTIAL_SECTOR,LSU reject due to partial sector valid
##A0034
The Load Store Unit rejected an instruction that had a L1 Data Cache line hit but the critical sector was not valid. Since the cache line is partially validated, a reload of that cache line is in progress. This is a fast reject and will be immediately redispatched. Combined Unit 0 + 1
#243,v,g,n,n,n,PM_LSU_REJECT_STEAL,LSU reject due to steal
##900AC
The Load Store Unit rejected an instruction because a cache or cache directory was being updated. This is a fast reject and will be immediately redispatched. Combined Unit 0 + 1
#244,u,g,n,s,n,PM_LSU_SRQ_EMPTY_CYC,Cycles SRQ empty
##0001C
The Store Request Queue is empty
#245,v,g,n,n,n,PM_LSU_ST_CHAINED,number of chained stores
##820EE
The Load Store Unit chained two store requests together and sent them as one to the L2
#246,v,g,n,n,n,PM_LWSYNC,Isync instruction completed
##8108E
A lightweight sync instruction completed.
#247,v,g,n,c,n,PM_MEM0_DP_CL_WR_GLOB,cacheline write setting dp to global side 0
##502A4
A memory cacheline write on memory controller 0 from a remote node. This event is sent from the Memory Controller clock domain and must be scaled accordingly.
#248,v,g,n,c,n,PM_MEM0_DP_CL_WR_LOC,cacheline write setting dp to local side 0
##502A6
A memory cacheline write on memory controller 0 from a local node. This event is sent from the Memory Controller clock domain and must be scaled accordingly.
#249,v,g,n,c,n,PM_MEM0_DP_RQ_GLOB_LOC,Memory read queue marking cache line double pump state from global to local side 0
##502A0
A memory cacheline read on memory controller 0 changed the double pump state from global to local. This event is sent from the Memory Controller clock domain and must be scaled accordingly.
#250,v,g,n,c,n,PM_MEM0_DP_RQ_LOC_GLOB,Memory read queue marking cache line double pump state from local to global side 0
##502A2
A memory cacheline read on memory controller 0 changed the double pump state from local to global. This event is sent from the Memory Controller clock domain and must be scaled accordingly.
#251,v,g,n,c,n,PM_MEM1_DP_CL_WR_GLOB,cacheline write setting dp to global side 1
##502AC
A memory cacheline write on memory controller 1 from a remote node. This event is sent from the Memory Controller clock domain and must be scaled accordingly.
#252,v,g,n,c,n,PM_MEM1_DP_CL_WR_LOC,cacheline write setting dp to local side 1
##502AE
A memory cacheline write on memory controller 1 from a local node. This event is sent from the Memory Controller clock domain and must be scaled accordingly.
#253,v,g,n,c,n,PM_MEM1_DP_RQ_GLOB_LOC,Memory read queue marking cache line double pump state from global to local side 1
##502A8
A memory cacheline read on memory controller 1 changed the double pump state from global to local. This event is sent from the Memory Controller clock domain and must be scaled accordingly.
#254,v,g,n,c,n,PM_MEM1_DP_RQ_LOC_GLOB,Memory read queue marking cache line double pump state from local to global side 1
##502AA
A memory cacheline read on memory controller 1 changed the double pump state from local to global. This event is sent from the Memory Controller clock domain and must be scaled accordingly.
#255,v,g,n,c,n,PM_MEM_DP_CL_WR_LOC,cache line write setting double pump state to local
##50234
A memory cacheline write from a local node. This event is sent from the Memory Controller clock domain and must be scaled accordingly. Combined unit 0 + 1.
#256,v,g,n,n,m,PM_MRK_DATA_FROM_DL2L3_MOD,Marked data loaded from distant L2 or L3 modified
##0304C
The processor's Data Cache was reloaded with modified (M) data from an L2  or L3 on a distant module due to a marked load.
#257,v,g,n,n,m,PM_MRK_DATA_FROM_L25_SHR,Marked data loaded from L2.5 shared
##0304E
The processor's Data Cache was reloaded with shared  (T or SL) data from the L2 of a chip on the same module as this processor is located due to a marked load.
#258,v,g,n,n,m,PM_MRK_DATA_FROM_LMEM,Marked data loaded from local memory
##0304A
The processor's Data Cache was reloaded due to a marked load from memory attached to the same module this proccessor is located on.
#259,v,g,n,n,m,PM_MRK_DTLB_REF,Marked Data TLB reference
##920E0
Total number of Data TLB references by a marked instruction for all page sizes. Page size is determined at TLB reload time.
#260,v,g,n,n,m,PM_MRK_FPU0_FIN,Marked instruction FPU0 processing finished
##D00A2
Floating Point Unit 0 finished a marked instruction.
#261,v,g,n,n,m,PM_MRK_FPU1_FIN,Marked instruction FPU1 processing finished
##D00AA
Floating Point Unit 1 finished a marked instruction.
#262,v,g,n,n,m,PM_MRK_INST_FIN,Marked instruction finished
##00018
One of the execution units finished a marked instruction. Instructions that finish may not necessary complete
#263,v,g,n,n,m,PM_MRK_INST_TIMEO,Marked Instruction finish timeout 
##0003E
The number of instructions finished since the last progress indicator from a marked instruction exceeded the threshold. The marked instruction was flushed.
#264,b,g,n,n,m,PM_MRK_LSU0_REJECT_L2MISS,LSU0 marked L2 miss reject
##930C4
This event never worked and was replaced by marked DERAT guess wrong
#265,v,g,n,n,m,PM_MRK_LSU0_REJECT_LHS,LSU0 marked load hit store reject
##930C6
Load Store Unit 0 rejected a marked load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully.
#266,v,g,n,n,m,PM_MRK_LSU0_REJECT_ULD,LSU0 marked unaligned load reject
##930C0
Load Store Unit 0 rejected a marked load instruction that spans a cache line boundary (128B). The LSU will pass the incremented address information to the FXU via the scratch register so that the subsequent address generation will access the next line.
#267,v,g,n,n,m,PM_MRK_LSU0_REJECT_UST,LSU0 marked unaligned store reject
##930C2
Load Store Unit 0 rejected a marked store instruction that spans a cache line boundary (128B). The LSU will pass the incremented address information to the FXU via the scratch register so that the subsequent address generation will access the next line.
#268,v,g,n,n,m,PM_MRK_LSU1_REJECT_LHS,LSU1 marked load hit store reject
##930CE
Load Store Unit 1 rejected a marked load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully.
#269,v,g,n,n,m,PM_MRK_LSU1_REJECT_ULD,LSU1 marked unaligned load reject
##930C8
Load Store Unit 1 rejected a marked load instruction that spans a cache line boundary (128B). The LSU will pass the incremented address information to the FXU via the scratch register so that the subsequent address generation will access the next line.
#270,v,g,n,n,m,PM_MRK_LSU1_REJECT_UST,LSU1 marked unaligned store reject
##930CA
Load Store Unit 1 rejected a marked store instruction that spans a cache line boundary (128B). The LSU will pass the incremented address information to the FXU via the scratch register so that the subsequent address generation will access the next line.
#271,v,g,n,n,m,PM_MRK_LSU_DERAT_MISS,Marked DERAT miss
##00012,00012
A marked instruction missed the DERAT
#272,c,g,n,n,m,PM_MRK_LSU_FIN,Marked instruction LSU processing finished
##0001A
One of the Load/Store Units finished a marked instruction. Instructions that finish may not necessary complete
#273,v,g,n,n,m,PM_MRK_LSU_REJECT_LHS,Marked load hit store reject
##93030
The Load Store Unit rejected a marked load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully.
#274,v,g,n,n,m,PM_MRK_LSU_REJECT_ULD,Marked unaligned load reject
##93032
The Load Store Unit rejected a marked load instruction that spans a cache line boundary (128B). The LSU will pass the incremented address information to the FXU via the scratch register so that the subsequent address generation will access the next line.
#275,v,g,n,n,m,PM_MRK_PTEG_FROM_DL2L3_MOD,Marked PTEG loaded from distant L2 or L3 modified
##12044
A Page Table Entry was loaded into the ERAT with modified (M) data from an L2  or L3 on a distant module due to a marked load or store.
#276,v,g,n,n,m,PM_MRK_PTEG_FROM_L25_SHR,Marked PTEG loaded from L2.5 shared
##12046
A Page Table Entry was loaded into the ERAT with shared  (T or SL) data from the L2 of a chip on the same module as this processor is located due to a marked load or store.
#277,v,g,n,n,m,PM_MRK_PTEG_FROM_L2MISS,Marked PTEG loaded from L2 miss
##12054
A Page Table Entry was loaded into the ERAT but not from the local L2 due to a marked load or store.
#278,v,g,n,n,m,PM_MRK_PTEG_FROM_LMEM,Marked PTEG loaded from local memory
##12042
A Page Table Entry was loaded into the ERAT from memory attached to the same module this proccessor is located on due to a marked load or store.
#279,v,g,n,n,m,PM_MRK_STCX_FAIL,Marked STCX failed
##830C4
A marked stcx (stwcx or stdcx) failed
#280,v,g,n,n,m,PM_MRK_VMX0_LD_WRBACK,Marked VMX0 load writeback valid
##600A6
A marked load returned data on VMX unit 0
#281,v,g,n,n,m,PM_MRK_VMX1_LD_WRBACK,Marked VMX1 load writeback valid
##600AE
A marked load returned data on VMX unit 1
#282,v,g,n,n,m,PM_MRK_VMX_COMPLEX_ISSUED,Marked VMX instruction issued to complex
##700AC
A marked instruction was issued to the VMX Complex pipeline.
#283,v,g,n,n,m,PM_MRK_VMX_FLOAT_ISSUED,Marked VMX instruction issued to float
##700A8
A marked instruction was issued to the VMX Float pipeline.
#284,v,g,n,n,m,PM_MRK_VMX_PERMUTE_ISSUED,Marked VMX instruction issued to permute
##700AE
A marked instruction was issued to the VMX Permute pipeline.
#285,v,g,n,n,m,PM_MRK_VMX_SIMPLE_ISSUED,Marked VMX instruction issued to simple
##700AA
A marked instruction was issued to the VMX Simple pipeline.
#286,v,g,n,n,m,PM_MRK_VMX_ST_ISSUED,Marked VMX store issued
##B00A8
A marked VMX Store was issued
#287,v,g,n,n,n,PM_NO_ITAG_CYC,Cyles no ITAG available
##400A8
Cycles when no ITAGS are available. This condition will block instruction fetch.
#288,v,g,n,n,n,PM_PMC3_OVERFLOW,PMC3 Overflow
##00014
Overflows from PMC3 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.
#289,v,g,n,n,n,PM_PTEG_FROM_DL2L3_MOD,PTEG loaded from distant L2 or L3 modified
##1304C
A Page Table Entry was loaded into the ERAT with modified (M) data from an L2  or L3 on a distant module due to a demand load or store.
#290,v,g,n,n,n,PM_PTEG_FROM_L25_SHR,PTEG loaded from L2.5 shared
##1304E
A Page Table Entry was loaded into the ERAT with shared  (T or SL) data from the L2 of a chip on the same module as this processor is located due to a demand load or store.
#291,v,g,n,n,n,PM_PTEG_FROM_LMEM,PTEG loaded from local memory
##1304A
A Page Table Entry was loaded into the ERAT from memory attached to the same module this proccessor is located on  due to a demand load or store.
#292,v,g,n,n,n,PM_PTEG_RELOAD_VALID,PTEG reload valid
##130C8
A Page Table Entry was loaded into the ERAT. POWER6 does not have a TLB
#293,v,g,n,n,n,PM_PURR,PURR Event
##00010
The Processor Utilization of Resources Register was incremented. The PURR registers will be incremented roughly in the ratio in which the instructions are dispatched from the two threads. 
#294,v,g,n,n,n,PM_SLB_MISS,SLB misses
##83032
Total of all Segment Lookaside Buffer (SLB) misses, Instructions + Data.
#295,v,g,n,n,n,PM_STCX,STCX executed
##830C6
STCX executed
#296,v,g,n,n,n,PM_STCX_CANCEL,stcx cancel by core
##830CC
A conditional store request to the nest was canceled by the core
#297,v,g,n,n,n,PM_STCX_FAIL,STCX failed
##830CE
A stcx (stwcx or stdcx) failed
#298,v,g,n,c,n,PM_ST_HIT_L2,L2 D cache store hits
##50734
L2 D cache store hits
#299,v,g,n,n,n,PM_ST_MISS_L1,L1 D cache store misses
##800A8
A store missed the dcache. Combined Unit 0 + 1.
#300,v,g,n,n,n,PM_ST_REF_L1,L1 D cache store references
##80034,800A6,800AE
Store references to the Data Cache. Combined Unit 0 + 1.
#301,v,g,n,n,n,PM_ST_REF_L1_BOTH,Both units L1 D cache store reference
##8003A
Both Load Store Units executed store references to the Data Cache at the same time.
#302,v,g,n,n,n,PM_SUSPENDED,Suspended
##00000
The counter is suspended (does not count).
#303,v,g,n,n,n,PM_SYNC_CYC,Sync duration
##920EC
Cycles a SYNC instruction is pending. Starts counting when the request is sent to the nest until the nest responds.
#304,v,g,n,s,n,PM_THRD_BOTH_RUN_CYC,Both threads in run cycles
##00004
Cycles when both threads had their run latches set. Operating systems use the run latch to indicate when they are doing useful work. 
#305,v,g,n,n,n,PM_THRD_L2MISS,Thread in L2 miss
##31080
This thread has a L2 miss pending.
#306,v,g,n,s,n,PM_THRD_LLA_BOTH_CYC,Both threads in Load Look Ahead
##00008
Cycles when both threads where in load look ahead mode.
#307,v,g,n,n,n,PM_THRD_PRIO_3_CYC,Cycles thread running at priority level 3
##22040
Cycles this thread was running at priority level 3.
#308,v,g,n,n,n,PM_THRD_PRIO_4_CYC,Cycles thread running at priority level 4
##22046
Cycles this thread was running at priority level 4.
#309,v,g,n,n,n,PM_THRD_PRIO_DIFF_5or6_CYC,Cycles thread priority difference is 5 or 6
##23040
Cycles when this thread's priority is higher than the other thread's priority by 5 or 6.
#310,v,g,n,n,n,PM_THRD_PRIO_DIFF_minus5or6_CYC,Cycles thread priority difference is -5 or -6
##23046
Cycles when this thread's priority is lower than the other thread's priority by 5 or 6.
#311,v,g,n,c,n,PM_THRD_SEL_T0,Decode selected thread 0
##31086
Thread selection picked thread 0 for decode.
#312,v,g,n,n,n,PM_TLB_REF,TLB reference
##920E8
Number of Data Translation requests from the ERAT. 
#313,v,g,n,n,n,PM_VMX0_INST_ISSUED,VMX0 instruction issued
##600A0
An instruction was issued to VMX unit 0
#314,v,g,n,n,n,PM_VMX0_LD_ISSUED,VMX0 load issued
##600A2
A load instruction was issued to VMX unit 0
#315,v,g,n,n,n,PM_VMX0_LD_WRBACK,VMX0 load writeback valid
##600A4
A load returned data on VMX unit 0
#316,v,g,n,n,n,PM_VMX0_STALL,VMX0 stall
##B00A4
Cycles the VMX unit 0 was stalled
#317,v,g,n,n,n,PM_VMX1_INST_ISSUED,VMX1 instruction issued
##600A8
An instruction was issued to VMX unit 1
#318,v,g,n,n,n,PM_VMX1_LD_ISSUED,VMX1 load issued
##600AA
A load instruction was issued to VMX unit 1
#319,v,g,n,n,n,PM_VMX1_LD_WRBACK,VMX1 load writeback valid
##600AC
A load returned data on VMX unit 1
#320,v,g,n,n,n,PM_VMX1_STALL,VMX1 stall
##B00AC
Cycles the VMX unit 1 was stalled
#321,v,g,n,n,n,PM_VMX_COMPLEX_ISSUED,VMX instruction issued to complex
##700A4
An instruction was issued to the VMX Complex pipeline.
#322,v,g,n,n,n,PM_VMX_FLOAT_ISSUED,VMX instruction issued to float
##700A0
An instruction was issued to the VMX Float pipeline.
#323,v,g,n,n,n,PM_VMX_FLOAT_MULTICYCLE,VMX multi-cycle floating point instruction issued
##B00A2
A multi-cycle instruction was issued to the VMX Float pipeline.
#324,v,g,n,n,n,PM_VMX_PERMUTE_ISSUED,VMX instruction issued to permute
##700A6
An instruction was issued to the VMX Permute pipeline.
#325,v,g,n,n,n,PM_VMX_RESULT_SAT_0_1,VMX valid result with sat bit is set (0->1)
##B00AE
An instruction finished on the VMX unit that set the saturation bit. This bit is sticky, once set to 1 it remains set to 1 until it is set to 0 by an mtvscr instruction.
#326,v,g,n,n,n,PM_VMX_RESULT_SAT_1,VMX valid result with sat=1
##B00A6
An instruction finished on the VMX unit with the saturation bit on. This bit is sticky, once set to 1 it remains set to 1 until it is set to 0 by an mtvscr instruction.
#327,v,g,n,n,n,PM_VMX_SIMPLE_ISSUED,VMX instruction issued to simple
##700A2
An instruction was issued to the VMX Simple pipeline.
#328,v,g,n,n,n,PM_VMX_ST_ISSUED,VMX store issued
##B00A0
A VMX Store was issued
#329,v,g,n,n,n,PM_0INST_FETCH_COUNT,Periods with no instructions fetched
##400A1
No instructions were fetched this periods (due to IFU hold, redirect, or icache miss)
#330,v,g,n,n,n,PM_IBUF_FULL_COUNT,Periods instruction buffer full
##400A5
Number of times the Instruction Buffer was full. The Instruction Buffer is a circular queue of 64 instructions per thread, organized as 16 groups of 4 instructions.
#331,v,g,n,n,n,PM_GCT_FULL_COUNT,Periods GCT full
##400A7
The Global Completion Table is completely full.
#332,v,g,n,n,n,PM_NO_ITAG_COUNT,Periods no ITAG available
##400A9
Number of periods when no ITAGS are available. This condition will block instruction fetch.
#333,v,g,n,n,n,PM_INST_TABLEWALK_COUNT,Periods doing instruction tablewalks
##920EB
Number of Instruction Tablewalks
#334,v,g,n,n,n,PM_SYNC_COUNT,SYNC instructions completed
##920ED
Number of SYNC instructions executed.
#335,v,g,n,n,n,PM_LSU_DERAT_MISS,DERAT misses
##00007
Total D-ERAT Misses. On POWER6 only one demand D-ERAT miss can be pending at a time. The processor may continue to execute instructions in Load Look Ahead mode while the miss is serviced.
#336,v,g,n,s,n,PM_THRD_BOTH_RUN_COUNT,Periods both threads in run cycles
##00005
Number of periods when both threads had their run latches set. Operating systems use the run latch to indicate when they are doing useful work. 
#337,v,g,n,c,n,PM_LLA_CYC,Load Look Ahead Active
##0C01E
Load Look Ahead Active. When a demand cache or ERAT miss is encountered, the processor continues dispatching instructions but inhibits the results from writing registers (i.e. the architected state of the machine is not changed), executing subsequent load instructions such that independent cache line miss requests maybe started.
#338,v,g,n,c,n,PM_NOT_LLA_CYC,Load Look Ahead not Active
##0401E
Load Look Ahead not Active
#339,v,g,n,c,n,PM_LLA_COUNT,Transitions into Load Look Ahead mode
##0C01F
Transitions into Load Look Ahead mode
#340,v,g,n,n,n,PM_DPU_WT_BR_MPRED_COUNT,Periods DISP unit is stalled due to branch misprediction
##0000D
Number of times that Instruction Dispatch had no instructions available to dispatch because of a branch mispredict.
#341,u,g,n,s,n,PM_LSU_SRQ_EMPTY_COUNT,Periods SRQ empty
##0001D
The Store Request Queue is empty
#342,v,g,n,n,n,PM_DERAT_REF_16G,DERAT reference for 16G page
##82070
A data request (load or store) referenced (accessed)  the ERAT for 16G page
#343,v,g,n,n,n,PM_DERAT_MISS_16G,DERAT misses for 16G page
##92070
A data request (load or store) missed the ERAT for 16G page and resulted in an ERAT reload.
#344,v,g,n,n,n,PM_IERAT_MISS_4K,IERAT misses for 4K page
##92076
A translation request for a 4KB page missed the Instruction Effective to Real Address Translation (ERAT) table
#345,v,g,n,n,m,PM_MRK_DERAT_REF_16G,Marked DERAT reference for 16G page
##82044
A marked data request (load or store) referenced (accessed)  the ERAT for 16G page
#346,v,g,n,n,m,PM_MRK_DERAT_MISS_16G,Marked DERAT misses for 16G page
##92044
A marked data request (load or store) missed the ERAT for 16G page and resulted in an ERAT reload.
#347,v,g,n,n,n,PM_RUN_PURR,Run PURR Event
##000F4
The Processor Utilization of Resources Register was incremented while the run latch was set. The PURR registers will be incremented roughly in the ratio in which the instructions are dispatched from the two threads. 

$$$$$$$$

{ counter 5 }
#0,v,g,n,n,n,PM_RUN_INST_CMPL,Run instructions completed
##00009
Number of run instructions completed. 

$$$$$$$$

{ counter 6 }
#0,v,g,n,n,n,PM_RUN_CYC,Run cycles
##00005
Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.