{ IBM_PROLOG_BEGIN_TAG { This is an automatically generated prolog. { { bos72X src/bos/usr/sbin/perf/pmapi/events/POWER10.evs 1.5 { { { { OBJECT CODE ONLY SOURCE MATERIALS { { COPYRIGHT International Business Machines Corp. 2020,2021 { All Rights Reserved { { The source code for this program is not published or otherwise { divested of its trade secrets, irrespective of what has been { deposited with the U.S. Copyright Office. { { IBM_PROLOG_END_TAG 1720,1729,1730,1745,1,1 { counter 1} #0,u,g,n,n,n,n,PM_SUSPENDED,Counter off ##10000 Counter off #1,u,g,n,n,n,n,PM_INST_CMPL,PowerPC instruction completed ##100FE PowerPC instruction completed #2,u,g,n,n,n,y,PM_EXEC_STALL_TRANSLATION,Cycles in which the oldest instruction in the pipeline suffered a TLB miss or ERAT miss and waited for it to resolve. ##10004 Cycles in which the oldest instruction in the pipeline suffered a TLB miss or ERAT miss and waited for it to resolve. #3,u,g,n,n,n,u,PM_DISP_STALL_HELD_OTHER_CYC,Cycles in which the next-to-complete (NTC) instruction is held at dispatch for any other reason ##10006 Cycles in which the next-to-complete (NTC) instruction is held at dispatch for any other reason #4,u,g,n,n,n,n,PM_RUN_SPURR,SPURR bit 59 toggled ##10008 SPURR bit 59 toggled #5,u,g,n,n,n,y,PM_PMC3_REWIND,The speculative event selected for PMC3 rewinds and the counter for PMC3 is not charged. ##1000A The speculative event selected for PMC3 rewinds and the counter for PMC3 is not charged. #6,u,g,n,n,n,y,PM_LSU_LD0_FIN,LSU Finished an internal operation in LD0 port ##1000C LSU Finished an internal operation in LD0 port #7,u,g,n,n,n,y,PM_MMA_ISSUED,MMA instruction issued ##1000E MMA instruction issued #8,u,g,n,n,n,y,PM_PMC4_OVERFLOW,The event selected for PMC4 caused the event counter to overflow. ##10010 The event selected for PMC4 caused the event counter to overflow. #9,u,g,n,n,n,y,PM_LSU_ST0_FIN,LSU Finished an internal operation in ST0 port ##10012 LSU Finished an internal operation in ST0 port #10,u,g,n,n,n,y,PM_LSU_ST4_FIN,LSU Finished an internal operation in ST4 port ##10014 LSU Finished an internal operation in ST4 port #11,u,g,n,n,n,y,PM_VSU0_ISSUE,VSU instruction issued to VSU pipe 0 ##10016 VSU instruction issued to VSU pipe 0 #12,u,g,n,n,n,u,PM_IC_DEMAND_CYC,Cycles in which an instruction reload is pending to satisfy a demand miss ##10018 Cycles in which an instruction reload is pending to satisfy a demand miss #13,u,g,n,n,n,n,PM_ULTRAVISOR_INST_CMPL,PowerPC instruction completed while the thread was in ultravisor state. ##1001C PowerPC instruction completed while the thread was in ultravisor state. #14,u,g,n,n,n,n,PM_CYC,Processor cycles ##100F0 Processor cycles #15,u,g,n,n,n,y,PM_PMC4_REWIND,The speculative event selected for PMC4 rewinds and the counter for PMC4 is not charged. ##10020 The speculative event selected for PMC4 rewinds and the counter for PMC4 is not charged. #16,u,g,n,n,n,y,PM_PMC2_SAVED,The conditions for the speculative event selected for PMC2 are met and PMC2 is charged. ##10022 The conditions for the speculative event selected for PMC2 are met and PMC2 is charged. #17,u,g,n,n,n,y,PM_PMC5_OVERFLOW,The event selected for PMC5 caused the event counter to overflow. ##10024 The event selected for PMC5 caused the event counter to overflow. #18,u,g,n,n,n,y,PM_EXT_INT_EBB,Cycles an external interrupt was asserted due to Event Based Branch. This means the PMU interrupt is being handled by user code. ##10026 Cycles an external interrupt was asserted due to Event Based Branch. This means the PMU interrupt is being handled by user code. #19,u,g,n,n,n,y,PM_NTC_FLUSH,The instruction was flushed after becoming next-to-complete (NTC) ##10028 The instruction was flushed after becoming next-to-complete (NTC) #20,u,g,n,n,n,y,PM_PMC3_HELD_CYC,Cycles when the speculative counter for PMC3 is frozen. ##1002A Cycles when the speculative counter for PMC3 is frozen. #21,u,g,n,n,n,u,PM_LD_PREFETCH_CACHE_LINE_MISS,The L1 cache was reloaded with a line that fulfills a prefetch request ##1002C The L1 cache was reloaded with a line that fulfills a prefetch request #22,u,g,n,n,m,y,PM_MRK_INST_ISSUED,Marked instruction issued. Note that stores always get issued twice, the address gets issued to the LSU and the data gets issued to the VSU. Also, issues can sometimes get killed/cancelled and cause multiple sequential issues for the same instruction. ##10132 Marked instruction issued. Note that stores always get issued twice, the address gets issued to the LSU and the data gets issued to the VSU. Also, issues can sometimes get killed/cancelled and cause multiple sequential issues for the same instruction. #23,u,g,n,n,m,n,PM_MRK_ST_DONE_L2,Marked store completed in L2 ##10134 Marked store completed in L2 #24,u,g,n,n,n,y,PM_DISP_STALL_TRANSLATION,Cycles when dispatch was stalled for this thread because the MMU was handling a translation miss. ##10038 Cycles when dispatch was stalled for this thread because the MMU was handling a translation miss. #25,u,g,n,n,n,y,PM_DISP_STALL_BR_MPRED_IC_L2,Cycles when dispatch was stalled while the instruction was fetched from the local L2 after suffering a branch mispredict. ##1003A Cycles when dispatch was stalled while the instruction was fetched from the local L2 after suffering a branch mispredict. #26,u,g,n,n,n,n,PM_EXEC_STALL_DMISS_L2L3,Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from either the local L2 or local L3. ##1003C Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from either the local L2 or local L3. #27,u,g,n,n,m,n,PM_MRK_LD_MISS_EXPOSED_CYC,Marked load exposed miss (use edge detect to count ) ##1013E Marked load exposed miss (use edge detect to count ) #28,u,g,n,n,n,y,PM_DATA_RADIX_L2_PTE_FROM_L2,A data Page Table Entry was reloaded to a level 2 page walk cache from the core's L2 cache. If MMCR1[16] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. ##14042 A data Page Table Entry was reloaded to a level 2 page walk cache from the core's L2 cache. If MMCR1[16] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. #29,u,g,n,n,n,y,PM_DATA_RADIX_L2_PDE_FROM_L2,A data Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 cache. If MMCR1[16] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. ##14044 A data Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 cache. If MMCR1[16] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. #30,u,g,n,n,n,y,PM_DATA_RADIX_L3_PTE_FROM_L2,A data Page Table Entry was reloaded to a level 3 page walk cache from the core's L2 cache. If MMCR1[16] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. ##14046 A data Page Table Entry was reloaded to a level 3 page walk cache from the core's L2 cache. If MMCR1[16] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. #31,u,g,n,n,n,y,PM_DATA_RADIX_L3_PDE_FROM_L2,A data Page Directory Entry was reloaded to a level 3 page walk cache from the core's L2 cache. If MMCR1[16] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. ##14048 A data Page Directory Entry was reloaded to a level 3 page walk cache from the core's L2 cache. If MMCR1[16] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. #32,u,g,n,n,n,y,PM_DATA_RADIX_L4_PTE_FROM_L2,A data Page Table Entry was reloaded to a level 4 page walk cache from the core's L2 cache. If MMCR1[16] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. ##1404A A data Page Table Entry was reloaded to a level 4 page walk cache from the core's L2 cache. If MMCR1[16] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. #33,u,g,n,n,n,y,PM_INST_RADIX_L2_PTE_FROM_L2,An instruction Page Table Entry was reloaded to a level 2 page walk cache from the core's L2 cache. If MMCR1[17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[17] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. ##1404E An instruction Page Table Entry was reloaded to a level 2 page walk cache from the core's L2 cache. If MMCR1[17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[17] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. #34,u,g,n,n,n,y,PM_INST_RADIX_L3_PTE_FROM_L2,An instruction Page Table Entry was reloaded to a level 3 page walk cache from the core's L2 cache. If MMCR1[17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[17] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. ##15042 An instruction Page Table Entry was reloaded to a level 3 page walk cache from the core's L2 cache. If MMCR1[17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[17] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. #35,u,g,n,n,n,y,PM_INST_RADIX_L3_PDE_FROM_L2,An instruction Page Directory Entry was reloaded to a level 3 page walk cache from the core's L2 cache. If MMCR1[17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[17] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. ##15044 An instruction Page Directory Entry was reloaded to a level 3 page walk cache from the core's L2 cache. If MMCR1[17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[17] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. #36,u,g,n,n,n,y,PM_INST_RADIX_L4_PTE_FROM_L2,An instruction Page Table Entry was reloaded to a level 4 page walk cache from the core's L2 cache. If MMCR1[17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[17] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. ##15046 An instruction Page Table Entry was reloaded to a level 4 page walk cache from the core's L2 cache. If MMCR1[17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[17] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. #37,u,g,n,n,n,y,PM_XFER_FROM_SRC_PMC1,The processor's L1 data cache was reloaded from the source specified in MMCR3[0:12]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads. ##1C040 The processor's L1 data cache was reloaded from the source specified in MMCR3[0:12]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads. #38,u,g,n,n,m,y,PM_MRK_XFER_FROM_SRC_PMC1,For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[0:12]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads. ##1C142 For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[0:12]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads. #39,u,g,n,n,m,y,PM_MRK_XFER_FROM_SRC_CYC_PMC1,Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[0:12]. ##1C144 Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[0:12]. #40,u,g,n,n,m,y,PM_MRK_DATA_FLUSHED_FROM_SRC_PMC1,Marked demand loads that attempted a reload, but were flushed ##1C146 Marked demand loads that attempted a reload, but were flushed #41,u,g,n,n,m,y,PM_MRK_DATA_FLUSHED_FROM_SRC_CYC_PMC1,Cycles spent attempting to reload a line from any source for a marked demand miss that was later flushed ##1C148 Cycles spent attempting to reload a line from any source for a marked demand miss that was later flushed #42,u,g,n,n,m,y,PM_MRK_SYS_PUMP_MPRED_RTY,Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for a marked instruction. Includes instructions and data lines ##1C14A Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for a marked instruction. Includes instructions and data lines #43,u,g,n,n,n,u,PM_SIAR_LOADED,SIAR written per thread ##1C04E SIAR written per thread #44,u,g,n,n,n,y,PM_MEM_READ,Reads from Memory from this thread (includes data/inst/xlate/l1prefetch/inst prefetch). This event count should be divided by two since the event is sourced from 2:1 clock domain. ##10056 Reads from Memory from this thread (includes data/inst/xlate/l1prefetch/inst prefetch). This event count should be divided by two since the event is sourced from 2:1 clock domain. #45,u,g,n,n,n,y,PM_EXEC_STALL_FIN_AT_DISP,Cycles in which the oldest instruction in the pipeline finished at dispatch and did not require execution in the LSU, BRU or VSU. ##10058 Cycles in which the oldest instruction in the pipeline finished at dispatch and did not require execution in the LSU, BRU or VSU. #46,u,g,n,n,n,y,PM_FLUSH_MPRED,A flush occurred due to a mispredicted branch. Includes target and direction ##1005A A flush occurred due to a mispredicted branch. Includes target and direction #47,u,g,n,n,m,y,PM_MRK_FAB_RSP_RD_T_INTV,Sampled Read got a T intervention ##1015E Sampled Read got a T intervention #48,u,g,n,n,n,y,PM_INST_CHIP_PUMP_CPRED,Initial and Final Pump Scope was chip pump (prediction=correct) for an instruction fetch ##14050 Initial and Final Pump Scope was chip pump (prediction=correct) for an instruction fetch #49,u,g,n,n,n,y,PM_INST_GRP_PUMP_MPRED_RTY,Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for an instruction fetch ##14052 Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for an instruction fetch #50,u,g,n,n,n,y,PM_INST_PUMP_CPRED,Pump prediction correct. Counts across all types of pumps for an instruction fetch ##14054 Pump prediction correct. Counts across all types of pumps for an instruction fetch #51,u,g,n,n,n,y,PM_LD_HIT_L1,Load finished without experiencing an L1 miss ##1505E Load finished without experiencing an L1 miss #52,u,g,n,n,n,y,PM_DATA_CHIP_PUMP_CPRED,Initial and Final Pump Scope was chip pump (prediction=correct) for a demand load ##1C050 Initial and Final Pump Scope was chip pump (prediction=correct) for a demand load #53,u,g,n,n,n,y,PM_DATA_GRP_PUMP_MPRED_RTY,Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a demand load ##1C052 Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a demand load #54,u,g,n,n,n,y,PM_DATA_PUMP_CPRED,Pump prediction correct. Counts across all types of pumps for a demand load ##1C054 Pump prediction correct. Counts across all types of pumps for a demand load #55,u,g,n,n,n,y,PM_DERAT_MISS_4K,Data ERAT Miss (Data TLB Access) page size 4K. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches ##1C056 Data ERAT Miss (Data TLB Access) page size 4K. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches #56,u,g,n,n,n,y,PM_DTLB_MISS_16G,Data TLB reload (after a miss) page size 16G. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches. ##1C058 Data TLB reload (after a miss) page size 16G. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches. #57,u,g,n,n,n,y,PM_DERAT_MISS_2M,Data ERAT Miss (Data TLB Access) page size 2M. Implies radix translation. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches ##1C05A Data ERAT Miss (Data TLB Access) page size 2M. Implies radix translation. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches #58,u,g,n,n,n,y,PM_DTLB_MISS_2M,Data TLB reload (after a miss) page size 2M. Implies radix translation was used. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches ##1C05C Data TLB reload (after a miss) page size 2M. Implies radix translation was used. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches #59,u,g,n,n,n,y,PM_ITLB_MISS_64K,Instruction TLB reload (after a miss) page size 64K. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches. ##1C05E Instruction TLB reload (after a miss) page size 64K. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches. #60,u,g,n,n,n,y,PM_DTLB_HIT_16G,Data TLB Hit (DERAT reload) page size 16G. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches ##1D050 Data TLB Hit (DERAT reload) page size 16G. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches #61,u,g,n,n,n,y,PM_DTLB_HIT_2M,Data TLB hit (DERAT reload) page size 2M. Implies radix translation. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches ##1D054 Data TLB hit (DERAT reload) page size 2M. Implies radix translation. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches #62,u,g,n,n,m,y,PM_MRK_LD_MISS_L1_CYC,Marked load latency. The latency measured for this event counts between the original launch of a load L1 miss to the relaunch of that same load l1 miss once data is back from the nest and the load is going to finish ##1D156 Marked load latency. The latency measured for this event counts between the original launch of a load L1 miss to the relaunch of that same load l1 miss once data is back from the nest and the load is going to finish #63,u,g,n,n,n,y,PM_ITLB_HIT_64K,Instruction TLB hit (IERAT reload) page size 64K. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches. ##1D058 Instruction TLB hit (IERAT reload) page size 64K. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches. #64,u,g,n,n,m,y,PM_MRK_DTLB_MISS_1G,Marked Data TLB reload (after a miss) page size 1G. Implies radix translation was used. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches ##1D15C Marked Data TLB reload (after a miss) page size 1G. Implies radix translation was used. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches #65,u,g,n,n,n,u,PM_DISP_STALL_HELD_HALT_CYC,Cycles in which the next-to-complete (NTC) instruction is held at dispatch because of power management ##1D05E Cycles in which the next-to-complete (NTC) instruction is held at dispatch because of power management #66,u,g,n,n,n,y,PM_DISP_STALL_HELD_STF_MAPPER_CYC,Cycles in which the next-to-complete (NTC) instruction is held at dispatch because the STF mapper/SRB was full. Includes GPR (count, link, tar), VSR, VMR, FPR ##1E050 Cycles in which the next-to-complete (NTC) instruction is held at dispatch because the STF mapper/SRB was full. Includes GPR (count, link, tar), VSR, VMR, FPR #67,u,g,n,n,m,y,PM_MRK_DERAT_MISS_16M,Data ERAT Miss (Data TLB Access) page size 16M for a marked instruction. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches ##1E152 Data ERAT Miss (Data TLB Access) page size 16M for a marked instruction. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches #68,u,g,n,n,n,y,PM_EXEC_STALL_DMISS_L21_L31,Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from another core's L2 or L3 on the same chip. ##1E054 Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from another core's L2 or L3 on the same chip. #69,u,g,n,n,n,y,PM_EXEC_STALL_STORE_PIPE,Cycles in which the oldest instruction in the pipeline was executing in the store unit. This does not include cycles spent handling store misses, PTESYNC instructions or TLBIE instructions. ##1E056 Cycles in which the oldest instruction in the pipeline was executing in the store unit. This does not include cycles spent handling store misses, PTESYNC instructions or TLBIE instructions. #70,u,g,n,n,n,y,PM_STCX_FAIL_FIN,Conditional store instruction (STCX) failed. LARX and STCX are instructions used to acquire a lock  ##1E058 Conditional store instruction (STCX) failed. LARX and STCX are instructions used to acquire a lock  #71,u,g,n,n,n,n,PM_CMPL_STALL_LWSYNC,Cycles in which the oldest instruction in the pipeline was a lwsync waiting to complete. ##1E05A Cycles in which the oldest instruction in the pipeline was a lwsync waiting to complete. #72,u,g,n,n,m,y,PM_MRK_L2_TM_REQ_ABORT,TM abort ##1E15E TM abort #73,u,g,n,n,m,n,PM_MRK_ST_L2_CYC,Cycles from L2 RC dispatch to L2 RC completion ##1F150 Cycles from L2 RC dispatch to L2 RC completion #74,u,g,n,n,m,y,PM_MRK_FAB_RSP_BKILL_CYC,Cycles L2 RC took for a bkill ##1F152 Cycles L2 RC took for a bkill #75,u,g,n,n,n,y,PM_DTLB_HIT,The PTE required by the instruction was resident in the TLB (data TLB access). When MMCR1[16]=0 this event counts only demand hits. When MMCR1[16]=1 this event includes demand and prefetch. Applies to both HPT and RPT ##1F054 The PTE required by the instruction was resident in the TLB (data TLB access). When MMCR1[16]=0 this event counts only demand hits. When MMCR1[16]=1 this event includes demand and prefetch. Applies to both HPT and RPT #76,u,g,n,n,n,y,PM_DISP_SS0_2_INSTR_CYC,Cycles in which Superslice 0 dispatches either 1 or 2 instructions ##1F056 Cycles in which Superslice 0 dispatches either 1 or 2 instructions #77,u,g,n,n,n,y,PM_DISP_HELD_CYC,Cycles dispatch is held ##1F058 Cycles dispatch is held #78,u,g,n,n,n,y,PM_DISP_HELD_SYNC_CYC,Cycles dispatch is held because of a synchronizing instruction that requires the ICT to be empty before dispatch ##1F05A Cycles dispatch is held because of a synchronizing instruction that requires the ICT to be empty before dispatch #79,u,g,n,n,m,n,PM_MRK_STCX_L2_CYC,Cycles spent in the nest portion of a marked Stcx instruction. It starts counting when the operation starts to drain to the L2 and it stops counting when the instruction retires from the Instruction Completion Table (ICT) in the Instruction Sequencing Unit (ISU) ##1F15C Cycles spent in the nest portion of a marked Stcx instruction. It starts counting when the operation starts to drain to the L2 and it stops counting when the instruction retires from the Instruction Completion Table (ICT) in the Instruction Sequencing Unit (ISU) #80,u,g,n,n,m,n,PM_MRK_START_PROBE_NOP_CMPL,Marked Start probe nop (AND R0,R0,R0) completed. ##1F15E Marked Start probe nop (AND R0,R0,R0) completed. #81,u,g,n,n,n,y,PM_TM_TRANS_RUN_CYC,Run cycles in transactional state ##10060 Run cycles in transactional state #82,u,g,n,n,n,y,PM_LD_L3MISS_PEND_CYC,Cycles in which an L3 miss was pending for this thread ##10062 Cycles in which an L3 miss was pending for this thread #83,u,g,n,n,n,y,PM_DISP_STALL_IC_L2,Cycles when dispatch was stalled while the instruction was fetched from the local L2. ##10064 Cycles when dispatch was stalled while the instruction was fetched from the local L2. #84,u,g,n,n,n,n,PM_ADJUNCT_CYC,Cycles in which the thread is in Adjunct state. MSR[S HV PR] bits = 011 ##10066 Cycles in which the thread is in Adjunct state. MSR[S HV PR] bits = 011 #85,u,g,n,n,n,y,PM_BR_FIN,A branch instruction finished. Includes predicted/mispredicted/unconditional ##10068 A branch instruction finished. Includes predicted/mispredicted/unconditional #86,u,g,n,n,n,y,PM_FX_LSU_FIN,Simple fixed point instruction issued to the store unit. Measured at finish time ##1006A Simple fixed point instruction issued to the store unit. Measured at finish time #87,u,g,n,n,n,n,PM_RUN_CYC_ST_MODE,Cycles when the run latch is set and the core is in ST mode ##1006C Cycles when the run latch is set and the core is in ST mode #88,u,g,n,n,m,y,PM_MRK_INST_DISP,The thread has dispatched a randomly sampled marked instruction ##101E0 The thread has dispatched a randomly sampled marked instruction #89,u,g,n,n,m,n,PM_MRK_BR_TAKEN_CMPL,Marked Branch Taken instruction completed ##101E2 Marked Branch Taken instruction completed #90,u,g,n,n,m,y,PM_MRK_L1_ICACHE_MISS,Marked instruction suffered an instruction cache miss ##101E4 Marked instruction suffered an instruction cache miss #91,u,g,t,n,m,y,PM_THRESH_EXC_4096,Threshold counter exceeded a count of 4096 ##101E6 Threshold counter exceeded a count of 4096 #92,u,g,t,n,m,y,PM_THRESH_EXC_256,Threshold counter exceeded a count of 256 ##101E8 Threshold counter exceeded a count of 256 #93,u,g,n,n,m,y,PM_MRK_L1_RELOAD_VALID,Marked demand reload ##101EA Marked demand reload #94,u,g,t,n,m,y,PM_THRESH_MET,Threshold exceeded ##101EC Threshold exceeded #95,u,g,n,n,n,n,PM_1PLUS_PPC_CMPL,Cycles in which at least one instruction is completed by this thread ##100F2 Cycles in which at least one instruction is completed by this thread #96,u,g,n,n,n,n,PM_FLOP_CMPL,Floating Point Operations Completed. Includes any type. It counts once for each 1, 2, 4 or 8 flop instruction. Use PM_1|2|4|8_FLOP_CMPL events to count flops ##100F4 Floating Point Operations Completed. Includes any type. It counts once for each 1, 2, 4 or 8 flop instruction. Use PM_1|2|4|8_FLOP_CMPL events to count flops #97,u,g,n,n,n,y,PM_IERAT_MISS,IERAT Reloaded to satisfy an IERAT miss. All page sizes are counted by this event. ##100F6 IERAT Reloaded to satisfy an IERAT miss. All page sizes are counted by this event. #98,u,g,n,n,n,y,PM_DISP_STALL_CYC,Cycles the ICT has no itags assigned to this thread (no instructions were dispatched during these cycles). ##100F8 Cycles the ICT has no itags assigned to this thread (no instructions were dispatched during these cycles). #99,u,g,n,n,n,n,PM_RUN_LATCH_ANY_THREAD_CYC,Cycles when at least one thread has the run latch set ##100FA Cycles when at least one thread has the run latch set #100,u,g,n,n,n,y,PM_LD_REF_L1,All L1 D cache load references counted at finish, gated by reject. In P9 and earlier this event counted only cacheable loads but in P10 both cacheable and non-cacheable loads are included ##100FC All L1 D cache load references counted at finish, gated by reject. In P9 and earlier this event counted only cacheable loads but in P10 both cacheable and non-cacheable loads are included #101,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3MISS,The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction. ##0007C0000001C142 The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction. #102,u,g,n,n,n,u,PM_DATA_FROM_L2MISS,The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss. ##0003C0000001C040 The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss. #103,u,g,n,n,n,n,PM_L3_CO_MEPF,L3 castouts in Mepf state for this core. ##100000016880 L3 castouts in Mepf state for this core. #104,u,g,n,n,n,u,PM_INST_FROM_L3MISS,The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss. ##000780000001C040 The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss. #105,u,g,n,n,n,u,PM_DATA_FROM_L3MISS,The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss. ##0007C0000001C040 The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss. #106,u,g,n,n,m,u,PM_MRK_INST_FROM_L3MISS,The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction. ##000780000001C142 The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction. #107,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2MISS,The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction. ##0003C0000001C142 The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction. #108,u,g,n,n,n,u,PM_EE_OFF_EXT_INT_CYC,Cycles in which MSR[EE] is off and external interrupts are active ##0000002080 Cycles in which MSR[EE] is off and external interrupts are active #109,u,g,n,n,n,u,PM_ISU_FLUSH,All flushes initiated by the Instruction Sequencing Unit (ISU). Excludes LSU NTC+1 flushes ##0000002880 All flushes initiated by the Instruction Sequencing Unit (ISU). Excludes LSU NTC+1 flushes #110,u,g,n,n,n,u,PM_ISU_FLUSH_DISP,Dispatch flushes occur when one thread is causing other threads to stall ##0000002084 Dispatch flushes occur when one thread is causing other threads to stall #111,u,g,n,n,n,u,PM_ISU_FLUSH_BALANCE,A balance flush occurred. Balance flushes are triggered when excessive L3 or TLB misses occur ##0000002884 A balance flush occurred. Balance flushes are triggered when excessive L3 or TLB misses occur #112,u,g,n,n,n,u,PM_ISU_FLUSH_PARTIAL,A flush occurred only to the odd ITAG of a pair. This type of flush requires an additional 10 cycles to process. More pairs of instructions can be included in this count. ##0000002088 A flush occurred only to the odd ITAG of a pair. This type of flush requires an additional 10 cycles to process. More pairs of instructions can be included in this count. #113,u,g,n,n,n,u,PM_ISU_FLUSH_DISP_SRQ_EMPTY,Dispatch flush while waiting for the SRQ to become empty: TLBIE, SLBIEG, SLBIET, EIEIO, TLBSYNC. ##0000002888 Dispatch flush while waiting for the SRQ to become empty: TLBIE, SLBIEG, SLBIET, EIEIO, TLBSYNC. #114,u,g,n,n,n,u,PM_ISU_FLUSH_LD_ECC_ERROR,A load instruction that accessed early data from memory and finished speculatively before the ECC was returned, gets flushed because of a later ECC error ##000000208C A load instruction that accessed early data from memory and finished speculatively before the ECC was returned, gets flushed because of a later ECC error #115,u,g,n,n,n,u,PM_ISU_FLUSH_LWSYNC,A flush to a lightweight synchronizing or barrier instruction (LWSYNC) instruction that had trouble. This event includes NTC flushes and NTC+1 flushes. ##000000288C A flush to a lightweight synchronizing or barrier instruction (LWSYNC) instruction that had trouble. This event includes NTC flushes and NTC+1 flushes. #116,u,g,n,n,n,u,PM_ISU_FLUSH_ISYNC,A flush to an isync instruction that had trouble. This event includes NTC flushes and NTC+1 flushes. ##0000002090 A flush to an isync instruction that had trouble. This event includes NTC flushes and NTC+1 flushes. #117,u,g,n,n,n,u,PM_ISU_FLUSH_HWSYNC,A flush to a heavyweight synchronizing or barrier instruction (HWSYNC) instruction that had trouble. This event includes NTC flushes and NTC+1 flushes. ##0000002094 A flush to a heavyweight synchronizing or barrier instruction (HWSYNC) instruction that had trouble. This event includes NTC flushes and NTC+1 flushes. #118,u,g,n,n,n,u,PM_ISU_FLUSH_MMA_OFF_CYC,If the MMA engine is off when an MMA instruction is issued, the instruction will issue and finish as a nop. It will then get flushed when it becomes NTC and it will not be refetched until the MMA engine is on. This event counts the number of cycles between the flush and the MMA engine turning on. ##0000002894 If the MMA engine is off when an MMA instruction is issued, the instruction will issue and finish as a nop. It will then get flushed when it becomes NTC and it will not be refetched until the MMA engine is on. This event counts the number of cycles between the flush and the MMA engine turning on. #119,u,g,n,n,n,u,PM_ISU_FLUSH_DISP_STF_REBAL,The Sliced Target File (STF) is the register file for GPRs, VSRs, LR, CTR, and TAR. This event indicates that an execution unit attempted to write to a slice that was full. In this case, the instruction gets flushed and the slices get rebalanced. ##00000028AC The Sliced Target File (STF) is the register file for GPRs, VSRs, LR, CTR, and TAR. This event indicates that an execution unit attempted to write to a slice that was full. In this case, the instruction gets flushed and the slices get rebalanced. #120,u,g,n,n,n,u,PM_START_PROBE_NOP_DISP,A start probe nop was dispatched. Instruction AND 0,0,0 ##00000020B0 A start probe nop was dispatched. Instruction AND 0,0,0 #121,u,g,n,n,n,u,PM_STOP_PROBE_NOP_DISP,A stop probe nop was dispatched. Instruction AND 1,1,1 ##00000028B0 A stop probe nop was dispatched. Instruction AND 1,1,1 #122,u,g,n,n,m,u,PM_MRK_STOP_PROBE_NOP_DISP,A stop probe nop was marked at dispatch. Instruction AND 1,1,1 ##00000021B4 A stop probe nop was marked at dispatch. Instruction AND 1,1,1 #123,u,g,n,n,n,u,PM_FUNCTION_CALL_DISP,bl instruction dispatched. Only one reported per cycle. It is possible to dispatch 8 instructions per cycle in single thread mode. ##00000020B8 bl instruction dispatched. Only one reported per cycle. It is possible to dispatch 8 instructions per cycle in single thread mode. #124,u,g,n,n,n,u,PM_FUNCTION_RETURN_DISP,blr instruction dispatched. Only one reported per cycle. It is possible to dispatch 8 instructions per cycle in single thread mode. ##00000028B8 blr instruction dispatched. Only one reported per cycle. It is possible to dispatch 8 instructions per cycle in single thread mode. #125,u,g,n,n,n,u,PM_0CYC_CONST_DISP,Xxor instruction dispatched. ##00000020BC Xxor instruction dispatched. #126,u,g,n,n,n,u,PM_ISSUE_HOLD_STAGS_CYC,Cycles in which one or more instructions are being held at issue while waiting for Store Tags to become available. These instructions could also be held simultaneously for other conditions. Other non-store instructions are allowed to issue while the store is being held. ##0000003080 Cycles in which one or more instructions are being held at issue while waiting for Store Tags to become available. These instructions could also be held simultaneously for other conditions. Other non-store instructions are allowed to issue while the store is being held. #127,u,g,n,n,n,u,PM_ISSUE_HOLD_LTAGS_CYC,Cycles in which one or more instructions are being held at issue while waiting for Load Tags to become available. These instructions could also be held simultaneously for other conditions. Other non-load instructions are allowed to issue while the load is being held. ##0000003880 Cycles in which one or more instructions are being held at issue while waiting for Load Tags to become available. These instructions could also be held simultaneously for other conditions. Other non-load instructions are allowed to issue while the load is being held. #128,u,g,n,n,n,u,PM_ISSUE_KILL_DL_MISS,An instruction was primed to issue but was killed before being written because one of the sources takes a data load miss. I.e. dependent data from a load does not get valid data ##0000003084 An instruction was primed to issue but was killed before being written because one of the sources takes a data load miss. I.e. dependent data from a load does not get valid data #129,u,g,n,n,n,u,PM_ISSUE_KILL_RESOURCE,An instruction was primed to issue but was killed before being written because a resource is unavailable. Includes BFU, FX-DIV, DFU, BRU and SFX instructions that would collide at finish with a store AGEN. ##0000003884 An instruction was primed to issue but was killed before being written because a resource is unavailable. Includes BFU, FX-DIV, DFU, BRU and SFX instructions that would collide at finish with a store AGEN. #130,u,g,n,n,n,u,PM_ISSUE_KILL_THROTTLE,An instruction was primed to issue but was killed before being written because power throttling was enabled ##0000003088 An instruction was primed to issue but was killed before being written because power throttling was enabled #131,u,g,n,n,n,u,PM_SHL_HIT,A dependency was created when a dispatched store matched the address for a load in the Store-Hit-Load Table. ##000000388C A dependency was created when a dispatched store matched the address for a load in the Store-Hit-Load Table. #132,u,g,n,n,n,u,PM_LHS_HIT,A dependency was created when a dispatched load matched the address for a store instruction in the Load-Hit-Store table. ##0000003890 A dependency was created when a dispatched load matched the address for a store instruction in the Load-Hit-Store table. #133,u,g,n,n,n,u,PM_LHS_CREATED,New entry added to the Load-Hit-Store table. ##0000003094 New entry added to the Load-Hit-Store table. #134,u,g,n,n,n,u,PM_LARX_HIT_LARX_HIT,A dependency was created for a LARX instruction that was dispatched and matched an older LARX in the Larx-hit-larx table. ##0000003894 A dependency was created for a LARX instruction that was dispatched and matched an older LARX in the Larx-hit-larx table. #135,u,g,n,n,n,u,PM_LARX_HIT_LARX_CREATED,New entry added to the Larx-hit-larx table. LARX and STCX are instructions used to acquire a lock.  ##0000003098 New entry added to the Larx-hit-larx table. LARX and STCX are instructions used to acquire a lock.  #136,u,g,n,n,n,u,PM_MMA_VSR_CONFLICT_FLUSH,A VSR operation references an ACC that has been primed. This is indicative of a context switch ##0000003898 A VSR operation references an ACC that has been primed. This is indicative of a context switch #137,u,g,n,n,n,u,PM_MMA_ACC_CONFLICT_FLUSH,An MMA instruction references an ACC that has not been primed. This is indicative of faulty software ##000000309C An MMA instruction references an ACC that has not been primed. This is indicative of faulty software #138,u,g,n,n,m,u,PM_MRK_MMA_ACC_VSR_CONFLICT,Either a marked MMA instruction references an ACC that has not been primed or a marked VSR operation references an ACC that has been primed ##000000399C Either a marked MMA instruction references an ACC that has not been primed or a marked VSR operation references an ACC that has been primed #139,u,g,n,n,n,u,PM_MMA_IN_USE_CYC,Cycles in which the MMA engine is actively being used by this thread. This is measured by counting the cycles in which at least one ACC register is primed for MMA use. ##00000030A0 Cycles in which the MMA engine is actively being used by this thread. This is measured by counting the cycles in which at least one ACC register is primed for MMA use. #140,u,g,n,n,n,u,PM_MMA_ON_CYC,Cycles in which this core's MMA engine is enabled. ##00000038A0 Cycles in which this core's MMA engine is enabled. #141,u,g,n,n,n,u,PM_DISP_HELD_OUT_OF_LTAGS_CYC,Cycles in which dispatch is held because the LRQ is full. No LTAGS are available. There are twice as many LTAGS as there are LRQ entries. The signal should be on if less than 8 tags, and should be off if greater than 24 tags, and could be on if in-between. In ST/SMT2, if less than 24 tags, signal can come on, and if less than 8 it will be on. In SMT4, if less than 12 tags, it can come on, if less than 4 tags it will be on. ##00000030B4 Cycles in which dispatch is held because the LRQ is full. No LTAGS are available. There are twice as many LTAGS as there are LRQ entries. The signal should be on if less than 8 tags, and should be off if greater than 24 tags, and could be on if in-between. In ST/SMT2, if less than 24 tags, signal can come on, and if less than 8 it will be on. In SMT4, if less than 12 tags, it can come on, if less than 4 tags it will be on. #142,u,g,n,n,n,u,PM_DISP_HELD_OUT_OF_STAGS_CYC,Cycles in which dispatch is held because the SRQ is full. No STAGS are available. There are twice as many STAGS as there are SRQ entries. The signal should be on if less than 8 tags, should be off is greater than 24 tags, and could be on if in-between. In ST/SMT2, if less than 24 tags, signal can come on, if less than 8 tags it will be on. In SMT4, if less than 12 tags, it can come on, if less than 4 tags it will be on. ##00000038B4 Cycles in which dispatch is held because the SRQ is full. No STAGS are available. There are twice as many STAGS as there are SRQ entries. The signal should be on if less than 8 tags, should be off is greater than 24 tags, and could be on if in-between. In ST/SMT2, if less than 24 tags, signal can come on, if less than 8 tags it will be on. In SMT4, if less than 12 tags, it can come on, if less than 4 tags it will be on. #143,u,g,n,n,n,u,PM_DISP_CLB_HELD_BALANCE_CYC,Dispatch/CLB Hold as cause of Balance Flush. ##00000030B8 Dispatch/CLB Hold as cause of Balance Flush. #144,u,g,n,n,n,u,PM_DISP_CLB_HELD_SRQ_EMPTY_CYC,Dispatch Hold: waiting for the SRQ to become empty: TLBIE, SLBIEG, SLBIET, EIEIO, TLBSYNC. This should exclude cycles when it is only waiting for the ICT to become empty. ##00000038B8 Dispatch Hold: waiting for the SRQ to become empty: TLBIE, SLBIEG, SLBIET, EIEIO, TLBSYNC. This should exclude cycles when it is only waiting for the ICT to become empty. #145,u,g,n,n,n,u,PM_DISP_PARTIAL,Dispatches in which the Instruction Sequencing Unit (ISU) dispatches instructions at either half rate or quarter rate. This can happen when some of the queues (or mapper subblocks) are either full, or close to full. ##00000030BC Dispatches in which the Instruction Sequencing Unit (ISU) dispatches instructions at either half rate or quarter rate. This can happen when some of the queues (or mapper subblocks) are either full, or close to full. #146,u,g,n,n,n,u,PM_ISYNC_CMPL,Isync completion count per thread ##00000038BC Isync completion count per thread #147,u,g,n,n,n,u,PM_LD0_8B_FIN,64-bit or smaller load finished in the LD0 load execution unit. ##000000C080 64-bit or smaller load finished in the LD0 load execution unit. #148,u,g,n,n,n,u,PM_LD1_8B_FIN,64-bit or smaller load finished in the LD1 load execution unit. ##000000C880 64-bit or smaller load finished in the LD1 load execution unit. #149,u,g,n,n,n,u,PM_LD0_16B_FIN,128-bit load finished in the LD0 load execution unit. ##000000C084 128-bit load finished in the LD0 load execution unit. #150,u,g,n,n,n,u,PM_LD1_16B_FIN,128-bit load finished in the LD1 load execution unit. ##000000C884 128-bit load finished in the LD1 load execution unit. #151,u,g,n,n,n,u,PM_LD0_32B_FIN,256-bit load finished in the LD0 load execution unit. ##000000C088 256-bit load finished in the LD0 load execution unit. #152,u,g,n,n,n,u,PM_LD1_32B_FIN,256-bit load finished in the LD1 load execution unit. ##000000C888 256-bit load finished in the LD1 load execution unit. #153,u,g,n,n,n,u,PM_LD0_VECTOR_FIN,Any vector load operation finished in the LD0 execution unit. Excludes load quad, larx quad, fused load double, load float double-pair. ##000000C08C Any vector load operation finished in the LD0 execution unit. Excludes load quad, larx quad, fused load double, load float double-pair. #154,u,g,n,n,n,u,PM_LD1_VECTOR_FIN,Any vector load operation finished in the LD1 execution unit. Excludes load quad, larx quad, fused load double, load float double-pair. ##000000C88C Any vector load operation finished in the LD1 execution unit. Excludes load quad, larx quad, fused load double, load float double-pair. #155,u,g,n,n,n,u,PM_LD0_UNALIGNED_FIN,Load instructions in LD0 port that are either unaligned, or treated as unaligned and require an additional recycle through the pipeline using the load gather buffer. This typically adds about 10 cycles to the latency of the instruction. This includes loads that cross the 128 byte boundary, octword loads that are not aligned, and a special forward progress case of a load that does not hit in the L1 and crosses the 32 byte boundary and is launched NTC. Counted at finish time. ##000000C090 Load instructions in LD0 port that are either unaligned, or treated as unaligned and require an additional recycle through the pipeline using the load gather buffer. This typically adds about 10 cycles to the latency of the instruction. This includes loads that cross the 128 byte boundary, octword loads that are not aligned, and a special forward progress case of a load that does not hit in the L1 and crosses the 32 byte boundary and is launched NTC. Counted at finish time. #156,u,g,n,n,n,u,PM_LD1_UNALIGNED_FIN,Load instructions in LD1 port that are either unaligned, or treated as unaligned and require an additional recycle through the pipeline using the load gather buffer. This typically adds about 10 cycles to the latency of the instruction. This includes loads that cross the 128 byte boundary, octword loads that are not aligned, and a special forward progress case of a load that does not hit in the L1 and crosses the 32 byte boundary and is launched NTC. Counted at finish time. ##000000C890 Load instructions in LD1 port that are either unaligned, or treated as unaligned and require an additional recycle through the pipeline using the load gather buffer. This typically adds about 10 cycles to the latency of the instruction. This includes loads that cross the 128 byte boundary, octword loads that are not aligned, and a special forward progress case of a load that does not hit in the L1 and crosses the 32 byte boundary and is launched NTC. Counted at finish time. #157,u,g,n,n,n,u,PM_ST0_8B_FIN,8-byte or smaller store finished in the ST0 store execution unit. ##000000C094 8-byte or smaller store finished in the ST0 store execution unit. #158,u,g,n,n,n,u,PM_ST1_8B_FIN,8-byte or smaller store finished in the ST1 store execution unit. ##000000C894 8-byte or smaller store finished in the ST1 store execution unit. #159,u,g,n,n,n,u,PM_ST0_16B_FIN,16-byte store finished in the ST0 store execution unit. ##000000C098 16-byte store finished in the ST0 store execution unit. #160,u,g,n,n,n,u,PM_ST1_16B_FIN,16-byte store finished in the ST1 store execution unit. ##000000C898 16-byte store finished in the ST1 store execution unit. #161,u,g,n,n,n,u,PM_ST0_32B_FIN,32-byte store finished in the ST0 store execution unit. ##000000C09C 32-byte store finished in the ST0 store execution unit. #162,u,g,n,n,n,u,PM_ST1_32B_FIN,32-byte store finished in the ST1 store execution unit. ##000000C89C 32-byte store finished in the ST1 store execution unit. #163,u,g,n,n,n,u,PM_ST0_VECTOR_FIN,Any vector store operation finished in the ST0 store execution unit. Excludes store quad, stcx quad, store float double-pair, fused store double. ##000000C0A0 Any vector store operation finished in the ST0 store execution unit. Excludes store quad, stcx quad, store float double-pair, fused store double. #164,u,g,n,n,n,u,PM_ST1_VECTOR_FIN,Any vector store operation finished in the ST1 store execution unit. Excludes store quad, stcx quad, store float double-pair, fused store double. ##000000C8A0 Any vector store operation finished in the ST1 store execution unit. Excludes store quad, stcx quad, store float double-pair, fused store double. #165,u,g,n,n,n,u,PM_ST0_UNALIGNED_FIN,Store instructions in ST0 port that are either unaligned, or treated as unaligned and require an additional recycle through the pipeline. This typically adds about 10 cycles to the latency of the instruction. This only includes stores that cross the 128 byte boundary. Counted at finish time. ##000000C0A4 Store instructions in ST0 port that are either unaligned, or treated as unaligned and require an additional recycle through the pipeline. This typically adds about 10 cycles to the latency of the instruction. This only includes stores that cross the 128 byte boundary. Counted at finish time. #166,u,g,n,n,n,u,PM_ST1_UNALIGNED_FIN,Store instructions in ST1 port that are either unaligned, or treated as unaligned and require an additional recycle through the pipeline. This typically adds about 10 cycles to the latency of the instruction. This only includes stores that cross the 128 byte boundary. Counted at finish time. ##000000C8A4 Store instructions in ST1 port that are either unaligned, or treated as unaligned and require an additional recycle through the pipeline. This typically adds about 10 cycles to the latency of the instruction. This only includes stores that cross the 128 byte boundary. Counted at finish time. #167,u,g,n,n,n,u,PM_FALSE_LHS,False Load-Hit-Store (LHS) match detected. Load and store have a partial Effective Address (EA) match but they are actually independent of each other. The other cases of false LHS cause flushes and they are instrumented with separate PMU events. ##000000C0A8 False Load-Hit-Store (LHS) match detected. Load and store have a partial Effective Address (EA) match but they are actually independent of each other. The other cases of false LHS cause flushes and they are instrumented with separate PMU events. #168,u,g,n,n,n,u,PM_LD0_LHS_REJECT,On the LD0 load execution unit, the real address of a load matched the real address of an earlier store and it is not possible to store forward because not all bytes required by the load are available on the store entry that was hit. In this case, the load must wait for the store to drain or for the store data to issue. ##000000C8A8 On the LD0 load execution unit, the real address of a load matched the real address of an earlier store and it is not possible to store forward because not all bytes required by the load are available on the store entry that was hit. In this case, the load must wait for the store to drain or for the store data to issue. #169,u,g,n,n,n,u,PM_LD1_LHS_REJECT,On the LD1 load execution unit, the real address of a load matched the real address of an earlier store and it is not possible to store forward because not all bytes required by the load are available on the store entry that was hit. In this case, the load must wait for the store to drain or for the store data to issue. ##000000C0AC On the LD1 load execution unit, the real address of a load matched the real address of an earlier store and it is not possible to store forward because not all bytes required by the load are available on the store entry that was hit. In this case, the load must wait for the store to drain or for the store data to issue. #170,u,g,n,n,n,u,PM_ST0_STORE_REJECT,Store reject on the ST0 store execution unit. All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up, to try again after the condition has been met. ##000000C8AC Store reject on the ST0 store execution unit. All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up, to try again after the condition has been met. #171,u,g,n,n,n,u,PM_ST1_STORE_REJECT,Store reject on the ST1 store execution unit. All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up, to try again after the condition has been met. ##000000C0B0 Store reject on the ST1 store execution unit. All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up, to try again after the condition has been met. #172,u,g,n,n,n,u,PM_ST_DRAIN_MERGE,Two stores drain together. Use PM_ST_CMPL as a divider. If one of the stores crosses a cache-line boundary, a store drain can be counted for each half. In this case, if there are three stores they will count as two merges. ##000000C8B0 Two stores drain together. Use PM_ST_CMPL as a divider. If one of the stores crosses a cache-line boundary, a store drain can be counted for each half. In this case, if there are three stores they will count as two merges. #173,u,g,n,n,n,u,PM_LMQ_MERGE,A load-hit-reload occurred. A load launched in the LSU and hit an existing LMQ entry which is fetching data for the same cacheline. ##000000C0B4 A load-hit-reload occurred. A load launched in the LSU and hit an existing LMQ entry which is fetching data for the same cacheline. #174,u,g,n,n,n,u,PM_STCX_CMPL,STCX data was sent to nest, i.e. total count of stcx. stcx instructions are not allowed to gather before the final drain-out to the L1 and L2, so this count is always accurate. ##000000C8B4 STCX data was sent to nest, i.e. total count of stcx. stcx instructions are not allowed to gather before the final drain-out to the L1 and L2, so this count is always accurate. #175,u,g,n,n,n,u,PM_NCST_CMPL,Counts when an I=1 store op is sent to the nest. This event counts at drain time and it may include up to 3 stores that have gathered for the same cache line before drain. ##000000C0B8 Counts when an I=1 store op is sent to the nest. This event counts at drain time and it may include up to 3 stores that have gathered for the same cache line before drain. #176,u,g,n,n,n,u,PM_STCX_SUCCESS_CMPL,STCX instructions that completed successfully. Specifically, counts only when a pass status is returned from the nest. ##000000C8B8 STCX instructions that completed successfully. Specifically, counts only when a pass status is returned from the nest. #177,u,g,n,n,n,u,PM_DC_RELOAD_COLLISIONS,A load reading the L1 cache has a bank collision with another load reading the same bank, or due to a cache-line reload writing to that bank of the L1 cache. ##000000C0BC A load reading the L1 cache has a bank collision with another load reading the same bank, or due to a cache-line reload writing to that bank of the L1 cache. #178,u,g,n,n,n,u,PM_DC_STORE_WRITE_COLLISIONS,A store writing the L1 cache at the same time as a reload or dkill writing the L1 cache that results in a bank collision. ##000000C8BC A store writing the L1 cache at the same time as a reload or dkill writing the L1 cache that results in a bank collision. #179,u,g,n,n,n,u,PM_LSU_SET_MPRED,Set prediction(set-p) miss. The entry was not found in the Set prediction table. The set-p table contains a hash of the EA and it helps access the L1 cache. ##000000D080 Set prediction(set-p) miss. The entry was not found in the Set prediction table. The set-p table contains a hash of the EA and it helps access the L1 cache. #180,u,g,n,n,n,u,PM_DERAT_HIT,A load or store instruction missed the data cache and hit in the primary ERAT. There is no secondary ERAT ##000000D880 A load or store instruction missed the data cache and hit in the primary ERAT. There is no secondary ERAT #181,u,g,n,n,n,u,PM_IERAT_HIT,An instruction fetch missed in the instruction cache and hit in the primary ERAT. There is no secondary ERAT ##000000D084 An instruction fetch missed in the instruction cache and hit in the primary ERAT. There is no secondary ERAT #182,u,g,n,n,n,u,PM_TIQ_BYPASS,A translation request bypasses the TIQ either because the TIQ is completely empty at the time of the request. ##000000D884 A translation request bypasses the TIQ either because the TIQ is completely empty at the time of the request. #183,u,g,n,n,n,u,PM_TIQ_ALLOC_CYC,Cycles when one or more operations on that thread allocated one or more TIQ entries ##000000D088 Cycles when one or more operations on that thread allocated one or more TIQ entries #184,u,g,n,n,n,u,PM_TIQ_HALF_FULL_CYC,Cycles in which the TIQ has 4 or less active entries ##000000D888 Cycles in which the TIQ has 4 or less active entries #185,u,g,n,n,n,u,PM_TIQ_ERAT_MISS_EMB_FULL_RESPIN,A load or store missed in the ERAT and found no space in the EMB. ##000000D08C A load or store missed in the ERAT and found no space in the EMB. #186,u,g,n,n,n,u,PM_EMB_FULL_CYC,Cycles in which the ERAT miss buffer is full. When the ERAT miss buffer is full the operation will go to the TIQ ##000000D88C Cycles in which the ERAT miss buffer is full. When the ERAT miss buffer is full the operation will go to the TIQ #187,u,g,n,n,n,u,PM_LSU_FLUSH_CYC,LSU flushes: includes all LSU flushes. This event only counts one flush per cycle but the hardware can flush up to 5 instructions per cycle. In general, multiple flushes for the same thread get consolidated into a single flush operation. ##000000D090 LSU flushes: includes all LSU flushes. This event only counts one flush per cycle but the hardware can flush up to 5 instructions per cycle. In general, multiple flushes for the same thread get consolidated into a single flush operation. #188,u,g,n,n,n,u,PM_LSU_FLUSH_CI,Load was not initially issued to the LSU as a cache inhibited (non-cacheable) load, but it was later determined to be cache inhibited. ##000000D890 Load was not initially issued to the LSU as a cache inhibited (non-cacheable) load, but it was later determined to be cache inhibited. #189,u,g,n,n,n,u,PM_LSU_FLUSH_ALL_WAYS_LOCKED,Non-speculative stores have locked all ways in the data cache and a newly-issued older store is not able to allocate a way for a given congruence class. ##000000D094 Non-speculative stores have locked all ways in the data cache and a newly-issued older store is not able to allocate a way for a given congruence class. #190,u,g,n,n,n,u,PM_LSU_FLUSH_LHL,If a load hits on an older load of the same address that has been snooped, or two loads of the same thread and address execute out of order and a store of another thread occurs to that address, the younger load will be flushed. The LSU only checks the out-of-orderness of the two loads and ignores the address in detecting this condition. ##000000D894 If a load hits on an older load of the same address that has been snooped, or two loads of the same thread and address execute out of order and a store of another thread occurs to that address, the younger load will be flushed. The LSU only checks the out-of-orderness of the two loads and ignores the address in detecting this condition. #191,u,g,n,n,n,u,PM_LSU_FLUSH_SAME_ICT_GRP,This flush happens if an ICT pair contains a store followed by a load to the same address with at least one byte of overlap between the two. ##000000D098 This flush happens if an ICT pair contains a store followed by a load to the same address with at least one byte of overlap between the two. #192,u,g,n,n,n,u,PM_LSU_REJECT_LHS,Effective Address (EA) alias reject: no EA match but Real Addresses do match. ##000000D898 Effective Address (EA) alias reject: no EA match but Real Addresses do match. #193,u,g,n,n,n,u,PM_LSU_FLUSH_SPECIAL,LSU workaround flush. These flushes are setup with programmable scan-only latches to perform various actions when the flush macro receives a trigger from the debug macros. These actions include things like flushing the next op encountered for a particular thread, or flushing the next op that is the Next To Complete (NTC) op that is encountered on a particular slice. The kind of flush that the workaround is setup to perform is highly variable. ##000000D09C LSU workaround flush. These flushes are setup with programmable scan-only latches to perform various actions when the flush macro receives a trigger from the debug macros. These actions include things like flushing the next op encountered for a particular thread, or flushing the next op that is the Next To Complete (NTC) op that is encountered on a particular slice. The kind of flush that the workaround is setup to perform is highly variable. #194,u,g,n,n,n,u,PM_LSU_FLUSH_SHL,The instruction was flushed because of a sequential load/store consistency issue. If a load or store hits on an older load that has either been snooped (for loads) or has stale data (for stores), a flush will occur. ##000000D89C The instruction was flushed because of a sequential load/store consistency issue. If a load or store hits on an older load that has either been snooped (for loads) or has stale data (for stores), a flush will occur. #195,u,g,n,n,n,u,PM_LSU_FLUSH_SAO,A Load-Hit-Load condition with Strong Address Ordering (SAO) will have address compare disabled and will flush. ##000000D0A0 A Load-Hit-Load condition with Strong Address Ordering (SAO) will have address compare disabled and will flush. #196,u,g,n,n,n,u,PM_LSU_FLUSH_LARX_STCX,A LARX is flushed because an older LARX has an LMQ reservation for the same thread. A STCX is flushed because an older STCX is in the STQ. The flush happens when the older LARX/STCX relaunches ##000000D8A0 A LARX is flushed because an older LARX has an LMQ reservation for the same thread. A STCX is flushed because an older STCX is in the STQ. The flush happens when the older LARX/STCX relaunches #197,u,g,n,n,n,u,PM_LSU_FLUSH_OTHER,Other LSU flushes, including: * Sync - a sync acknowledge from the L2 caused a search of the LRQ for the oldest snooped load. This will either signal a Precise Flush of the oldest snooped load, or a Flush Next PPC. * Data Valid Flush Next - several cases of this, one example is store and reload are lined up such that a store-hit-reload scenario exists and the CDF has already launched and has gotten bad/stale data. * Bad Data Valid (DVAL) Flush Next - might be a few cases of this, one example is a larxa (D-cache hit) return data and DVAL signal, but can't allocate to the LMQ (either the LMQ is full, or some other reason). Already signaled DVAL but can't watch it for snoop_hit_larx. Need to take the “bad dval” back and flush all younger ops). ##000000D0A4 Other LSU flushes, including: * Sync - a sync acknowledge from the L2 caused a search of the LRQ for the oldest snooped load. This will either signal a Precise Flush of the oldest snooped load, or a Flush Next PPC. * Data Valid Flush Next - several cases of this, one example is store and reload are lined up such that a store-hit-reload scenario exists and the CDF has already launched and has gotten bad/stale data. * Bad Data Valid (DVAL) Flush Next - might be a few cases of this, one example is a larxa (D-cache hit) return data and DVAL signal, but can't allocate to the LMQ (either the LMQ is full, or some other reason). Already signaled DVAL but can't watch it for snoop_hit_larx. Need to take the “bad dval” back and flush all younger ops). #198,u,g,n,n,n,u,PM_DC_PREF_HW_ALLOC,Prefetch stream allocated by the hardware prefetch mechanism ##000000D8A4 Prefetch stream allocated by the hardware prefetch mechanism #199,u,g,n,n,n,u,PM_DC_PREF_SW_ALLOC,Prefetch stream allocated by software prefetching ##000000D0A8 Prefetch stream allocated by software prefetching #200,u,g,n,n,n,u,PM_DC_PREF_STRIDED_ALLOC,Strided prefetch stream allocated by either the software or hardware mechanisms ##000000D8A8 Strided prefetch stream allocated by either the software or hardware mechanisms #201,u,g,n,n,n,u,PM_DC_PREF_CONS_ALLOC,Prefetch stream allocated in the conservative phase by either the hardware prefetch mechanism or software prefetch. The sum of this pair subtracted from the total number of allocs will give the total allocs in normal phase ##000000D0AC Prefetch stream allocated in the conservative phase by either the hardware prefetch mechanism or software prefetch. The sum of this pair subtracted from the total number of allocs will give the total allocs in normal phase #202,u,g,n,n,n,u,PM_DC_PREF_XCONS_ALLOC,Prefetch stream allocated in the Ultra conservative phase by either the hardware prefetch mechanism or software prefetch ##000000D8AC Prefetch stream allocated in the Ultra conservative phase by either the hardware prefetch mechanism or software prefetch #203,u,g,n,n,n,u,PM_DC_PREF_CONF,A demand load referenced a line in an active prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. Includes forwards and backwards streams ##000000D0B0 A demand load referenced a line in an active prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. Includes forwards and backwards streams #204,u,g,n,n,n,u,PM_DC_PREF_FUZZY_CONF,A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up) ##000000D8B0 A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up) #205,u,g,n,n,n,u,PM_DC_PREF_STRIDED_CONF,A demand load referenced a line in an active strided prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. ##000000D0B4 A demand load referenced a line in an active strided prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. #206,u,g,n,n,n,u,PM_DC_PREF_DEALLOC_NO_CONF,A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up) ##000000D8B4 A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up) #207,u,g,n,n,n,u,PM_L1_SW_PREF,Software L1 Prefetches, including SW Transient Prefetches ##000000D0B8 Software L1 Prefetches, including SW Transient Prefetches #208,u,g,n,n,n,u,PM_L3_SW_PREF,L3 load prefetch, sourced from a software prefetch stream, was sent to the nest ##000000D0BC L3 load prefetch, sourced from a software prefetch stream, was sent to the nest #209,u,g,n,n,n,u,PM_SNOOP_TLBIE_MY_LPAR_CYC,TLBIE snoops executed in the LSU ##000000F080 TLBIE snoops executed in the LSU #210,u,g,n,n,n,u,PM_SNOOP_TLBIE_CYC,Cycles in which TLBIE snoops are executed in the LSU ##000000F880 Cycles in which TLBIE snoops are executed in the LSU #211,u,g,n,n,n,u,PM_SNOOP_TLBIE_CACHE_WALK_CYC,TLBIE snoop cycles in which the data cache is being walked ##000000F084 TLBIE snoop cycles in which the data cache is being walked #212,u,g,n,n,n,u,PM_SNOOP_TLBIE_WAIT_ST_CYC,TLBIE snoop cycles in which older stores are still draining ##000000F884 TLBIE snoop cycles in which older stores are still draining #213,u,g,n,n,n,u,PM_SNOOP_TLBIE_WAIT_LD_CYC,TLBIE snoop cycles in which older loads are still draining ##000000F088 TLBIE snoop cycles in which older loads are still draining #214,u,g,n,n,n,u,PM_SNOOP_TLBIE_WAIT_IFU_CYC,TLBIE snoop cycles in which the Load-Store unit is waiting for the instruction cache to be walked ##000000F888 TLBIE snoop cycles in which the Load-Store unit is waiting for the instruction cache to be walked #215,u,g,n,n,n,u,PM_SNOOP_TLBIE_WAIT_MMU_CYC,TLBIE snoop cycles in which the Load-Store unit is waiting for the MMU to finish invalidation ##000000F08C TLBIE snoop cycles in which the Load-Store unit is waiting for the MMU to finish invalidation #216,u,g,n,n,n,u,PM_LD0_SETP_HIT_EADIR_MISS,A load in the LD0 execution unit matched the setp Effective Address (EA) hash function for one of the ways in the L1. But the full EA does not match the L1 directory, so the request is sent to the L1 miss pipe. ##000000F094 A load in the LD0 execution unit matched the setp Effective Address (EA) hash function for one of the ways in the L1. But the full EA does not match the L1 directory, so the request is sent to the L1 miss pipe. #217,u,g,n,n,n,u,PM_SAME_EA_DIFF_CTXTAG_RADIR_HIT,A load or store did not get a full Effective Address (EA) plus Context match in the EA directory, so it is sent to the L1 miss pipe. In particular, a full EA match, but a context miss occurred. In the L1 miss pipe, the Real Address (RA) directory lookup finds that the real address is in the L1, but allocated in the EA directory with a different context. ##000000F898 A load or store did not get a full Effective Address (EA) plus Context match in the EA directory, so it is sent to the L1 miss pipe. In particular, a full EA match, but a context miss occurred. In the L1 miss pipe, the Real Address (RA) directory lookup finds that the real address is in the L1, but allocated in the EA directory with a different context. #218,u,g,n,n,n,u,PM_CTXT_MP4_ALLOC,A new entry is created in the 4 entry Context Alias Table due to a load or store that L1 missed due to same EA/different context, but whose Real Address (RA) was found in the L1 during (RA) directory lookup in the miss pipe. ##000000F09C A new entry is created in the 4 entry Context Alias Table due to a load or store that L1 missed due to same EA/different context, but whose Real Address (RA) was found in the L1 during (RA) directory lookup in the miss pipe. #219,u,g,n,n,n,u,PM_CTXT_ALIAS_HIT_CONTRIB,A load or a store in the miss pipe hits in the Real Address (RA) directory and also on one of the 4 entries of the Context Alias Table. The index and way getting an RA directory hit is written with a context alias tag to allow future L1 hits. ##000000F89C A load or a store in the miss pipe hits in the Real Address (RA) directory and also on one of the 4 entries of the Context Alias Table. The index and way getting an RA directory hit is written with a context alias tag to allow future L1 hits. #220,u,g,n,n,n,u,PM_START_NEW_RENAME,Upon creation of a new Context Alias Table entry, a 4k walk is initiated to set the Alias Tag valid for the 31 other congruence classes. The walk is only initiated after it is confirmed that at least 2 other congruence classes detected a context alias situation.  ##000000F0A0 Upon creation of a new Context Alias Table entry, a 4k walk is initiated to set the Alias Tag valid for the 31 other congruence classes. The walk is only initiated after it is confirmed that at least 2 other congruence classes detected a context alias situation.  #221,u,g,n,n,n,u,PM_STORE_ALLOCATE,A store misses the L1 Effective Address (EA) Directory and allocates an L1 index and way with its address for use in tracking the store address in the Load-Store Unit (LSU) during the SRQ lifetime of the store. ##000000F8A0 A store misses the L1 Effective Address (EA) Directory and allocates an L1 index and way with its address for use in tracking the store address in the Load-Store Unit (LSU) during the SRQ lifetime of the store. #222,u,g,n,n,n,u,PM_LOAD_ALLOC_DEPRA_FOR_ALL_WAYS_LOCKED,A load miss allocates an Load Miss Queue (LMQ) entry however it is not able to allocate an L1 index and way for load hazard detection in the LRQ because all 8 ways are locked, either by stores in the SRQ or other loads in the LMQ. The current load is instead marked deprecated. CDF will occur but it will be marked deprecated in the LRQ and ordering hazard checking will be pessimistic. ##000000F0A4 A load miss allocates an Load Miss Queue (LMQ) entry however it is not able to allocate an L1 index and way for load hazard detection in the LRQ because all 8 ways are locked, either by stores in the SRQ or other loads in the LMQ. The current load is instead marked deprecated. CDF will occur but it will be marked deprecated in the LRQ and ordering hazard checking will be pessimistic. #223,u,g,n,n,n,u,PM_STORE_REJECT_FOR_ALL_WAYS_LOCKED,A store misses the L1 Effective Address (EA) Directory, but cannot allocates an L1 index and way with its address due to all 8 ways being locked, either by stores already in the SRQ or by loads in the LMQ. The store is rejected and relaunched immediately. ##000000F8A4 A store misses the L1 Effective Address (EA) Directory, but cannot allocates an L1 index and way with its address due to all 8 ways being locked, either by stores already in the SRQ or by loads in the LMQ. The store is rejected and relaunched immediately. #224,u,g,n,n,n,u,PM_DERAT_HIT_4K,A load or store instruction missed the data cache and hit in the primary ERAT. Page size = 4K ##000000F0B0 A load or store instruction missed the data cache and hit in the primary ERAT. Page size = 4K #225,u,g,n,n,n,u,PM_IERAT_HIT_4K,An instruction fetch missed in the instruction cache and hit in the primary ERAT. Page size = 4k ##000000F8B0 An instruction fetch missed in the instruction cache and hit in the primary ERAT. Page size = 4k #226,u,g,n,n,n,u,PM_DERAT_HIT_64K,A load or store instruction missed the data cache and hit in the primary ERAT. Page size =64k ##000000F0B4 A load or store instruction missed the data cache and hit in the primary ERAT. Page size =64k #227,u,g,n,n,n,u,PM_IERAT_HIT_64K,An instruction fetch missed in the instruction cache and hit in the primary ERAT. Page size = 64k ##000000F8B4 An instruction fetch missed in the instruction cache and hit in the primary ERAT. Page size = 64k #228,u,g,n,n,n,u,PM_DERAT_HIT_2M,A load or store instruction missed the data cache and hit in the primary ERAT. Page size = 2M ##000000F0B8 A load or store instruction missed the data cache and hit in the primary ERAT. Page size = 2M #229,u,g,n,n,n,u,PM_IERAT_HIT_2M,An instruction fetch missed in the instruction cache and hit in the primary ERAT. Page size = 2M ##000000F8B8 An instruction fetch missed in the instruction cache and hit in the primary ERAT. Page size = 2M #230,u,g,n,n,n,u,PM_DERAT_HIT_1G,A load or store instruction missed the data cache and hit in the primary ERAT. Page size = 1G ##000000F0BC A load or store instruction missed the data cache and hit in the primary ERAT. Page size = 1G #231,u,g,n,n,n,u,PM_IERAT_HIT_1G,An instruction fetch missed in the instruction cache and hit in the primary ERAT. Page size = 1G ##000000F8BC An instruction fetch missed in the instruction cache and hit in the primary ERAT. Page size = 1G #232,u,g,n,n,n,u,PM_INST_FROM_L1,An instruction fetch hit in the L1. Each fetch group contains 8 instructions. The same line can hit 4 times if 32 sequential instructions are fetched. ##0000004080 An instruction fetch hit in the L1. Each fetch group contains 8 instructions. The same line can hit 4 times if 32 sequential instructions are fetched. #233,u,g,n,n,n,u,PM_NO_FETCH_BANK_CONFLICT_CYC,Cycles in which no instructions are fetched because of an interleave conflict. The ifar logic will detect an interleave conflict and kill the data that was read that cycle. ##0000004880 Cycles in which no instructions are fetched because of an interleave conflict. The ifar logic will detect an interleave conflict and kill the data that was read that cycle. #234,u,g,n,n,n,u,PM_NO_FETCH_EAT_FULL_CYC,Cycles in which no instructions are fetched because there is no room in EAT ##0000004084 Cycles in which no instructions are fetched because there is no room in EAT #235,u,g,n,n,n,u,PM_NO_FETCH_IBUF_FULL_CYC,Cycles in which no instructions are fetched because there is no room in the instruction buffers ##0000004884 Cycles in which no instructions are fetched because there is no room in the instruction buffers #236,u,g,n,n,n,u,PM_NO_FETCH_THROTTLE_CYC,Cycles in which no instructions are fetched for this thread because it is being throttled ##0000004088 Cycles in which no instructions are fetched for this thread because it is being throttled #237,u,g,n,n,n,u,PM_FETCH_CYC,Cycles in which instructions are successfully fetched from the instruction cache ##0000004888 Cycles in which instructions are successfully fetched from the instruction cache #238,u,g,n,n,n,u,PM_NO_FETCH_THROTTLE_POWMAN_CYC,Cycles in which the thread is throttled because of power management ##000000408C Cycles in which the thread is throttled because of power management #239,u,g,n,n,n,u,PM_NO_FETCH_THROTTLE_OTHER_CYC,Cycles in which the thread is throttled for a reason other than power management, relative priority and dynamic priority. This includes throttles for speculation for power or performance, independently decided by the IFAR ##000000488C Cycles in which the thread is throttled for a reason other than power management, relative priority and dynamic priority. This includes throttles for speculation for power or performance, independently decided by the IFAR #240,u,g,n,n,n,u,PM_NO_FETCH_THROTTLE_REL_PRIO_CYC,Cycles in which the thread is throttled because of relative priority. This is thread arbitration based on the Relative Priority Register (RPR). ##0000004090 Cycles in which the thread is throttled because of relative priority. This is thread arbitration based on the Relative Priority Register (RPR). #241,u,g,n,n,n,u,PM_NO_FETCH_THROTTLE_DYN_PRIO_CYC,Cycles in which the thread is throttled because of dynamic priority. This is the generic thread arbitration without relative thread priority. A thread may also be throttled if an instruction cache reload for a different thread occurs in the same cycle. ##0000004890 Cycles in which the thread is throttled because of dynamic priority. This is the generic thread arbitration without relative thread priority. A thread may also be throttled if an instruction cache reload for a different thread occurs in the same cycle. #242,u,g,n,n,n,u,PM_DECODE_THROTTLE_IIF_CYC,Cycles in which decode was held for a thread due to an Instruction-In-Flight throttle (WOF). This event will increment regardless of other decode holds being present ##0000004894 Cycles in which decode was held for a thread due to an Instruction-In-Flight throttle (WOF). This event will increment regardless of other decode holds being present #243,u,g,n,n,n,u,PM_DECODE_HOLD_NO_ITAGS,Cycles in which the IFU was not able to decode and transmit one or more instructions because all itags were in use. This means the ICT is full for this thread. This event will only increment when no other hold is present. ##0000004098 Cycles in which the IFU was not able to decode and transmit one or more instructions because all itags were in use. This means the ICT is full for this thread. This event will only increment when no other hold is present. #244,u,g,n,n,n,u,PM_DECODE_THROTTLE_IPC_CYC,Cycles in which decode is throttled because M over N throttle is active (WOF). This event will increment regardless of other decode holds being present ##0000004898 Cycles in which decode is throttled because M over N throttle is active (WOF). This event will increment regardless of other decode holds being present #245,u,g,n,n,n,u,PM_IC_INVALIDATE,A line in the instruction cache has been invalidated by an ICBI ##000000409C A line in the instruction cache has been invalidated by an ICBI #246,u,g,n,n,n,u,PM_IC_RELOAD_PRIVATE,An instruction cache line was brought in private for a specific thread. Most lines are brought in shared for all four threads. ##000000489C An instruction cache line was brought in private for a specific thread. Most lines are brought in shared for all four threads. #247,u,g,n,n,n,u,PM_IC_PREF_REQ,Instruction prefetch requests ##00000040A0 Instruction prefetch requests #248,u,g,n,n,n,u,PM_FUSED_BACK_TO_BACK,Back to back two-cycle execution. Counted at decode time ##00000048A0 Back to back two-cycle execution. Counted at decode time #249,u,g,n,n,n,u,PM_FUSED_DESTRUCTIVE,The first and second instruction have the same target register. Counted at decode time ##00000040A4 The first and second instruction have the same target register. Counted at decode time #250,u,g,n,n,n,u,PM_FUSED_RESULT,Two fused PowerPC (PPC set) instructions: the first PPC instruction, in age order, is the result of the second PPC instruction. Counted at decode time. ##00000048A4 Two fused PowerPC (PPC set) instructions: the first PPC instruction, in age order, is the result of the second PPC instruction. Counted at decode time. #251,u,g,n,n,n,u,PM_FUSED_TOGETHER,Produce 2 results together. Ex instruction having a fusable compare: fabs f3,f1 ##00000040A8 Produce 2 results together. Ex instruction having a fusable compare: fabs f3,f1 #252,u,g,n,n,n,u,PM_FUSED_LOADCOMPARE,Fusion of a load and a compare immediate referencing the load's data. Ex: ldx r3,r1,r2 ##00000048A8 Fusion of a load and a compare immediate referencing the load's data. Ex: ldx r3,r1,r2 #253,u,g,n,n,n,u,PM_FUSED_LOAD_LOAD,Fusion of two displacement loads (meeting the requirements for load-load fusion). ##00000040AC Fusion of two displacement loads (meeting the requirements for load-load fusion). #254,u,g,n,n,n,u,PM_BCQ_FULL_CYC,Cycles in which all 12 entries of the BCQ are full ##00000040B0 Cycles in which all 12 entries of the BCQ are full #255,u,g,n,n,n,u,PM_BR_FIN_FROM_BCQ,Branches that were issued with sources not ready (CR=0), counted at finish time. Branches go to the BCQ when their sources are not ready. ##00000048B0 Branches that were issued with sources not ready (CR=0), counted at finish time. Branches go to the BCQ when their sources are not ready. #256,u,g,n,n,n,u,PM_BR_TKN_FIN,A taken branch (conditional or unconditional) finished ##00000040B4 A taken branch (conditional or unconditional) finished #257,u,g,n,n,n,u,PM_BR_TKN_UNCOND_FIN,An unconditional branch finished. All unconditional branches are taken. ##00000048B4 An unconditional branch finished. All unconditional branches are taken. #258,u,g,n,n,n,u,PM_PRED_BR_TKN_COND_DIR,A conditional branch finished with correctly predicted direction. Resolved taken ##00000040B8 A conditional branch finished with correctly predicted direction. Resolved taken #259,u,g,n,n,n,u,PM_PRED_BR_NTKN_COND_DIR,A conditional branch finished with correctly predicted direction. Resolved not taken ##00000048B8 A conditional branch finished with correctly predicted direction. Resolved not taken #260,u,g,n,n,n,u,PM_MPRED_BR_TKN_COND_DIR,A conditional branch finished with mispredicted direction. Resolved taken ##00000040BC A conditional branch finished with mispredicted direction. Resolved taken #261,u,g,n,n,n,u,PM_MPRED_BR_NTKN_COND_DIR,A conditional branch finished with mispredicted direction. Resolved not taken ##00000048BC A conditional branch finished with mispredicted direction. Resolved not taken #262,u,g,n,n,n,u,PM_PRED_BR_TKN_COND_TGT_DIR,A conditional branch finished with correctly predicted target and direction. Resolved taken ##0000005080 A conditional branch finished with correctly predicted target and direction. Resolved taken #263,u,g,n,n,n,u,PM_PRED_BR_NTKN_COND_TGT_DIR,A conditional branch finished with correctly predicted target and direction. Resolved not taken ##0000005880 A conditional branch finished with correctly predicted target and direction. Resolved not taken #264,u,g,n,n,n,u,PM_MPRED_BR_NTKN_COND_TGT_DIR,A conditional branch finished with mispredicted target and direction. Resolved not taken ##0000005884 A conditional branch finished with mispredicted target and direction. Resolved not taken #265,u,g,n,n,n,u,PM_BR_PRED_TKN_COND_DIR_LBHT_LSEL,A conditional branch finished with correctly predicted direction using the Local Branch History Table selected by the local selector. Resolved taken ##0000005088 A conditional branch finished with correctly predicted direction using the Local Branch History Table selected by the local selector. Resolved taken #266,u,g,n,n,n,u,PM_BR_PRED_TKN_COND_DIR_LBHT_GSEL,A conditional branch finished with correctly predicted direction using the Local Branch History Table selected with the global selector. Resolved taken ##0000005888 A conditional branch finished with correctly predicted direction using the Local Branch History Table selected with the global selector. Resolved taken #267,u,g,n,n,n,u,PM_BR_PRED_TKN_COND_DIR_GBHT,A conditional branch finished with correctly predicted direction using the Global Branch History Table. Resolved taken ##000000508C A conditional branch finished with correctly predicted direction using the Global Branch History Table. Resolved taken #268,u,g,n,n,n,u,PM_BR_PRED_TKN_COND_DIR_TAGE,A conditional branch finished with correctly predicted direction using a TAGE override. Resolved taken ##000000588C A conditional branch finished with correctly predicted direction using a TAGE override. Resolved taken #269,u,g,n,n,n,u,PM_BR_PRED_TKN_COND_DIR_TOP,A conditional branch finished with correctly predicted direction using a TOP override to the BHT. Resolved taken ##0000005090 A conditional branch finished with correctly predicted direction using a TOP override to the BHT. Resolved taken #270,u,g,n,n,n,u,PM_BR_PRED_TKN_COND_TGT_COUNT_LCC,A conditional branch finished with correctly predicted target using the local count cache. Resolved taken ##0000005890 A conditional branch finished with correctly predicted target using the local count cache. Resolved taken #271,u,g,n,n,n,u,PM_BR_PRED_TKN_COND_TGT_COUNT_GCC,A conditional branch finished with correctly predicted target using the global count cache. Resolved taken ##0000005094 A conditional branch finished with correctly predicted target using the global count cache. Resolved taken #272,u,g,n,n,n,u,PM_BR_PRED_TKN_COND_TGT_COUNT_TIP,A conditional branch finished with correctly predicted target using the count TIP override to the count cache. Resolved taken ##0000005894 A conditional branch finished with correctly predicted target using the count TIP override to the count cache. Resolved taken #273,u,g,n,n,n,u,PM_BR_PRED_TKN_TGT_LINK,A conditional or unconditional branch finished with correctly predicted target using the Link register (bclr[l]) and predicted by Link Stack (BH(1)=0). Resolved taken ##0000005098 A conditional or unconditional branch finished with correctly predicted target using the Link register (bclr[l]) and predicted by Link Stack (BH(1)=0). Resolved taken #274,u,g,n,n,n,u,PM_BR_PRED_NTKN_COND_DIR_LBHT_LSEL,A conditional branch finished with correctly predicted direction using the Local Branch History Table selected by the local selector. Resolved not taken ##0000005898 A conditional branch finished with correctly predicted direction using the Local Branch History Table selected by the local selector. Resolved not taken #275,u,g,n,n,n,u,PM_BR_PRED_NTKN_COND_DIR_LBHT_GSEL,A conditional branch finished with correctly predicted direction using the Local Branch History Table selected with the global selector. Resolved not taken ##000000509C A conditional branch finished with correctly predicted direction using the Local Branch History Table selected with the global selector. Resolved not taken #276,u,g,n,n,n,u,PM_BR_PRED_NTKN_COND_DIR_GBHT,A conditional branch finished with correctly predicted direction using the Global Branch History Table. Resolved not taken ##000000589C A conditional branch finished with correctly predicted direction using the Global Branch History Table. Resolved not taken #277,u,g,n,n,n,u,PM_BR_PRED_NTKN_COND_DIR_TAGE,A conditional branch finished with correctly predicted direction using a TAGE override. Resolved not taken ##00000050A0 A conditional branch finished with correctly predicted direction using a TAGE override. Resolved not taken #278,u,g,n,n,n,u,PM_BR_PRED_NTKN_COND_DIR_TOP,A conditional branch finished with correctly predicted direction using a TOP override to the BHT. Resolved not taken ##00000058A0 A conditional branch finished with correctly predicted direction using a TOP override to the BHT. Resolved not taken #279,u,g,n,n,n,u,PM_SHL_CREATED,An Store-Hit-Load Table entry was created as a result of an SHL Flush. ##00000050A4 An Store-Hit-Load Table entry was created as a result of an SHL Flush. #280,u,g,n,n,n,u,PM_SHL_ST_DEPENDENCY,A fetched instruction hit in the Store-Hit-Load Table. ##00000058A4 A fetched instruction hit in the Store-Hit-Load Table. #281,u,g,n,n,n,u,PM_IEADIR_HIT_IDIR_MISS,A fetch hit in the IEADIR but missed in the IDIR. This is usually due to IEADIR aliasing, but could be due to an IDIR invalidate that did not invalidate the corresponding IEADIR entry. ##00000050A8 A fetch hit in the IEADIR but missed in the IDIR. This is usually due to IEADIR aliasing, but could be due to an IDIR invalidate that did not invalidate the corresponding IEADIR entry. #282,u,g,n,n,n,u,PM_ICACHE_MISS_DUE_TO_CTXTTAG,A fetch missed the instruction cache due to a context tag miscompare. All other fields matched. This is similar to PM_IEA_TRACKING_TABLE_WRITE but is not restricted to context tags restricted to IEA Sharing and does not require IEA Sharing to be enabled. ##00000058A8 A fetch missed the instruction cache due to a context tag miscompare. All other fields matched. This is similar to PM_IEA_TRACKING_TABLE_WRITE but is not restricted to context tags restricted to IEA Sharing and does not require IEA Sharing to be enabled. #283,u,g,n,n,n,u,PM_BR_MPRED_TKN_COND_DIR_LBHT_LSEL,A conditional branch finished with mispredicted direction using the Local Branch History Table selected by the local selector. Resolved taken ##00000050AC A conditional branch finished with mispredicted direction using the Local Branch History Table selected by the local selector. Resolved taken #284,u,g,n,n,n,u,PM_BR_MPRED_TKN_COND_DIR_LBHT_GSEL,A conditional branch finished with mispredicted direction using the Local Branch History Table selected with the global selector. Resolved taken ##00000058AC A conditional branch finished with mispredicted direction using the Local Branch History Table selected with the global selector. Resolved taken #285,u,g,n,n,n,u,PM_BR_MPRED_TKN_COND_DIR_GBHT,A conditional branch finished with mispredicted direction using the Global Branch History Table. Resolved taken ##00000050B0 A conditional branch finished with mispredicted direction using the Global Branch History Table. Resolved taken #286,u,g,n,n,n,u,PM_BR_MPRED_TKN_COND_DIR_TAGE,A conditional branch finished with mispredicted direction using a TAGE override. Resolved taken ##00000058B0 A conditional branch finished with mispredicted direction using a TAGE override. Resolved taken #287,u,g,n,n,n,u,PM_BR_MPRED_TKN_COND_DIR_TOP,A conditional branch finished with mispredicted direction using a TOP override to the BHT. Resolved taken ##00000050B4 A conditional branch finished with mispredicted direction using a TOP override to the BHT. Resolved taken #288,u,g,n,n,n,u,PM_BR_MPRED_TKN_COND_TGT_COUNT_LCC,A conditional branch finished with mispredicted target using the local count cache. Resolved taken ##00000058B4 A conditional branch finished with mispredicted target using the local count cache. Resolved taken #289,u,g,n,n,n,u,PM_BR_MPRED_TKN_COND_TGT_COUNT_GCC,A conditional branch finished with mispredicted target using the global count cache. Resolved taken ##00000050B8 A conditional branch finished with mispredicted target using the global count cache. Resolved taken #290,u,g,n,n,n,u,PM_BR_MPRED_TKN_COND_TGT_COUNT_TIP,A conditional branch finished with mispredicted target using the count TIP override to the count cache. Resolved taken ##00000058B8 A conditional branch finished with mispredicted target using the count TIP override to the count cache. Resolved taken #291,u,g,n,n,n,u,PM_BR_MPRED_TKN_TGT_LINK,A conditional or unconditional branch finished with mispredicted target using the Link register. Resolved taken ##00000050BC A conditional or unconditional branch finished with mispredicted target using the Link register. Resolved taken #292,u,g,n,n,n,u,PM_BR_MPRED_NTKN_COND_DIR_LBHT_LSEL,A conditional branch finished with mispredicted direction using the Local Branch History Table selected by the local selector. Resolved not taken ##00000058BC A conditional branch finished with mispredicted direction using the Local Branch History Table selected by the local selector. Resolved not taken #293,u,g,n,n,n,u,PM_BR_MPRED_NTKN_COND_DIR_LBHT_GSEL,A conditional branch finished with mispredicted direction using the Local Branch History Table selected with the global selector. Resolved not taken ##000000E080 A conditional branch finished with mispredicted direction using the Local Branch History Table selected with the global selector. Resolved not taken #294,u,g,n,n,n,u,PM_BR_MPRED_NTKN_COND_DIR_GBHT,A conditional branch finished with mispredicted direction using the Global Branch History Table. Resolved not taken ##000000E880 A conditional branch finished with mispredicted direction using the Global Branch History Table. Resolved not taken #295,u,g,n,n,n,u,PM_BR_MPRED_NTKN_COND_DIR_TAGE,A conditional branch finished with mispredicted direction using a TAGE override. Resolved not taken ##000000E084 A conditional branch finished with mispredicted direction using a TAGE override. Resolved not taken #296,u,g,n,n,n,u,PM_BR_MPRED_NTKN_COND_DIR_TOP,A conditional branch finished with mispredicted direction using a TOP override to the BHT. Resolved not taken ##000000E884 A conditional branch finished with mispredicted direction using a TOP override to the BHT. Resolved not taken #297,u,g,n,n,n,u,PM_IEA_ALIAS_TABLE_WRITE,IFU EA Sharing was detected and the sharing info was written to the IFU Alias Table. ##000000E088 IFU EA Sharing was detected and the sharing info was written to the IFU Alias Table. #298,u,g,n,n,n,u,PM_IEA_ALIAS_TABLE_HIT,Instruction cache reload hit on the Alias Table and was written to the ICache as an IEA Shared entry. ##000000E888 Instruction cache reload hit on the Alias Table and was written to the ICache as an IEA Shared entry. #299,u,g,n,n,n,u,PM_IEA_TRACKING_TABLE_WRITE,Instruction cache miss occurred where ICache EA Sharing may be possible. i.e. All IDIR fields matched except the context tag and the incumbent context tag is compatible with IEA Sharing. ##000000E08C Instruction cache miss occurred where ICache EA Sharing may be possible. i.e. All IDIR fields matched except the context tag and the incumbent context tag is compatible with IEA Sharing. #300,u,g,n,n,n,u,PM_IEA_ICACHE_SHARED_HIT,Instruction cache hit occurred on an entry that is marked as IEA Sharing. This does not include ICache reload bypasses. ##000000E88C Instruction cache hit occurred on an entry that is marked as IEA Sharing. This does not include ICache reload bypasses. #301,u,g,n,n,n,u,PM_BR_BTAC_INV_TGT,BTAC predicts a target that is different from what the BHT and count cache predict. The BTAC entry is invalidated. Reported at fetch time ##000000E890 BTAC predicts a target that is different from what the BHT and count cache predict. The BTAC entry is invalidated. Reported at fetch time #302,u,g,n,n,n,u,PM_BR_BTAC_INV_DIR,BTAC predicts taken for a branch that the BHT predicts not taken, so that BTAC entry is invalidated. Reported at fetch time ##000000E094 BTAC predicts taken for a branch that the BHT predicts not taken, so that BTAC entry is invalidated. Reported at fetch time #303,u,g,n,n,n,u,PM_BR_PRED_COND_BTAC,A conditional branch finished with correctly predicted target or direction using the BTAC. Reported at fetch time ##000000E894 A conditional branch finished with correctly predicted target or direction using the BTAC. Reported at fetch time #304,u,g,n,n,n,u,PM_MPRED_BR_FIN,A conditional branch mispredicted its direction or target address. Counted at finish time ##000000E098 A conditional branch mispredicted its direction or target address. Counted at finish time #305,u,g,n,n,n,u,PM_BR_PRED_TKN_SWHINT,A software hinted branch finished and the branch resolved taken and the hint was correct. ##000000E898 A software hinted branch finished and the branch resolved taken and the hint was correct. #306,u,g,n,n,n,u,PM_BR_PRED_NTKN_SWHINT,A software hinted branch finished and the branch resolved not taken and the hint was correct. ##000000E09C A software hinted branch finished and the branch resolved not taken and the hint was correct. #307,u,g,n,n,n,u,PM_BR_MPRED_TKN_SWHINT,A software hinted branch finished and the branch resolved taken and the hint was incorrect. ##000000E89C A software hinted branch finished and the branch resolved taken and the hint was incorrect. #308,u,g,n,n,n,u,PM_BR_MPRED_NTKN_SWHINT,A software hinted branch finished and the branch resolved not taken and the hint was incorrect. ##000000E0A0 A software hinted branch finished and the branch resolved not taken and the hint was incorrect. #309,u,g,n,n,n,u,PM_BACK_BRANCH,Branch whose target address is lower than the program counter ##000000E0A4 Branch whose target address is lower than the program counter #310,u,g,n,n,n,u,PM_TLB_ACCESS_L3PREF,Incoming L3 prefetches that access the TLB (there is no L3 instruction prefetching in POWER10). L3 prefetches access the TLB directly, without accessing the ERAT ##0000008080 Incoming L3 prefetches that access the TLB (there is no L3 instruction prefetching in POWER10). L3 prefetches access the TLB directly, without accessing the ERAT #311,u,g,n,n,n,u,PM_TLB_CHILD_PURGE_CYC,Cycles spent in a TLB scrub. Counted for radix or HPT translations. Implies a parent eviction ##0000008880 Cycles spent in a TLB scrub. Counted for radix or HPT translations. Implies a parent eviction #312,u,g,n,n,n,u,PM_REJ_MMU,The MMU rejects a translation for any reason. This includes loads/stores/ifetches. ##0000008884 The MMU rejects a translation for any reason. This includes loads/stores/ifetches. #313,u,g,n,n,n,u,PM_REJ_EXEC_NTC_SLEEP_SELECT,The operation is rejected because it must be NTC to translate. This includes loads/stores/ifetches. ##0000008088 The operation is rejected because it must be NTC to translate. This includes loads/stores/ifetches. #314,u,g,n,n,n,u,PM_RDXWALK_INSTR_CYC,Cycles when an instruction(MMU type fetch) tablewalk is active. ##000000808C Cycles when an instruction(MMU type fetch) tablewalk is active. #315,u,g,n,n,n,u,PM_RDXWALK_DATA_CYC,Data Tablewalk Cycles. Cycles in which at least one tablewalk is in progress. This event includes data, demand and prefetch(MMU type LD, ST, L1 Prefetch). There can be up to 4 tablewalks in one cycle. ##000000888C Data Tablewalk Cycles. Cycles in which at least one tablewalk is in progress. This event includes data, demand and prefetch(MMU type LD, ST, L1 Prefetch). There can be up to 4 tablewalks in one cycle. #316,u,g,n,n,n,u,PM_REJ_TABLEWALK_L2_PDE_MERGE,A translation is rejected on a level 2 PDE boundary. This is only valid for radix. This is when the incoming translation matches on the 1G address boundary, but not a 2M address boundary. ##0000008090 A translation is rejected on a level 2 PDE boundary. This is only valid for radix. This is when the incoming translation matches on the 1G address boundary, but not a 2M address boundary. #317,u,g,n,n,n,u,PM_REJ_TABLEWALK_L3_PDE_MERGE,A translation is rejected on a level 3 PDE boundary. This is when the incoming translation matches on the 2M address boundary, but not the 64k address boundary. This is only valid in radix translations. ##0000008890 A translation is rejected on a level 3 PDE boundary. This is when the incoming translation matches on the 2M address boundary, but not the 64k address boundary. This is only valid in radix translations. #318,u,g,n,n,n,u,PM_REJ_TABLEWALK_PTE_MERGE,A translation is rejected on a PTE boundary. This indicates that the table walk merged due to a full 4k or 64k address match. This is valid for both Radix and HPT. In HPT this is both the parent hit, child miss case, and the parent miss case. ##0000008094 A translation is rejected on a PTE boundary. This indicates that the table walk merged due to a full 4k or 64k address match. This is valid for both Radix and HPT. In HPT this is both the parent hit, child miss case, and the parent miss case. #319,u,g,n,n,m,u,PM_MRK_DTABLEWALK_CYC,Cycles a data(MMU type LD, ST, L1 PF) tablewalk is in progress for a marked instruction. ##0000008894 Cycles a data(MMU type LD, ST, L1 PF) tablewalk is in progress for a marked instruction. #320,u,g,n,n,n,u,PM_XLATE_HPT_MODE_CYC,MMU reports every cycle the thread is in HPT translation mode (as opposed to radix mode) ##0000008098 MMU reports every cycle the thread is in HPT translation mode (as opposed to radix mode) #321,u,g,n,n,n,u,PM_XLATE_RADIX_MODE_CYC,MMU reports every cycle the thread is in radix translation mode (as opposed to HPT mode) ##0000008898 MMU reports every cycle the thread is in radix translation mode (as opposed to HPT mode) #322,u,g,n,n,n,u,PM_XLATE_L2_REQ,The MMU requested a line from L2 for translation. It may be satisfied from L2 and beyond. Includes speculative instructions. Includes instruction, prefetch and demand. ##000000809C The MMU requested a line from L2 for translation. It may be satisfied from L2 and beyond. Includes speculative instructions. Includes instruction, prefetch and demand. #323,u,g,n,n,n,u,PM_RDXTLB_ANY_NSTD_ANY_HST_HIT,Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup. If this event increments, one and only one of the following must also increment: PM_RDXTLB_ANY_NSTD_64K_HST_HIT, PM_RDXTLB_ANY_NSTD_2M_HST_HIT, or PM_RDXTLB_ANY_NSTD_1G_HST_HIT ##00000080A0 Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup. If this event increments, one and only one of the following must also increment: PM_RDXTLB_ANY_NSTD_64K_HST_HIT, PM_RDXTLB_ANY_NSTD_2M_HST_HIT, or PM_RDXTLB_ANY_NSTD_1G_HST_HIT #324,u,g,n,n,n,u,PM_RDXTLB_ANY_NSTD_4K_HST_HIT,Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup w/ the 4K page size. Due to P10 microarchitecture, this event will never increment. ##00000088A0 Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup w/ the 4K page size. Due to P10 microarchitecture, this event will never increment. #325,u,g,n,n,n,u,PM_RDXTLB_ANY_NSTD_64K_HST_HIT,Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup w/ the 64K page size. ##00000080A4 Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup w/ the 64K page size. #326,u,g,n,n,n,u,PM_RDXTLB_ANY_NSTD_2M_HST_HIT,Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup w/ the 2M page size. ##00000088A4 Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup w/ the 2M page size. #327,u,g,n,n,n,u,PM_RDXTLB_ANY_NSTD_1G_HST_HIT,Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup w/ the 1G page size. ##00000080A8 Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup w/ the 1G page size. #328,u,g,n,n,n,u,PM_RDXTLB_ANY_NSTD_ACC,Qualified as nested radix translations. There was a TLB lookup for any nested radix partition scoped translation. ##00000088A8 Qualified as nested radix translations. There was a TLB lookup for any nested radix partition scoped translation. #329,u,g,n,n,n,u,PM_RDXTLB_ANY_NSTD_MISS,Qualified as nested radix translations. There was a complete TLB miss on any intermediate TLB lookup. ##00000080AC Qualified as nested radix translations. There was a complete TLB miss on any intermediate TLB lookup. #330,u,g,n,n,n,u,PM_SNOOP_TLBIE_ARB_CYC,Cycles the MMU is in the process of arbitrating an incoming TLBIE snoop, but the snoop has not yet acquired the MML lock. ##0000009080 Cycles the MMU is in the process of arbitrating an incoming TLBIE snoop, but the snoop has not yet acquired the MML lock. #331,u,g,n,n,n,u,PM_SNOOP_TLBIE_TLB_INV_CYC,Cycles the MMU is in the process of walking the TLB for a TLBIE. From the time the probe is installed to the time the probe is uninstalled. ##0000009880 Cycles the MMU is in the process of walking the TLB for a TLBIE. From the time the probe is installed to the time the probe is uninstalled. #332,u,g,n,n,n,u,PM_SNOOP_TLBIE_NOT_MY_LPAR_CONTEXT_TABLE_HIT_CYC,Total duration of the snoop TLBIE when there is a context table hit, but a not-my-lpar (LSU is counting my-lpar case). ##0000009084 Total duration of the snoop TLBIE when there is a context table hit, but a not-my-lpar (LSU is counting my-lpar case). #333,u,g,n,n,n,u,PM_SNOOP_TLBIE_NOT_MY_LPAR_CONTEXT_TABLE_MISS_CYC,Total duration of the snoop TLBIE when there is a context table miss. ##0000009884 Total duration of the snoop TLBIE when there is a context table miss. #334,u,g,n,n,n,u,PM_SNOOP_TLBIE,Total number of TLBIE snoops ##0000009088 Total number of TLBIE snoops #335,u,g,n,n,n,u,PM_DTLB_ACCESS_ERAT_MISS,The TLB was read to satisfy a load or store ERAT miss. This includes demands and L1 prefetching data(MMU type LD, ST, L1PF) ##000000908C The TLB was read to satisfy a load or store ERAT miss. This includes demands and L1 prefetching data(MMU type LD, ST, L1PF) #336,u,g,n,n,n,u,PM_ITLB_ACCESS_ERAT_MISS,The TLB was read to satisfy an instruction ERAT miss. This includes demands and L1 prefetching for instruction (MMU Type Fetch) ##000000988C The TLB was read to satisfy an instruction ERAT miss. This includes demands and L1 prefetching for instruction (MMU Type Fetch) #337,u,g,n,n,n,u,PM_HPTWALK_INSTR_CYC,Cycles when an instruction tablewalk is active. This is qualified for HPT translations. ##0000009090 Cycles when an instruction tablewalk is active. This is qualified for HPT translations. #338,u,g,n,n,n,u,PM_HPTWALK_DATA_CYC,Data Tablewalk Cycles. Cycles in which at least one tablewalk is in progress. This event includes data and instruction, demand and prefetch. There can be up to 4 tablewalks in one cycle. (MMU Type LD, ST, L1PF) ##0000009890 Data Tablewalk Cycles. Cycles in which at least one tablewalk is in progress. This event includes data and instruction, demand and prefetch. There can be up to 4 tablewalks in one cycle. (MMU Type LD, ST, L1PF) #339,u,g,n,n,n,u,PM_REJ_PROBE_MATCH_PRS0,A load/store, fetch, or prefetch was rejected because it matched on a partition scoped probe. This is set for both Radix and HPT ##0000009094 A load/store, fetch, or prefetch was rejected because it matched on a partition scoped probe. This is set for both Radix and HPT #340,u,g,n,n,n,u,PM_REJ_PROBE_MATCH_PRS1,A load/store, fetch, or prefetch was rejected because it matched on a process scoped probe. This is Radix only ##0000009894 A load/store, fetch, or prefetch was rejected because it matched on a process scoped probe. This is Radix only #341,u,g,n,n,n,u,PM_REJ_PROBE_MATCH_MML,A load/store, fetch, or prefetch was rejected because it matched on the MML lock. This is set for both Radix and HPT ##0000009098 A load/store, fetch, or prefetch was rejected because it matched on the MML lock. This is set for both Radix and HPT #342,u,g,n,n,n,u,PM_REJ_PIPE_COLLISION_2ND_RELOAD,A load/store or fetch was rejected because there was a collision in the MMU pipeline with a 2nd pass & a reload. ##0000009898 A load/store or fetch was rejected because there was a collision in the MMU pipeline with a 2nd pass & a reload. #343,u,g,n,n,n,u,PM_REJ_XMQ_FULL,A translation was rejected because the MMU was full. ##000000909C A translation was rejected because the MMU was full. #344,u,g,n,n,n,u,PM_BLOCK_ERAT_WRITE,A valid translation reloaded the ERAT with block write enabled. ##000000989C A valid translation reloaded the ERAT with block write enabled. #345,u,g,n,n,n,u,PM_2ND_PASS_RADIX,The 2nd pass for Radix was initiated. ##00000090A0 The 2nd pass for Radix was initiated. #346,u,g,n,n,n,u,PM_2ND_PASS_HPT,The 2nd pass for HPT was initiated. This doesn't include VA hash mispredicts. ##00000098A0 The 2nd pass for HPT was initiated. This doesn't include VA hash mispredicts. #347,u,g,n,n,n,u,PM_VA_HASH_MPRED,The 1st pass for HPT was rejected due to VA hash mispredicts. ##00000090A4 The 1st pass for HPT was rejected due to VA hash mispredicts. #348,u,g,n,n,n,u,PM_CHILD_PURGE_HIT,Total amount of congruence classes that found at least 1 invalidation match for a child purge. ##000000A080 Total amount of congruence classes that found at least 1 invalidation match for a child purge. #349,u,g,n,n,n,u,PM_TLBIE_INV_CC_PRS0_COMPOSITE_CHILD_HASH,Congruence classes that found at least 1 invalidation match for a partition scoped hash match. ##000000A084 Congruence classes that found at least 1 invalidation match for a partition scoped hash match. #350,u,g,n,n,n,u,PM_TLBIE_INV_CC_PRS0_COMPOSITE_PARENT_HASH,Congruence classes that found at least 1 invalidation match for a partition scoped parent hash match. ##000000A884 Congruence classes that found at least 1 invalidation match for a partition scoped parent hash match. #351,u,g,n,n,n,u,PM_TLBIE_INV_ATTEMPT_CC_PRS0_COMPOSITE_CHILD,A partition scoped child hash invalidation was sent to the TLB. ##000000A088 A partition scoped child hash invalidation was sent to the TLB. #352,u,g,n,n,n,u,PM_TLBIE_INV_ATTEMPT_CC_PRS0_COMPOSITE_PARENT,A partition scoped parent hash invalidation was sent to the TLB. ##000000A888 A partition scoped parent hash invalidation was sent to the TLB. #353,u,g,n,n,n,u,PM_TLBIE_INV_ATTEMPT_HPT_PRECISE,Precise TLBIES sent to TLB in HPT. ##000000A08C Precise TLBIES sent to TLB in HPT. #354,u,g,n,n,n,u,PM_TLBIE_INV_CC_HPT_PRECISE,Precise TLBIEs sent to TLB for HPT invalidations and had at least 1 matching entry in the congruence class. ##000000A88C Precise TLBIEs sent to TLB for HPT invalidations and had at least 1 matching entry in the congruence class. #355,u,g,n,n,n,u,PM_CASE_A_HIT_MTPID,mtpid instruction found a Case A Context Table Hit. ##000000A090 mtpid instruction found a Case A Context Table Hit. #356,u,g,n,n,n,u,PM_CASE_A_HIT_MTLPID,mtlpid instruction found a Case A Context Table Hit. ##000000A890 mtlpid instruction found a Case A Context Table Hit. #357,u,g,n,n,n,u,PM_CASE_B_HIT_MTLPID,A mtlpid instruction found a Case B Context table hit. ##000000A094 A mtlpid instruction found a Case B Context table hit. #358,u,g,n,n,n,u,PM_CASE_C_HIT_MTPID,A mtpid instruction found a Case C Context table hit. ##000000A894 A mtpid instruction found a Case C Context table hit. #359,u,g,n,n,n,u,PM_CASE_A_MISS_MTPID,A mtpid instruction found a Case A context table miss ##000000A098 A mtpid instruction found a Case A context table miss #360,u,g,n,n,n,u,PM_CASE_A_MISS_MTLPID,A mtlpid instruction found a Case A Context table miss ##000000A898 A mtlpid instruction found a Case A Context table miss #361,u,g,n,n,n,u,PM_CASE_B_MISS_MTLPID,A mtlpid instruction found a Case B Context table miss ##000000A09C A mtlpid instruction found a Case B Context table miss #362,u,g,n,n,n,u,PM_CASE_C_MISS_MTPID,A mtpid instruction found a Case C Context table miss. ##000000A89C A mtpid instruction found a Case C Context table miss. #363,u,g,n,n,n,u,PM_MTPID,The thread executed a mtpid instruction. ##000000A0A0 The thread executed a mtpid instruction. #364,u,g,n,n,n,u,PM_MTLPID,The thread executed a mtlpid instruction. ##000000A8A0 The thread executed a mtlpid instruction. #365,u,g,n,n,n,u,PM_CASE_A_SNOOP_TLBIE_HIT,A snoop hit on a Case A context tag. ##000000A0A4 A snoop hit on a Case A context tag. #366,u,g,n,n,n,u,PM_CASE_B_SNOOP_TLBIE_HIT,A snoop hit on a Case B Context tag. ##000000A8A4 A snoop hit on a Case B Context tag. #367,u,g,n,n,n,u,PM_CASE_C_SNOOP_TLBIE_HIT,A snoop hit on a Case C context tag. ##000000A0A8 A snoop hit on a Case C context tag. #368,u,g,n,n,n,u,PM_CASE_D_SNOOP_TLBIE_HIT,A snoop hit on a Case D context tag. ##000000A8A8 A snoop hit on a Case D context tag. #369,u,g,n,n,n,u,PM_SNOOP_TLBIE_NOT_MY_LPAR_CONTEXT_TABLE_HIT,A snoop found a not-my-lpar but found a context table hit. ##000000A0AC A snoop found a not-my-lpar but found a context table hit. #370,u,g,n,n,n,u,PM_SNOOP_TLBIE_NOT_MY_LPAR_CONTEXT_TABLE_MISS,A snoop found a not-my-lpar but found a context table miss. ##000000A8AC A snoop found a not-my-lpar but found a context table miss. #371,u,g,n,n,n,u,PM_LPAR_SNOOP_HIT,A snoop found a "my-lpar" match. ##000000A0B0 A snoop found a "my-lpar" match. #372,u,g,n,n,n,u,PM_L3_PF_MISS_L3,L3 PF missed in L3. L3 received an L3PF request from the core (or possibly the L2 if enabled), for a line that was not already in the L3 cache. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##100000016080 L3 PF missed in L3. L3 received an L3PF request from the core (or possibly the L2 if enabled), for a line that was not already in the L3 cache. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #373,u,g,n,n,n,u,PM_L3_HIT,L3 Hits. Any L2 read that hits in the L3, including data load and store, instruction load or translate load. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##120000016080 L3 Hits. Any L2 read that hits in the L3, including data load and store, instruction load or translate load. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #374,u,g,n,n,n,u,PM_L3_MISS,L3 Misses. Any L2 read to the L3 that misses in the L3, including data load and store, instruction load or translate load. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##120000016880 L3 Misses. Any L2 read to the L3 that misses in the L3, including data load and store, instruction load or translate load. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #375,u,g,n,n,n,u,PM_TM_SC_CO,L3 castout of line that was StoreCopy (original value of speculatively written line) in a "Transaction". Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##130000016080 L3 castout of line that was StoreCopy (original value of speculatively written line) in a "Transaction". Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #376,u,g,n,n,n,u,PM_TM_CAM_OVERFLOW,L3 TM CAM is full when a L2 castout of TM_SC line occurs. Line is pushed to memory. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##130000016880 L3 TM CAM is full when a L2 castout of TM_SC line occurs. Line is pushed to memory. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #377,u,g,n,n,n,u,PM_L3_WI_USAGE,Lifetime, sample of Write Inject machine 0 valid. Increments while Write Inject machine 0 is valid. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##140000016880 Lifetime, sample of Write Inject machine 0 valid. Increments while Write Inject machine 0 is valid. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #378,u,g,n,n,n,u,PM_L3_P0_LCO_NO_DATA,Dataless L3 LCO sent port 0. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##150000016080 Dataless L3 LCO sent port 0. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #379,u,g,n,n,n,u,PM_L3_P1_LCO_NO_DATA,Dataless L3 LCO sent port 1. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##150000016880 Dataless L3 LCO sent port 1. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #380,u,g,n,n,n,u,PM_L3_SN_USAGE,Rotating sample of 16 snoop valids. Increments while selected L3 snoop machine is valid. Every 48 clocks, switches among the 16 snoop machines. Thus, indicates overall utilization of the snoop machines. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##160000016080 Rotating sample of 16 snoop valids. Increments while selected L3 snoop machine is valid. Every 48 clocks, switches among the 16 snoop machines. Thus, indicates overall utilization of the snoop machines. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #381,u,g,n,n,n,u,PM_L3_CI_USAGE,Rotating sample of 16 CI or CO actives. Increments while selected L3 CI or CO machine is active. Every 48 clocks, switches among the 16 CI/CO machine pairs. Thus, indicates overall utilization of the CI/CO machines. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##160000016880 Rotating sample of 16 CI or CO actives. Increments while selected L3 CI or CO machine is active. Every 48 clocks, switches among the 16 CI/CO machine pairs. Thus, indicates overall utilization of the CI/CO machines. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #382,u,g,n,n,n,u,PM_L3_P0_PF_RTY,L3 PF received retry on fabric CRESP port 0, every retry counted. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##170000016080 L3 PF received retry on fabric CRESP port 0, every retry counted. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #383,u,g,n,n,n,u,PM_L3_P1_PF_RTY,L3 PF received retry on fabric CRESP port 1, every retry counted. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##170000016880 L3 PF received retry on fabric CRESP port 1, every retry counted. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #384,u,g,n,n,n,u,PM_L3_P0_NODE_PUMP,L3 PF sent with nodal scope from PF machine 0-23, counts even retried requests. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##180000016080 L3 PF sent with nodal scope from PF machine 0-23, counts even retried requests. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #385,u,g,n,n,n,u,PM_L3_P1_NODE_PUMP,L3 PF sent with nodal scope from PF machine 24-47, counts even retried requests. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##180000016880 L3 PF sent with nodal scope from PF machine 24-47, counts even retried requests. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #386,u,g,n,n,n,u,PM_L3_LOC_GUESS_CORRECT,L3 Prefetch scope predictor selected LNS and was correct. Increments when data received for L3 PF machine 0 or 24. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##190000016080 L3 Prefetch scope predictor selected LNS and was correct. Increments when data received for L3 PF machine 0 or 24. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #387,u,g,n,n,n,u,PM_L3_GRP_GUESS_CORRECT,L3 Prefetch scope predictor selected GS or NNS and was correct. Increments when data received for L3 PF machine 0 or 24. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##190000016880 L3 Prefetch scope predictor selected GS or NNS and was correct. Increments when data received for L3 PF machine 0 or 24. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #388,u,g,n,n,n,u,PM_L3_P0_LCO_RTY,L3 initiated LCO received retry on fabric CRESP port 0 (can try 4 times). Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##1A0000016080 L3 initiated LCO received retry on fabric CRESP port 0 (can try 4 times). Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #389,u,g,n,n,n,u,PM_L3_P1_LCO_RTY,L3 initiated LCO received retry on fabric CRESP port 1 (can try 4 times). Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##1A0000016880 L3 initiated LCO received retry on fabric CRESP port 1 (can try 4 times). Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #390,u,g,n,n,n,u,PM_L3_WI0_BUSY,Rotating sample of 16 WI valid. Increments when selected L3 WI machine is valid. Every 48 clocks, switches among the 16 WI machines. Thus, indicates overall utilization of the WI machines. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##1B0000016080 Rotating sample of 16 WI valid. Increments when selected L3 WI machine is valid. Every 48 clocks, switches among the 16 WI machines. Thus, indicates overall utilization of the WI machines. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #391,u,g,n,n,n,u,PM_L2_LD,All successful D-side Load dispatches for this thread (L2 miss + L2 hits). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##000000016080 All successful D-side Load dispatches for this thread (L2 miss + L2 hits). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #392,u,g,n,n,n,u,PM_L2_ST,All successful D-side store dispatches for this thread (L2 miss + L2 hits). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##000000016880 All successful D-side store dispatches for this thread (L2 miss + L2 hits). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #393,u,g,n,n,n,u,PM_L2_CASTOUT_MOD,A line in an Exclusive (M,Mu,Me) state is evicted from the L2. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##010000016080 A line in an Exclusive (M,Mu,Me) state is evicted from the L2. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #394,u,g,n,n,n,u,PM_L2_CASTOUT_SHR,A line in a Shared (Tx,Sx) state is evicted from the L2. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##010000016880 A line in a Shared (Tx,Sx) state is evicted from the L2. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #395,u,g,n,n,n,u,PM_L2_ISIDE_DSIDE_ATTEMPT,All D-side-Ld or I-side-instruction-fetch dispatch attempts for this thread. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##020000016080 All D-side-Ld or I-side-instruction-fetch dispatch attempts for this thread. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #396,u,g,n,n,n,u,PM_L2_ISIDE_DSIDE_FAIL_ADDR,All D-side-Ld or I-side-instruction-fetch dispatch attempts for this thread that failed due to an address collision conflicts with an L2 machine already working on this line (e.g. ld-hit-stq or Read-claim/Castout/Snoop machines). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##020000016880 All D-side-Ld or I-side-instruction-fetch dispatch attempts for this thread that failed due to an address collision conflicts with an L2 machine already working on this line (e.g. ld-hit-stq or Read-claim/Castout/Snoop machines). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #397,u,g,n,n,n,u,PM_L2_SN_M_WR_DONE,SNP dispatched for a write and was M (true M) ##030000016080 SNP dispatched for a write and was M (true M) #398,u,g,n,n,n,u,PM_CO_DISP_FAIL,CO dispatch failed due to all CO machines being busy. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##030000016880 CO dispatch failed due to all CO machines being busy. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #399,u,g,n,n,n,u,PM_L2_LOC_GUESS_CORRECT,L2 guess local (LNS) and guess was correct (ie data local). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##040000016080 L2 guess local (LNS) and guess was correct (ie data local). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #400,u,g,n,n,n,u,PM_L2_LOC_GUESS_WRONG,L2 guess local (LNS) and guess was not correct (ie data not on chip). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##040000016880 L2 guess local (LNS) and guess was not correct (ie data not on chip). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #401,u,g,n,n,n,u,PM_L2_ST_ALL,Total number of store operations. Does not include pte_update, copy/paste, barriers, etc. This signal can then be used in conjunction with PM_L2_ST_GATHER_ALL to calculate the percentage of total stores gathered. Since the event is time-sliced across all 4 threads, the event count should be multiplied by 4. ##050000016080 Total number of store operations. Does not include pte_update, copy/paste, barriers, etc. This signal can then be used in conjunction with PM_L2_ST_GATHER_ALL to calculate the percentage of total stores gathered. Since the event is time-sliced across all 4 threads, the event count should be multiplied by 4. #402,u,g,n,n,n,u,PM_ISIDE_ATTEMPT,All I-side-instruction-fetch dispatch attempts for this thread. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##050000016880 All I-side-instruction-fetch dispatch attempts for this thread. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #403,u,g,n,n,n,u,PM_L2_RC0_BUSY,RC mach 0 Busy. Used by PMU to sample ave RC lifetime (mach0 used as sample point). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##060000016080 RC mach 0 Busy. Used by PMU to sample ave RC lifetime (mach0 used as sample point). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #404,u,g,n,n,n,u,PM_L2_RC_USAGE,Continuous 16 cycle (2to1) window where this signals rotates thru sampling each RC machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##060000016880 Continuous 16 cycle (2to1) window where this signals rotates thru sampling each RC machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #405,u,g,n,n,n,u,PM_L2_ST_CAUSED_TM_FAIL,Non-TM Store caused a TM transaction in any thread to fail. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##070000016080 Non-TM Store caused a TM transaction in any thread to fail. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #406,u,g,n,n,n,u,PM_L2_LD_CAUSED_TM_FAIL,Non-TM Load caused any thread to fail. Event count should be multiplied by 2 since the data is coming from a 2:1 clock domain and the data is time sliced across all 4 threads. ##070000016880 Non-TM Load caused any thread to fail. Event count should be multiplied by 2 since the data is coming from a 2:1 clock domain and the data is time sliced across all 4 threads. #407,u,g,n,n,n,u,PM_L2_SN0_BUSY,SN mach 0 Busy. Used by PMU to sample ave SN lifetime (mach0 used as sample point). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##080000016080 SN mach 0 Busy. Used by PMU to sample ave SN lifetime (mach0 used as sample point). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #408,u,g,n,n,n,u,PM_L2_L1PF_READ,Valid when first beat of data comes in for an L1PF where data came from memory or L4. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##080000016880 Valid when first beat of data comes in for an L1PF where data came from memory or L4. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #409,u,g,n,n,n,u,PM_L2_ISIDE_DSIDE_ST_ATTEMPT,All D-side-Ld, D-side-St or I-side-instruction-fetch dispatch attempts for this thread. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##090000016080 All D-side-Ld, D-side-St or I-side-instruction-fetch dispatch attempts for this thread. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #410,u,g,n,n,n,u,PM_L2_TM_FOOTPR_OVERFLOW_LD,One TM thread was running and Load footprint was lost due to capacity Cast Out or full TMDIR/LVDIR. Event count should be multiplied by 2 since the data is coming from a 2:1 clock domain and the data is time sliced across all 4 threads. ##0A0000016080 One TM thread was running and Load footprint was lost due to capacity Cast Out or full TMDIR/LVDIR. Event count should be multiplied by 2 since the data is coming from a 2:1 clock domain and the data is time sliced across all 4 threads. #411,u,g,n,n,n,u,PM_L2_TM_END,Total number of TM transactions, including passing and failing ones. Event count should be multiplied by 2 since the data is coming from a 2:1 clock domain and the data is time sliced across all 4 threads. ##0A0000016880 Total number of TM transactions, including passing and failing ones. Event count should be multiplied by 2 since the data is coming from a 2:1 clock domain and the data is time sliced across all 4 threads. #412,u,g,n,n,n,u,PM_L2_TLBIE_SLBIE_START,NCU Master received a TLBIE/SLBIEG/SLBIAG operation from the core. Event count should be multiplied by 2 since the data is coming from a 2:1 clock domain and the data is time sliced across all 4 threads. ##0B0000016080 NCU Master received a TLBIE/SLBIEG/SLBIAG operation from the core. Event count should be multiplied by 2 since the data is coming from a 2:1 clock domain and the data is time sliced across all 4 threads. #413,u,g,n,n,n,u,PM_L2_TLBIE_SLBIE_DELAY,Cycles when a TLBIE/SLBIEG/SLBIAG command was held in a hottemp condition by the NCU Master. Multiply this count by 1000 to obtain the total number of cycles. This can be divided by PM_L2_TLBIE_SLBIE_SENT to obtain the average time a TLBIE/SLBIEG/SLBIAG command was held. Event count should be multiplied by 2 since the data is coming from a 2:1 clock domain and the data is time sliced across all 4 threads. ##0B0000016880 Cycles when a TLBIE/SLBIEG/SLBIAG command was held in a hottemp condition by the NCU Master. Multiply this count by 1000 to obtain the total number of cycles. This can be divided by PM_L2_TLBIE_SLBIE_SENT to obtain the average time a TLBIE/SLBIEG/SLBIAG command was held. Event count should be multiplied by 2 since the data is coming from a 2:1 clock domain and the data is time sliced across all 4 threads. #414,u,g,n,n,n,u,PM_ST_DATA_FROM_L2,Store data line hit in the local L2. Includes cache-line states Sx, Tx, Mx. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##0C0000016080 Store data line hit in the local L2. Includes cache-line states Sx, Tx, Mx. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #415,u,g,n,n,n,u,PM_ST_DATA_FROM_L3,Store data line hit in the local L3. Includes cache-line states Tx and Mx. If the cache line is in the Sx state, the RC machine will send a RWITM command. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##0C0000016880 Store data line hit in the local L3. Includes cache-line states Tx and Mx. If the cache line is in the Sx state, the RC machine will send a RWITM command. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #416,u,g,n,n,n,u,PM_L2_LD_DISP,All successful D-side-Ld or I-side-instruction-fetch dispatches for this thread. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##0F0000016080 All successful D-side-Ld or I-side-instruction-fetch dispatches for this thread. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #417,u,g,n,n,n,u,PM_L2_ST_DISP,All successful D-side store dispatches for this thread. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##0F0000016880 All successful D-side store dispatches for this thread. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #418,u,g,n,n,n,u,PM_DATA_RADIX_PROCESS_L2_PTE_FROM_L2,A data Page Table Entry was reloaded to a level 2 page walk cache from the core's L2 cache due to a process scoped demand miss. ##000000000014242 A data Page Table Entry was reloaded to a level 2 page walk cache from the core's L2 cache due to a process scoped demand miss. #419,u,g,n,n,n,u,PM_DATA_RADIX_PROCESS_L2_PDE_FROM_L2,A data Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 cache due to a process scoped demand miss. ##000000000014244 A data Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 cache due to a process scoped demand miss. #420,u,g,n,n,n,u,PM_DATA_RADIX_PROCESS_L3_PTE_FROM_L2,A data Page Table Entry was reloaded to a level 3 page walk cache from the core's L2 cache due to a process scoped demand miss. ##000000000014246 A data Page Table Entry was reloaded to a level 3 page walk cache from the core's L2 cache due to a process scoped demand miss. #421,u,g,n,n,n,u,PM_DATA_RADIX_PROCESS_L3_PDE_FROM_L2,A data Page Directory Entry was reloaded to a level 3 page walk cache from the core's L2 cache due to a process scoped demand miss. ##000000000014248 A data Page Directory Entry was reloaded to a level 3 page walk cache from the core's L2 cache due to a process scoped demand miss. #422,u,g,n,n,n,u,PM_DATA_RADIX_PROCESS_L4_PTE_FROM_L2,A data Page Table Entry was reloaded to a level 4 page walk cache from the core's L2 cache due to a process scoped demand miss. ##00000000001424A A data Page Table Entry was reloaded to a level 4 page walk cache from the core's L2 cache due to a process scoped demand miss. #423,u,g,n,n,n,u,PM_INST_RADIX_PROCESS_L2_PTE_FROM_L2,An instruction Page Table Entry was reloaded to a level 2 page walk cache from the core's L2 cache due to a process scoped demand miss. ##00000000001424E An instruction Page Table Entry was reloaded to a level 2 page walk cache from the core's L2 cache due to a process scoped demand miss. #424,u,g,n,n,n,u,PM_INST_RADIX_PROCESS_L3_PTE_FROM_L2,An instruction Page Table Entry was reloaded to a level 3 page walk cache from the core's L2 cache due to a process scoped demand miss. ##000000000015242 An instruction Page Table Entry was reloaded to a level 3 page walk cache from the core's L2 cache due to a process scoped demand miss. #425,u,g,n,n,n,u,PM_INST_RADIX_PROCESS_L3_PDE_FROM_L2,An instruction Page Directory Entry was reloaded to a level 3 page walk cache from the core's L2 cache due to a process scoped demand miss. ##000000000015244 An instruction Page Directory Entry was reloaded to a level 3 page walk cache from the core's L2 cache due to a process scoped demand miss. #426,u,g,n,n,n,u,PM_INST_RADIX_PROCESS_L4_PTE_FROM_L2,An instruction Page Table Entry was reloaded to a level 4 page walk cache from the core's L2 cache due to a process scoped demand miss. ##000000000015246 An instruction Page Table Entry was reloaded to a level 4 page walk cache from the core's L2 cache due to a process scoped demand miss. #427,u,g,n,n,n,u,PM_DATA_RADIX_PROCESS_L2_PTE_FROM_L2_ALL,A data Page Table Entry was reloaded to a level 2 page walk cache from the core's L2 cache due to a process scoped demand or prefetch miss. ##000000000214242 A data Page Table Entry was reloaded to a level 2 page walk cache from the core's L2 cache due to a process scoped demand or prefetch miss. #428,u,g,n,n,n,u,PM_DATA_RADIX_PROCESS_L2_PDE_FROM_L2_ALL,A data Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 cache due to a process scoped demand or prefetch miss. ##000000000214244 A data Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 cache due to a process scoped demand or prefetch miss. #429,u,g,n,n,n,u,PM_DATA_RADIX_PROCESS_L3_PTE_FROM_L2_ALL,A data Page Table Entry was reloaded to a level 2 page walk cache from the core's L2 cache due to a process scoped demand or prefetch miss. ##000000000214246 A data Page Table Entry was reloaded to a level 2 page walk cache from the core's L2 cache due to a process scoped demand or prefetch miss. #430,u,g,n,n,n,u,PM_DATA_RADIX_PROCESS_L3_PDE_FROM_L2_ALL,A data Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 cache due to a process scoped demand or prefetch miss. ##000000000214248 A data Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 cache due to a process scoped demand or prefetch miss. #431,u,g,n,n,n,u,PM_DATA_RADIX_PROCESS_L4_PTE_FROM_L2_ALL,A data Page Table Entry was reloaded to a level 2 page walk cache from the core's L2 cache due to a process scoped demand or prefetch miss. ##00000000021424A A data Page Table Entry was reloaded to a level 2 page walk cache from the core's L2 cache due to a process scoped demand or prefetch miss. #432,u,g,n,n,n,u,PM_INST_RADIX_PROCESS_L2_PTE_FROM_L2_ALL,An instruction Page Table Entry was reloaded to a level 2 page walk cache from the core's L2 cache due to a process scoped demand or prefetch miss. ##00000000011424E An instruction Page Table Entry was reloaded to a level 2 page walk cache from the core's L2 cache due to a process scoped demand or prefetch miss. #433,u,g,n,n,n,u,PM_INST_RADIX_PROCESS_L3_PTE_FROM_L2_ALL,An instruction Page Table Entry was reloaded to a level 2 page walk cache from the core's L2 cache due to a process scoped demand or prefetch miss. ##000000000115242 An instruction Page Table Entry was reloaded to a level 2 page walk cache from the core's L2 cache due to a process scoped demand or prefetch miss. #434,u,g,n,n,n,u,PM_INST_RADIX_PROCESS_L3_PDE_FROM_L2_ALL,An instruction Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 cache due to a process scoped demand or prefetch miss. ##000000000115244 An instruction Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 cache due to a process scoped demand or prefetch miss. #435,u,g,n,n,n,u,PM_INST_RADIX_PROCESS_L4_PTE_FROM_L2_ALL,An instruction Page Table Entry was reloaded to a level 2 page walk cache from the core's L2 cache due to a process scoped demand or prefetch miss. ##000000000115246 An instruction Page Table Entry was reloaded to a level 2 page walk cache from the core's L2 cache due to a process scoped demand or prefetch miss. #436,u,g,n,n,n,u,PM_INST_FROM_L2,The processor's instruction cache was reloaded from the local core's L2 due to a demand miss. ##000300000001C040 The processor's instruction cache was reloaded from the local core's L2 due to a demand miss. #437,u,g,n,n,n,u,PM_IPTEG_FROM_L2,The processor's instruction page table entry was reloaded from the local core's L2 due to a demand miss. ##000320000001C040 The processor's instruction page table entry was reloaded from the local core's L2 due to a demand miss. #438,u,g,n,n,n,u,PM_DATA_FROM_L2,The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss. ##000340000001C040 The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss. #439,u,g,n,n,n,u,PM_DPTEG_FROM_L2,The processor's data page table entry was reloaded from the local core's L2 due to a demand miss. ##000360000001C040 The processor's data page table entry was reloaded from the local core's L2 due to a demand miss. #440,u,g,n,n,n,u,PM_INST_FROM_L2_ALL,The processor's instruction cache was reloaded from the local core's L2 due to a demand miss or prefetch reload. ##000300000011C040 The processor's instruction cache was reloaded from the local core's L2 due to a demand miss or prefetch reload. #441,u,g,n,n,n,u,PM_IPTEG_FROM_L2_ALL,The processor's instruction page table entry was reloaded from the local core's L2 due to a demand miss or prefetch reload. ##000320000011C040 The processor's instruction page table entry was reloaded from the local core's L2 due to a demand miss or prefetch reload. #442,u,g,n,n,n,u,PM_DATA_FROM_L2_ALL,The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss or prefetch reload. ##000340000021C040 The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss or prefetch reload. #443,u,g,n,n,n,u,PM_DPTEG_FROM_L2_ALL,The processor's data page table entry was reloaded from the local core's L2 due to a demand miss or prefetch reload. ##000360000021C040 The processor's data page table entry was reloaded from the local core's L2 due to a demand miss or prefetch reload. #444,u,g,n,n,n,u,PM_INST_FROM_L1MISS,The processor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss. ##003F00000001C040 The processor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss. #445,u,g,n,n,n,u,PM_IPTEG_FROM_L1MISS,The processor's instruction page table entry was reloaded from a source beyond the local core's L1 due to a demand miss. ##003F20000001C040 The processor's instruction page table entry was reloaded from a source beyond the local core's L1 due to a demand miss. #446,u,g,n,n,n,u,PM_DATA_FROM_L1MISS,The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss. ##003F40000001C040 The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss. #447,u,g,n,n,n,u,PM_DPTEG_FROM_L1MISS,The processor's data page table entry was reloaded from a source beyond the local core's L1 due to a demand miss. ##003F60000001C040 The processor's data page table entry was reloaded from a source beyond the local core's L1 due to a demand miss. #448,u,g,n,n,n,u,PM_INST_FROM_L1MISS_ALL,The processor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. ##003F00000011C040 The processor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. #449,u,g,n,n,n,u,PM_IPTEG_FROM_L1MISS_ALL,The processor's instruction page table entry was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. ##003F20000011C040 The processor's instruction page table entry was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. #450,u,g,n,n,n,u,PM_DATA_FROM_L1MISS_ALL,The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. ##003F40000021C040 The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. #451,u,g,n,n,n,u,PM_DPTEG_FROM_L1MISS_ALL,The processor's data page table entry was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. ##003F60000021C040 The processor's data page table entry was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. #452,u,g,n,n,n,u,PM_IPTEG_FROM_L2_NO_CONFLICT,The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. ##000020000001C040 The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. #453,u,g,n,n,n,u,PM_DATA_FROM_L2_NO_CONFLICT,The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. ##000040000001C040 The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. #454,u,g,n,n,n,u,PM_DPTEG_FROM_L2_NO_CONFLICT,The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. ##000060000001C040 The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. #455,u,g,n,n,n,u,PM_IPTEG_FROM_L2_NO_CONFLICT_ALL,The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. ##000020000011C040 The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. #456,u,g,n,n,n,u,PM_DATA_FROM_L2_NO_CONFLICT_ALL,The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. ##000040000021C040 The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. #457,u,g,n,n,n,u,PM_DPTEG_FROM_L2_NO_CONFLICT_ALL,The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. ##000060000021C040 The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. #458,u,g,n,n,n,u,PM_IPTEG_FROM_L2_MEPF,The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. ##004020000001C040 The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. #459,u,g,n,n,n,u,PM_DATA_FROM_L2_MEPF,The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. ##004040000001C040 The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. #460,u,g,n,n,n,u,PM_DPTEG_FROM_L2_MEPF,The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. ##004060000001C040 The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. #461,u,g,n,n,n,u,PM_IPTEG_FROM_L2_MEPF_ALL,The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. ##004020000011C040 The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. #462,u,g,n,n,n,u,PM_DATA_FROM_L2_MEPF_ALL,The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. ##004040000021C040 The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. #463,u,g,n,n,n,u,PM_DPTEG_FROM_L2_MEPF_ALL,The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. ##004060000021C040 The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. #464,u,g,n,n,n,u,PM_IPTEG_FROM_L2_LDHITST_CONFLICT,The processor's instruction page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. ##008020000001C040 The processor's instruction page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. #465,u,g,n,n,n,u,PM_DATA_FROM_L2_LDHITST_CONFLICT,The processor's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. ##008040000001C040 The processor's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. #466,u,g,n,n,n,u,PM_DPTEG_FROM_L2_LDHITST_CONFLICT,The processor's data page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. ##008060000001C040 The processor's data page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. #467,u,g,n,n,n,u,PM_IPTEG_FROM_L2_LDHITST_CONFLICT_ALL,The processor's instruction page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. ##008020000011C040 The processor's instruction page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. #468,u,g,n,n,n,u,PM_DATA_FROM_L2_LDHITST_CONFLICT_ALL,The processor's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. ##008040000021C040 The processor's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. #469,u,g,n,n,n,u,PM_DPTEG_FROM_L2_LDHITST_CONFLICT_ALL,The processor's data page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. ##008060000021C040 The processor's data page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. #470,u,g,n,n,n,u,PM_IPTEG_FROM_L2_OTHER_CONFLICT,The processor's instruction page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. ##00C020000001C040 The processor's instruction page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. #471,u,g,n,n,n,u,PM_DATA_FROM_L2_OTHER_CONFLICT,The processor's L1 data cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. ##00C040000001C040 The processor's L1 data cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. #472,u,g,n,n,n,u,PM_DPTEG_FROM_L2_OTHER_CONFLICT,The processor's data page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. ##00C060000001C040 The processor's data page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. #473,u,g,n,n,n,u,PM_IPTEG_FROM_L2_OTHER_CONFLICT_ALL,The processor's instruction page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. ##00C020000011C040 The processor's instruction page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. #474,u,g,n,n,n,u,PM_DATA_FROM_L2_OTHER_CONFLICT_ALL,The processor's L1 data cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. ##00C040000021C040 The processor's L1 data cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. #475,u,g,n,n,n,u,PM_DPTEG_FROM_L2_OTHER_CONFLICT_ALL,The processor's data page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. ##00C060000021C040 The processor's data page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. #476,u,g,n,n,n,u,PM_INST_FROM_L2MISS,The processor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss. ##000380000001C040 The processor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss. #477,u,g,n,n,n,u,PM_IPTEG_FROM_L2MISS,The processor's instruction page table entry was reloaded from a source beyond the local core's L2 due to a demand miss. ##0003A0000001C040 The processor's instruction page table entry was reloaded from a source beyond the local core's L2 due to a demand miss. #478,u,g,n,n,n,u,PM_DPTEG_FROM_L2MISS,The processor's data page table entry was reloaded from a source beyond the local core's L2 due to a demand miss. ##0003E0000001C040 The processor's data page table entry was reloaded from a source beyond the local core's L2 due to a demand miss. #479,u,g,n,n,n,u,PM_INST_FROM_L2MISS_ALL,The processor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. ##000380000011C040 The processor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. #480,u,g,n,n,n,u,PM_IPTEG_FROM_L2MISS_ALL,The processor's instruction page table entry was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. ##0003A0000011C040 The processor's instruction page table entry was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. #481,u,g,n,n,n,u,PM_DATA_FROM_L2MISS_ALL,The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. ##0003C0000021C040 The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. #482,u,g,n,n,n,u,PM_DPTEG_FROM_L2MISS_ALL,The processor's data page table entry was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. ##0003E0000021C040 The processor's data page table entry was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. #483,u,g,n,n,n,u,PM_INST_FROM_L3,The processor's instruction cache was reloaded from the local core's L3 due to a demand miss. ##010300000001C040 The processor's instruction cache was reloaded from the local core's L3 due to a demand miss. #484,u,g,n,n,n,u,PM_IPTEG_FROM_L3,The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss. ##010320000001C040 The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss. #485,u,g,n,n,n,u,PM_DATA_FROM_L3,The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss. ##010340000001C040 The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss. #486,u,g,n,n,n,u,PM_DPTEG_FROM_L3,The processor's data page table entry was reloaded from the local core's L3 due to a demand miss. ##010360000001C040 The processor's data page table entry was reloaded from the local core's L3 due to a demand miss. #487,u,g,n,n,n,u,PM_INST_FROM_L3_ALL,The processor's instruction cache was reloaded from the local core's L3 due to a demand miss or prefetch reload. ##010300000011C040 The processor's instruction cache was reloaded from the local core's L3 due to a demand miss or prefetch reload. #488,u,g,n,n,n,u,PM_IPTEG_FROM_L3_ALL,The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload. ##010320000011C040 The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload. #489,u,g,n,n,n,u,PM_DATA_FROM_L3_ALL,The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload. ##010340000021C040 The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload. #490,u,g,n,n,n,u,PM_DPTEG_FROM_L3_ALL,The processor's data page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload. ##010360000021C040 The processor's data page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload. #491,u,g,n,n,n,u,PM_IPTEG_FROM_L3_NO_CONFLICT,The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. ##010020000001C040 The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. #492,u,g,n,n,n,u,PM_DATA_FROM_L3_NO_CONFLICT,The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. ##010040000001C040 The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. #493,u,g,n,n,n,u,PM_DPTEG_FROM_L3_NO_CONFLICT,The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. ##010060000001C040 The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. #494,u,g,n,n,n,u,PM_IPTEG_FROM_L3_NO_CONFLICT_ALL,The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. ##010020000011C040 The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. #495,u,g,n,n,n,u,PM_DATA_FROM_L3_NO_CONFLICT_ALL,The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. ##010040000021C040 The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. #496,u,g,n,n,n,u,PM_DPTEG_FROM_L3_NO_CONFLICT_ALL,The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. ##010060000021C040 The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. #497,u,g,n,n,n,u,PM_IPTEG_FROM_L3_MEPF,The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. ##014020000001C040 The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. #498,u,g,n,n,n,u,PM_DATA_FROM_L3_MEPF,The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. ##014040000001C040 The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. #499,u,g,n,n,n,u,PM_DPTEG_FROM_L3_MEPF,The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. ##014060000001C040 The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. #500,u,g,n,n,n,u,PM_IPTEG_FROM_L3_MEPF_ALL,The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. ##014020000011C040 The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. #501,u,g,n,n,n,u,PM_DATA_FROM_L3_MEPF_ALL,The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. ##014040000021C040 The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. #502,u,g,n,n,n,u,PM_DPTEG_FROM_L3_MEPF_ALL,The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. ##014060000021C040 The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. #503,u,g,n,n,n,u,PM_IPTEG_FROM_L3_CONFLICT,The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss. ##01C020000001C040 The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss. #504,u,g,n,n,n,u,PM_DATA_FROM_L3_CONFLICT,The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss. ##01C040000001C040 The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss. #505,u,g,n,n,n,u,PM_DPTEG_FROM_L3_CONFLICT,The processor's data page table entry was reloaded from the local core's L3 due to a demand miss. ##01C060000001C040 The processor's data page table entry was reloaded from the local core's L3 due to a demand miss. #506,u,g,n,n,n,u,PM_IPTEG_FROM_L3_CONFLICT_ALL,The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload. ##01C020000011C040 The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload. #507,u,g,n,n,n,u,PM_DATA_FROM_L3_CONFLICT_ALL,The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload. ##01C040000021C040 The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload. #508,u,g,n,n,n,u,PM_DPTEG_FROM_L3_CONFLICT_ALL,The processor's data page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload. ##01C060000021C040 The processor's data page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload. #509,u,g,n,n,n,u,PM_IPTEG_FROM_L3MISS,The processor's instruction page table entry was reloaded from beyond the local core's L3 due to a demand miss. ##0007A0000001C040 The processor's instruction page table entry was reloaded from beyond the local core's L3 due to a demand miss. #510,u,g,n,n,n,u,PM_DPTEG_FROM_L3MISS,The processor's data page table entry was reloaded from beyond the local core's L3 due to a demand miss. ##0007E0000001C040 The processor's data page table entry was reloaded from beyond the local core's L3 due to a demand miss. #511,u,g,n,n,n,u,PM_INST_FROM_L3MISS_ALL,The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. ##000780000011C040 The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. #512,u,g,n,n,n,u,PM_IPTEG_FROM_L3MISS_ALL,The processor's instruction page table entry was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. ##0007A0000011C040 The processor's instruction page table entry was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. #513,u,g,n,n,n,u,PM_DATA_FROM_L3MISS_ALL,The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. ##0007C0000021C040 The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. #514,u,g,n,n,n,u,PM_DPTEG_FROM_L3MISS_ALL,The processor's data page table entry was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. ##0007E0000021C040 The processor's data page table entry was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. #515,u,g,n,n,n,u,PM_IPTEG_FROM_L21_REGENT_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. ##080020000001C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. #516,u,g,n,n,n,u,PM_DATA_FROM_L21_REGENT_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. ##080040000001C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. #517,u,g,n,n,n,u,PM_DPTEG_FROM_L21_REGENT_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. ##080060000001C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. #518,u,g,n,n,n,u,PM_IPTEG_FROM_L21_REGENT_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. ##080020000011C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. #519,u,g,n,n,n,u,PM_DATA_FROM_L21_REGENT_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. ##080040000021C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. #520,u,g,n,n,n,u,PM_DPTEG_FROM_L21_REGENT_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. ##080060000021C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. #521,u,g,n,n,n,u,PM_IPTEG_FROM_L21_REGENT_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. ##084020000001C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. #522,u,g,n,n,n,u,PM_DATA_FROM_L21_REGENT_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. ##084040000001C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. #523,u,g,n,n,n,u,PM_DPTEG_FROM_L21_REGENT_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. ##084060000001C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. #524,u,g,n,n,n,u,PM_IPTEG_FROM_L21_REGENT_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. ##084020000011C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. #525,u,g,n,n,n,u,PM_DATA_FROM_L21_REGENT_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. ##084040000021C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. #526,u,g,n,n,n,u,PM_DPTEG_FROM_L21_REGENT_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. ##084060000021C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. #527,u,g,n,n,n,u,PM_INST_FROM_L21_REGENT,The processor's instruction cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. ##080100000001C040 The processor's instruction cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. #528,u,g,n,n,n,u,PM_IPTEG_FROM_L21_REGENT,The processor's instruction page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. ##080120000001C040 The processor's instruction page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. #529,u,g,n,n,n,u,PM_DATA_FROM_L21_REGENT,The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. ##080140000001C040 The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. #530,u,g,n,n,n,u,PM_DPTEG_FROM_L21_REGENT,The processor's data page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. ##080160000001C040 The processor's data page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. #531,u,g,n,n,n,u,PM_INST_FROM_L21_REGENT_ALL,The processor's instruction cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. ##080100000011C040 The processor's instruction cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. #532,u,g,n,n,n,u,PM_IPTEG_FROM_L21_REGENT_ALL,The processor's instruction page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. ##080120000011C040 The processor's instruction page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. #533,u,g,n,n,n,u,PM_DATA_FROM_L21_REGENT_ALL,The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. ##080140000021C040 The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. #534,u,g,n,n,n,u,PM_DPTEG_FROM_L21_REGENT_ALL,The processor's data page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. ##080160000021C040 The processor's data page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. #535,u,g,n,n,n,u,PM_IPTEG_FROM_L31_REGENT_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. ##088020000001C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. #536,u,g,n,n,n,u,PM_DATA_FROM_L31_REGENT_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. ##088040000001C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. #537,u,g,n,n,n,u,PM_DPTEG_FROM_L31_REGENT_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. ##088060000001C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. #538,u,g,n,n,n,u,PM_IPTEG_FROM_L31_REGENT_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##088020000011C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. #539,u,g,n,n,n,u,PM_DATA_FROM_L31_REGENT_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##088040000021C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. #540,u,g,n,n,n,u,PM_DPTEG_FROM_L31_REGENT_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##088060000021C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. #541,u,g,n,n,n,u,PM_IPTEG_FROM_L31_REGENT_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. ##08C020000001C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. #542,u,g,n,n,n,u,PM_DATA_FROM_L31_REGENT_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. ##08C040000001C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. #543,u,g,n,n,n,u,PM_DPTEG_FROM_L31_REGENT_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. ##08C060000001C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. #544,u,g,n,n,n,u,PM_IPTEG_FROM_L31_REGENT_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##08C020000011C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. #545,u,g,n,n,n,u,PM_DATA_FROM_L31_REGENT_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##08C040000021C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. #546,u,g,n,n,n,u,PM_DPTEG_FROM_L31_REGENT_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##08C060000021C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. #547,u,g,n,n,n,u,PM_INST_FROM_L31_REGENT,The processor's instruction cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. ##088100000001C040 The processor's instruction cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. #548,u,g,n,n,n,u,PM_IPTEG_FROM_L31_REGENT,The processor's instruction page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. ##088120000001C040 The processor's instruction page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. #549,u,g,n,n,n,u,PM_DATA_FROM_L31_REGENT,The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. ##088140000001C040 The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. #550,u,g,n,n,n,u,PM_DPTEG_FROM_L31_REGENT,The processor's data page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. ##088160000001C040 The processor's data page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. #551,u,g,n,n,n,u,PM_INST_FROM_L31_REGENT_ALL,The processor's instruction cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##088100000011C040 The processor's instruction cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. #552,u,g,n,n,n,u,PM_IPTEG_FROM_L31_REGENT_ALL,The processor's instruction page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##088120000011C040 The processor's instruction page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. #553,u,g,n,n,n,u,PM_DATA_FROM_L31_REGENT_ALL,The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##088140000021C040 The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. #554,u,g,n,n,n,u,PM_DPTEG_FROM_L31_REGENT_ALL,The processor's data page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##088160000021C040 The processor's data page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. #555,u,g,n,n,n,u,PM_IPTEG_FROM_REGENT_L2L3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. ##080220000001C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. #556,u,g,n,n,n,u,PM_DATA_FROM_REGENT_L2L3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. ##080240000001C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. #557,u,g,n,n,n,u,PM_DPTEG_FROM_REGENT_L2L3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. ##080260000001C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. #558,u,g,n,n,n,u,PM_IPTEG_FROM_REGENT_L2L3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##080220000011C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. #559,u,g,n,n,n,u,PM_DATA_FROM_REGENT_L2L3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##080240000021C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. #560,u,g,n,n,n,u,PM_DPTEG_FROM_REGENT_L2L3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##080260000021C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. #561,u,g,n,n,n,u,PM_IPTEG_FROM_REGENT_L2L3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. ##084220000001C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. #562,u,g,n,n,n,u,PM_DATA_FROM_REGENT_L2L3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. ##084240000001C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. #563,u,g,n,n,n,u,PM_DPTEG_FROM_REGENT_L2L3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. ##084260000001C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. #564,u,g,n,n,n,u,PM_IPTEG_FROM_REGENT_L2L3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##084220000011C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. #565,u,g,n,n,n,u,PM_DATA_FROM_REGENT_L2L3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##084240000021C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. #566,u,g,n,n,n,u,PM_DPTEG_FROM_REGENT_L2L3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##084260000021C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. #567,u,g,n,n,n,u,PM_INST_FROM_REGENT_L2L3,The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. ##080300000001C040 The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. #568,u,g,n,n,n,u,PM_IPTEG_FROM_REGENT_L2L3,The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. ##080320000001C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. #569,u,g,n,n,n,u,PM_DATA_FROM_REGENT_L2L3,The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. ##080340000001C040 The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. #570,u,g,n,n,n,u,PM_DPTEG_FROM_REGENT_L2L3,The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. ##080360000001C040 The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. #571,u,g,n,n,n,u,PM_INST_FROM_REGENT_L2L3_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##080300000011C040 The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. #572,u,g,n,n,n,u,PM_IPTEG_FROM_REGENT_L2L3_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##080320000011C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. #573,u,g,n,n,n,u,PM_DATA_FROM_REGENT_L2L3_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##080340000021C040 The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. #574,u,g,n,n,n,u,PM_DPTEG_FROM_REGENT_L2L3_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##080360000021C040 The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. #575,u,g,n,n,n,u,PM_IPTEG_FROM_L21_NON_REGENT_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. ##0A0020000001C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. #576,u,g,n,n,n,u,PM_DATA_FROM_L21_NON_REGENT_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. ##0A0040000001C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. #577,u,g,n,n,n,u,PM_DPTEG_FROM_L21_NON_REGENT_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. ##0A0060000001C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. #578,u,g,n,n,n,u,PM_IPTEG_FROM_L21_NON_REGENT_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0020000011C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. #579,u,g,n,n,n,u,PM_DATA_FROM_L21_NON_REGENT_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0040000021C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. #580,u,g,n,n,n,u,PM_DPTEG_FROM_L21_NON_REGENT_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0060000021C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. #581,u,g,n,n,n,u,PM_IPTEG_FROM_L21_NON_REGENT_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. ##0A4020000001C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. #582,u,g,n,n,n,u,PM_DATA_FROM_L21_NON_REGENT_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. ##0A4040000001C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. #583,u,g,n,n,n,u,PM_DPTEG_FROM_L21_NON_REGENT_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. ##0A4060000001C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. #584,u,g,n,n,n,u,PM_IPTEG_FROM_L21_NON_REGENT_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A4020000011C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. #585,u,g,n,n,n,u,PM_DATA_FROM_L21_NON_REGENT_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A4040000021C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. #586,u,g,n,n,n,u,PM_DPTEG_FROM_L21_NON_REGENT_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A4060000021C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. #587,u,g,n,n,n,u,PM_INST_FROM_L21_NON_REGENT,The processor's instruction cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. ##0A0100000001C040 The processor's instruction cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. #588,u,g,n,n,n,u,PM_IPTEG_FROM_L21_NON_REGENT,The processor's instruction page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. ##0A0120000001C040 The processor's instruction page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. #589,u,g,n,n,n,u,PM_DATA_FROM_L21_NON_REGENT,The processor's L1 data cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. ##0A0140000001C040 The processor's L1 data cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. #590,u,g,n,n,n,u,PM_DPTEG_FROM_L21_NON_REGENT,The processor's data page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. ##0A0160000001C040 The processor's data page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. #591,u,g,n,n,n,u,PM_INST_FROM_L21_NON_REGENT_ALL,The processor's instruction cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0100000011C040 The processor's instruction cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. #592,u,g,n,n,n,u,PM_IPTEG_FROM_L21_NON_REGENT_ALL,The processor's instruction page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0120000011C040 The processor's instruction page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. #593,u,g,n,n,n,u,PM_DATA_FROM_L21_NON_REGENT_ALL,The processor's L1 data cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0140000021C040 The processor's L1 data cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. #594,u,g,n,n,n,u,PM_DPTEG_FROM_L21_NON_REGENT_ALL,The processor's data page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0160000021C040 The processor's data page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. #595,u,g,n,n,n,u,PM_IPTEG_FROM_L31_NON_REGENT_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. ##0A8020000001C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. #596,u,g,n,n,n,u,PM_DATA_FROM_L31_NON_REGENT_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. ##0A8040000001C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. #597,u,g,n,n,n,u,PM_DPTEG_FROM_L31_NON_REGENT_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. ##0A8060000001C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. #598,u,g,n,n,n,u,PM_IPTEG_FROM_L31_NON_REGENT_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A8020000011C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. #599,u,g,n,n,n,u,PM_DATA_FROM_L31_NON_REGENT_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A8040000021C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. #600,u,g,n,n,n,u,PM_DPTEG_FROM_L31_NON_REGENT_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A8060000021C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. #601,u,g,n,n,n,u,PM_IPTEG_FROM_L31_NON_REGENT_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. ##0AC020000001C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. #602,u,g,n,n,n,u,PM_DATA_FROM_L31_NON_REGENT_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. ##0AC040000001C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. #603,u,g,n,n,n,u,PM_DPTEG_FROM_L31_NON_REGENT_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. ##0AC060000001C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. #604,u,g,n,n,n,u,PM_IPTEG_FROM_L31_NON_REGENT_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0AC020000011C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. #605,u,g,n,n,n,u,PM_DATA_FROM_L31_NON_REGENT_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0AC040000021C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. #606,u,g,n,n,n,u,PM_DPTEG_FROM_L31_NON_REGENT_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0AC060000021C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. #607,u,g,n,n,n,u,PM_INST_FROM_L31_NON_REGENT,The processor's instruction cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. ##0A8100000001C040 The processor's instruction cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. #608,u,g,n,n,n,u,PM_IPTEG_FROM_L31_NON_REGENT,The processor's instruction page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. ##0A8120000001C040 The processor's instruction page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. #609,u,g,n,n,n,u,PM_DATA_FROM_L31_NON_REGENT,The processor's L1 data cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. ##0A8140000001C040 The processor's L1 data cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. #610,u,g,n,n,n,u,PM_DPTEG_FROM_L31_NON_REGENT,The processor's data page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. ##0A8160000001C040 The processor's data page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. #611,u,g,n,n,n,u,PM_INST_FROM_L31_NON_REGENT_ALL,The processor's instruction cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A8100000011C040 The processor's instruction cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. #612,u,g,n,n,n,u,PM_IPTEG_FROM_L31_NON_REGENT_ALL,The processor's instruction page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A8120000011C040 The processor's instruction page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. #613,u,g,n,n,n,u,PM_DATA_FROM_L31_NON_REGENT_ALL,The processor's L1 data cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A8140000021C040 The processor's L1 data cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. #614,u,g,n,n,n,u,PM_DPTEG_FROM_L31_NON_REGENT_ALL,The processor's data page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A8160000021C040 The processor's data page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. #615,u,g,n,n,n,u,PM_IPTEG_FROM_NON_REGENT_L2L3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. ##0A0220000001C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. #616,u,g,n,n,n,u,PM_DATA_FROM_NON_REGENT_L2L3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. ##0A0240000001C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. #617,u,g,n,n,n,u,PM_DPTEG_FROM_NON_REGENT_L2L3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. ##0A0260000001C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. #618,u,g,n,n,n,u,PM_IPTEG_FROM_NON_REGENT_L2L3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0220000011C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. #619,u,g,n,n,n,u,PM_DATA_FROM_NON_REGENT_L2L3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0240000021C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. #620,u,g,n,n,n,u,PM_DPTEG_FROM_NON_REGENT_L2L3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0260000021C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. #621,u,g,n,n,n,u,PM_IPTEG_FROM_NON_REGENT_L2L3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. ##0A4220000001C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. #622,u,g,n,n,n,u,PM_DATA_FROM_NON_REGENT_L2L3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. ##0A4240000001C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. #623,u,g,n,n,n,u,PM_DPTEG_FROM_NON_REGENT_L2L3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. ##0A4260000001C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. #624,u,g,n,n,n,u,PM_IPTEG_FROM_NON_REGENT_L2L3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A4220000011C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. #625,u,g,n,n,n,u,PM_DATA_FROM_NON_REGENT_L2L3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A4240000021C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. #626,u,g,n,n,n,u,PM_DPTEG_FROM_NON_REGENT_L2L3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A4260000021C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. #627,u,g,n,n,n,u,PM_INST_FROM_NON_REGENT_L2L3,The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. ##0A0300000001C040 The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. #628,u,g,n,n,n,u,PM_IPTEG_FROM_NON_REGENT_L2L3,The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. ##0A0320000001C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. #629,u,g,n,n,n,u,PM_DATA_FROM_NON_REGENT_L2L3,The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. ##0A0340000001C040 The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. #630,u,g,n,n,n,u,PM_DPTEG_FROM_NON_REGENT_L2L3,The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. ##0A0360000001C040 The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. #631,u,g,n,n,n,u,PM_INST_FROM_NON_REGENT_L2L3_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0300000011C040 The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. #632,u,g,n,n,n,u,PM_IPTEG_FROM_NON_REGENT_L2L3_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0320000011C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. #633,u,g,n,n,n,u,PM_DATA_FROM_NON_REGENT_L2L3_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0340000021C040 The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. #634,u,g,n,n,n,u,PM_DPTEG_FROM_NON_REGENT_L2L3_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0360000021C040 The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. #635,u,g,n,n,n,u,PM_INST_FROM_LMEM,The processor's instruction cache was reloaded from the local chip's memory due to a demand miss. ##094100000001C040 The processor's instruction cache was reloaded from the local chip's memory due to a demand miss. #636,u,g,n,n,n,u,PM_IPTEG_FROM_LMEM,The processor's instruction page table entry was reloaded from the local chip's memory due to a demand miss. ##094020000001C040 The processor's instruction page table entry was reloaded from the local chip's memory due to a demand miss. #637,u,g,n,n,n,u,PM_DATA_FROM_LMEM,The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss. ##094040000001C040 The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss. #638,u,g,n,n,n,u,PM_DPTEG_FROM_LMEM,The processor's data page table entry was reloaded from the local chip's memory due to a demand miss. ##094060000001C040 The processor's data page table entry was reloaded from the local chip's memory due to a demand miss. #639,u,g,n,n,n,u,PM_INST_FROM_LMEM_ALL,The processor's instruction cache was reloaded from the local chip's memory due to a demand miss or prefetch reload. ##094100000011C040 The processor's instruction cache was reloaded from the local chip's memory due to a demand miss or prefetch reload. #640,u,g,n,n,n,u,PM_IPTEG_FROM_LMEM_ALL,The processor's instruction page table entry was reloaded from the local chip's memory due to a demand miss or prefetch reload. ##094020000011C040 The processor's instruction page table entry was reloaded from the local chip's memory due to a demand miss or prefetch reload. #641,u,g,n,n,n,u,PM_DATA_FROM_LMEM_ALL,The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss or prefetch reload. ##094040000021C040 The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss or prefetch reload. #642,u,g,n,n,n,u,PM_DPTEG_FROM_LMEM_ALL,The processor's data page table entry was reloaded from the local chip's memory due to a demand miss or prefetch reload. ##094060000021C040 The processor's data page table entry was reloaded from the local chip's memory due to a demand miss or prefetch reload. #643,u,g,n,n,n,u,PM_IPTEG_FROM_L_OC_CACHE,The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss. ##098020000001C040 The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss. #644,u,g,n,n,n,u,PM_DATA_FROM_L_OC_CACHE,The processor's L1 data cache was reloaded from the local chip's OpenCapp cache due to a demand miss. ##098040000001C040 The processor's L1 data cache was reloaded from the local chip's OpenCapp cache due to a demand miss. #645,u,g,n,n,n,u,PM_DPTEG_FROM_L_OC_CACHE,The processor's data page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss. ##098060000001C040 The processor's data page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss. #646,u,g,n,n,n,u,PM_IPTEG_FROM_L_OC_CACHE_ALL,The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. ##098020000011C040 The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. #647,u,g,n,n,n,u,PM_DATA_FROM_L_OC_CACHE_ALL,The processor's L1 data cache was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. ##098040000021C040 The processor's L1 data cache was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. #648,u,g,n,n,n,u,PM_DPTEG_FROM_L_OC_CACHE_ALL,The processor's data page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. ##098060000021C040 The processor's data page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. #649,u,g,n,n,n,u,PM_IPTEG_FROM_L_OC_MEM,The processor's instruction page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss. ##09C020000001C040 The processor's instruction page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss. #650,u,g,n,n,n,u,PM_DATA_FROM_L_OC_MEM,The processor's L1 data cache was reloaded from the local chip's OpenCapp memory due to a demand miss. ##09C040000001C040 The processor's L1 data cache was reloaded from the local chip's OpenCapp memory due to a demand miss. #651,u,g,n,n,n,u,PM_DPTEG_FROM_L_OC_MEM,The processor's data page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss. ##09C060000001C040 The processor's data page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss. #652,u,g,n,n,n,u,PM_IPTEG_FROM_L_OC_MEM_ALL,The processor's instruction page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. ##09C020000011C040 The processor's instruction page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. #653,u,g,n,n,n,u,PM_DATA_FROM_L_OC_MEM_ALL,The processor's L1 data cache was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. ##09C040000021C040 The processor's L1 data cache was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. #654,u,g,n,n,n,u,PM_DPTEG_FROM_L_OC_MEM_ALL,The processor's data page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. ##09C060000021C040 The processor's data page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. #655,u,g,n,n,n,u,PM_INST_FROM_L_OC_ANY,The processor's instruction cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. ##098100000001C040 The processor's instruction cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. #656,u,g,n,n,n,u,PM_IPTEG_FROM_L_OC_ANY,The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. ##098120000001C040 The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. #657,u,g,n,n,n,u,PM_DATA_FROM_L_OC_ANY,The processor's L1 data cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. ##098140000001C040 The processor's L1 data cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. #658,u,g,n,n,n,u,PM_DPTEG_FROM_L_OC_ANY,The processor's data page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. ##098160000001C040 The processor's data page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. #659,u,g,n,n,n,u,PM_INST_FROM_L_OC_ANY_ALL,The processor's instruction cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##098100000011C040 The processor's instruction cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #660,u,g,n,n,n,u,PM_IPTEG_FROM_L_OC_ANY_ALL,The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##098120000011C040 The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #661,u,g,n,n,n,u,PM_DATA_FROM_L_OC_ANY_ALL,The processor's L1 data cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##098140000021C040 The processor's L1 data cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #662,u,g,n,n,n,u,PM_DPTEG_FROM_L_OC_ANY_ALL,The processor's data page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##098160000021C040 The processor's data page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #663,u,g,n,n,n,u,PM_IPTEG_FROM_RL2_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. ##0C0020000001C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. #664,u,g,n,n,n,u,PM_DATA_FROM_RL2_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. ##0C0040000001C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. #665,u,g,n,n,n,u,PM_DPTEG_FROM_RL2_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. ##0C0060000001C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. #666,u,g,n,n,n,u,PM_IPTEG_FROM_RL2_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. ##0C0020000011C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. #667,u,g,n,n,n,u,PM_DATA_FROM_RL2_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. ##0C0040000021C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. #668,u,g,n,n,n,u,PM_DPTEG_FROM_RL2_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. ##0C0060000021C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. #669,u,g,n,n,n,u,PM_IPTEG_FROM_RL2_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. ##0C4020000001C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. #670,u,g,n,n,n,u,PM_DATA_FROM_RL2_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. ##0C4040000001C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. #671,u,g,n,n,n,u,PM_DPTEG_FROM_RL2_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. ##0C4060000001C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. #672,u,g,n,n,n,u,PM_IPTEG_FROM_RL2_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. ##0C4020000011C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. #673,u,g,n,n,n,u,PM_DATA_FROM_RL2_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. ##0C4040000021C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. #674,u,g,n,n,n,u,PM_DPTEG_FROM_RL2_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. ##0C4060000021C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. #675,u,g,n,n,n,u,PM_INST_FROM_RL2,The processor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss. ##0C0100000001C040 The processor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss. #676,u,g,n,n,n,u,PM_IPTEG_FROM_RL2,The processor's instruction page table entry was reloaded from another core's L2 from a remote chip due to a demand miss. ##0C0120000001C040 The processor's instruction page table entry was reloaded from another core's L2 from a remote chip due to a demand miss. #677,u,g,n,n,n,u,PM_DATA_FROM_RL2,The processor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss. ##0C0140000001C040 The processor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss. #678,u,g,n,n,n,u,PM_DPTEG_FROM_RL2,The processor's data page table entry was reloaded from another core's L2 from a remote chip due to a demand miss. ##0C0160000001C040 The processor's data page table entry was reloaded from another core's L2 from a remote chip due to a demand miss. #679,u,g,n,n,n,u,PM_INST_FROM_RL2_ALL,The processor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. ##0C0100000011C040 The processor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. #680,u,g,n,n,n,u,PM_IPTEG_FROM_RL2_ALL,The processor's instruction page table entry was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. ##0C0120000011C040 The processor's instruction page table entry was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. #681,u,g,n,n,n,u,PM_DATA_FROM_RL2_ALL,The processor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. ##0C0140000021C040 The processor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. #682,u,g,n,n,n,u,PM_DPTEG_FROM_RL2_ALL,The processor's data page table entry was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. ##0C0160000021C040 The processor's data page table entry was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. #683,u,g,n,n,n,u,PM_IPTEG_FROM_RL3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. ##0C8020000001C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. #684,u,g,n,n,n,u,PM_DATA_FROM_RL3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. ##0C8040000001C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. #685,u,g,n,n,n,u,PM_DPTEG_FROM_RL3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. ##0C8060000001C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. #686,u,g,n,n,n,u,PM_IPTEG_FROM_RL3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. ##0C8020000011C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. #687,u,g,n,n,n,u,PM_DATA_FROM_RL3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. ##0C8040000021C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. #688,u,g,n,n,n,u,PM_DPTEG_FROM_RL3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. ##0C8060000021C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. #689,u,g,n,n,n,u,PM_IPTEG_FROM_RL3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. ##0CC020000001C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. #690,u,g,n,n,n,u,PM_DATA_FROM_RL3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. ##0CC040000001C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. #691,u,g,n,n,n,u,PM_DPTEG_FROM_RL3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. ##0CC060000001C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. #692,u,g,n,n,n,u,PM_IPTEG_FROM_RL3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. ##0CC020000011C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. #693,u,g,n,n,n,u,PM_DATA_FROM_RL3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. ##0CC040000021C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. #694,u,g,n,n,n,u,PM_DPTEG_FROM_RL3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. ##0CC060000021C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. #695,u,g,n,n,n,u,PM_INST_FROM_RL3,The processor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss. ##0C8100000001C040 The processor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss. #696,u,g,n,n,n,u,PM_IPTEG_FROM_RL3,The processor's instruction page table entry was reloaded from another core's L3 from a remote chip due to a demand miss. ##0C8120000001C040 The processor's instruction page table entry was reloaded from another core's L3 from a remote chip due to a demand miss. #697,u,g,n,n,n,u,PM_DATA_FROM_RL3,The processor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss. ##0C8140000001C040 The processor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss. #698,u,g,n,n,n,u,PM_DPTEG_FROM_RL3,The processor's data page table entry was reloaded from another core's L3 from a remote chip due to a demand miss. ##0C8160000001C040 The processor's data page table entry was reloaded from another core's L3 from a remote chip due to a demand miss. #699,u,g,n,n,n,u,PM_INST_FROM_RL3_ALL,The processor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. ##0C8100000011C040 The processor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. #700,u,g,n,n,n,u,PM_IPTEG_FROM_RL3_ALL,The processor's instruction page table entry was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. ##0C8120000011C040 The processor's instruction page table entry was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. #701,u,g,n,n,n,u,PM_DATA_FROM_RL3_ALL,The processor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. ##0C8140000021C040 The processor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. #702,u,g,n,n,n,u,PM_DPTEG_FROM_RL3_ALL,The processor's data page table entry was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. ##0C8160000021C040 The processor's data page table entry was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. #703,u,g,n,n,n,u,PM_IPTEG_FROM_RL2L3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. ##0C0220000001C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. #704,u,g,n,n,n,u,PM_DATA_FROM_RL2L3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. ##0C0240000001C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. #705,u,g,n,n,n,u,PM_DPTEG_FROM_RL2L3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. ##0C0260000001C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. #706,u,g,n,n,n,u,PM_IPTEG_FROM_RL2L3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. ##0C0220000011C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. #707,u,g,n,n,n,u,PM_DATA_FROM_RL2L3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. ##0C0240000021C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. #708,u,g,n,n,n,u,PM_DPTEG_FROM_RL2L3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. ##0C0260000021C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. #709,u,g,n,n,n,u,PM_IPTEG_FROM_RL2L3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. ##0C4220000001C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. #710,u,g,n,n,n,u,PM_DATA_FROM_RL2L3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. ##0C4240000001C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. #711,u,g,n,n,n,u,PM_DPTEG_FROM_RL2L3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. ##0C4260000001C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. #712,u,g,n,n,n,u,PM_IPTEG_FROM_RL2L3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. ##0C4220000011C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. #713,u,g,n,n,n,u,PM_DATA_FROM_RL2L3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. ##0C4240000021C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. #714,u,g,n,n,n,u,PM_DPTEG_FROM_RL2L3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. ##0C4260000021C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. #715,u,g,n,n,n,u,PM_INST_FROM_RL2L3,The processor's instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. ##0C0300000001C040 The processor's instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. #716,u,g,n,n,n,u,PM_IPTEG_FROM_RL2L3,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. ##0C0320000001C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. #717,u,g,n,n,n,u,PM_DATA_FROM_RL2L3,The processor's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. ##0C0340000001C040 The processor's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. #718,u,g,n,n,n,u,PM_DPTEG_FROM_RL2L3,The processor's data page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. ##0C0360000001C040 The processor's data page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. #719,u,g,n,n,n,u,PM_INST_FROM_RL2L3_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. ##0C0300000011C040 The processor's instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. #720,u,g,n,n,n,u,PM_IPTEG_FROM_RL2L3_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. ##0C0320000011C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. #721,u,g,n,n,n,u,PM_DATA_FROM_RL2L3_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. ##0C0340000021C040 The processor's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. #722,u,g,n,n,n,u,PM_DPTEG_FROM_RL2L3_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. ##0C0360000021C040 The processor's data page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. #723,u,g,n,n,n,u,PM_INST_FROM_RMEM,The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss. ##0D4100000001C040 The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss. #724,u,g,n,n,n,u,PM_IPTEG_FROM_RMEM,The processor's instruction page table entry was reloaded from remote memory (MC slow) due to a demand miss. ##0D4020000001C040 The processor's instruction page table entry was reloaded from remote memory (MC slow) due to a demand miss. #725,u,g,n,n,n,u,PM_DATA_FROM_RMEM,The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss. ##0D4040000001C040 The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss. #726,u,g,n,n,n,u,PM_DPTEG_FROM_RMEM,The processor's data page table entry was reloaded from remote memory (MC slow) due to a demand miss. ##0D4060000001C040 The processor's data page table entry was reloaded from remote memory (MC slow) due to a demand miss. #727,u,g,n,n,n,u,PM_INST_FROM_RMEM_ALL,The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. ##0D4100000011C040 The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. #728,u,g,n,n,n,u,PM_IPTEG_FROM_RMEM_ALL,The processor's instruction page table entry was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. ##0D4020000011C040 The processor's instruction page table entry was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. #729,u,g,n,n,n,u,PM_DATA_FROM_RMEM_ALL,The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. ##0D4040000021C040 The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. #730,u,g,n,n,n,u,PM_DPTEG_FROM_RMEM_ALL,The processor's data page table entry was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. ##0D4060000021C040 The processor's data page table entry was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. #731,u,g,n,n,n,u,PM_IPTEG_FROM_R_OC_CACHE,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss. ##0D8020000001C040 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss. #732,u,g,n,n,n,u,PM_DATA_FROM_R_OC_CACHE,The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache due to a demand miss. ##0D8040000001C040 The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache due to a demand miss. #733,u,g,n,n,n,u,PM_DPTEG_FROM_R_OC_CACHE,The processor's data page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss. ##0D8060000001C040 The processor's data page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss. #734,u,g,n,n,n,u,PM_IPTEG_FROM_R_OC_CACHE_ALL,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. ##0D8020000011C040 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. #735,u,g,n,n,n,u,PM_DATA_FROM_R_OC_CACHE_ALL,The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. ##0D8040000021C040 The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. #736,u,g,n,n,n,u,PM_DPTEG_FROM_R_OC_CACHE_ALL,The processor's data page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. ##0D8060000021C040 The processor's data page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. #737,u,g,n,n,n,u,PM_IPTEG_FROM_R_OC_MEM,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss. ##0DC020000001C040 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss. #738,u,g,n,n,n,u,PM_DATA_FROM_R_OC_MEM,The processor's L1 data cache was reloaded from a remote chip's OpenCapp memory due to a demand miss. ##0DC040000001C040 The processor's L1 data cache was reloaded from a remote chip's OpenCapp memory due to a demand miss. #739,u,g,n,n,n,u,PM_DPTEG_FROM_R_OC_MEM,The processor's data page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss. ##0DC060000001C040 The processor's data page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss. #740,u,g,n,n,n,u,PM_IPTEG_FROM_R_OC_MEM_ALL,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. ##0DC020000011C040 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. #741,u,g,n,n,n,u,PM_DATA_FROM_R_OC_MEM_ALL,The processor's L1 data cache was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. ##0DC040000021C040 The processor's L1 data cache was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. #742,u,g,n,n,n,u,PM_DPTEG_FROM_R_OC_MEM_ALL,The processor's data page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. ##0DC060000021C040 The processor's data page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. #743,u,g,n,n,n,u,PM_INST_FROM_R_OC_ANY,The processor's instruction cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. ##0D8100000001C040 The processor's instruction cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. #744,u,g,n,n,n,u,PM_IPTEG_FROM_R_OC_ANY,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. ##0D8120000001C040 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. #745,u,g,n,n,n,u,PM_DATA_FROM_R_OC_ANY,The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. ##0D8140000001C040 The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. #746,u,g,n,n,n,u,PM_DPTEG_FROM_R_OC_ANY,The processor's data page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. ##0D8160000001C040 The processor's data page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. #747,u,g,n,n,n,u,PM_INST_FROM_R_OC_ANY_ALL,The processor's instruction cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##0D8100000011C040 The processor's instruction cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #748,u,g,n,n,n,u,PM_IPTEG_FROM_R_OC_ANY_ALL,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##0D8120000011C040 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #749,u,g,n,n,n,u,PM_DATA_FROM_R_OC_ANY_ALL,The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##0D8140000021C040 The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #750,u,g,n,n,n,u,PM_DPTEG_FROM_R_OC_ANY_ALL,The processor's data page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##0D8160000021C040 The processor's data page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #751,u,g,n,n,n,u,PM_IPTEG_FROM_DL2_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. ##0E0020000001C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. #752,u,g,n,n,n,u,PM_DATA_FROM_DL2_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. ##0E0040000001C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. #753,u,g,n,n,n,u,PM_DPTEG_FROM_DL2_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. ##0E0060000001C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. #754,u,g,n,n,n,u,PM_IPTEG_FROM_DL2_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. ##0E0020000011C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. #755,u,g,n,n,n,u,PM_DATA_FROM_DL2_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. ##0E0040000021C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. #756,u,g,n,n,n,u,PM_DPTEG_FROM_DL2_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. ##0E0060000021C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. #757,u,g,n,n,n,u,PM_IPTEG_FROM_DL2_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. ##0E4020000001C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. #758,u,g,n,n,n,u,PM_DATA_FROM_DL2_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. ##0E4040000001C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. #759,u,g,n,n,n,u,PM_DPTEG_FROM_DL2_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. ##0E4060000001C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. #760,u,g,n,n,n,u,PM_IPTEG_FROM_DL2_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. ##0E4020000011C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. #761,u,g,n,n,n,u,PM_DATA_FROM_DL2_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. ##0E4040000021C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. #762,u,g,n,n,n,u,PM_DPTEG_FROM_DL2_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. ##0E4060000021C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. #763,u,g,n,n,n,u,PM_INST_FROM_DL2,The processor's instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss. ##0E0100000001C040 The processor's instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss. #764,u,g,n,n,n,u,PM_IPTEG_FROM_DL2,The processor's instruction page table entry was reloaded from another core's L2 from a distant chip due to a demand miss. ##0E0120000001C040 The processor's instruction page table entry was reloaded from another core's L2 from a distant chip due to a demand miss. #765,u,g,n,n,n,u,PM_DATA_FROM_DL2,The processor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss. ##0E0140000001C040 The processor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss. #766,u,g,n,n,n,u,PM_DPTEG_FROM_DL2,The processor's data page table entry was reloaded from another core's L2 from a distant chip due to a demand miss. ##0E0160000001C040 The processor's data page table entry was reloaded from another core's L2 from a distant chip due to a demand miss. #767,u,g,n,n,n,u,PM_INST_FROM_DL2_ALL,The processor's instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. ##0E0100000011C040 The processor's instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. #768,u,g,n,n,n,u,PM_IPTEG_FROM_DL2_ALL,The processor's instruction page table entry was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. ##0E0120000011C040 The processor's instruction page table entry was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. #769,u,g,n,n,n,u,PM_DATA_FROM_DL2_ALL,The processor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. ##0E0140000021C040 The processor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. #770,u,g,n,n,n,u,PM_DPTEG_FROM_DL2_ALL,The processor's data page table entry was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. ##0E0160000021C040 The processor's data page table entry was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. #771,u,g,n,n,n,u,PM_IPTEG_FROM_DL3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. ##0E8020000001C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. #772,u,g,n,n,n,u,PM_DATA_FROM_DL3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. ##0E8040000001C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. #773,u,g,n,n,n,u,PM_DPTEG_FROM_DL3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. ##0E8060000001C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. #774,u,g,n,n,n,u,PM_IPTEG_FROM_DL3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. ##0E8020000011C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. #775,u,g,n,n,n,u,PM_DATA_FROM_DL3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. ##0E8040000021C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. #776,u,g,n,n,n,u,PM_DPTEG_FROM_DL3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. ##0E8060000021C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. #777,u,g,n,n,n,u,PM_IPTEG_FROM_DL3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. ##0EC020000001C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. #778,u,g,n,n,n,u,PM_DATA_FROM_DL3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. ##0EC040000001C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. #779,u,g,n,n,n,u,PM_DPTEG_FROM_DL3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. ##0EC060000001C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. #780,u,g,n,n,n,u,PM_IPTEG_FROM_DL3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. ##0EC020000011C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. #781,u,g,n,n,n,u,PM_DATA_FROM_DL3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. ##0EC040000021C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. #782,u,g,n,n,n,u,PM_DPTEG_FROM_DL3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. ##0EC060000021C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. #783,u,g,n,n,n,u,PM_INST_FROM_DL3,The processor's instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss. ##0E8100000001C040 The processor's instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss. #784,u,g,n,n,n,u,PM_IPTEG_FROM_DL3,The processor's instruction page table entry was reloaded from another core's L3 from a distant chip due to a demand miss. ##0E8120000001C040 The processor's instruction page table entry was reloaded from another core's L3 from a distant chip due to a demand miss. #785,u,g,n,n,n,u,PM_DATA_FROM_DL3,The processor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss. ##0E8140000001C040 The processor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss. #786,u,g,n,n,n,u,PM_DPTEG_FROM_DL3,The processor's data page table entry was reloaded from another core's L3 from a distant chip due to a demand miss. ##0E8160000001C040 The processor's data page table entry was reloaded from another core's L3 from a distant chip due to a demand miss. #787,u,g,n,n,n,u,PM_INST_FROM_DL3_ALL,The processor's instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. ##0E8100000011C040 The processor's instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. #788,u,g,n,n,n,u,PM_IPTEG_FROM_DL3_ALL,The processor's instruction page table entry was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. ##0E8120000011C040 The processor's instruction page table entry was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. #789,u,g,n,n,n,u,PM_DATA_FROM_DL3_ALL,The processor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. ##0E8140000021C040 The processor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. #790,u,g,n,n,n,u,PM_DPTEG_FROM_DL3_ALL,The processor's data page table entry was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. ##0E8160000021C040 The processor's data page table entry was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. #791,u,g,n,n,n,u,PM_IPTEG_FROM_DL2L3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. ##0E0220000001C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. #792,u,g,n,n,n,u,PM_DATA_FROM_DL2L3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. ##0E0240000001C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. #793,u,g,n,n,n,u,PM_DPTEG_FROM_DL2L3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. ##0E0260000001C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. #794,u,g,n,n,n,u,PM_IPTEG_FROM_DL2L3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. ##0E0220000011C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. #795,u,g,n,n,n,u,PM_DATA_FROM_DL2L3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. ##0E0240000021C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. #796,u,g,n,n,n,u,PM_DPTEG_FROM_DL2L3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. ##0E0260000021C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. #797,u,g,n,n,n,u,PM_IPTEG_FROM_DL2L3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. ##0E4220000001C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. #798,u,g,n,n,n,u,PM_DATA_FROM_DL2L3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. ##0E4240000001C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. #799,u,g,n,n,n,u,PM_DPTEG_FROM_DL2L3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. ##0E4260000001C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. #800,u,g,n,n,n,u,PM_IPTEG_FROM_DL2L3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. ##0E4220000011C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. #801,u,g,n,n,n,u,PM_DATA_FROM_DL2L3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. ##0E4240000021C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. #802,u,g,n,n,n,u,PM_DPTEG_FROM_DL2L3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. ##0E4260000021C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. #803,u,g,n,n,n,u,PM_INST_FROM_DL2L3,The processor's instruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. ##0E0300000001C040 The processor's instruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. #804,u,g,n,n,n,u,PM_IPTEG_FROM_DL2L3,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. ##0E0320000001C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. #805,u,g,n,n,n,u,PM_DATA_FROM_DL2L3,The processor's L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. ##0E0340000001C040 The processor's L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. #806,u,g,n,n,n,u,PM_DPTEG_FROM_DL2L3,The processor's data page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. ##0E0360000001C040 The processor's data page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. #807,u,g,n,n,n,u,PM_INST_FROM_DL2L3_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. ##0E0300000011C040 The processor's instruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. #808,u,g,n,n,n,u,PM_IPTEG_FROM_DL2L3_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. ##0E0320000011C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. #809,u,g,n,n,n,u,PM_DATA_FROM_DL2L3_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. ##0E0340000021C040 The processor's L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. #810,u,g,n,n,n,u,PM_DPTEG_FROM_DL2L3_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. ##0E0360000021C040 The processor's data page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. #811,u,g,n,n,n,u,PM_INST_FROM_DMEM,The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss. ##0F4100000001C040 The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss. #812,u,g,n,n,n,u,PM_IPTEG_FROM_DMEM,The processor's instruction page table entry was reloaded from distant memory (MC slow) due to a demand miss. ##0F4020000001C040 The processor's instruction page table entry was reloaded from distant memory (MC slow) due to a demand miss. #813,u,g,n,n,n,u,PM_DATA_FROM_DMEM,The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss. ##0F4040000001C040 The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss. #814,u,g,n,n,n,u,PM_DPTEG_FROM_DMEM,The processor's data page table entry was reloaded from distant memory (MC slow) due to a demand miss. ##0F4060000001C040 The processor's data page table entry was reloaded from distant memory (MC slow) due to a demand miss. #815,u,g,n,n,n,u,PM_INST_FROM_DMEM_ALL,The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. ##0F4100000011C040 The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. #816,u,g,n,n,n,u,PM_IPTEG_FROM_DMEM_ALL,The processor's instruction page table entry was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. ##0F4020000011C040 The processor's instruction page table entry was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. #817,u,g,n,n,n,u,PM_DATA_FROM_DMEM_ALL,The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. ##0F4040000021C040 The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. #818,u,g,n,n,n,u,PM_DPTEG_FROM_DMEM_ALL,The processor's data page table entry was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. ##0F4060000021C040 The processor's data page table entry was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. #819,u,g,n,n,n,u,PM_IPTEG_FROM_D_OC_CACHE,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss. ##0F8020000001C040 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss. #820,u,g,n,n,n,u,PM_DATA_FROM_D_OC_CACHE,The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache due to a demand miss. ##0F8040000001C040 The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache due to a demand miss. #821,u,g,n,n,n,u,PM_DPTEG_FROM_D_OC_CACHE,The processor's data page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss. ##0F8060000001C040 The processor's data page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss. #822,u,g,n,n,n,u,PM_IPTEG_FROM_D_OC_CACHE_ALL,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. ##0F8020000011C040 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. #823,u,g,n,n,n,u,PM_DATA_FROM_D_OC_CACHE_ALL,The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. ##0F8040000021C040 The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. #824,u,g,n,n,n,u,PM_DPTEG_FROM_D_OC_CACHE_ALL,The processor's data page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. ##0F8060000021C040 The processor's data page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. #825,u,g,n,n,n,u,PM_IPTEG_FROM_D_OC_MEM,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss. ##0FC020000001C040 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss. #826,u,g,n,n,n,u,PM_DATA_FROM_D_OC_MEM,The processor's L1 data cache was reloaded from a distant chip's OpenCapp memory due to a demand miss. ##0FC040000001C040 The processor's L1 data cache was reloaded from a distant chip's OpenCapp memory due to a demand miss. #827,u,g,n,n,n,u,PM_DPTEG_FROM_D_OC_MEM,The processor's data page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss. ##0FC060000001C040 The processor's data page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss. #828,u,g,n,n,n,u,PM_IPTEG_FROM_D_OC_MEM_ALL,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. ##0FC020000011C040 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. #829,u,g,n,n,n,u,PM_DATA_FROM_D_OC_MEM_ALL,The processor's L1 data cache was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. ##0FC040000021C040 The processor's L1 data cache was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. #830,u,g,n,n,n,u,PM_DPTEG_FROM_D_OC_MEM_ALL,The processor's data page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. ##0FC060000021C040 The processor's data page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. #831,u,g,n,n,n,u,PM_INST_FROM_D_OC_ANY,The processor's instruction cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. ##0F8100000001C040 The processor's instruction cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. #832,u,g,n,n,n,u,PM_IPTEG_FROM_D_OC_ANY,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. ##0F8120000001C040 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. #833,u,g,n,n,n,u,PM_DATA_FROM_D_OC_ANY,The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. ##0F8140000001C040 The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. #834,u,g,n,n,n,u,PM_DPTEG_FROM_D_OC_ANY,The processor's data page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. ##0F8160000001C040 The processor's data page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. #835,u,g,n,n,n,u,PM_INST_FROM_D_OC_ANY_ALL,The processor's instruction cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##0F8100000011C040 The processor's instruction cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #836,u,g,n,n,n,u,PM_IPTEG_FROM_D_OC_ANY_ALL,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##0F8120000011C040 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #837,u,g,n,n,n,u,PM_DATA_FROM_D_OC_ANY_ALL,The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##0F8140000021C040 The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #838,u,g,n,n,n,u,PM_DPTEG_FROM_D_OC_ANY_ALL,The processor's data page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##0F8160000021C040 The processor's data page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #839,u,g,n,n,n,u,PM_INST_FROM_ONCHIP_CACHE,The processor's instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss. ##080B00000001C040 The processor's instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss. #840,u,g,n,n,n,u,PM_IPTEG_FROM_ONCHIP_CACHE,The processor's instruction page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss. ##080B20000001C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss. #841,u,g,n,n,n,u,PM_DATA_FROM_ONCHIP_CACHE,The processor's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss. ##080B40000001C040 The processor's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss. #842,u,g,n,n,n,u,PM_DPTEG_FROM_ONCHIP_CACHE,The processor's data page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss. ##080B60000001C040 The processor's data page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss. #843,u,g,n,n,n,u,PM_INST_FROM_ONCHIP_CACHE_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. ##080B00000011C040 The processor's instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. #844,u,g,n,n,n,u,PM_IPTEG_FROM_ONCHIP_CACHE_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. ##080B20000011C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. #845,u,g,n,n,n,u,PM_DATA_FROM_ONCHIP_CACHE_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. ##080B40000021C040 The processor's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. #846,u,g,n,n,n,u,PM_DPTEG_FROM_ONCHIP_CACHE_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. ##080B60000021C040 The processor's data page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. #847,u,g,n,n,n,u,PM_INST_FROM_OFFCHIP_CACHE,The processor's instruction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss. ##0C0B00000001C040 The processor's instruction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss. #848,u,g,n,n,n,u,PM_IPTEG_FROM_OFFCHIP_CACHE,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss. ##0C0B20000001C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss. #849,u,g,n,n,n,u,PM_DATA_FROM_OFFCHIP_CACHE,The processor's L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss. ##0C0B40000001C040 The processor's L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss. #850,u,g,n,n,n,u,PM_DPTEG_FROM_OFFCHIP_CACHE,The processor's data page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss. ##0C0B60000001C040 The processor's data page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss. #851,u,g,n,n,n,u,PM_INST_FROM_OFFCHIP_CACHE_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. ##0C0B00000011C040 The processor's instruction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. #852,u,g,n,n,n,u,PM_IPTEG_FROM_OFFCHIP_CACHE_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. ##0C0B20000011C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. #853,u,g,n,n,n,u,PM_DATA_FROM_OFFCHIP_CACHE_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. ##0C0B40000021C040 The processor's L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. #854,u,g,n,n,n,u,PM_DPTEG_FROM_OFFCHIP_CACHE_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. ##0C0B60000021C040 The processor's data page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. #855,u,g,n,n,n,u,PM_INST_FROM_ANY_MEMORY,The processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss. ##095900000001C040 The processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss. #856,u,g,n,n,n,u,PM_IPTEG_FROM_ANY_MEMORY,The processor's instruction page table entry was reloaded from any chip's memory (MC slow) due to a demand miss. ##095820000001C040 The processor's instruction page table entry was reloaded from any chip's memory (MC slow) due to a demand miss. #857,u,g,n,n,n,u,PM_DATA_FROM_ANY_MEMORY,The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss. ##095840000001C040 The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss. #858,u,g,n,n,n,u,PM_DPTEG_FROM_ANY_MEMORY,The processor's data page table entry was reloaded from any chip's memory (MC slow) due to a demand miss. ##095860000001C040 The processor's data page table entry was reloaded from any chip's memory (MC slow) due to a demand miss. #859,u,g,n,n,n,u,PM_INST_FROM_ANY_MEMORY_ALL,The processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. ##095900000011C040 The processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. #860,u,g,n,n,n,u,PM_IPTEG_FROM_ANY_MEMORY_ALL,The processor's instruction page table entry was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. ##095820000011C040 The processor's instruction page table entry was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. #861,u,g,n,n,n,u,PM_DATA_FROM_ANY_MEMORY_ALL,The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. ##095840000021C040 The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. #862,u,g,n,n,n,u,PM_DPTEG_FROM_ANY_MEMORY_ALL,The processor's data page table entry was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. ##095860000021C040 The processor's data page table entry was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. #863,u,g,n,n,m,u,PM_MRK_INST_FROM_L2,The processor's instruction cache was reloaded from the local core's L2 due to a demand miss for a marked instruction. ##000300000001C142 The processor's instruction cache was reloaded from the local core's L2 due to a demand miss for a marked instruction. #864,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2,The processor's instruction page table entry was reloaded from the local core's L2 due to a demand miss for a marked instruction. ##000320000001C142 The processor's instruction page table entry was reloaded from the local core's L2 due to a demand miss for a marked instruction. #865,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2,The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss for a marked instruction. ##000340000001C142 The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss for a marked instruction. #866,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2,The processor's data page table entry was reloaded from the local core's L2 due to a demand miss for a marked instruction. ##000360000001C142 The processor's data page table entry was reloaded from the local core's L2 due to a demand miss for a marked instruction. #867,u,g,n,n,m,u,PM_MRK_INST_FROM_L2_ALL,The processor's instruction cache was reloaded from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##000300000011C142 The processor's instruction cache was reloaded from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #868,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_ALL,The processor's instruction page table entry was reloaded from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##000320000011C142 The processor's instruction page table entry was reloaded from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #869,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_ALL,The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##000340000021C142 The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #870,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_ALL,The processor's data page table entry was reloaded from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##000360000021C142 The processor's data page table entry was reloaded from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #871,u,g,n,n,m,u,PM_MRK_INST_FROM_L1MISS,The processor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss for a marked instruction. ##003F00000001C142 The processor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss for a marked instruction. #872,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L1MISS,The processor's instruction page table entry was reloaded from a source beyond the local core's L1 due to a demand miss for a marked instruction. ##003F20000001C142 The processor's instruction page table entry was reloaded from a source beyond the local core's L1 due to a demand miss for a marked instruction. #873,u,g,n,n,m,u,PM_MRK_DATA_FROM_L1MISS,The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss for a marked instruction. ##003F40000001C142 The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss for a marked instruction. #874,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L1MISS,The processor's data page table entry was reloaded from a source beyond the local core's L1 due to a demand miss for a marked instruction. ##003F60000001C142 The processor's data page table entry was reloaded from a source beyond the local core's L1 due to a demand miss for a marked instruction. #875,u,g,n,n,m,u,PM_MRK_INST_FROM_L1MISS_ALL,The processor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload for a marked instruction. ##003F00000011C142 The processor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload for a marked instruction. #876,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L1MISS_ALL,The processor's instruction page table entry was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload for a marked instruction. ##003F20000011C142 The processor's instruction page table entry was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload for a marked instruction. #877,u,g,n,n,m,u,PM_MRK_DATA_FROM_L1MISS_ALL,The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload for a marked instruction. ##003F40000021C142 The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload for a marked instruction. #878,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L1MISS_ALL,The processor's data page table entry was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload for a marked instruction. ##003F60000021C142 The processor's data page table entry was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload for a marked instruction. #879,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_NO_CONFLICT,The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss for a marked instruction. ##000020000001C142 The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss for a marked instruction. #880,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_NO_CONFLICT,The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss for a marked instruction. ##000040000001C142 The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss for a marked instruction. #881,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_NO_CONFLICT,The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss for a marked instruction. ##000060000001C142 The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss for a marked instruction. #882,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_NO_CONFLICT_ALL,The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##000020000011C142 The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #883,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_NO_CONFLICT_ALL,The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##000040000021C142 The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #884,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_NO_CONFLICT_ALL,The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##000060000021C142 The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #885,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_MEPF,The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss for a marked instruction. ##004020000001C142 The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss for a marked instruction. #886,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_MEPF,The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss for a marked instruction. ##004040000001C142 The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss for a marked instruction. #887,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_MEPF,The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss for a marked instruction. ##004060000001C142 The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss for a marked instruction. #888,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_MEPF_ALL,The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##004020000011C142 The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #889,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_MEPF_ALL,The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##004040000021C142 The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #890,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_MEPF_ALL,The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##004060000021C142 The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #891,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_LDHITST_CONFLICT,The processor's instruction page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. ##008020000001C142 The processor's instruction page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. #892,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_LDHITST_CONFLICT,The processor's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. ##008040000001C142 The processor's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. #893,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_LDHITST_CONFLICT,The processor's data page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. ##008060000001C142 The processor's data page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. #894,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_LDHITST_CONFLICT_ALL,The processor's instruction page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##008020000011C142 The processor's instruction page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #895,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_LDHITST_CONFLICT_ALL,The processor's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##008040000021C142 The processor's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #896,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_LDHITST_CONFLICT_ALL,The processor's data page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##008060000021C142 The processor's data page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #897,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_OTHER_CONFLICT,The processor's instruction page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. ##00C020000001C142 The processor's instruction page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. #898,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_OTHER_CONFLICT,The processor's L1 data cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. ##00C040000001C142 The processor's L1 data cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. #899,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_OTHER_CONFLICT,The processor's data page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. ##00C060000001C142 The processor's data page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. #900,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_OTHER_CONFLICT_ALL,The processor's instruction page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##00C020000011C142 The processor's instruction page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #901,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_OTHER_CONFLICT_ALL,The processor's L1 data cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##00C040000021C142 The processor's L1 data cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #902,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_OTHER_CONFLICT_ALL,The processor's data page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##00C060000021C142 The processor's data page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #903,u,g,n,n,m,u,PM_MRK_INST_FROM_L2MISS,The processor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction. ##000380000001C142 The processor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction. #904,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2MISS,The processor's instruction page table entry was reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction. ##0003A0000001C142 The processor's instruction page table entry was reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction. #905,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2MISS,The processor's data page table entry was reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction. ##0003E0000001C142 The processor's data page table entry was reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction. #906,u,g,n,n,m,u,PM_MRK_INST_FROM_L2MISS_ALL,The processor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##000380000011C142 The processor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #907,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2MISS_ALL,The processor's instruction page table entry was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##0003A0000011C142 The processor's instruction page table entry was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #908,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2MISS_ALL,The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##0003C0000021C142 The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #909,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2MISS_ALL,The processor's data page table entry was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##0003E0000021C142 The processor's data page table entry was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #910,u,g,n,n,m,u,PM_MRK_INST_FROM_L3,The processor's instruction cache was reloaded from the local core's L3 due to a demand miss for a marked instruction. ##010300000001C142 The processor's instruction cache was reloaded from the local core's L3 due to a demand miss for a marked instruction. #911,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3,The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss for a marked instruction. ##010320000001C142 The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss for a marked instruction. #912,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3,The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss for a marked instruction. ##010340000001C142 The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss for a marked instruction. #913,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3,The processor's data page table entry was reloaded from the local core's L3 due to a demand miss for a marked instruction. ##010360000001C142 The processor's data page table entry was reloaded from the local core's L3 due to a demand miss for a marked instruction. #914,u,g,n,n,m,u,PM_MRK_INST_FROM_L3_ALL,The processor's instruction cache was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##010300000011C142 The processor's instruction cache was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #915,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_ALL,The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##010320000011C142 The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #916,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_ALL,The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##010340000021C142 The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #917,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_ALL,The processor's data page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##010360000021C142 The processor's data page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #918,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_NO_CONFLICT,The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss for a marked instruction. ##010020000001C142 The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss for a marked instruction. #919,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_NO_CONFLICT,The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss for a marked instruction. ##010040000001C142 The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss for a marked instruction. #920,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_NO_CONFLICT,The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss for a marked instruction. ##010060000001C142 The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss for a marked instruction. #921,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_NO_CONFLICT_ALL,The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##010020000011C142 The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #922,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_NO_CONFLICT_ALL,The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##010040000021C142 The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #923,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_NO_CONFLICT_ALL,The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##010060000021C142 The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #924,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_MEPF,The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss for a marked instruction. ##014020000001C142 The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss for a marked instruction. #925,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_MEPF,The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss for a marked instruction. ##014040000001C142 The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss for a marked instruction. #926,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_MEPF,The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss for a marked instruction. ##014060000001C142 The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss for a marked instruction. #927,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_MEPF_ALL,The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##014020000011C142 The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #928,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_MEPF_ALL,The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##014040000021C142 The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #929,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_MEPF_ALL,The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##014060000021C142 The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #930,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_CONFLICT,The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss for a marked instruction. ##01C020000001C142 The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss for a marked instruction. #931,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_CONFLICT,The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss for a marked instruction. ##01C040000001C142 The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss for a marked instruction. #932,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_CONFLICT,The processor's data page table entry was reloaded from the local core's L3 due to a demand miss for a marked instruction. ##01C060000001C142 The processor's data page table entry was reloaded from the local core's L3 due to a demand miss for a marked instruction. #933,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_CONFLICT_ALL,The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##01C020000011C142 The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #934,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_CONFLICT_ALL,The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##01C040000021C142 The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #935,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_CONFLICT_ALL,The processor's data page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##01C060000021C142 The processor's data page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #936,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3MISS,The processor's instruction page table entry was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction. ##0007A0000001C142 The processor's instruction page table entry was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction. #937,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3MISS,The processor's data page table entry was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction. ##0007E0000001C142 The processor's data page table entry was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction. #938,u,g,n,n,m,u,PM_MRK_INST_FROM_L3MISS_ALL,The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##000780000011C142 The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #939,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3MISS_ALL,The processor's instruction page table entry was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##0007A0000011C142 The processor's instruction page table entry was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #940,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3MISS_ALL,The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##0007C0000021C142 The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #941,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3MISS_ALL,The processor's data page table entry was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##0007E0000021C142 The processor's data page table entry was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #942,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. ##080020000001C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. #943,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. ##080040000001C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. #944,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. ##080060000001C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. #945,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080020000011C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #946,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080040000021C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #947,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080060000021C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #948,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. ##084020000001C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. #949,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. ##084040000001C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. #950,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. ##084060000001C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. #951,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##084020000011C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #952,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##084040000021C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #953,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##084060000021C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #954,u,g,n,n,m,u,PM_MRK_INST_FROM_L21_REGENT,The processor's instruction cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. ##080100000001C142 The processor's instruction cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. #955,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT,The processor's instruction page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. ##080120000001C142 The processor's instruction page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. #956,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT,The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. ##080140000001C142 The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. #957,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT,The processor's data page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. ##080160000001C142 The processor's data page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. #958,u,g,n,n,m,u,PM_MRK_INST_FROM_L21_REGENT_ALL,The processor's instruction cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080100000011C142 The processor's instruction cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #959,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_ALL,The processor's instruction page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080120000011C142 The processor's instruction page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #960,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_ALL,The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080140000021C142 The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #961,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_ALL,The processor's data page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080160000021C142 The processor's data page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #962,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##088020000001C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. #963,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##088040000001C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. #964,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##088060000001C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. #965,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##088020000011C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #966,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##088040000021C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #967,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##088060000021C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #968,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##08C020000001C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. #969,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##08C040000001C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. #970,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##08C060000001C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. #971,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##08C020000011C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #972,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##08C040000021C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #973,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##08C060000021C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #974,u,g,n,n,m,u,PM_MRK_INST_FROM_L31_REGENT,The processor's instruction cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##088100000001C142 The processor's instruction cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. #975,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT,The processor's instruction page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##088120000001C142 The processor's instruction page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. #976,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT,The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##088140000001C142 The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. #977,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT,The processor's data page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##088160000001C142 The processor's data page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. #978,u,g,n,n,m,u,PM_MRK_INST_FROM_L31_REGENT_ALL,The processor's instruction cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##088100000011C142 The processor's instruction cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #979,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_ALL,The processor's instruction page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##088120000011C142 The processor's instruction page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #980,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_ALL,The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##088140000021C142 The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #981,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_ALL,The processor's data page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##088160000021C142 The processor's data page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #982,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##080220000001C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. #983,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##080240000001C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. #984,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##080260000001C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. #985,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080220000011C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #986,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080240000021C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #987,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080260000021C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #988,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##084220000001C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. #989,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##084240000001C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. #990,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##084260000001C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. #991,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##084220000011C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #992,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##084240000021C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #993,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##084260000021C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #994,u,g,n,n,m,u,PM_MRK_INST_FROM_REGENT_L2L3,The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##080300000001C142 The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. #995,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3,The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##080320000001C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. #996,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3,The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##080340000001C142 The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. #997,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3,The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##080360000001C142 The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. #998,u,g,n,n,m,u,PM_MRK_INST_FROM_REGENT_L2L3_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080300000011C142 The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #999,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080320000011C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #1000,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080340000021C142 The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #1001,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080360000021C142 The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #1002,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0020000001C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. #1003,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0040000001C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. #1004,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0060000001C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. #1005,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0020000011C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1006,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0040000021C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1007,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0060000021C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1008,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A4020000001C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. #1009,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A4040000001C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. #1010,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A4060000001C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. #1011,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A4020000011C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1012,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A4040000021C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1013,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A4060000021C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1014,u,g,n,n,m,u,PM_MRK_INST_FROM_L21_NON_REGENT,The processor's instruction cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0100000001C142 The processor's instruction cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. #1015,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT,The processor's instruction page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0120000001C142 The processor's instruction page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. #1016,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT,The processor's L1 data cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0140000001C142 The processor's L1 data cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. #1017,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT,The processor's data page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0160000001C142 The processor's data page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. #1018,u,g,n,n,m,u,PM_MRK_INST_FROM_L21_NON_REGENT_ALL,The processor's instruction cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0100000011C142 The processor's instruction cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1019,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_ALL,The processor's instruction page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0120000011C142 The processor's instruction page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1020,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_ALL,The processor's L1 data cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0140000021C142 The processor's L1 data cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1021,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_ALL,The processor's data page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0160000021C142 The processor's data page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1022,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A8020000001C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1023,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A8040000001C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1024,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A8060000001C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1025,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A8020000011C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1026,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A8040000021C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1027,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A8060000021C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1028,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0AC020000001C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1029,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0AC040000001C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1030,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0AC060000001C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1031,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0AC020000011C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1032,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0AC040000021C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1033,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0AC060000021C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1034,u,g,n,n,m,u,PM_MRK_INST_FROM_L31_NON_REGENT,The processor's instruction cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A8100000001C142 The processor's instruction cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1035,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT,The processor's instruction page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A8120000001C142 The processor's instruction page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1036,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT,The processor's L1 data cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A8140000001C142 The processor's L1 data cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1037,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT,The processor's data page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A8160000001C142 The processor's data page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1038,u,g,n,n,m,u,PM_MRK_INST_FROM_L31_NON_REGENT_ALL,The processor's instruction cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A8100000011C142 The processor's instruction cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1039,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_ALL,The processor's instruction page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A8120000011C142 The processor's instruction page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1040,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_ALL,The processor's L1 data cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A8140000021C142 The processor's L1 data cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1041,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_ALL,The processor's data page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A8160000021C142 The processor's data page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1042,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0220000001C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1043,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0240000001C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1044,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0260000001C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1045,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0220000011C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1046,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0240000021C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1047,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0260000021C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1048,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A4220000001C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1049,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A4240000001C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1050,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A4260000001C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1051,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A4220000011C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1052,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A4240000021C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1053,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A4260000021C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1054,u,g,n,n,m,u,PM_MRK_INST_FROM_NON_REGENT_L2L3,The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0300000001C142 The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1055,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3,The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0320000001C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1056,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3,The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0340000001C142 The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1057,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3,The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0360000001C142 The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1058,u,g,n,n,m,u,PM_MRK_INST_FROM_NON_REGENT_L2L3_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0300000011C142 The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1059,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0320000011C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1060,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0340000021C142 The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1061,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0360000021C142 The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1062,u,g,n,n,m,u,PM_MRK_INST_FROM_LMEM,The processor's instruction cache was reloaded from the local chip's memory due to a demand miss for a marked instruction. ##094100000001C142 The processor's instruction cache was reloaded from the local chip's memory due to a demand miss for a marked instruction. #1063,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_LMEM,The processor's instruction page table entry was reloaded from the local chip's memory due to a demand miss for a marked instruction. ##094020000001C142 The processor's instruction page table entry was reloaded from the local chip's memory due to a demand miss for a marked instruction. #1064,u,g,n,n,m,u,PM_MRK_DATA_FROM_LMEM,The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss for a marked instruction. ##094040000001C142 The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss for a marked instruction. #1065,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_LMEM,The processor's data page table entry was reloaded from the local chip's memory due to a demand miss for a marked instruction. ##094060000001C142 The processor's data page table entry was reloaded from the local chip's memory due to a demand miss for a marked instruction. #1066,u,g,n,n,m,u,PM_MRK_INST_FROM_LMEM_ALL,The processor's instruction cache was reloaded from the local chip's memory due to a demand miss or prefetch reload for a marked instruction. ##094100000011C142 The processor's instruction cache was reloaded from the local chip's memory due to a demand miss or prefetch reload for a marked instruction. #1067,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_LMEM_ALL,The processor's instruction page table entry was reloaded from the local chip's memory due to a demand miss or prefetch reload for a marked instruction. ##094020000011C142 The processor's instruction page table entry was reloaded from the local chip's memory due to a demand miss or prefetch reload for a marked instruction. #1068,u,g,n,n,m,u,PM_MRK_DATA_FROM_LMEM_ALL,The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss or prefetch reload for a marked instruction. ##094040000021C142 The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss or prefetch reload for a marked instruction. #1069,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_LMEM_ALL,The processor's data page table entry was reloaded from the local chip's memory due to a demand miss or prefetch reload for a marked instruction. ##094060000021C142 The processor's data page table entry was reloaded from the local chip's memory due to a demand miss or prefetch reload for a marked instruction. #1070,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_CACHE,The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss for a marked instruction. ##098020000001C142 The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss for a marked instruction. #1071,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_CACHE,The processor's L1 data cache was reloaded from the local chip's OpenCapp cache due to a demand miss for a marked instruction. ##098040000001C142 The processor's L1 data cache was reloaded from the local chip's OpenCapp cache due to a demand miss for a marked instruction. #1072,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_CACHE,The processor's data page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss for a marked instruction. ##098060000001C142 The processor's data page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss for a marked instruction. #1073,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_CACHE_ALL,The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. ##098020000011C142 The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. #1074,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_CACHE_ALL,The processor's L1 data cache was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. ##098040000021C142 The processor's L1 data cache was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. #1075,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_CACHE_ALL,The processor's data page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. ##098060000021C142 The processor's data page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. #1076,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_MEM,The processor's instruction page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss for a marked instruction. ##09C020000001C142 The processor's instruction page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss for a marked instruction. #1077,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_MEM,The processor's L1 data cache was reloaded from the local chip's OpenCapp memory due to a demand miss for a marked instruction. ##09C040000001C142 The processor's L1 data cache was reloaded from the local chip's OpenCapp memory due to a demand miss for a marked instruction. #1078,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_MEM,The processor's data page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss for a marked instruction. ##09C060000001C142 The processor's data page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss for a marked instruction. #1079,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_MEM_ALL,The processor's instruction page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. ##09C020000011C142 The processor's instruction page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. #1080,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_MEM_ALL,The processor's L1 data cache was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. ##09C040000021C142 The processor's L1 data cache was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. #1081,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_MEM_ALL,The processor's data page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. ##09C060000021C142 The processor's data page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. #1082,u,g,n,n,m,u,PM_MRK_INST_FROM_L_OC_ANY,The processor's instruction cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##098100000001C142 The processor's instruction cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1083,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_ANY,The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##098120000001C142 The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1084,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_ANY,The processor's L1 data cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##098140000001C142 The processor's L1 data cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1085,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_ANY,The processor's data page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##098160000001C142 The processor's data page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1086,u,g,n,n,m,u,PM_MRK_INST_FROM_L_OC_ANY_ALL,The processor's instruction cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##098100000011C142 The processor's instruction cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1087,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_ANY_ALL,The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##098120000011C142 The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1088,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_ANY_ALL,The processor's L1 data cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##098140000021C142 The processor's L1 data cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1089,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_ANY_ALL,The processor's data page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##098160000021C142 The processor's data page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1090,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. ##0C0020000001C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. #1091,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. ##0C0040000001C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. #1092,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. ##0C0060000001C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. #1093,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0020000011C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1094,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0040000021C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1095,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0060000021C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1096,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. ##0C4020000001C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. #1097,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. ##0C4040000001C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. #1098,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. ##0C4060000001C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. #1099,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C4020000011C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1100,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C4040000021C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1101,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C4060000021C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1102,u,g,n,n,m,u,PM_MRK_INST_FROM_RL2,The processor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss for a marked instruction. ##0C0100000001C142 The processor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss for a marked instruction. #1103,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2,The processor's instruction page table entry was reloaded from another core's L2 from a remote chip due to a demand miss for a marked instruction. ##0C0120000001C142 The processor's instruction page table entry was reloaded from another core's L2 from a remote chip due to a demand miss for a marked instruction. #1104,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2,The processor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss for a marked instruction. ##0C0140000001C142 The processor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss for a marked instruction. #1105,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2,The processor's data page table entry was reloaded from another core's L2 from a remote chip due to a demand miss for a marked instruction. ##0C0160000001C142 The processor's data page table entry was reloaded from another core's L2 from a remote chip due to a demand miss for a marked instruction. #1106,u,g,n,n,m,u,PM_MRK_INST_FROM_RL2_ALL,The processor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0100000011C142 The processor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1107,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_ALL,The processor's instruction page table entry was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0120000011C142 The processor's instruction page table entry was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1108,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_ALL,The processor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0140000021C142 The processor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1109,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_ALL,The processor's data page table entry was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0160000021C142 The processor's data page table entry was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1110,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. ##0C8020000001C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. #1111,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. ##0C8040000001C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. #1112,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. ##0C8060000001C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. #1113,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C8020000011C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1114,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C8040000021C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1115,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C8060000021C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1116,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. ##0CC020000001C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. #1117,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. ##0CC040000001C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. #1118,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. ##0CC060000001C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. #1119,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0CC020000011C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1120,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0CC040000021C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1121,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0CC060000021C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1122,u,g,n,n,m,u,PM_MRK_INST_FROM_RL3,The processor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss for a marked instruction. ##0C8100000001C142 The processor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss for a marked instruction. #1123,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3,The processor's instruction page table entry was reloaded from another core's L3 from a remote chip due to a demand miss for a marked instruction. ##0C8120000001C142 The processor's instruction page table entry was reloaded from another core's L3 from a remote chip due to a demand miss for a marked instruction. #1124,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3,The processor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss for a marked instruction. ##0C8140000001C142 The processor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss for a marked instruction. #1125,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3,The processor's data page table entry was reloaded from another core's L3 from a remote chip due to a demand miss for a marked instruction. ##0C8160000001C142 The processor's data page table entry was reloaded from another core's L3 from a remote chip due to a demand miss for a marked instruction. #1126,u,g,n,n,m,u,PM_MRK_INST_FROM_RL3_ALL,The processor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C8100000011C142 The processor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1127,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_ALL,The processor's instruction page table entry was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C8120000011C142 The processor's instruction page table entry was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1128,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_ALL,The processor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C8140000021C142 The processor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1129,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_ALL,The processor's data page table entry was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C8160000021C142 The processor's data page table entry was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1130,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. ##0C0220000001C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. #1131,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. ##0C0240000001C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. #1132,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. ##0C0260000001C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. #1133,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0220000011C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1134,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0240000021C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1135,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0260000021C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1136,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. ##0C4220000001C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. #1137,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. ##0C4240000001C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. #1138,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. ##0C4260000001C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. #1139,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C4220000011C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1140,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C4240000021C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1141,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C4260000021C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1142,u,g,n,n,m,u,PM_MRK_INST_FROM_RL2L3,The processor's instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. ##0C0300000001C142 The processor's instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. #1143,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. ##0C0320000001C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. #1144,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3,The processor's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. ##0C0340000001C142 The processor's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. #1145,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3,The processor's data page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. ##0C0360000001C142 The processor's data page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. #1146,u,g,n,n,m,u,PM_MRK_INST_FROM_RL2L3_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0300000011C142 The processor's instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1147,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0320000011C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1148,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0340000021C142 The processor's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1149,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0360000021C142 The processor's data page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1150,u,g,n,n,m,u,PM_MRK_INST_FROM_RMEM,The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss for a marked instruction. ##0D4100000001C142 The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss for a marked instruction. #1151,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RMEM,The processor's instruction page table entry was reloaded from remote memory (MC slow) due to a demand miss for a marked instruction. ##0D4020000001C142 The processor's instruction page table entry was reloaded from remote memory (MC slow) due to a demand miss for a marked instruction. #1152,u,g,n,n,m,u,PM_MRK_DATA_FROM_RMEM,The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss for a marked instruction. ##0D4040000001C142 The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss for a marked instruction. #1153,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RMEM,The processor's data page table entry was reloaded from remote memory (MC slow) due to a demand miss for a marked instruction. ##0D4060000001C142 The processor's data page table entry was reloaded from remote memory (MC slow) due to a demand miss for a marked instruction. #1154,u,g,n,n,m,u,PM_MRK_INST_FROM_RMEM_ALL,The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##0D4100000011C142 The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1155,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RMEM_ALL,The processor's instruction page table entry was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##0D4020000011C142 The processor's instruction page table entry was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1156,u,g,n,n,m,u,PM_MRK_DATA_FROM_RMEM_ALL,The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##0D4040000021C142 The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1157,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RMEM_ALL,The processor's data page table entry was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##0D4060000021C142 The processor's data page table entry was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1158,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_CACHE,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss for a marked instruction. ##0D8020000001C142 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss for a marked instruction. #1159,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_CACHE,The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache due to a demand miss for a marked instruction. ##0D8040000001C142 The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache due to a demand miss for a marked instruction. #1160,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_CACHE,The processor's data page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss for a marked instruction. ##0D8060000001C142 The processor's data page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss for a marked instruction. #1161,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_CACHE_ALL,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. ##0D8020000011C142 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. #1162,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_CACHE_ALL,The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. ##0D8040000021C142 The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. #1163,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_CACHE_ALL,The processor's data page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. ##0D8060000021C142 The processor's data page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. #1164,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_MEM,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss for a marked instruction. ##0DC020000001C142 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss for a marked instruction. #1165,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_MEM,The processor's L1 data cache was reloaded from a remote chip's OpenCapp memory due to a demand miss for a marked instruction. ##0DC040000001C142 The processor's L1 data cache was reloaded from a remote chip's OpenCapp memory due to a demand miss for a marked instruction. #1166,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_MEM,The processor's data page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss for a marked instruction. ##0DC060000001C142 The processor's data page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss for a marked instruction. #1167,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_MEM_ALL,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. ##0DC020000011C142 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. #1168,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_MEM_ALL,The processor's L1 data cache was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. ##0DC040000021C142 The processor's L1 data cache was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. #1169,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_MEM_ALL,The processor's data page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. ##0DC060000021C142 The processor's data page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. #1170,u,g,n,n,m,u,PM_MRK_INST_FROM_R_OC_ANY,The processor's instruction cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##0D8100000001C142 The processor's instruction cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1171,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_ANY,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##0D8120000001C142 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1172,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_ANY,The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##0D8140000001C142 The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1173,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_ANY,The processor's data page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##0D8160000001C142 The processor's data page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1174,u,g,n,n,m,u,PM_MRK_INST_FROM_R_OC_ANY_ALL,The processor's instruction cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##0D8100000011C142 The processor's instruction cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1175,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_ANY_ALL,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##0D8120000011C142 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1176,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_ANY_ALL,The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##0D8140000021C142 The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1177,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_ANY_ALL,The processor's data page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##0D8160000021C142 The processor's data page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1178,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. ##0E0020000001C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. #1179,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. ##0E0040000001C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. #1180,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. ##0E0060000001C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. #1181,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0020000011C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1182,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0040000021C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1183,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0060000021C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1184,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. ##0E4020000001C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. #1185,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. ##0E4040000001C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. #1186,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. ##0E4060000001C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. #1187,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E4020000011C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1188,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E4040000021C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1189,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E4060000021C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1190,u,g,n,n,m,u,PM_MRK_INST_FROM_DL2,The processor's instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss for a marked instruction. ##0E0100000001C142 The processor's instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss for a marked instruction. #1191,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2,The processor's instruction page table entry was reloaded from another core's L2 from a distant chip due to a demand miss for a marked instruction. ##0E0120000001C142 The processor's instruction page table entry was reloaded from another core's L2 from a distant chip due to a demand miss for a marked instruction. #1192,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2,The processor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss for a marked instruction. ##0E0140000001C142 The processor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss for a marked instruction. #1193,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2,The processor's data page table entry was reloaded from another core's L2 from a distant chip due to a demand miss for a marked instruction. ##0E0160000001C142 The processor's data page table entry was reloaded from another core's L2 from a distant chip due to a demand miss for a marked instruction. #1194,u,g,n,n,m,u,PM_MRK_INST_FROM_DL2_ALL,The processor's instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0100000011C142 The processor's instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1195,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_ALL,The processor's instruction page table entry was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0120000011C142 The processor's instruction page table entry was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1196,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_ALL,The processor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0140000021C142 The processor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1197,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_ALL,The processor's data page table entry was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0160000021C142 The processor's data page table entry was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1198,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. ##0E8020000001C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. #1199,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. ##0E8040000001C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. #1200,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. ##0E8060000001C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. #1201,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E8020000011C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1202,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E8040000021C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1203,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E8060000021C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1204,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. ##0EC020000001C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. #1205,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. ##0EC040000001C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. #1206,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. ##0EC060000001C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. #1207,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0EC020000011C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1208,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0EC040000021C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1209,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0EC060000021C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1210,u,g,n,n,m,u,PM_MRK_INST_FROM_DL3,The processor's instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss for a marked instruction. ##0E8100000001C142 The processor's instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss for a marked instruction. #1211,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3,The processor's instruction page table entry was reloaded from another core's L3 from a distant chip due to a demand miss for a marked instruction. ##0E8120000001C142 The processor's instruction page table entry was reloaded from another core's L3 from a distant chip due to a demand miss for a marked instruction. #1212,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3,The processor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss for a marked instruction. ##0E8140000001C142 The processor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss for a marked instruction. #1213,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3,The processor's data page table entry was reloaded from another core's L3 from a distant chip due to a demand miss for a marked instruction. ##0E8160000001C142 The processor's data page table entry was reloaded from another core's L3 from a distant chip due to a demand miss for a marked instruction. #1214,u,g,n,n,m,u,PM_MRK_INST_FROM_DL3_ALL,The processor's instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E8100000011C142 The processor's instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1215,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_ALL,The processor's instruction page table entry was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E8120000011C142 The processor's instruction page table entry was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1216,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_ALL,The processor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E8140000021C142 The processor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1217,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_ALL,The processor's data page table entry was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E8160000021C142 The processor's data page table entry was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1218,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. ##0E0220000001C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. #1219,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. ##0E0240000001C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. #1220,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. ##0E0260000001C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. #1221,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0220000011C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1222,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0240000021C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1223,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0260000021C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1224,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. ##0E4220000001C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. #1225,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. ##0E4240000001C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. #1226,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. ##0E4260000001C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. #1227,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E4220000011C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1228,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E4240000021C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1229,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E4260000021C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1230,u,g,n,n,m,u,PM_MRK_INST_FROM_DL2L3,The processor's instruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. ##0E0300000001C142 The processor's instruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. #1231,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. ##0E0320000001C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. #1232,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3,The processor's L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. ##0E0340000001C142 The processor's L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. #1233,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3,The processor's data page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. ##0E0360000001C142 The processor's data page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. #1234,u,g,n,n,m,u,PM_MRK_INST_FROM_DL2L3_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0300000011C142 The processor's instruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1235,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0320000011C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1236,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0340000021C142 The processor's L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1237,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0360000021C142 The processor's data page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1238,u,g,n,n,m,u,PM_MRK_INST_FROM_DMEM,The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss for a marked instruction. ##0F4100000001C142 The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss for a marked instruction. #1239,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DMEM,The processor's instruction page table entry was reloaded from distant memory (MC slow) due to a demand miss for a marked instruction. ##0F4020000001C142 The processor's instruction page table entry was reloaded from distant memory (MC slow) due to a demand miss for a marked instruction. #1240,u,g,n,n,m,u,PM_MRK_DATA_FROM_DMEM,The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss for a marked instruction. ##0F4040000001C142 The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss for a marked instruction. #1241,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DMEM,The processor's data page table entry was reloaded from distant memory (MC slow) due to a demand miss for a marked instruction. ##0F4060000001C142 The processor's data page table entry was reloaded from distant memory (MC slow) due to a demand miss for a marked instruction. #1242,u,g,n,n,m,u,PM_MRK_INST_FROM_DMEM_ALL,The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##0F4100000011C142 The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1243,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DMEM_ALL,The processor's instruction page table entry was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##0F4020000011C142 The processor's instruction page table entry was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1244,u,g,n,n,m,u,PM_MRK_DATA_FROM_DMEM_ALL,The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##0F4040000021C142 The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1245,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DMEM_ALL,The processor's data page table entry was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##0F4060000021C142 The processor's data page table entry was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1246,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_CACHE,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss for a marked instruction. ##0F8020000001C142 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss for a marked instruction. #1247,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_CACHE,The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache due to a demand miss for a marked instruction. ##0F8040000001C142 The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache due to a demand miss for a marked instruction. #1248,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_CACHE,The processor's data page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss for a marked instruction. ##0F8060000001C142 The processor's data page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss for a marked instruction. #1249,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_CACHE_ALL,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. ##0F8020000011C142 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. #1250,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_CACHE_ALL,The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. ##0F8040000021C142 The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. #1251,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_CACHE_ALL,The processor's data page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. ##0F8060000021C142 The processor's data page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. #1252,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_MEM,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss for a marked instruction. ##0FC020000001C142 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss for a marked instruction. #1253,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_MEM,The processor's L1 data cache was reloaded from a distant chip's OpenCapp memory due to a demand miss for a marked instruction. ##0FC040000001C142 The processor's L1 data cache was reloaded from a distant chip's OpenCapp memory due to a demand miss for a marked instruction. #1254,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_MEM,The processor's data page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss for a marked instruction. ##0FC060000001C142 The processor's data page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss for a marked instruction. #1255,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_MEM_ALL,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. ##0FC020000011C142 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. #1256,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_MEM_ALL,The processor's L1 data cache was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. ##0FC040000021C142 The processor's L1 data cache was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. #1257,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_MEM_ALL,The processor's data page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. ##0FC060000021C142 The processor's data page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. #1258,u,g,n,n,m,u,PM_MRK_INST_FROM_D_OC_ANY,The processor's instruction cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##0F8100000001C142 The processor's instruction cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1259,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_ANY,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##0F8120000001C142 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1260,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_ANY,The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##0F8140000001C142 The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1261,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_ANY,The processor's data page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##0F8160000001C142 The processor's data page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1262,u,g,n,n,m,u,PM_MRK_INST_FROM_D_OC_ANY_ALL,The processor's instruction cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##0F8100000011C142 The processor's instruction cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1263,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_ANY_ALL,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##0F8120000011C142 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1264,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_ANY_ALL,The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##0F8140000021C142 The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1265,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_ANY_ALL,The processor's data page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##0F8160000021C142 The processor's data page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1266,u,g,n,n,m,u,PM_MRK_INST_FROM_ONCHIP_CACHE,The processor's instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss for a marked instruction. ##080B00000001C142 The processor's instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss for a marked instruction. #1267,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_ONCHIP_CACHE,The processor's instruction page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss for a marked instruction. ##080B20000001C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss for a marked instruction. #1268,u,g,n,n,m,u,PM_MRK_DATA_FROM_ONCHIP_CACHE,The processor's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss for a marked instruction. ##080B40000001C142 The processor's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss for a marked instruction. #1269,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_ONCHIP_CACHE,The processor's data page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss for a marked instruction. ##080B60000001C142 The processor's data page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss for a marked instruction. #1270,u,g,n,n,m,u,PM_MRK_INST_FROM_ONCHIP_CACHE_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload for a marked instruction. ##080B00000011C142 The processor's instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload for a marked instruction. #1271,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_ONCHIP_CACHE_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload for a marked instruction. ##080B20000011C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload for a marked instruction. #1272,u,g,n,n,m,u,PM_MRK_DATA_FROM_ONCHIP_CACHE_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload for a marked instruction. ##080B40000021C142 The processor's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload for a marked instruction. #1273,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_ONCHIP_CACHE_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload for a marked instruction. ##080B60000021C142 The processor's data page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload for a marked instruction. #1274,u,g,n,n,m,u,PM_MRK_INST_FROM_OFFCHIP_CACHE,The processor's instruction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss for a marked instruction. ##0C0B00000001C142 The processor's instruction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss for a marked instruction. #1275,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_OFFCHIP_CACHE,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss for a marked instruction. ##0C0B20000001C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss for a marked instruction. #1276,u,g,n,n,m,u,PM_MRK_DATA_FROM_OFFCHIP_CACHE,The processor's L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss for a marked instruction. ##0C0B40000001C142 The processor's L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss for a marked instruction. #1277,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_OFFCHIP_CACHE,The processor's data page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss for a marked instruction. ##0C0B60000001C142 The processor's data page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss for a marked instruction. #1278,u,g,n,n,m,u,PM_MRK_INST_FROM_OFFCHIP_CACHE_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload for a marked instruction. ##0C0B00000011C142 The processor's instruction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload for a marked instruction. #1279,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_OFFCHIP_CACHE_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload for a marked instruction. ##0C0B20000011C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload for a marked instruction. #1280,u,g,n,n,m,u,PM_MRK_DATA_FROM_OFFCHIP_CACHE_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload for a marked instruction. ##0C0B40000021C142 The processor's L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload for a marked instruction. #1281,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_OFFCHIP_CACHE_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload for a marked instruction. ##0C0B60000021C142 The processor's data page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload for a marked instruction. #1282,u,g,n,n,m,u,PM_MRK_INST_FROM_ANY_MEMORY,The processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss for a marked instruction. ##095900000001C142 The processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss for a marked instruction. #1283,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_ANY_MEMORY,The processor's instruction page table entry was reloaded from any chip's memory (MC slow) due to a demand miss for a marked instruction. ##095820000001C142 The processor's instruction page table entry was reloaded from any chip's memory (MC slow) due to a demand miss for a marked instruction. #1284,u,g,n,n,m,u,PM_MRK_DATA_FROM_ANY_MEMORY,The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss for a marked instruction. ##095840000001C142 The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss for a marked instruction. #1285,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_ANY_MEMORY,The processor's data page table entry was reloaded from any chip's memory (MC slow) due to a demand miss for a marked instruction. ##095860000001C142 The processor's data page table entry was reloaded from any chip's memory (MC slow) due to a demand miss for a marked instruction. #1286,u,g,n,n,m,u,PM_MRK_INST_FROM_ANY_MEMORY_ALL,The processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##095900000011C142 The processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1287,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_ANY_MEMORY_ALL,The processor's instruction page table entry was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##095820000011C142 The processor's instruction page table entry was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1288,u,g,n,n,m,u,PM_MRK_DATA_FROM_ANY_MEMORY_ALL,The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##095840000021C142 The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1289,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_ANY_MEMORY_ALL,The processor's data page table entry was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##095860000021C142 The processor's data page table entry was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1290,u,g,n,n,m,u,PM_MRK_INST_FROM_L2_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local core's L2 due to a demand miss. Divide this count by PM_MRK_INST_FROM_L2 to obtain the average L2 latency for instruction reloads. ##000300000001C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local core's L2 due to a demand miss. Divide this count by PM_MRK_INST_FROM_L2 to obtain the average L2 latency for instruction reloads. #1291,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2 to obtain the average L2 latency for instruction page table reloads. ##000320000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2 to obtain the average L2 latency for instruction page table reloads. #1292,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2 to obtain the average L2 latency for data reloads. ##000340000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2 to obtain the average L2 latency for data reloads. #1293,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2 to obtain the average L2 latency for data page table reloads. ##000360000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2 to obtain the average L2 latency for data page table reloads. #1294,u,g,n,n,m,u,PM_MRK_INST_FROM_L2_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L2_ALL to obtain the average L2_ALL latency for instruction reloads. ##000300000011C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L2_ALL to obtain the average L2_ALL latency for instruction reloads. #1295,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2_ALL to obtain the average L2_ALL latency for instruction page table reloads. ##000320000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2_ALL to obtain the average L2_ALL latency for instruction page table reloads. #1296,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2_ALL to obtain the average L2_ALL latency for data reloads. ##000340000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2_ALL to obtain the average L2_ALL latency for data reloads. #1297,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2_ALL to obtain the average L2_ALL latency for data page table reloads. ##000360000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2_ALL to obtain the average L2_ALL latency for data page table reloads. #1298,u,g,n,n,m,u,PM_MRK_INST_FROM_L1MISS_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a source beyond the local core's L1 due to a demand miss. Divide this count by PM_MRK_INST_FROM_L1MISS to obtain the average L1MISS latency for instruction reloads. ##003F00000001C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a source beyond the local core's L1 due to a demand miss. Divide this count by PM_MRK_INST_FROM_L1MISS to obtain the average L1MISS latency for instruction reloads. #1299,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L1MISS_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a source beyond the local core's L1 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L1MISS to obtain the average L1MISS latency for instruction page table reloads. ##003F20000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a source beyond the local core's L1 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L1MISS to obtain the average L1MISS latency for instruction page table reloads. #1300,u,g,n,n,m,u,PM_MRK_DATA_FROM_L1MISS_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a source beyond the local core's L1 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L1MISS to obtain the average L1MISS latency for data reloads. ##003F40000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a source beyond the local core's L1 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L1MISS to obtain the average L1MISS latency for data reloads. #1301,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L1MISS_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a source beyond the local core's L1 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L1MISS to obtain the average L1MISS latency for data page table reloads. ##003F60000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a source beyond the local core's L1 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L1MISS to obtain the average L1MISS latency for data page table reloads. #1302,u,g,n,n,m,u,PM_MRK_INST_FROM_L1MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L1MISS_ALL to obtain the average L1MISS_ALL latency for instruction reloads. ##003F00000011C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L1MISS_ALL to obtain the average L1MISS_ALL latency for instruction reloads. #1303,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L1MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L1MISS_ALL to obtain the average L1MISS_ALL latency for instruction page table reloads. ##003F20000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L1MISS_ALL to obtain the average L1MISS_ALL latency for instruction page table reloads. #1304,u,g,n,n,m,u,PM_MRK_DATA_FROM_L1MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L1MISS_ALL to obtain the average L1MISS_ALL latency for data reloads. ##003F40000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L1MISS_ALL to obtain the average L1MISS_ALL latency for data reloads. #1305,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L1MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L1MISS_ALL to obtain the average L1MISS_ALL latency for data page table reloads. ##003F60000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L1MISS_ALL to obtain the average L1MISS_ALL latency for data page table reloads. #1306,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_NO_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2_NO_CONFLICT to obtain the average L2_NO_CONFLICT latency for instruction page table reloads. ##000020000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2_NO_CONFLICT to obtain the average L2_NO_CONFLICT latency for instruction page table reloads. #1307,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2_NO_CONFLICT to obtain the average L2_NO_CONFLICT latency for data reloads. ##000040000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2_NO_CONFLICT to obtain the average L2_NO_CONFLICT latency for data reloads. #1308,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_NO_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2_NO_CONFLICT to obtain the average L2_NO_CONFLICT latency for data page table reloads. ##000060000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2_NO_CONFLICT to obtain the average L2_NO_CONFLICT latency for data page table reloads. #1309,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_NO_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2_NO_CONFLICT_ALL to obtain the average L2_NO_CONFLICT_ALL latency for instruction page table reloads. ##000020000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2_NO_CONFLICT_ALL to obtain the average L2_NO_CONFLICT_ALL latency for instruction page table reloads. #1310,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_NO_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2_NO_CONFLICT_ALL to obtain the average L2_NO_CONFLICT_ALL latency for data reloads. ##000040000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2_NO_CONFLICT_ALL to obtain the average L2_NO_CONFLICT_ALL latency for data reloads. #1311,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_NO_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2_NO_CONFLICT_ALL to obtain the average L2_NO_CONFLICT_ALL latency for data page table reloads. ##000060000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2_NO_CONFLICT_ALL to obtain the average L2_NO_CONFLICT_ALL latency for data page table reloads. #1312,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_MEPF_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2_MEPF to obtain the average L2_MEPF latency for instruction page table reloads. ##004020000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2_MEPF to obtain the average L2_MEPF latency for instruction page table reloads. #1313,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_MEPF_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2_MEPF to obtain the average L2_MEPF latency for data reloads. ##004040000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2_MEPF to obtain the average L2_MEPF latency for data reloads. #1314,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_MEPF_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2_MEPF to obtain the average L2_MEPF latency for data page table reloads. ##004060000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2_MEPF to obtain the average L2_MEPF latency for data page table reloads. #1315,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_MEPF_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2_MEPF_ALL to obtain the average L2_MEPF_ALL latency for instruction page table reloads. ##004020000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2_MEPF_ALL to obtain the average L2_MEPF_ALL latency for instruction page table reloads. #1316,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_MEPF_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2_MEPF_ALL to obtain the average L2_MEPF_ALL latency for data reloads. ##004040000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2_MEPF_ALL to obtain the average L2_MEPF_ALL latency for data reloads. #1317,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_MEPF_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2_MEPF_ALL to obtain the average L2_MEPF_ALL latency for data page table reloads. ##004060000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2_MEPF_ALL to obtain the average L2_MEPF_ALL latency for data page table reloads. #1318,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_LDHITST_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2_LDHITST_CONFLICT to obtain the average L2_LDHITST_CONFLICT latency for instruction page table reloads. ##008020000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2_LDHITST_CONFLICT to obtain the average L2_LDHITST_CONFLICT latency for instruction page table reloads. #1319,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_LDHITST_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2_LDHITST_CONFLICT to obtain the average L2_LDHITST_CONFLICT latency for data reloads. ##008040000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2_LDHITST_CONFLICT to obtain the average L2_LDHITST_CONFLICT latency for data reloads. #1320,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_LDHITST_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2_LDHITST_CONFLICT to obtain the average L2_LDHITST_CONFLICT latency for data page table reloads. ##008060000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2_LDHITST_CONFLICT to obtain the average L2_LDHITST_CONFLICT latency for data page table reloads. #1321,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_LDHITST_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2_LDHITST_CONFLICT_ALL to obtain the average L2_LDHITST_CONFLICT_ALL latency for instruction page table reloads. ##008020000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2_LDHITST_CONFLICT_ALL to obtain the average L2_LDHITST_CONFLICT_ALL latency for instruction page table reloads. #1322,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_LDHITST_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2_LDHITST_CONFLICT_ALL to obtain the average L2_LDHITST_CONFLICT_ALL latency for data reloads. ##008040000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2_LDHITST_CONFLICT_ALL to obtain the average L2_LDHITST_CONFLICT_ALL latency for data reloads. #1323,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_LDHITST_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2_LDHITST_CONFLICT_ALL to obtain the average L2_LDHITST_CONFLICT_ALL latency for data page table reloads. ##008060000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2_LDHITST_CONFLICT_ALL to obtain the average L2_LDHITST_CONFLICT_ALL latency for data page table reloads. #1324,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_OTHER_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2_OTHER_CONFLICT to obtain the average L2_OTHER_CONFLICT latency for instruction page table reloads. ##00C020000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2_OTHER_CONFLICT to obtain the average L2_OTHER_CONFLICT latency for instruction page table reloads. #1325,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_OTHER_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2_OTHER_CONFLICT to obtain the average L2_OTHER_CONFLICT latency for data reloads. ##00C040000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2_OTHER_CONFLICT to obtain the average L2_OTHER_CONFLICT latency for data reloads. #1326,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_OTHER_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2_OTHER_CONFLICT to obtain the average L2_OTHER_CONFLICT latency for data page table reloads. ##00C060000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2_OTHER_CONFLICT to obtain the average L2_OTHER_CONFLICT latency for data page table reloads. #1327,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_OTHER_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2_OTHER_CONFLICT_ALL to obtain the average L2_OTHER_CONFLICT_ALL latency for instruction page table reloads. ##00C020000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2_OTHER_CONFLICT_ALL to obtain the average L2_OTHER_CONFLICT_ALL latency for instruction page table reloads. #1328,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_OTHER_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2_OTHER_CONFLICT_ALL to obtain the average L2_OTHER_CONFLICT_ALL latency for data reloads. ##00C040000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2_OTHER_CONFLICT_ALL to obtain the average L2_OTHER_CONFLICT_ALL latency for data reloads. #1329,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_OTHER_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2_OTHER_CONFLICT_ALL to obtain the average L2_OTHER_CONFLICT_ALL latency for data page table reloads. ##00C060000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2_OTHER_CONFLICT_ALL to obtain the average L2_OTHER_CONFLICT_ALL latency for data page table reloads. #1330,u,g,n,n,m,u,PM_MRK_INST_FROM_L2MISS_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a source beyond the local core's L2 due to a demand miss. Divide this count by PM_MRK_INST_FROM_L2MISS to obtain the average L2MISS latency for instruction reloads. ##000380000001C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a source beyond the local core's L2 due to a demand miss. Divide this count by PM_MRK_INST_FROM_L2MISS to obtain the average L2MISS latency for instruction reloads. #1331,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2MISS_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a source beyond the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2MISS to obtain the average L2MISS latency for instruction page table reloads. ##0003A0000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a source beyond the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2MISS to obtain the average L2MISS latency for instruction page table reloads. #1332,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2MISS_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a source beyond the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2MISS to obtain the average L2MISS latency for data reloads. ##0003C0000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a source beyond the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2MISS to obtain the average L2MISS latency for data reloads. #1333,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2MISS_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a source beyond the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2MISS to obtain the average L2MISS latency for data page table reloads. ##0003E0000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a source beyond the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2MISS to obtain the average L2MISS latency for data page table reloads. #1334,u,g,n,n,m,u,PM_MRK_INST_FROM_L2MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L2MISS_ALL to obtain the average L2MISS_ALL latency for instruction reloads. ##000380000011C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L2MISS_ALL to obtain the average L2MISS_ALL latency for instruction reloads. #1335,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2MISS_ALL to obtain the average L2MISS_ALL latency for instruction page table reloads. ##0003A0000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2MISS_ALL to obtain the average L2MISS_ALL latency for instruction page table reloads. #1336,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2MISS_ALL to obtain the average L2MISS_ALL latency for data reloads. ##0003C0000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2MISS_ALL to obtain the average L2MISS_ALL latency for data reloads. #1337,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2MISS_ALL to obtain the average L2MISS_ALL latency for data page table reloads. ##0003E0000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2MISS_ALL to obtain the average L2MISS_ALL latency for data page table reloads. #1338,u,g,n,n,m,u,PM_MRK_INST_FROM_L3_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_INST_FROM_L3 to obtain the average L3 latency for instruction reloads. ##010300000001C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_INST_FROM_L3 to obtain the average L3 latency for instruction reloads. #1339,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L3 to obtain the average L3 latency for instruction page table reloads. ##010320000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L3 to obtain the average L3 latency for instruction page table reloads. #1340,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L3 to obtain the average L3 latency for data reloads. ##010340000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L3 to obtain the average L3 latency for data reloads. #1341,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L3 to obtain the average L3 latency for data page table reloads. ##010360000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L3 to obtain the average L3 latency for data page table reloads. #1342,u,g,n,n,m,u,PM_MRK_INST_FROM_L3_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L3_ALL to obtain the average L3_ALL latency for instruction reloads. ##010300000011C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L3_ALL to obtain the average L3_ALL latency for instruction reloads. #1343,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L3_ALL to obtain the average L3_ALL latency for instruction page table reloads. ##010320000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L3_ALL to obtain the average L3_ALL latency for instruction page table reloads. #1344,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L3_ALL to obtain the average L3_ALL latency for data reloads. ##010340000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L3_ALL to obtain the average L3_ALL latency for data reloads. #1345,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L3_ALL to obtain the average L3_ALL latency for data page table reloads. ##010360000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L3_ALL to obtain the average L3_ALL latency for data page table reloads. #1346,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_NO_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L3_NO_CONFLICT to obtain the average L3_NO_CONFLICT latency for instruction page table reloads. ##010020000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L3_NO_CONFLICT to obtain the average L3_NO_CONFLICT latency for instruction page table reloads. #1347,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L3_NO_CONFLICT to obtain the average L3_NO_CONFLICT latency for data reloads. ##010040000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L3_NO_CONFLICT to obtain the average L3_NO_CONFLICT latency for data reloads. #1348,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_NO_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L3_NO_CONFLICT to obtain the average L3_NO_CONFLICT latency for data page table reloads. ##010060000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L3_NO_CONFLICT to obtain the average L3_NO_CONFLICT latency for data page table reloads. #1349,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_NO_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L3_NO_CONFLICT_ALL to obtain the average L3_NO_CONFLICT_ALL latency for instruction page table reloads. ##010020000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L3_NO_CONFLICT_ALL to obtain the average L3_NO_CONFLICT_ALL latency for instruction page table reloads. #1350,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_NO_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L3_NO_CONFLICT_ALL to obtain the average L3_NO_CONFLICT_ALL latency for data reloads. ##010040000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L3_NO_CONFLICT_ALL to obtain the average L3_NO_CONFLICT_ALL latency for data reloads. #1351,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_NO_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L3_NO_CONFLICT_ALL to obtain the average L3_NO_CONFLICT_ALL latency for data page table reloads. ##010060000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L3_NO_CONFLICT_ALL to obtain the average L3_NO_CONFLICT_ALL latency for data page table reloads. #1352,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_MEPF_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L3_MEPF to obtain the average L3_MEPF latency for instruction page table reloads. ##014020000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L3_MEPF to obtain the average L3_MEPF latency for instruction page table reloads. #1353,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_MEPF_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L3_MEPF to obtain the average L3_MEPF latency for data reloads. ##014040000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L3_MEPF to obtain the average L3_MEPF latency for data reloads. #1354,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_MEPF_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L3_MEPF to obtain the average L3_MEPF latency for data page table reloads. ##014060000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L3_MEPF to obtain the average L3_MEPF latency for data page table reloads. #1355,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_MEPF_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L3_MEPF_ALL to obtain the average L3_MEPF_ALL latency for instruction page table reloads. ##014020000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L3_MEPF_ALL to obtain the average L3_MEPF_ALL latency for instruction page table reloads. #1356,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_MEPF_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L3_MEPF_ALL to obtain the average L3_MEPF_ALL latency for data reloads. ##014040000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L3_MEPF_ALL to obtain the average L3_MEPF_ALL latency for data reloads. #1357,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_MEPF_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L3_MEPF_ALL to obtain the average L3_MEPF_ALL latency for data page table reloads. ##014060000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L3_MEPF_ALL to obtain the average L3_MEPF_ALL latency for data page table reloads. #1358,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L3_CONFLICT to obtain the average L3_CONFLICT latency for instruction page table reloads. ##01C020000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L3_CONFLICT to obtain the average L3_CONFLICT latency for instruction page table reloads. #1359,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L3_CONFLICT to obtain the average L3_CONFLICT latency for data reloads. ##01C040000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L3_CONFLICT to obtain the average L3_CONFLICT latency for data reloads. #1360,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L3_CONFLICT to obtain the average L3_CONFLICT latency for data page table reloads. ##01C060000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L3_CONFLICT to obtain the average L3_CONFLICT latency for data page table reloads. #1361,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L3_CONFLICT_ALL to obtain the average L3_CONFLICT_ALL latency for instruction page table reloads. ##01C020000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L3_CONFLICT_ALL to obtain the average L3_CONFLICT_ALL latency for instruction page table reloads. #1362,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L3_CONFLICT_ALL to obtain the average L3_CONFLICT_ALL latency for data reloads. ##01C040000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L3_CONFLICT_ALL to obtain the average L3_CONFLICT_ALL latency for data reloads. #1363,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L3_CONFLICT_ALL to obtain the average L3_CONFLICT_ALL latency for data page table reloads. ##01C060000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L3_CONFLICT_ALL to obtain the average L3_CONFLICT_ALL latency for data page table reloads. #1364,u,g,n,n,m,u,PM_MRK_INST_FROM_L3MISS_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from beyond the local core's L3 due to a demand miss. Divide this count by PM_MRK_INST_FROM_L3MISS to obtain the average L3MISS latency for instruction reloads. ##000780000001C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from beyond the local core's L3 due to a demand miss. Divide this count by PM_MRK_INST_FROM_L3MISS to obtain the average L3MISS latency for instruction reloads. #1365,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3MISS_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from beyond the local core's L3 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L3MISS to obtain the average L3MISS latency for instruction page table reloads. ##0007A0000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from beyond the local core's L3 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L3MISS to obtain the average L3MISS latency for instruction page table reloads. #1366,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3MISS_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from beyond the local core's L3 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L3MISS to obtain the average L3MISS latency for data reloads. ##0007C0000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from beyond the local core's L3 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L3MISS to obtain the average L3MISS latency for data reloads. #1367,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3MISS_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from beyond the local core's L3 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L3MISS to obtain the average L3MISS latency for data page table reloads. ##0007E0000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from beyond the local core's L3 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L3MISS to obtain the average L3MISS latency for data page table reloads. #1368,u,g,n,n,m,u,PM_MRK_INST_FROM_L3MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L3MISS_ALL to obtain the average L3MISS_ALL latency for instruction reloads. ##000780000011C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L3MISS_ALL to obtain the average L3MISS_ALL latency for instruction reloads. #1369,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L3MISS_ALL to obtain the average L3MISS_ALL latency for instruction page table reloads. ##0007A0000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L3MISS_ALL to obtain the average L3MISS_ALL latency for instruction page table reloads. #1370,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L3MISS_ALL to obtain the average L3MISS_ALL latency for data reloads. ##0007C0000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L3MISS_ALL to obtain the average L3MISS_ALL latency for data reloads. #1371,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L3MISS_ALL to obtain the average L3MISS_ALL latency for data page table reloads. ##0007E0000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L3MISS_ALL to obtain the average L3MISS_ALL latency for data page table reloads. #1372,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT_SHR to obtain the average L21_REGENT_SHR latency for instruction page table reloads. ##080020000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT_SHR to obtain the average L21_REGENT_SHR latency for instruction page table reloads. #1373,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_REGENT_SHR to obtain the average L21_REGENT_SHR latency for data reloads. ##080040000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_REGENT_SHR to obtain the average L21_REGENT_SHR latency for data reloads. #1374,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT_SHR to obtain the average L21_REGENT_SHR latency for data page table reloads. ##080060000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT_SHR to obtain the average L21_REGENT_SHR latency for data page table reloads. #1375,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT_SHR_ALL to obtain the average L21_REGENT_SHR_ALL latency for instruction page table reloads. ##080020000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT_SHR_ALL to obtain the average L21_REGENT_SHR_ALL latency for instruction page table reloads. #1376,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_REGENT_SHR_ALL to obtain the average L21_REGENT_SHR_ALL latency for data reloads. ##080040000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_REGENT_SHR_ALL to obtain the average L21_REGENT_SHR_ALL latency for data reloads. #1377,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT_SHR_ALL to obtain the average L21_REGENT_SHR_ALL latency for data page table reloads. ##080060000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT_SHR_ALL to obtain the average L21_REGENT_SHR_ALL latency for data page table reloads. #1378,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT_MOD to obtain the average L21_REGENT_MOD latency for instruction page table reloads. ##084020000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT_MOD to obtain the average L21_REGENT_MOD latency for instruction page table reloads. #1379,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_REGENT_MOD to obtain the average L21_REGENT_MOD latency for data reloads. ##084040000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_REGENT_MOD to obtain the average L21_REGENT_MOD latency for data reloads. #1380,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT_MOD to obtain the average L21_REGENT_MOD latency for data page table reloads. ##084060000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT_MOD to obtain the average L21_REGENT_MOD latency for data page table reloads. #1381,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT_MOD_ALL to obtain the average L21_REGENT_MOD_ALL latency for instruction page table reloads. ##084020000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT_MOD_ALL to obtain the average L21_REGENT_MOD_ALL latency for instruction page table reloads. #1382,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_REGENT_MOD_ALL to obtain the average L21_REGENT_MOD_ALL latency for data reloads. ##084040000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_REGENT_MOD_ALL to obtain the average L21_REGENT_MOD_ALL latency for data reloads. #1383,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT_MOD_ALL to obtain the average L21_REGENT_MOD_ALL latency for data page table reloads. ##084060000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT_MOD_ALL to obtain the average L21_REGENT_MOD_ALL latency for data page table reloads. #1384,u,g,n,n,m,u,PM_MRK_INST_FROM_L21_REGENT_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_L21_REGENT to obtain the average L21_REGENT latency for instruction reloads. ##080100000001C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_L21_REGENT to obtain the average L21_REGENT latency for instruction reloads. #1385,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT to obtain the average L21_REGENT latency for instruction page table reloads. ##080120000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT to obtain the average L21_REGENT latency for instruction page table reloads. #1386,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_REGENT to obtain the average L21_REGENT latency for data reloads. ##080140000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_REGENT to obtain the average L21_REGENT latency for data reloads. #1387,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT to obtain the average L21_REGENT latency for data page table reloads. ##080160000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT to obtain the average L21_REGENT latency for data page table reloads. #1388,u,g,n,n,m,u,PM_MRK_INST_FROM_L21_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L21_REGENT_ALL to obtain the average L21_REGENT_ALL latency for instruction reloads. ##080100000011C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L21_REGENT_ALL to obtain the average L21_REGENT_ALL latency for instruction reloads. #1389,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT_ALL to obtain the average L21_REGENT_ALL latency for instruction page table reloads. ##080120000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT_ALL to obtain the average L21_REGENT_ALL latency for instruction page table reloads. #1390,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_REGENT_ALL to obtain the average L21_REGENT_ALL latency for data reloads. ##080140000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_REGENT_ALL to obtain the average L21_REGENT_ALL latency for data reloads. #1391,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT_ALL to obtain the average L21_REGENT_ALL latency for data page table reloads. ##080160000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT_ALL to obtain the average L21_REGENT_ALL latency for data page table reloads. #1392,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT_SHR to obtain the average L31_REGENT_SHR latency for instruction page table reloads. ##088020000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT_SHR to obtain the average L31_REGENT_SHR latency for instruction page table reloads. #1393,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_REGENT_SHR to obtain the average L31_REGENT_SHR latency for data reloads. ##088040000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_REGENT_SHR to obtain the average L31_REGENT_SHR latency for data reloads. #1394,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT_SHR to obtain the average L31_REGENT_SHR latency for data page table reloads. ##088060000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT_SHR to obtain the average L31_REGENT_SHR latency for data page table reloads. #1395,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT_SHR_ALL to obtain the average L31_REGENT_SHR_ALL latency for instruction page table reloads. ##088020000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT_SHR_ALL to obtain the average L31_REGENT_SHR_ALL latency for instruction page table reloads. #1396,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_REGENT_SHR_ALL to obtain the average L31_REGENT_SHR_ALL latency for data reloads. ##088040000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_REGENT_SHR_ALL to obtain the average L31_REGENT_SHR_ALL latency for data reloads. #1397,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT_SHR_ALL to obtain the average L31_REGENT_SHR_ALL latency for data page table reloads. ##088060000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT_SHR_ALL to obtain the average L31_REGENT_SHR_ALL latency for data page table reloads. #1398,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT_MOD to obtain the average L31_REGENT_MOD latency for instruction page table reloads. ##08C020000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT_MOD to obtain the average L31_REGENT_MOD latency for instruction page table reloads. #1399,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_REGENT_MOD to obtain the average L31_REGENT_MOD latency for data reloads. ##08C040000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_REGENT_MOD to obtain the average L31_REGENT_MOD latency for data reloads. #1400,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT_MOD to obtain the average L31_REGENT_MOD latency for data page table reloads. ##08C060000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT_MOD to obtain the average L31_REGENT_MOD latency for data page table reloads. #1401,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT_MOD_ALL to obtain the average L31_REGENT_MOD_ALL latency for instruction page table reloads. ##08C020000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT_MOD_ALL to obtain the average L31_REGENT_MOD_ALL latency for instruction page table reloads. #1402,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_REGENT_MOD_ALL to obtain the average L31_REGENT_MOD_ALL latency for data reloads. ##08C040000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_REGENT_MOD_ALL to obtain the average L31_REGENT_MOD_ALL latency for data reloads. #1403,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT_MOD_ALL to obtain the average L31_REGENT_MOD_ALL latency for data page table reloads. ##08C060000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT_MOD_ALL to obtain the average L31_REGENT_MOD_ALL latency for data page table reloads. #1404,u,g,n,n,m,u,PM_MRK_INST_FROM_L31_REGENT_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_L31_REGENT to obtain the average L31_REGENT latency for instruction reloads. ##088100000001C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_L31_REGENT to obtain the average L31_REGENT latency for instruction reloads. #1405,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT to obtain the average L31_REGENT latency for instruction page table reloads. ##088120000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT to obtain the average L31_REGENT latency for instruction page table reloads. #1406,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_REGENT to obtain the average L31_REGENT latency for data reloads. ##088140000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_REGENT to obtain the average L31_REGENT latency for data reloads. #1407,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT to obtain the average L31_REGENT latency for data page table reloads. ##088160000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT to obtain the average L31_REGENT latency for data page table reloads. #1408,u,g,n,n,m,u,PM_MRK_INST_FROM_L31_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L31_REGENT_ALL to obtain the average L31_REGENT_ALL latency for instruction reloads. ##088100000011C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L31_REGENT_ALL to obtain the average L31_REGENT_ALL latency for instruction reloads. #1409,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT_ALL to obtain the average L31_REGENT_ALL latency for instruction page table reloads. ##088120000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT_ALL to obtain the average L31_REGENT_ALL latency for instruction page table reloads. #1410,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_REGENT_ALL to obtain the average L31_REGENT_ALL latency for data reloads. ##088140000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_REGENT_ALL to obtain the average L31_REGENT_ALL latency for data reloads. #1411,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT_ALL to obtain the average L31_REGENT_ALL latency for data page table reloads. ##088160000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT_ALL to obtain the average L31_REGENT_ALL latency for data page table reloads. #1412,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3_SHR to obtain the average REGENT_L2L3_SHR latency for instruction page table reloads. ##080220000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3_SHR to obtain the average REGENT_L2L3_SHR latency for instruction page table reloads. #1413,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3_SHR to obtain the average REGENT_L2L3_SHR latency for data reloads. ##080240000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3_SHR to obtain the average REGENT_L2L3_SHR latency for data reloads. #1414,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3_SHR to obtain the average REGENT_L2L3_SHR latency for data page table reloads. ##080260000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3_SHR to obtain the average REGENT_L2L3_SHR latency for data page table reloads. #1415,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3_SHR_ALL to obtain the average REGENT_L2L3_SHR_ALL latency for instruction page table reloads. ##080220000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3_SHR_ALL to obtain the average REGENT_L2L3_SHR_ALL latency for instruction page table reloads. #1416,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3_SHR_ALL to obtain the average REGENT_L2L3_SHR_ALL latency for data reloads. ##080240000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3_SHR_ALL to obtain the average REGENT_L2L3_SHR_ALL latency for data reloads. #1417,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3_SHR_ALL to obtain the average REGENT_L2L3_SHR_ALL latency for data page table reloads. ##080260000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3_SHR_ALL to obtain the average REGENT_L2L3_SHR_ALL latency for data page table reloads. #1418,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3_MOD to obtain the average REGENT_L2L3_MOD latency for instruction page table reloads. ##084220000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3_MOD to obtain the average REGENT_L2L3_MOD latency for instruction page table reloads. #1419,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3_MOD to obtain the average REGENT_L2L3_MOD latency for data reloads. ##084240000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3_MOD to obtain the average REGENT_L2L3_MOD latency for data reloads. #1420,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3_MOD to obtain the average REGENT_L2L3_MOD latency for data page table reloads. ##084260000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3_MOD to obtain the average REGENT_L2L3_MOD latency for data page table reloads. #1421,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3_MOD_ALL to obtain the average REGENT_L2L3_MOD_ALL latency for instruction page table reloads. ##084220000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3_MOD_ALL to obtain the average REGENT_L2L3_MOD_ALL latency for instruction page table reloads. #1422,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3_MOD_ALL to obtain the average REGENT_L2L3_MOD_ALL latency for data reloads. ##084240000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3_MOD_ALL to obtain the average REGENT_L2L3_MOD_ALL latency for data reloads. #1423,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3_MOD_ALL to obtain the average REGENT_L2L3_MOD_ALL latency for data page table reloads. ##084260000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3_MOD_ALL to obtain the average REGENT_L2L3_MOD_ALL latency for data page table reloads. #1424,u,g,n,n,m,u,PM_MRK_INST_FROM_REGENT_L2L3_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_REGENT_L2L3 to obtain the average REGENT_L2L3 latency for instruction reloads. ##080300000001C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_REGENT_L2L3 to obtain the average REGENT_L2L3 latency for instruction reloads. #1425,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3 to obtain the average REGENT_L2L3 latency for instruction page table reloads. ##080320000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3 to obtain the average REGENT_L2L3 latency for instruction page table reloads. #1426,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3 to obtain the average REGENT_L2L3 latency for data reloads. ##080340000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3 to obtain the average REGENT_L2L3 latency for data reloads. #1427,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3 to obtain the average REGENT_L2L3 latency for data page table reloads. ##080360000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3 to obtain the average REGENT_L2L3 latency for data page table reloads. #1428,u,g,n,n,m,u,PM_MRK_INST_FROM_REGENT_L2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_REGENT_L2L3_ALL to obtain the average REGENT_L2L3_ALL latency for instruction reloads. ##080300000011C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_REGENT_L2L3_ALL to obtain the average REGENT_L2L3_ALL latency for instruction reloads. #1429,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3_ALL to obtain the average REGENT_L2L3_ALL latency for instruction page table reloads. ##080320000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3_ALL to obtain the average REGENT_L2L3_ALL latency for instruction page table reloads. #1430,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3_ALL to obtain the average REGENT_L2L3_ALL latency for data reloads. ##080340000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3_ALL to obtain the average REGENT_L2L3_ALL latency for data reloads. #1431,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3_ALL to obtain the average REGENT_L2L3_ALL latency for data page table reloads. ##080360000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3_ALL to obtain the average REGENT_L2L3_ALL latency for data page table reloads. #1432,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT_SHR to obtain the average L21_NON_REGENT_SHR latency for instruction page table reloads. ##0A0020000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT_SHR to obtain the average L21_NON_REGENT_SHR latency for instruction page table reloads. #1433,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT_SHR to obtain the average L21_NON_REGENT_SHR latency for data reloads. ##0A0040000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT_SHR to obtain the average L21_NON_REGENT_SHR latency for data reloads. #1434,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT_SHR to obtain the average L21_NON_REGENT_SHR latency for data page table reloads. ##0A0060000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT_SHR to obtain the average L21_NON_REGENT_SHR latency for data page table reloads. #1435,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT_SHR_ALL to obtain the average L21_NON_REGENT_SHR_ALL latency for instruction page table reloads. ##0A0020000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT_SHR_ALL to obtain the average L21_NON_REGENT_SHR_ALL latency for instruction page table reloads. #1436,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT_SHR_ALL to obtain the average L21_NON_REGENT_SHR_ALL latency for data reloads. ##0A0040000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT_SHR_ALL to obtain the average L21_NON_REGENT_SHR_ALL latency for data reloads. #1437,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT_SHR_ALL to obtain the average L21_NON_REGENT_SHR_ALL latency for data page table reloads. ##0A0060000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT_SHR_ALL to obtain the average L21_NON_REGENT_SHR_ALL latency for data page table reloads. #1438,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT_MOD to obtain the average L21_NON_REGENT_MOD latency for instruction page table reloads. ##0A4020000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT_MOD to obtain the average L21_NON_REGENT_MOD latency for instruction page table reloads. #1439,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT_MOD to obtain the average L21_NON_REGENT_MOD latency for data reloads. ##0A4040000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT_MOD to obtain the average L21_NON_REGENT_MOD latency for data reloads. #1440,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT_MOD to obtain the average L21_NON_REGENT_MOD latency for data page table reloads. ##0A4060000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT_MOD to obtain the average L21_NON_REGENT_MOD latency for data page table reloads. #1441,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT_MOD_ALL to obtain the average L21_NON_REGENT_MOD_ALL latency for instruction page table reloads. ##0A4020000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT_MOD_ALL to obtain the average L21_NON_REGENT_MOD_ALL latency for instruction page table reloads. #1442,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT_MOD_ALL to obtain the average L21_NON_REGENT_MOD_ALL latency for data reloads. ##0A4040000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT_MOD_ALL to obtain the average L21_NON_REGENT_MOD_ALL latency for data reloads. #1443,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT_MOD_ALL to obtain the average L21_NON_REGENT_MOD_ALL latency for data page table reloads. ##0A4060000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT_MOD_ALL to obtain the average L21_NON_REGENT_MOD_ALL latency for data page table reloads. #1444,u,g,n,n,m,u,PM_MRK_INST_FROM_L21_NON_REGENT_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_L21_NON_REGENT to obtain the average L21_NON_REGENT latency for instruction reloads. ##0A0100000001C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_L21_NON_REGENT to obtain the average L21_NON_REGENT latency for instruction reloads. #1445,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT to obtain the average L21_NON_REGENT latency for instruction page table reloads. ##0A0120000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT to obtain the average L21_NON_REGENT latency for instruction page table reloads. #1446,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT to obtain the average L21_NON_REGENT latency for data reloads. ##0A0140000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT to obtain the average L21_NON_REGENT latency for data reloads. #1447,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT to obtain the average L21_NON_REGENT latency for data page table reloads. ##0A0160000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT to obtain the average L21_NON_REGENT latency for data page table reloads. #1448,u,g,n,n,m,u,PM_MRK_INST_FROM_L21_NON_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L21_NON_REGENT_ALL to obtain the average L21_NON_REGENT_ALL latency for instruction reloads. ##0A0100000011C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L21_NON_REGENT_ALL to obtain the average L21_NON_REGENT_ALL latency for instruction reloads. #1449,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT_ALL to obtain the average L21_NON_REGENT_ALL latency for instruction page table reloads. ##0A0120000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT_ALL to obtain the average L21_NON_REGENT_ALL latency for instruction page table reloads. #1450,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT_ALL to obtain the average L21_NON_REGENT_ALL latency for data reloads. ##0A0140000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT_ALL to obtain the average L21_NON_REGENT_ALL latency for data reloads. #1451,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT_ALL to obtain the average L21_NON_REGENT_ALL latency for data page table reloads. ##0A0160000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT_ALL to obtain the average L21_NON_REGENT_ALL latency for data page table reloads. #1452,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT_SHR to obtain the average L31_NON_REGENT_SHR latency for instruction page table reloads. ##0A8020000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT_SHR to obtain the average L31_NON_REGENT_SHR latency for instruction page table reloads. #1453,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT_SHR to obtain the average L31_NON_REGENT_SHR latency for data reloads. ##0A8040000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT_SHR to obtain the average L31_NON_REGENT_SHR latency for data reloads. #1454,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT_SHR to obtain the average L31_NON_REGENT_SHR latency for data page table reloads. ##0A8060000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT_SHR to obtain the average L31_NON_REGENT_SHR latency for data page table reloads. #1455,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT_SHR_ALL to obtain the average L31_NON_REGENT_SHR_ALL latency for instruction page table reloads. ##0A8020000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT_SHR_ALL to obtain the average L31_NON_REGENT_SHR_ALL latency for instruction page table reloads. #1456,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT_SHR_ALL to obtain the average L31_NON_REGENT_SHR_ALL latency for data reloads. ##0A8040000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT_SHR_ALL to obtain the average L31_NON_REGENT_SHR_ALL latency for data reloads. #1457,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT_SHR_ALL to obtain the average L31_NON_REGENT_SHR_ALL latency for data page table reloads. ##0A8060000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT_SHR_ALL to obtain the average L31_NON_REGENT_SHR_ALL latency for data page table reloads. #1458,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT_MOD to obtain the average L31_NON_REGENT_MOD latency for instruction page table reloads. ##0AC020000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT_MOD to obtain the average L31_NON_REGENT_MOD latency for instruction page table reloads. #1459,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT_MOD to obtain the average L31_NON_REGENT_MOD latency for data reloads. ##0AC040000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT_MOD to obtain the average L31_NON_REGENT_MOD latency for data reloads. #1460,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT_MOD to obtain the average L31_NON_REGENT_MOD latency for data page table reloads. ##0AC060000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT_MOD to obtain the average L31_NON_REGENT_MOD latency for data page table reloads. #1461,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT_MOD_ALL to obtain the average L31_NON_REGENT_MOD_ALL latency for instruction page table reloads. ##0AC020000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT_MOD_ALL to obtain the average L31_NON_REGENT_MOD_ALL latency for instruction page table reloads. #1462,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT_MOD_ALL to obtain the average L31_NON_REGENT_MOD_ALL latency for data reloads. ##0AC040000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT_MOD_ALL to obtain the average L31_NON_REGENT_MOD_ALL latency for data reloads. #1463,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT_MOD_ALL to obtain the average L31_NON_REGENT_MOD_ALL latency for data page table reloads. ##0AC060000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT_MOD_ALL to obtain the average L31_NON_REGENT_MOD_ALL latency for data page table reloads. #1464,u,g,n,n,m,u,PM_MRK_INST_FROM_L31_NON_REGENT_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_L31_NON_REGENT to obtain the average L31_NON_REGENT latency for instruction reloads. ##0A8100000001C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_L31_NON_REGENT to obtain the average L31_NON_REGENT latency for instruction reloads. #1465,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT to obtain the average L31_NON_REGENT latency for instruction page table reloads. ##0A8120000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT to obtain the average L31_NON_REGENT latency for instruction page table reloads. #1466,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT to obtain the average L31_NON_REGENT latency for data reloads. ##0A8140000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT to obtain the average L31_NON_REGENT latency for data reloads. #1467,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT to obtain the average L31_NON_REGENT latency for data page table reloads. ##0A8160000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT to obtain the average L31_NON_REGENT latency for data page table reloads. #1468,u,g,n,n,m,u,PM_MRK_INST_FROM_L31_NON_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L31_NON_REGENT_ALL to obtain the average L31_NON_REGENT_ALL latency for instruction reloads. ##0A8100000011C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L31_NON_REGENT_ALL to obtain the average L31_NON_REGENT_ALL latency for instruction reloads. #1469,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT_ALL to obtain the average L31_NON_REGENT_ALL latency for instruction page table reloads. ##0A8120000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT_ALL to obtain the average L31_NON_REGENT_ALL latency for instruction page table reloads. #1470,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT_ALL to obtain the average L31_NON_REGENT_ALL latency for data reloads. ##0A8140000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT_ALL to obtain the average L31_NON_REGENT_ALL latency for data reloads. #1471,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT_ALL to obtain the average L31_NON_REGENT_ALL latency for data page table reloads. ##0A8160000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT_ALL to obtain the average L31_NON_REGENT_ALL latency for data page table reloads. #1472,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_SHR to obtain the average NON_REGENT_L2L3_SHR latency for instruction page table reloads. ##0A0220000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_SHR to obtain the average NON_REGENT_L2L3_SHR latency for instruction page table reloads. #1473,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3_SHR to obtain the average NON_REGENT_L2L3_SHR latency for data reloads. ##0A0240000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3_SHR to obtain the average NON_REGENT_L2L3_SHR latency for data reloads. #1474,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_SHR to obtain the average NON_REGENT_L2L3_SHR latency for data page table reloads. ##0A0260000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_SHR to obtain the average NON_REGENT_L2L3_SHR latency for data page table reloads. #1475,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_SHR_ALL to obtain the average NON_REGENT_L2L3_SHR_ALL latency for instruction page table reloads. ##0A0220000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_SHR_ALL to obtain the average NON_REGENT_L2L3_SHR_ALL latency for instruction page table reloads. #1476,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3_SHR_ALL to obtain the average NON_REGENT_L2L3_SHR_ALL latency for data reloads. ##0A0240000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3_SHR_ALL to obtain the average NON_REGENT_L2L3_SHR_ALL latency for data reloads. #1477,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_SHR_ALL to obtain the average NON_REGENT_L2L3_SHR_ALL latency for data page table reloads. ##0A0260000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_SHR_ALL to obtain the average NON_REGENT_L2L3_SHR_ALL latency for data page table reloads. #1478,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_MOD to obtain the average NON_REGENT_L2L3_MOD latency for instruction page table reloads. ##0A4220000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_MOD to obtain the average NON_REGENT_L2L3_MOD latency for instruction page table reloads. #1479,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3_MOD to obtain the average NON_REGENT_L2L3_MOD latency for data reloads. ##0A4240000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3_MOD to obtain the average NON_REGENT_L2L3_MOD latency for data reloads. #1480,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_MOD to obtain the average NON_REGENT_L2L3_MOD latency for data page table reloads. ##0A4260000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_MOD to obtain the average NON_REGENT_L2L3_MOD latency for data page table reloads. #1481,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_MOD_ALL to obtain the average NON_REGENT_L2L3_MOD_ALL latency for instruction page table reloads. ##0A4220000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_MOD_ALL to obtain the average NON_REGENT_L2L3_MOD_ALL latency for instruction page table reloads. #1482,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3_MOD_ALL to obtain the average NON_REGENT_L2L3_MOD_ALL latency for data reloads. ##0A4240000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3_MOD_ALL to obtain the average NON_REGENT_L2L3_MOD_ALL latency for data reloads. #1483,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_MOD_ALL to obtain the average NON_REGENT_L2L3_MOD_ALL latency for data page table reloads. ##0A4260000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_MOD_ALL to obtain the average NON_REGENT_L2L3_MOD_ALL latency for data page table reloads. #1484,u,g,n,n,m,u,PM_MRK_INST_FROM_NON_REGENT_L2L3_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_NON_REGENT_L2L3 to obtain the average NON_REGENT_L2L3 latency for instruction reloads. ##0A0300000001C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_NON_REGENT_L2L3 to obtain the average NON_REGENT_L2L3 latency for instruction reloads. #1485,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3 to obtain the average NON_REGENT_L2L3 latency for instruction page table reloads. ##0A0320000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3 to obtain the average NON_REGENT_L2L3 latency for instruction page table reloads. #1486,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3 to obtain the average NON_REGENT_L2L3 latency for data reloads. ##0A0340000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3 to obtain the average NON_REGENT_L2L3 latency for data reloads. #1487,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3 to obtain the average NON_REGENT_L2L3 latency for data page table reloads. ##0A0360000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3 to obtain the average NON_REGENT_L2L3 latency for data page table reloads. #1488,u,g,n,n,m,u,PM_MRK_INST_FROM_NON_REGENT_L2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_NON_REGENT_L2L3_ALL to obtain the average NON_REGENT_L2L3_ALL latency for instruction reloads. ##0A0300000011C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_NON_REGENT_L2L3_ALL to obtain the average NON_REGENT_L2L3_ALL latency for instruction reloads. #1489,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_ALL to obtain the average NON_REGENT_L2L3_ALL latency for instruction page table reloads. ##0A0320000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_ALL to obtain the average NON_REGENT_L2L3_ALL latency for instruction page table reloads. #1490,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3_ALL to obtain the average NON_REGENT_L2L3_ALL latency for data reloads. ##0A0340000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3_ALL to obtain the average NON_REGENT_L2L3_ALL latency for data reloads. #1491,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_ALL to obtain the average NON_REGENT_L2L3_ALL latency for data page table reloads. ##0A0360000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_ALL to obtain the average NON_REGENT_L2L3_ALL latency for data page table reloads. #1492,u,g,n,n,m,u,PM_MRK_INST_FROM_LMEM_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local chip's memory due to a demand miss. Divide this count by PM_MRK_INST_FROM_LMEM to obtain the average LMEM latency for instruction reloads. ##094100000001C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local chip's memory due to a demand miss. Divide this count by PM_MRK_INST_FROM_LMEM to obtain the average LMEM latency for instruction reloads. #1493,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_LMEM_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_LMEM to obtain the average LMEM latency for instruction page table reloads. ##094020000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_LMEM to obtain the average LMEM latency for instruction page table reloads. #1494,u,g,n,n,m,u,PM_MRK_DATA_FROM_LMEM_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_LMEM to obtain the average LMEM latency for data reloads. ##094040000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_LMEM to obtain the average LMEM latency for data reloads. #1495,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_LMEM_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_LMEM to obtain the average LMEM latency for data page table reloads. ##094060000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_LMEM to obtain the average LMEM latency for data page table reloads. #1496,u,g,n,n,m,u,PM_MRK_INST_FROM_LMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local chip's memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_LMEM_ALL to obtain the average LMEM_ALL latency for instruction reloads. ##094100000011C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local chip's memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_LMEM_ALL to obtain the average LMEM_ALL latency for instruction reloads. #1497,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_LMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_LMEM_ALL to obtain the average LMEM_ALL latency for instruction page table reloads. ##094020000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_LMEM_ALL to obtain the average LMEM_ALL latency for instruction page table reloads. #1498,u,g,n,n,m,u,PM_MRK_DATA_FROM_LMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_LMEM_ALL to obtain the average LMEM_ALL latency for data reloads. ##094040000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_LMEM_ALL to obtain the average LMEM_ALL latency for data reloads. #1499,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_LMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_LMEM_ALL to obtain the average LMEM_ALL latency for data page table reloads. ##094060000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_LMEM_ALL to obtain the average LMEM_ALL latency for data page table reloads. #1500,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_CACHE_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L_OC_CACHE to obtain the average L_OC_CACHE latency for instruction page table reloads. ##098020000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L_OC_CACHE to obtain the average L_OC_CACHE latency for instruction page table reloads. #1501,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_CACHE_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L_OC_CACHE to obtain the average L_OC_CACHE latency for data reloads. ##098040000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L_OC_CACHE to obtain the average L_OC_CACHE latency for data reloads. #1502,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_CACHE_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L_OC_CACHE to obtain the average L_OC_CACHE latency for data page table reloads. ##098060000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L_OC_CACHE to obtain the average L_OC_CACHE latency for data page table reloads. #1503,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L_OC_CACHE_ALL to obtain the average L_OC_CACHE_ALL latency for instruction page table reloads. ##098020000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L_OC_CACHE_ALL to obtain the average L_OC_CACHE_ALL latency for instruction page table reloads. #1504,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L_OC_CACHE_ALL to obtain the average L_OC_CACHE_ALL latency for data reloads. ##098040000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L_OC_CACHE_ALL to obtain the average L_OC_CACHE_ALL latency for data reloads. #1505,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L_OC_CACHE_ALL to obtain the average L_OC_CACHE_ALL latency for data page table reloads. ##098060000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L_OC_CACHE_ALL to obtain the average L_OC_CACHE_ALL latency for data page table reloads. #1506,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_MEM_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L_OC_MEM to obtain the average L_OC_MEM latency for instruction page table reloads. ##09C020000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L_OC_MEM to obtain the average L_OC_MEM latency for instruction page table reloads. #1507,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_MEM_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L_OC_MEM to obtain the average L_OC_MEM latency for data reloads. ##09C040000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L_OC_MEM to obtain the average L_OC_MEM latency for data reloads. #1508,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_MEM_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L_OC_MEM to obtain the average L_OC_MEM latency for data page table reloads. ##09C060000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L_OC_MEM to obtain the average L_OC_MEM latency for data page table reloads. #1509,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_MEM_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L_OC_MEM_ALL to obtain the average L_OC_MEM_ALL latency for instruction page table reloads. ##09C020000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L_OC_MEM_ALL to obtain the average L_OC_MEM_ALL latency for instruction page table reloads. #1510,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_MEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L_OC_MEM_ALL to obtain the average L_OC_MEM_ALL latency for data reloads. ##09C040000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L_OC_MEM_ALL to obtain the average L_OC_MEM_ALL latency for data reloads. #1511,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_MEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L_OC_MEM_ALL to obtain the average L_OC_MEM_ALL latency for data page table reloads. ##09C060000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L_OC_MEM_ALL to obtain the average L_OC_MEM_ALL latency for data page table reloads. #1512,u,g,n,n,m,u,PM_MRK_INST_FROM_L_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_INST_FROM_L_OC_ANY to obtain the average L_OC_ANY latency for instruction reloads. ##098100000001C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_INST_FROM_L_OC_ANY to obtain the average L_OC_ANY latency for instruction reloads. #1513,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L_OC_ANY to obtain the average L_OC_ANY latency for instruction page table reloads. ##098120000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L_OC_ANY to obtain the average L_OC_ANY latency for instruction page table reloads. #1514,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L_OC_ANY to obtain the average L_OC_ANY latency for data reloads. ##098140000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L_OC_ANY to obtain the average L_OC_ANY latency for data reloads. #1515,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L_OC_ANY to obtain the average L_OC_ANY latency for data page table reloads. ##098160000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L_OC_ANY to obtain the average L_OC_ANY latency for data page table reloads. #1516,u,g,n,n,m,u,PM_MRK_INST_FROM_L_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L_OC_ANY_ALL to obtain the average L_OC_ANY_ALL latency for instruction reloads. ##098100000011C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L_OC_ANY_ALL to obtain the average L_OC_ANY_ALL latency for instruction reloads. #1517,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L_OC_ANY_ALL to obtain the average L_OC_ANY_ALL latency for instruction page table reloads. ##098120000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L_OC_ANY_ALL to obtain the average L_OC_ANY_ALL latency for instruction page table reloads. #1518,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L_OC_ANY_ALL to obtain the average L_OC_ANY_ALL latency for data reloads. ##098140000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L_OC_ANY_ALL to obtain the average L_OC_ANY_ALL latency for data reloads. #1519,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L_OC_ANY_ALL to obtain the average L_OC_ANY_ALL latency for data page table reloads. ##098160000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L_OC_ANY_ALL to obtain the average L_OC_ANY_ALL latency for data page table reloads. #1520,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2_SHR to obtain the average RL2_SHR latency for instruction page table reloads. ##0C0020000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2_SHR to obtain the average RL2_SHR latency for instruction page table reloads. #1521,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2_SHR to obtain the average RL2_SHR latency for data reloads. ##0C0040000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2_SHR to obtain the average RL2_SHR latency for data reloads. #1522,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2_SHR to obtain the average RL2_SHR latency for data page table reloads. ##0C0060000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2_SHR to obtain the average RL2_SHR latency for data page table reloads. #1523,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2_SHR_ALL to obtain the average RL2_SHR_ALL latency for instruction page table reloads. ##0C0020000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2_SHR_ALL to obtain the average RL2_SHR_ALL latency for instruction page table reloads. #1524,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2_SHR_ALL to obtain the average RL2_SHR_ALL latency for data reloads. ##0C0040000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2_SHR_ALL to obtain the average RL2_SHR_ALL latency for data reloads. #1525,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2_SHR_ALL to obtain the average RL2_SHR_ALL latency for data page table reloads. ##0C0060000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2_SHR_ALL to obtain the average RL2_SHR_ALL latency for data page table reloads. #1526,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2_MOD to obtain the average RL2_MOD latency for instruction page table reloads. ##0C4020000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2_MOD to obtain the average RL2_MOD latency for instruction page table reloads. #1527,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2_MOD to obtain the average RL2_MOD latency for data reloads. ##0C4040000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2_MOD to obtain the average RL2_MOD latency for data reloads. #1528,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2_MOD to obtain the average RL2_MOD latency for data page table reloads. ##0C4060000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2_MOD to obtain the average RL2_MOD latency for data page table reloads. #1529,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2_MOD_ALL to obtain the average RL2_MOD_ALL latency for instruction page table reloads. ##0C4020000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2_MOD_ALL to obtain the average RL2_MOD_ALL latency for instruction page table reloads. #1530,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2_MOD_ALL to obtain the average RL2_MOD_ALL latency for data reloads. ##0C4040000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2_MOD_ALL to obtain the average RL2_MOD_ALL latency for data reloads. #1531,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2_MOD_ALL to obtain the average RL2_MOD_ALL latency for data page table reloads. ##0C4060000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2_MOD_ALL to obtain the average RL2_MOD_ALL latency for data page table reloads. #1532,u,g,n,n,m,u,PM_MRK_INST_FROM_RL2_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_RL2 to obtain the average RL2 latency for instruction reloads. ##0C0100000001C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_RL2 to obtain the average RL2 latency for instruction reloads. #1533,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2 to obtain the average RL2 latency for instruction page table reloads. ##0C0120000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2 to obtain the average RL2 latency for instruction page table reloads. #1534,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2 to obtain the average RL2 latency for data reloads. ##0C0140000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2 to obtain the average RL2 latency for data reloads. #1535,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2 to obtain the average RL2 latency for data page table reloads. ##0C0160000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2 to obtain the average RL2 latency for data page table reloads. #1536,u,g,n,n,m,u,PM_MRK_INST_FROM_RL2_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_RL2_ALL to obtain the average RL2_ALL latency for instruction reloads. ##0C0100000011C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_RL2_ALL to obtain the average RL2_ALL latency for instruction reloads. #1537,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2_ALL to obtain the average RL2_ALL latency for instruction page table reloads. ##0C0120000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2_ALL to obtain the average RL2_ALL latency for instruction page table reloads. #1538,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2_ALL to obtain the average RL2_ALL latency for data reloads. ##0C0140000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2_ALL to obtain the average RL2_ALL latency for data reloads. #1539,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2_ALL to obtain the average RL2_ALL latency for data page table reloads. ##0C0160000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2_ALL to obtain the average RL2_ALL latency for data page table reloads. #1540,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL3_SHR to obtain the average RL3_SHR latency for instruction page table reloads. ##0C8020000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL3_SHR to obtain the average RL3_SHR latency for instruction page table reloads. #1541,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL3_SHR to obtain the average RL3_SHR latency for data reloads. ##0C8040000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL3_SHR to obtain the average RL3_SHR latency for data reloads. #1542,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL3_SHR to obtain the average RL3_SHR latency for data page table reloads. ##0C8060000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL3_SHR to obtain the average RL3_SHR latency for data page table reloads. #1543,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL3_SHR_ALL to obtain the average RL3_SHR_ALL latency for instruction page table reloads. ##0C8020000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL3_SHR_ALL to obtain the average RL3_SHR_ALL latency for instruction page table reloads. #1544,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL3_SHR_ALL to obtain the average RL3_SHR_ALL latency for data reloads. ##0C8040000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL3_SHR_ALL to obtain the average RL3_SHR_ALL latency for data reloads. #1545,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL3_SHR_ALL to obtain the average RL3_SHR_ALL latency for data page table reloads. ##0C8060000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL3_SHR_ALL to obtain the average RL3_SHR_ALL latency for data page table reloads. #1546,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL3_MOD to obtain the average RL3_MOD latency for instruction page table reloads. ##0CC020000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL3_MOD to obtain the average RL3_MOD latency for instruction page table reloads. #1547,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL3_MOD to obtain the average RL3_MOD latency for data reloads. ##0CC040000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL3_MOD to obtain the average RL3_MOD latency for data reloads. #1548,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL3_MOD to obtain the average RL3_MOD latency for data page table reloads. ##0CC060000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL3_MOD to obtain the average RL3_MOD latency for data page table reloads. #1549,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL3_MOD_ALL to obtain the average RL3_MOD_ALL latency for instruction page table reloads. ##0CC020000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL3_MOD_ALL to obtain the average RL3_MOD_ALL latency for instruction page table reloads. #1550,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL3_MOD_ALL to obtain the average RL3_MOD_ALL latency for data reloads. ##0CC040000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL3_MOD_ALL to obtain the average RL3_MOD_ALL latency for data reloads. #1551,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL3_MOD_ALL to obtain the average RL3_MOD_ALL latency for data page table reloads. ##0CC060000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL3_MOD_ALL to obtain the average RL3_MOD_ALL latency for data page table reloads. #1552,u,g,n,n,m,u,PM_MRK_INST_FROM_RL3_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_RL3 to obtain the average RL3 latency for instruction reloads. ##0C8100000001C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_RL3 to obtain the average RL3 latency for instruction reloads. #1553,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL3 to obtain the average RL3 latency for instruction page table reloads. ##0C8120000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL3 to obtain the average RL3 latency for instruction page table reloads. #1554,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL3 to obtain the average RL3 latency for data reloads. ##0C8140000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL3 to obtain the average RL3 latency for data reloads. #1555,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL3 to obtain the average RL3 latency for data page table reloads. ##0C8160000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL3 to obtain the average RL3 latency for data page table reloads. #1556,u,g,n,n,m,u,PM_MRK_INST_FROM_RL3_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_RL3_ALL to obtain the average RL3_ALL latency for instruction reloads. ##0C8100000011C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_RL3_ALL to obtain the average RL3_ALL latency for instruction reloads. #1557,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL3_ALL to obtain the average RL3_ALL latency for instruction page table reloads. ##0C8120000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL3_ALL to obtain the average RL3_ALL latency for instruction page table reloads. #1558,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL3_ALL to obtain the average RL3_ALL latency for data reloads. ##0C8140000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL3_ALL to obtain the average RL3_ALL latency for data reloads. #1559,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL3_ALL to obtain the average RL3_ALL latency for data page table reloads. ##0C8160000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL3_ALL to obtain the average RL3_ALL latency for data page table reloads. #1560,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2L3_SHR to obtain the average RL2L3_SHR latency for instruction page table reloads. ##0C0220000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2L3_SHR to obtain the average RL2L3_SHR latency for instruction page table reloads. #1561,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2L3_SHR to obtain the average RL2L3_SHR latency for data reloads. ##0C0240000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2L3_SHR to obtain the average RL2L3_SHR latency for data reloads. #1562,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2L3_SHR to obtain the average RL2L3_SHR latency for data page table reloads. ##0C0260000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2L3_SHR to obtain the average RL2L3_SHR latency for data page table reloads. #1563,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2L3_SHR_ALL to obtain the average RL2L3_SHR_ALL latency for instruction page table reloads. ##0C0220000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2L3_SHR_ALL to obtain the average RL2L3_SHR_ALL latency for instruction page table reloads. #1564,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2L3_SHR_ALL to obtain the average RL2L3_SHR_ALL latency for data reloads. ##0C0240000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2L3_SHR_ALL to obtain the average RL2L3_SHR_ALL latency for data reloads. #1565,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2L3_SHR_ALL to obtain the average RL2L3_SHR_ALL latency for data page table reloads. ##0C0260000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2L3_SHR_ALL to obtain the average RL2L3_SHR_ALL latency for data page table reloads. #1566,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2L3_MOD to obtain the average RL2L3_MOD latency for instruction page table reloads. ##0C4220000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2L3_MOD to obtain the average RL2L3_MOD latency for instruction page table reloads. #1567,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2L3_MOD to obtain the average RL2L3_MOD latency for data reloads. ##0C4240000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2L3_MOD to obtain the average RL2L3_MOD latency for data reloads. #1568,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2L3_MOD to obtain the average RL2L3_MOD latency for data page table reloads. ##0C4260000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2L3_MOD to obtain the average RL2L3_MOD latency for data page table reloads. #1569,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2L3_MOD_ALL to obtain the average RL2L3_MOD_ALL latency for instruction page table reloads. ##0C4220000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2L3_MOD_ALL to obtain the average RL2L3_MOD_ALL latency for instruction page table reloads. #1570,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2L3_MOD_ALL to obtain the average RL2L3_MOD_ALL latency for data reloads. ##0C4240000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2L3_MOD_ALL to obtain the average RL2L3_MOD_ALL latency for data reloads. #1571,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2L3_MOD_ALL to obtain the average RL2L3_MOD_ALL latency for data page table reloads. ##0C4260000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2L3_MOD_ALL to obtain the average RL2L3_MOD_ALL latency for data page table reloads. #1572,u,g,n,n,m,u,PM_MRK_INST_FROM_RL2L3_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_RL2L3 to obtain the average RL2L3 latency for instruction reloads. ##0C0300000001C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_RL2L3 to obtain the average RL2L3 latency for instruction reloads. #1573,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2L3 to obtain the average RL2L3 latency for instruction page table reloads. ##0C0320000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2L3 to obtain the average RL2L3 latency for instruction page table reloads. #1574,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2L3 to obtain the average RL2L3 latency for data reloads. ##0C0340000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2L3 to obtain the average RL2L3 latency for data reloads. #1575,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2L3 to obtain the average RL2L3 latency for data page table reloads. ##0C0360000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2L3 to obtain the average RL2L3 latency for data page table reloads. #1576,u,g,n,n,m,u,PM_MRK_INST_FROM_RL2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_RL2L3_ALL to obtain the average RL2L3_ALL latency for instruction reloads. ##0C0300000011C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_RL2L3_ALL to obtain the average RL2L3_ALL latency for instruction reloads. #1577,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2L3_ALL to obtain the average RL2L3_ALL latency for instruction page table reloads. ##0C0320000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2L3_ALL to obtain the average RL2L3_ALL latency for instruction page table reloads. #1578,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2L3_ALL to obtain the average RL2L3_ALL latency for data reloads. ##0C0340000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2L3_ALL to obtain the average RL2L3_ALL latency for data reloads. #1579,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2L3_ALL to obtain the average RL2L3_ALL latency for data page table reloads. ##0C0360000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2L3_ALL to obtain the average RL2L3_ALL latency for data page table reloads. #1580,u,g,n,n,m,u,PM_MRK_INST_FROM_RMEM_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from remote memory (MC slow) due to a demand miss. Divide this count by PM_MRK_INST_FROM_RMEM to obtain the average RMEM latency for instruction reloads. ##0D4100000001C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from remote memory (MC slow) due to a demand miss. Divide this count by PM_MRK_INST_FROM_RMEM to obtain the average RMEM latency for instruction reloads. #1581,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RMEM_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from remote memory (MC slow) due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RMEM to obtain the average RMEM latency for instruction page table reloads. ##0D4020000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from remote memory (MC slow) due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RMEM to obtain the average RMEM latency for instruction page table reloads. #1582,u,g,n,n,m,u,PM_MRK_DATA_FROM_RMEM_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from remote memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RMEM to obtain the average RMEM latency for data reloads. ##0D4040000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from remote memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RMEM to obtain the average RMEM latency for data reloads. #1583,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RMEM_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from remote memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RMEM to obtain the average RMEM latency for data page table reloads. ##0D4060000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from remote memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RMEM to obtain the average RMEM latency for data page table reloads. #1584,u,g,n,n,m,u,PM_MRK_INST_FROM_RMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_RMEM_ALL to obtain the average RMEM_ALL latency for instruction reloads. ##0D4100000011C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_RMEM_ALL to obtain the average RMEM_ALL latency for instruction reloads. #1585,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RMEM_ALL to obtain the average RMEM_ALL latency for instruction page table reloads. ##0D4020000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RMEM_ALL to obtain the average RMEM_ALL latency for instruction page table reloads. #1586,u,g,n,n,m,u,PM_MRK_DATA_FROM_RMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RMEM_ALL to obtain the average RMEM_ALL latency for data reloads. ##0D4040000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RMEM_ALL to obtain the average RMEM_ALL latency for data reloads. #1587,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RMEM_ALL to obtain the average RMEM_ALL latency for data page table reloads. ##0D4060000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RMEM_ALL to obtain the average RMEM_ALL latency for data page table reloads. #1588,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_CACHE_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_R_OC_CACHE to obtain the average R_OC_CACHE latency for instruction page table reloads. ##0D8020000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_R_OC_CACHE to obtain the average R_OC_CACHE latency for instruction page table reloads. #1589,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_CACHE_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DATA_FROM_R_OC_CACHE to obtain the average R_OC_CACHE latency for data reloads. ##0D8040000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DATA_FROM_R_OC_CACHE to obtain the average R_OC_CACHE latency for data reloads. #1590,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_CACHE_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_R_OC_CACHE to obtain the average R_OC_CACHE latency for data page table reloads. ##0D8060000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_R_OC_CACHE to obtain the average R_OC_CACHE latency for data page table reloads. #1591,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_R_OC_CACHE_ALL to obtain the average R_OC_CACHE_ALL latency for instruction page table reloads. ##0D8020000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_R_OC_CACHE_ALL to obtain the average R_OC_CACHE_ALL latency for instruction page table reloads. #1592,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_R_OC_CACHE_ALL to obtain the average R_OC_CACHE_ALL latency for data reloads. ##0D8040000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_R_OC_CACHE_ALL to obtain the average R_OC_CACHE_ALL latency for data reloads. #1593,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_R_OC_CACHE_ALL to obtain the average R_OC_CACHE_ALL latency for data page table reloads. ##0D8060000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_R_OC_CACHE_ALL to obtain the average R_OC_CACHE_ALL latency for data page table reloads. #1594,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_MEM_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_R_OC_MEM to obtain the average R_OC_MEM latency for instruction page table reloads. ##0DC020000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_R_OC_MEM to obtain the average R_OC_MEM latency for instruction page table reloads. #1595,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_MEM_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_R_OC_MEM to obtain the average R_OC_MEM latency for data reloads. ##0DC040000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_R_OC_MEM to obtain the average R_OC_MEM latency for data reloads. #1596,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_MEM_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_R_OC_MEM to obtain the average R_OC_MEM latency for data page table reloads. ##0DC060000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_R_OC_MEM to obtain the average R_OC_MEM latency for data page table reloads. #1597,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_MEM_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_R_OC_MEM_ALL to obtain the average R_OC_MEM_ALL latency for instruction page table reloads. ##0DC020000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_R_OC_MEM_ALL to obtain the average R_OC_MEM_ALL latency for instruction page table reloads. #1598,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_MEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_R_OC_MEM_ALL to obtain the average R_OC_MEM_ALL latency for data reloads. ##0DC040000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_R_OC_MEM_ALL to obtain the average R_OC_MEM_ALL latency for data reloads. #1599,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_MEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_R_OC_MEM_ALL to obtain the average R_OC_MEM_ALL latency for data page table reloads. ##0DC060000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_R_OC_MEM_ALL to obtain the average R_OC_MEM_ALL latency for data page table reloads. #1600,u,g,n,n,m,u,PM_MRK_INST_FROM_R_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_INST_FROM_R_OC_ANY to obtain the average R_OC_ANY latency for instruction reloads. ##0D8100000001C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_INST_FROM_R_OC_ANY to obtain the average R_OC_ANY latency for instruction reloads. #1601,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_R_OC_ANY to obtain the average R_OC_ANY latency for instruction page table reloads. ##0D8120000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_R_OC_ANY to obtain the average R_OC_ANY latency for instruction page table reloads. #1602,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_R_OC_ANY to obtain the average R_OC_ANY latency for data reloads. ##0D8140000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_R_OC_ANY to obtain the average R_OC_ANY latency for data reloads. #1603,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_R_OC_ANY to obtain the average R_OC_ANY latency for data page table reloads. ##0D8160000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_R_OC_ANY to obtain the average R_OC_ANY latency for data page table reloads. #1604,u,g,n,n,m,u,PM_MRK_INST_FROM_R_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_R_OC_ANY_ALL to obtain the average R_OC_ANY_ALL latency for instruction reloads. ##0D8100000011C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_R_OC_ANY_ALL to obtain the average R_OC_ANY_ALL latency for instruction reloads. #1605,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_R_OC_ANY_ALL to obtain the average R_OC_ANY_ALL latency for instruction page table reloads. ##0D8120000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_R_OC_ANY_ALL to obtain the average R_OC_ANY_ALL latency for instruction page table reloads. #1606,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_R_OC_ANY_ALL to obtain the average R_OC_ANY_ALL latency for data reloads. ##0D8140000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_R_OC_ANY_ALL to obtain the average R_OC_ANY_ALL latency for data reloads. #1607,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_R_OC_ANY_ALL to obtain the average R_OC_ANY_ALL latency for data page table reloads. ##0D8160000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_R_OC_ANY_ALL to obtain the average R_OC_ANY_ALL latency for data page table reloads. #1608,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2_SHR to obtain the average DL2_SHR latency for instruction page table reloads. ##0E0020000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2_SHR to obtain the average DL2_SHR latency for instruction page table reloads. #1609,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2_SHR to obtain the average DL2_SHR latency for data reloads. ##0E0040000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2_SHR to obtain the average DL2_SHR latency for data reloads. #1610,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2_SHR to obtain the average DL2_SHR latency for data page table reloads. ##0E0060000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2_SHR to obtain the average DL2_SHR latency for data page table reloads. #1611,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2_SHR_ALL to obtain the average DL2_SHR_ALL latency for instruction page table reloads. ##0E0020000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2_SHR_ALL to obtain the average DL2_SHR_ALL latency for instruction page table reloads. #1612,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2_SHR_ALL to obtain the average DL2_SHR_ALL latency for data reloads. ##0E0040000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2_SHR_ALL to obtain the average DL2_SHR_ALL latency for data reloads. #1613,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2_SHR_ALL to obtain the average DL2_SHR_ALL latency for data page table reloads. ##0E0060000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2_SHR_ALL to obtain the average DL2_SHR_ALL latency for data page table reloads. #1614,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2_MOD to obtain the average DL2_MOD latency for instruction page table reloads. ##0E4020000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2_MOD to obtain the average DL2_MOD latency for instruction page table reloads. #1615,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2_MOD to obtain the average DL2_MOD latency for data reloads. ##0E4040000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2_MOD to obtain the average DL2_MOD latency for data reloads. #1616,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2_MOD to obtain the average DL2_MOD latency for data page table reloads. ##0E4060000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2_MOD to obtain the average DL2_MOD latency for data page table reloads. #1617,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2_MOD_ALL to obtain the average DL2_MOD_ALL latency for instruction page table reloads. ##0E4020000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2_MOD_ALL to obtain the average DL2_MOD_ALL latency for instruction page table reloads. #1618,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2_MOD_ALL to obtain the average DL2_MOD_ALL latency for data reloads. ##0E4040000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2_MOD_ALL to obtain the average DL2_MOD_ALL latency for data reloads. #1619,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2_MOD_ALL to obtain the average DL2_MOD_ALL latency for data page table reloads. ##0E4060000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2_MOD_ALL to obtain the average DL2_MOD_ALL latency for data page table reloads. #1620,u,g,n,n,m,u,PM_MRK_INST_FROM_DL2_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_DL2 to obtain the average DL2 latency for instruction reloads. ##0E0100000001C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_DL2 to obtain the average DL2 latency for instruction reloads. #1621,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2 to obtain the average DL2 latency for instruction page table reloads. ##0E0120000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2 to obtain the average DL2 latency for instruction page table reloads. #1622,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2 to obtain the average DL2 latency for data reloads. ##0E0140000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2 to obtain the average DL2 latency for data reloads. #1623,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2 to obtain the average DL2 latency for data page table reloads. ##0E0160000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2 to obtain the average DL2 latency for data page table reloads. #1624,u,g,n,n,m,u,PM_MRK_INST_FROM_DL2_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_DL2_ALL to obtain the average DL2_ALL latency for instruction reloads. ##0E0100000011C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_DL2_ALL to obtain the average DL2_ALL latency for instruction reloads. #1625,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2_ALL to obtain the average DL2_ALL latency for instruction page table reloads. ##0E0120000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2_ALL to obtain the average DL2_ALL latency for instruction page table reloads. #1626,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2_ALL to obtain the average DL2_ALL latency for data reloads. ##0E0140000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2_ALL to obtain the average DL2_ALL latency for data reloads. #1627,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2_ALL to obtain the average DL2_ALL latency for data page table reloads. ##0E0160000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2_ALL to obtain the average DL2_ALL latency for data page table reloads. #1628,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL3_SHR to obtain the average DL3_SHR latency for instruction page table reloads. ##0E8020000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL3_SHR to obtain the average DL3_SHR latency for instruction page table reloads. #1629,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL3_SHR to obtain the average DL3_SHR latency for data reloads. ##0E8040000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL3_SHR to obtain the average DL3_SHR latency for data reloads. #1630,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL3_SHR to obtain the average DL3_SHR latency for data page table reloads. ##0E8060000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL3_SHR to obtain the average DL3_SHR latency for data page table reloads. #1631,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL3_SHR_ALL to obtain the average DL3_SHR_ALL latency for instruction page table reloads. ##0E8020000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL3_SHR_ALL to obtain the average DL3_SHR_ALL latency for instruction page table reloads. #1632,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL3_SHR_ALL to obtain the average DL3_SHR_ALL latency for data reloads. ##0E8040000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL3_SHR_ALL to obtain the average DL3_SHR_ALL latency for data reloads. #1633,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL3_SHR_ALL to obtain the average DL3_SHR_ALL latency for data page table reloads. ##0E8060000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL3_SHR_ALL to obtain the average DL3_SHR_ALL latency for data page table reloads. #1634,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL3_MOD to obtain the average DL3_MOD latency for instruction page table reloads. ##0EC020000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL3_MOD to obtain the average DL3_MOD latency for instruction page table reloads. #1635,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL3_MOD to obtain the average DL3_MOD latency for data reloads. ##0EC040000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL3_MOD to obtain the average DL3_MOD latency for data reloads. #1636,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL3_MOD to obtain the average DL3_MOD latency for data page table reloads. ##0EC060000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL3_MOD to obtain the average DL3_MOD latency for data page table reloads. #1637,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL3_MOD_ALL to obtain the average DL3_MOD_ALL latency for instruction page table reloads. ##0EC020000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL3_MOD_ALL to obtain the average DL3_MOD_ALL latency for instruction page table reloads. #1638,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL3_MOD_ALL to obtain the average DL3_MOD_ALL latency for data reloads. ##0EC040000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL3_MOD_ALL to obtain the average DL3_MOD_ALL latency for data reloads. #1639,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL3_MOD_ALL to obtain the average DL3_MOD_ALL latency for data page table reloads. ##0EC060000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL3_MOD_ALL to obtain the average DL3_MOD_ALL latency for data page table reloads. #1640,u,g,n,n,m,u,PM_MRK_INST_FROM_DL3_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_DL3 to obtain the average DL3 latency for instruction reloads. ##0E8100000001C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_DL3 to obtain the average DL3 latency for instruction reloads. #1641,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL3 to obtain the average DL3 latency for instruction page table reloads. ##0E8120000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL3 to obtain the average DL3 latency for instruction page table reloads. #1642,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL3 to obtain the average DL3 latency for data reloads. ##0E8140000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL3 to obtain the average DL3 latency for data reloads. #1643,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL3 to obtain the average DL3 latency for data page table reloads. ##0E8160000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL3 to obtain the average DL3 latency for data page table reloads. #1644,u,g,n,n,m,u,PM_MRK_INST_FROM_DL3_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_DL3_ALL to obtain the average DL3_ALL latency for instruction reloads. ##0E8100000011C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_DL3_ALL to obtain the average DL3_ALL latency for instruction reloads. #1645,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL3_ALL to obtain the average DL3_ALL latency for instruction page table reloads. ##0E8120000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL3_ALL to obtain the average DL3_ALL latency for instruction page table reloads. #1646,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL3_ALL to obtain the average DL3_ALL latency for data reloads. ##0E8140000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL3_ALL to obtain the average DL3_ALL latency for data reloads. #1647,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL3_ALL to obtain the average DL3_ALL latency for data page table reloads. ##0E8160000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL3_ALL to obtain the average DL3_ALL latency for data page table reloads. #1648,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2L3_SHR to obtain the average DL2L3_SHR latency for instruction page table reloads. ##0E0220000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2L3_SHR to obtain the average DL2L3_SHR latency for instruction page table reloads. #1649,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2L3_SHR to obtain the average DL2L3_SHR latency for data reloads. ##0E0240000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2L3_SHR to obtain the average DL2L3_SHR latency for data reloads. #1650,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2L3_SHR to obtain the average DL2L3_SHR latency for data page table reloads. ##0E0260000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2L3_SHR to obtain the average DL2L3_SHR latency for data page table reloads. #1651,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2L3_SHR_ALL to obtain the average DL2L3_SHR_ALL latency for instruction page table reloads. ##0E0220000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2L3_SHR_ALL to obtain the average DL2L3_SHR_ALL latency for instruction page table reloads. #1652,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2L3_SHR_ALL to obtain the average DL2L3_SHR_ALL latency for data reloads. ##0E0240000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2L3_SHR_ALL to obtain the average DL2L3_SHR_ALL latency for data reloads. #1653,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2L3_SHR_ALL to obtain the average DL2L3_SHR_ALL latency for data page table reloads. ##0E0260000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2L3_SHR_ALL to obtain the average DL2L3_SHR_ALL latency for data page table reloads. #1654,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2L3_MOD to obtain the average DL2L3_MOD latency for instruction page table reloads. ##0E4220000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2L3_MOD to obtain the average DL2L3_MOD latency for instruction page table reloads. #1655,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2L3_MOD to obtain the average DL2L3_MOD latency for data reloads. ##0E4240000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2L3_MOD to obtain the average DL2L3_MOD latency for data reloads. #1656,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2L3_MOD to obtain the average DL2L3_MOD latency for data page table reloads. ##0E4260000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2L3_MOD to obtain the average DL2L3_MOD latency for data page table reloads. #1657,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2L3_MOD_ALL to obtain the average DL2L3_MOD_ALL latency for instruction page table reloads. ##0E4220000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2L3_MOD_ALL to obtain the average DL2L3_MOD_ALL latency for instruction page table reloads. #1658,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2L3_MOD_ALL to obtain the average DL2L3_MOD_ALL latency for data reloads. ##0E4240000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2L3_MOD_ALL to obtain the average DL2L3_MOD_ALL latency for data reloads. #1659,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2L3_MOD_ALL to obtain the average DL2L3_MOD_ALL latency for data page table reloads. ##0E4260000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2L3_MOD_ALL to obtain the average DL2L3_MOD_ALL latency for data page table reloads. #1660,u,g,n,n,m,u,PM_MRK_INST_FROM_DL2L3_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_DL2L3 to obtain the average DL2L3 latency for instruction reloads. ##0E0300000001C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_DL2L3 to obtain the average DL2L3 latency for instruction reloads. #1661,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2L3 to obtain the average DL2L3 latency for instruction page table reloads. ##0E0320000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2L3 to obtain the average DL2L3 latency for instruction page table reloads. #1662,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2L3 to obtain the average DL2L3 latency for data reloads. ##0E0340000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2L3 to obtain the average DL2L3 latency for data reloads. #1663,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2L3 to obtain the average DL2L3 latency for data page table reloads. ##0E0360000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2L3 to obtain the average DL2L3 latency for data page table reloads. #1664,u,g,n,n,m,u,PM_MRK_INST_FROM_DL2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_DL2L3_ALL to obtain the average DL2L3_ALL latency for instruction reloads. ##0E0300000011C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_DL2L3_ALL to obtain the average DL2L3_ALL latency for instruction reloads. #1665,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2L3_ALL to obtain the average DL2L3_ALL latency for instruction page table reloads. ##0E0320000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2L3_ALL to obtain the average DL2L3_ALL latency for instruction page table reloads. #1666,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2L3_ALL to obtain the average DL2L3_ALL latency for data reloads. ##0E0340000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2L3_ALL to obtain the average DL2L3_ALL latency for data reloads. #1667,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2L3_ALL to obtain the average DL2L3_ALL latency for data page table reloads. ##0E0360000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2L3_ALL to obtain the average DL2L3_ALL latency for data page table reloads. #1668,u,g,n,n,m,u,PM_MRK_INST_FROM_DMEM_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from distant memory (MC slow) due to a demand miss. Divide this count by PM_MRK_INST_FROM_DMEM to obtain the average DMEM latency for instruction reloads. ##0F4100000001C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from distant memory (MC slow) due to a demand miss. Divide this count by PM_MRK_INST_FROM_DMEM to obtain the average DMEM latency for instruction reloads. #1669,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DMEM_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from distant memory (MC slow) due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DMEM to obtain the average DMEM latency for instruction page table reloads. ##0F4020000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from distant memory (MC slow) due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DMEM to obtain the average DMEM latency for instruction page table reloads. #1670,u,g,n,n,m,u,PM_MRK_DATA_FROM_DMEM_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from distant memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DMEM to obtain the average DMEM latency for data reloads. ##0F4040000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from distant memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DMEM to obtain the average DMEM latency for data reloads. #1671,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DMEM_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from distant memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DMEM to obtain the average DMEM latency for data page table reloads. ##0F4060000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from distant memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DMEM to obtain the average DMEM latency for data page table reloads. #1672,u,g,n,n,m,u,PM_MRK_INST_FROM_DMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_DMEM_ALL to obtain the average DMEM_ALL latency for instruction reloads. ##0F4100000011C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_DMEM_ALL to obtain the average DMEM_ALL latency for instruction reloads. #1673,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DMEM_ALL to obtain the average DMEM_ALL latency for instruction page table reloads. ##0F4020000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DMEM_ALL to obtain the average DMEM_ALL latency for instruction page table reloads. #1674,u,g,n,n,m,u,PM_MRK_DATA_FROM_DMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DMEM_ALL to obtain the average DMEM_ALL latency for data reloads. ##0F4040000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DMEM_ALL to obtain the average DMEM_ALL latency for data reloads. #1675,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DMEM_ALL to obtain the average DMEM_ALL latency for data page table reloads. ##0F4060000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DMEM_ALL to obtain the average DMEM_ALL latency for data page table reloads. #1676,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_CACHE_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_D_OC_CACHE to obtain the average D_OC_CACHE latency for instruction page table reloads. ##0F8020000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_D_OC_CACHE to obtain the average D_OC_CACHE latency for instruction page table reloads. #1677,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_CACHE_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DATA_FROM_D_OC_CACHE to obtain the average D_OC_CACHE latency for data reloads. ##0F8040000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DATA_FROM_D_OC_CACHE to obtain the average D_OC_CACHE latency for data reloads. #1678,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_CACHE_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_D_OC_CACHE to obtain the average D_OC_CACHE latency for data page table reloads. ##0F8060000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_D_OC_CACHE to obtain the average D_OC_CACHE latency for data page table reloads. #1679,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_D_OC_CACHE_ALL to obtain the average D_OC_CACHE_ALL latency for instruction page table reloads. ##0F8020000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_D_OC_CACHE_ALL to obtain the average D_OC_CACHE_ALL latency for instruction page table reloads. #1680,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_D_OC_CACHE_ALL to obtain the average D_OC_CACHE_ALL latency for data reloads. ##0F8040000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_D_OC_CACHE_ALL to obtain the average D_OC_CACHE_ALL latency for data reloads. #1681,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_D_OC_CACHE_ALL to obtain the average D_OC_CACHE_ALL latency for data page table reloads. ##0F8060000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_D_OC_CACHE_ALL to obtain the average D_OC_CACHE_ALL latency for data page table reloads. #1682,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_MEM_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_D_OC_MEM to obtain the average D_OC_MEM latency for instruction page table reloads. ##0FC020000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_D_OC_MEM to obtain the average D_OC_MEM latency for instruction page table reloads. #1683,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_MEM_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_D_OC_MEM to obtain the average D_OC_MEM latency for data reloads. ##0FC040000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_D_OC_MEM to obtain the average D_OC_MEM latency for data reloads. #1684,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_MEM_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_D_OC_MEM to obtain the average D_OC_MEM latency for data page table reloads. ##0FC060000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_D_OC_MEM to obtain the average D_OC_MEM latency for data page table reloads. #1685,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_MEM_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_D_OC_MEM_ALL to obtain the average D_OC_MEM_ALL latency for instruction page table reloads. ##0FC020000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_D_OC_MEM_ALL to obtain the average D_OC_MEM_ALL latency for instruction page table reloads. #1686,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_MEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_D_OC_MEM_ALL to obtain the average D_OC_MEM_ALL latency for data reloads. ##0FC040000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_D_OC_MEM_ALL to obtain the average D_OC_MEM_ALL latency for data reloads. #1687,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_MEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_D_OC_MEM_ALL to obtain the average D_OC_MEM_ALL latency for data page table reloads. ##0FC060000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_D_OC_MEM_ALL to obtain the average D_OC_MEM_ALL latency for data page table reloads. #1688,u,g,n,n,m,u,PM_MRK_INST_FROM_D_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_INST_FROM_D_OC_ANY to obtain the average D_OC_ANY latency for instruction reloads. ##0F8100000001C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_INST_FROM_D_OC_ANY to obtain the average D_OC_ANY latency for instruction reloads. #1689,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_D_OC_ANY to obtain the average D_OC_ANY latency for instruction page table reloads. ##0F8120000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_D_OC_ANY to obtain the average D_OC_ANY latency for instruction page table reloads. #1690,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_D_OC_ANY to obtain the average D_OC_ANY latency for data reloads. ##0F8140000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_D_OC_ANY to obtain the average D_OC_ANY latency for data reloads. #1691,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_D_OC_ANY to obtain the average D_OC_ANY latency for data page table reloads. ##0F8160000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_D_OC_ANY to obtain the average D_OC_ANY latency for data page table reloads. #1692,u,g,n,n,m,u,PM_MRK_INST_FROM_D_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_D_OC_ANY_ALL to obtain the average D_OC_ANY_ALL latency for instruction reloads. ##0F8100000011C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_D_OC_ANY_ALL to obtain the average D_OC_ANY_ALL latency for instruction reloads. #1693,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_D_OC_ANY_ALL to obtain the average D_OC_ANY_ALL latency for instruction page table reloads. ##0F8120000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_D_OC_ANY_ALL to obtain the average D_OC_ANY_ALL latency for instruction page table reloads. #1694,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_D_OC_ANY_ALL to obtain the average D_OC_ANY_ALL latency for data reloads. ##0F8140000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_D_OC_ANY_ALL to obtain the average D_OC_ANY_ALL latency for data reloads. #1695,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_D_OC_ANY_ALL to obtain the average D_OC_ANY_ALL latency for data page table reloads. ##0F8160000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_D_OC_ANY_ALL to obtain the average D_OC_ANY_ALL latency for data page table reloads. #1696,u,g,n,n,m,u,PM_MRK_INST_FROM_ONCHIP_CACHE_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_ONCHIP_CACHE to obtain the average ONCHIP_CACHE latency for instruction reloads. ##080B00000001C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_ONCHIP_CACHE to obtain the average ONCHIP_CACHE latency for instruction reloads. #1697,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_ONCHIP_CACHE_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_ONCHIP_CACHE to obtain the average ONCHIP_CACHE latency for instruction page table reloads. ##080B20000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_ONCHIP_CACHE to obtain the average ONCHIP_CACHE latency for instruction page table reloads. #1698,u,g,n,n,m,u,PM_MRK_DATA_FROM_ONCHIP_CACHE_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_ONCHIP_CACHE to obtain the average ONCHIP_CACHE latency for data reloads. ##080B40000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_ONCHIP_CACHE to obtain the average ONCHIP_CACHE latency for data reloads. #1699,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_ONCHIP_CACHE_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_ONCHIP_CACHE to obtain the average ONCHIP_CACHE latency for data page table reloads. ##080B60000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_ONCHIP_CACHE to obtain the average ONCHIP_CACHE latency for data page table reloads. #1700,u,g,n,n,m,u,PM_MRK_INST_FROM_ONCHIP_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_ONCHIP_CACHE_ALL to obtain the average ONCHIP_CACHE_ALL latency for instruction reloads. ##080B00000011C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_ONCHIP_CACHE_ALL to obtain the average ONCHIP_CACHE_ALL latency for instruction reloads. #1701,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_ONCHIP_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_ONCHIP_CACHE_ALL to obtain the average ONCHIP_CACHE_ALL latency for instruction page table reloads. ##080B20000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_ONCHIP_CACHE_ALL to obtain the average ONCHIP_CACHE_ALL latency for instruction page table reloads. #1702,u,g,n,n,m,u,PM_MRK_DATA_FROM_ONCHIP_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_ONCHIP_CACHE_ALL to obtain the average ONCHIP_CACHE_ALL latency for data reloads. ##080B40000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_ONCHIP_CACHE_ALL to obtain the average ONCHIP_CACHE_ALL latency for data reloads. #1703,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_ONCHIP_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_ONCHIP_CACHE_ALL to obtain the average ONCHIP_CACHE_ALL latency for data page table reloads. ##080B60000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_ONCHIP_CACHE_ALL to obtain the average ONCHIP_CACHE_ALL latency for data page table reloads. #1704,u,g,n,n,m,u,PM_MRK_INST_FROM_OFFCHIP_CACHE_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_OFFCHIP_CACHE to obtain the average OFFCHIP_CACHE latency for instruction reloads. ##0C0B00000001C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_OFFCHIP_CACHE to obtain the average OFFCHIP_CACHE latency for instruction reloads. #1705,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_OFFCHIP_CACHE_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_OFFCHIP_CACHE to obtain the average OFFCHIP_CACHE latency for instruction page table reloads. ##0C0B20000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_OFFCHIP_CACHE to obtain the average OFFCHIP_CACHE latency for instruction page table reloads. #1706,u,g,n,n,m,u,PM_MRK_DATA_FROM_OFFCHIP_CACHE_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_OFFCHIP_CACHE to obtain the average OFFCHIP_CACHE latency for data reloads. ##0C0B40000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_OFFCHIP_CACHE to obtain the average OFFCHIP_CACHE latency for data reloads. #1707,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_OFFCHIP_CACHE_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_OFFCHIP_CACHE to obtain the average OFFCHIP_CACHE latency for data page table reloads. ##0C0B60000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_OFFCHIP_CACHE to obtain the average OFFCHIP_CACHE latency for data page table reloads. #1708,u,g,n,n,m,u,PM_MRK_INST_FROM_OFFCHIP_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_OFFCHIP_CACHE_ALL to obtain the average OFFCHIP_CACHE_ALL latency for instruction reloads. ##0C0B00000011C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_OFFCHIP_CACHE_ALL to obtain the average OFFCHIP_CACHE_ALL latency for instruction reloads. #1709,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_OFFCHIP_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_OFFCHIP_CACHE_ALL to obtain the average OFFCHIP_CACHE_ALL latency for instruction page table reloads. ##0C0B20000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_OFFCHIP_CACHE_ALL to obtain the average OFFCHIP_CACHE_ALL latency for instruction page table reloads. #1710,u,g,n,n,m,u,PM_MRK_DATA_FROM_OFFCHIP_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_OFFCHIP_CACHE_ALL to obtain the average OFFCHIP_CACHE_ALL latency for data reloads. ##0C0B40000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_OFFCHIP_CACHE_ALL to obtain the average OFFCHIP_CACHE_ALL latency for data reloads. #1711,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_OFFCHIP_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_OFFCHIP_CACHE_ALL to obtain the average OFFCHIP_CACHE_ALL latency for data page table reloads. ##0C0B60000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_OFFCHIP_CACHE_ALL to obtain the average OFFCHIP_CACHE_ALL latency for data page table reloads. #1712,u,g,n,n,m,u,PM_MRK_INST_FROM_ANY_MEMORY_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from any chip's memory (MC slow) due to a demand miss. Divide this count by PM_MRK_INST_FROM_ANY_MEMORY to obtain the average ANY_MEMORY latency for instruction reloads. ##095900000001C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from any chip's memory (MC slow) due to a demand miss. Divide this count by PM_MRK_INST_FROM_ANY_MEMORY to obtain the average ANY_MEMORY latency for instruction reloads. #1713,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_ANY_MEMORY_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from any chip's memory (MC slow) due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_ANY_MEMORY to obtain the average ANY_MEMORY latency for instruction page table reloads. ##095820000001C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from any chip's memory (MC slow) due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_ANY_MEMORY to obtain the average ANY_MEMORY latency for instruction page table reloads. #1714,u,g,n,n,m,u,PM_MRK_DATA_FROM_ANY_MEMORY_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from any chip's memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DATA_FROM_ANY_MEMORY to obtain the average ANY_MEMORY latency for data reloads. ##095840000001C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from any chip's memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DATA_FROM_ANY_MEMORY to obtain the average ANY_MEMORY latency for data reloads. #1715,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_ANY_MEMORY_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from any chip's memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_ANY_MEMORY to obtain the average ANY_MEMORY latency for data page table reloads. ##095860000001C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from any chip's memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_ANY_MEMORY to obtain the average ANY_MEMORY latency for data page table reloads. #1716,u,g,n,n,m,u,PM_MRK_INST_FROM_ANY_MEMORY_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_ANY_MEMORY_ALL to obtain the average ANY_MEMORY_ALL latency for instruction reloads. ##095900000011C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_ANY_MEMORY_ALL to obtain the average ANY_MEMORY_ALL latency for instruction reloads. #1717,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_ANY_MEMORY_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_ANY_MEMORY_ALL to obtain the average ANY_MEMORY_ALL latency for instruction page table reloads. ##095820000011C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_ANY_MEMORY_ALL to obtain the average ANY_MEMORY_ALL latency for instruction page table reloads. #1718,u,g,n,n,m,u,PM_MRK_DATA_FROM_ANY_MEMORY_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_ANY_MEMORY_ALL to obtain the average ANY_MEMORY_ALL latency for data reloads. ##095840000021C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_ANY_MEMORY_ALL to obtain the average ANY_MEMORY_ALL latency for data reloads. #1719,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_ANY_MEMORY_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_ANY_MEMORY_ALL to obtain the average ANY_MEMORY_ALL latency for data page table reloads. ##095860000021C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_ANY_MEMORY_ALL to obtain the average ANY_MEMORY_ALL latency for data page table reloads. $$$$$$$$ { counter 2} #0,u,g,n,n,n,n,PM_SUSPENDED,Counter off ##20000 Counter off #1,u,g,n,n,n,n,PM_INST_CMPL,PowerPC instruction completed ##20002 PowerPC instruction completed #2,u,g,n,n,n,n,PM_CYC,Processor cycles ##2001E Processor cycles #3,u,g,n,n,n,y,PM_BR_FIN,A branch instruction finished. Includes predicted/mispredicted/unconditional ##2F04A A branch instruction finished. Includes predicted/mispredicted/unconditional #4,u,g,n,n,n,y,PM_ISSUE_STALL,Cycles in which the oldest instruction in the pipeline was dispatched but not issued yet. ##20004 Cycles in which the oldest instruction in the pipeline was dispatched but not issued yet. #5,u,g,n,n,n,y,PM_DISP_STALL_HELD_ISSQ_FULL_CYC,Cycles in which the next-to-complete (NTC) instruction is held at dispatch due to Issue queue full. Includes issue queue and branch queue ##20006 Cycles in which the next-to-complete (NTC) instruction is held at dispatch due to Issue queue full. Includes issue queue and branch queue #6,u,g,n,n,m,n,PM_MRK_TLBIE_CYC,Latency of TLBIE instructions from the cycle they become next-to-finish (NTF) until they complete in the nest ##20108 Latency of TLBIE instructions from the cycle they become next-to-finish (NTF) until they complete in the nest #7,u,g,n,n,n,n,PM_HYPERVISOR_CYC,Cycles when the thread is in Hypervisor state. MSR[S HV PR]=010 ##2000A Cycles when the thread is in Hypervisor state. MSR[S HV PR]=010 #8,u,g,n,n,n,n,PM_RUN_LATCH_ALL_THREADS_CYC,Cycles when the run latch is set for all threads. ##2000C Cycles when the run latch is set for all threads. #9,u,g,n,n,n,y,PM_LSU_LD1_FIN,LSU Finished an internal operation in LD1 port ##2000E LSU Finished an internal operation in LD1 port #10,u,g,n,n,n,y,PM_PMC1_OVERFLOW,The event selected for PMC1 caused the event counter to overflow. ##20010 The event selected for PMC1 caused the event counter to overflow. #11,u,g,n,n,m,y,PM_MRK_NTF_FIN,The marked instruction became the oldest in the pipeline before it finished. It excludes instructions that finish at dispatch ##20112 The marked instruction became the oldest in the pipeline before it finished. It excludes instructions that finish at dispatch #12,u,g,n,n,m,n,PM_MRK_L2_RC_DISP,Marked instruction RC dispatched in L2 ##20114 Marked instruction RC dispatched in L2 #13,u,g,n,n,n,y,PM_ST_FIN,Store finish count. Includes speculative activity ##20016 Store finish count. Includes speculative activity #14,u,g,n,n,n,y,PM_ST_FWD,Store forwards that finished ##20018 Store forwards that finished #15,u,g,n,n,n,y,PM_ITLB_HIT,The PTE required to translate the instruction address was resident in the TLB (instruction TLB access/IERAT reload). Applies to both HPT and RPT. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches. ##2001A The PTE required to translate the instruction address was resident in the TLB (instruction TLB access/IERAT reload). Applies to both HPT and RPT. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches. #16,u,g,n,n,m,n,PM_MRK_NTF_CYC,Cycles in which the marked instruction is the oldest in the pipeline (next-to-finish or next-to-complete) ##2011C Cycles in which the marked instruction is the oldest in the pipeline (next-to-finish or next-to-complete) #17,u,g,n,n,n,y,PM_EXEC_STALL_LSU,Cycles in which the oldest instruction in the pipeline was executing in the Load Store Unit. This does not include simple fixed point instructions. ##2C010 Cycles in which the oldest instruction in the pipeline was executing in the Load Store Unit. This does not include simple fixed point instructions. #18,u,g,n,n,n,u,PM_MMA_AVAIL_NACTIVE,MMA is powered up and available, but has no active MMA instructions to execute ##2C012 MMA is powered up and available, but has no active MMA instructions to execute #19,u,g,n,n,n,n,PM_CMPL_STALL_SPECIAL,Cycles in which the oldest instruction in the pipeline required special handling before completing. ##2C014 Cycles in which the oldest instruction in the pipeline required special handling before completing. #20,u,g,n,n,n,y,PM_DISP_STALL_IERAT_ONLY_MISS,Cycles when dispatch was stalled while waiting to resolve an instruction ERAT miss ##2C016 Cycles when dispatch was stalled while waiting to resolve an instruction ERAT miss #21,u,g,n,n,n,y,PM_EXEC_STALL_DMISS_L3MISS,Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from a source beyond the local L2 or local L3. ##2C018 Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from a source beyond the local L2 or local L3. #22,u,g,n,n,n,y,PM_EXEC_STALL_DMISS_OFF_CHIP,Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from a remote chip. ##2C01C Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from a remote chip. #23,u,g,n,n,n,y,PM_DISP_STALL_BR_MPRED_IC_L3,Cycles when dispatch was stalled while the instruction was fetched from the local L3 after suffering a branch mispredict. ##2C01E Cycles when dispatch was stalled while the instruction was fetched from the local L3 after suffering a branch mispredict. #24,u,g,n,n,n,y,PM_LSU_ST1_FIN,LSU Finished an internal operation in ST1 port ##2D010 LSU Finished an internal operation in ST1 port #25,u,g,n,n,n,y,PM_VSU1_ISSUE,VSU instruction issued to VSU pipe 1 ##2D012 VSU instruction issued to VSU pipe 1 #26,u,g,n,n,n,y,PM_EXEC_STALL_VSU,Cycles in which the oldest instruction in the pipeline was executing in the VSU (includes FXU, VSU, CRU). ##2D018 Cycles in which the oldest instruction in the pipeline was executing in the VSU (includes FXU, VSU, CRU). #27,u,g,n,n,n,y,PM_DISP_STALL_IC_MISS,Cycles when dispatch was stalled for this thread due to an instruction cache miss. ##2D01A Cycles when dispatch was stalled for this thread due to an instruction cache miss. #28,u,g,n,n,n,n,PM_CMPL_STALL_STCX,Cycles in which the oldest instruction in the pipeline was a stcx waiting for resolution from the nest before completing. ##2D01C Cycles in which the oldest instruction in the pipeline was a stcx waiting for resolution from the nest before completing. #29,u,g,n,n,n,n,PM_ADJUNCT_INST_CMPL,PowerPC instruction completed while the thread was in Adjunct state. ##2E010 PowerPC instruction completed while the thread was in Adjunct state. #30,u,g,n,n,n,y,PM_STCX_FIN,Conditional store instruction (STCX) finished. LARX and STCX are instructions used to acquire a lock ##2E014 Conditional store instruction (STCX) finished. LARX and STCX are instructions used to acquire a lock #31,u,g,n,n,n,y,PM_EXT_INT_HYP,Cycles an external interrupt was active that was initiated by the Hypervisor ##2E016 Cycles an external interrupt was active that was initiated by the Hypervisor #32,u,g,n,n,n,y,PM_DISP_STALL_FETCH,Cycles when dispatch was stalled for this thread because Fetch was being held ##2E018 Cycles when dispatch was stalled for this thread because Fetch was being held #33,u,g,n,n,n,y,PM_DISP_STALL_HELD_XVFC_MAPPER_CYC,Cycles in which the next-to-complete (NTC) instruction is held at dispatch because the XVFC mapper/SRB was full ##2E01A Cycles in which the next-to-complete (NTC) instruction is held at dispatch because the XVFC mapper/SRB was full #34,u,g,n,n,n,y,PM_EXEC_STALL_TLBIE,Cycles in which the oldest instruction in the pipeline was a TLBIE instruction executing in the Load Store Unit. ##2E01C Cycles in which the oldest instruction in the pipeline was a TLBIE instruction executing in the Load Store Unit. #35,u,g,n,n,n,y,PM_EXEC_STALL_NTC_FLUSH,Cycles in which the oldest instruction in the pipeline was executing in any unit before it was flushed. Note that if the flush of the oldest instruction happens after finish, the cycles from dispatch to issue will be included in PM_DISP_STALL and the cycles from issue to finish will be included in PM_EXEC_STALL and its corresponding children. This event will also count cycles when the previous next-to-finish (NTF) instruction is still completing and the new NTF instruction is stalled at dispatch. ##2E01E Cycles in which the oldest instruction in the pipeline was executing in any unit before it was flushed. Note that if the flush of the oldest instruction happens after finish, the cycles from dispatch to issue will be included in PM_DISP_STALL and the cycles from issue to finish will be included in PM_EXEC_STALL and its corresponding children. This event will also count cycles when the previous next-to-finish (NTF) instruction is still completing and the new NTF instruction is stalled at dispatch. #36,u,g,n,n,m,y,PM_MRK_DATA_GRP_PUMP_MPRED_RTY,Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a marked demand load ##2D12C Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a marked demand load #37,u,g,n,n,m,y,PM_MRK_DTLB_HIT,The PTE required by the instruction was resident in the TLB (data TLB access) for the marked instruction. When MMCR1[16]=0 this event counts only demand hits. When MMCR1[16]=1 this event includes demand and prefetch. Applies to both HPT and RPT ##2D12E The PTE required by the instruction was resident in the TLB (data TLB access) for the marked instruction. When MMCR1[16]=0 this event counts only demand hits. When MMCR1[16]=1 this event includes demand and prefetch. Applies to both HPT and RPT #38,u,g,n,n,m,y,PM_MRK_INST_DECODED,An instruction was marked at decode time. Random Instruction Sampling (RIS) only ##20130 An instruction was marked at decode time. Random Instruction Sampling (RIS) only #39,u,g,n,n,m,y,PM_MRK_DFU_ISSUE,The marked instruction was a decimal floating point operation issued to the VSU. Measured at issue time. ##20132 The marked instruction was a decimal floating point operation issued to the VSU. Measured at issue time. #40,u,g,n,n,m,y,PM_MRK_FXU_ISSUE,The marked instruction was a fixed point operation issued to the VSU. Measured at issue time. ##20134 The marked instruction was a fixed point operation issued to the VSU. Measured at issue time. #41,u,g,n,n,m,n,PM_MRK_ST_NEST,A store has been sampled/marked and is at the point of execution where it has completed in the core and can no longer be flushed. At this point the store is sent to the L2. ##20138 A store has been sampled/marked and is at the point of execution where it has completed in the core and can no longer be flushed. At this point the store is sent to the L2. #42,u,g,n,n,m,y,PM_MRK_BRU_FIN,Marked Branch instruction finished ##2013A Marked Branch instruction finished #43,u,g,n,n,m,y,PM_MRK_FX_LSU_FIN,The marked instruction was simple fixed point that was issued to the store unit. Measured at finish time ##2013C The marked instruction was simple fixed point that was issued to the store unit. Measured at finish time #44,u,g,n,n,n,y,PM_PTESYNC_FIN,Ptesync instruction finished in the store unit. Only one ptesync can finish at a time. ##2003E Ptesync instruction finished in the store unit. Only one ptesync can finish at a time. #45,u,g,n,n,n,y,PM_DATA_RADIX_L2_PTE_FROM_L3,A data Page Table Entry was reloaded to a level 2 page walk cache from the core's L3 cache. If MMCR1[16] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. ##24042 A data Page Table Entry was reloaded to a level 2 page walk cache from the core's L3 cache. If MMCR1[16] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. #46,u,g,n,n,n,y,PM_DATA_RADIX_L2_PDE_FROM_L3,A data Page Directory Entry was reloaded to a level 2 page walk cache from the core's L3 cache. If MMCR1[16] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. ##24044 A data Page Directory Entry was reloaded to a level 2 page walk cache from the core's L3 cache. If MMCR1[16] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. #47,u,g,n,n,n,y,PM_DATA_RADIX_L3_PTE_FROM_L3,A data Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 cache. If MMCR1[16] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. ##24046 A data Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 cache. If MMCR1[16] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. #48,u,g,n,n,n,y,PM_DATA_RADIX_L3_PDE_FROM_L3,A data Page Directory Entry was reloaded to a level 3 page walk cache from the core's L3 cache. If MMCR1[16] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. ##24048 A data Page Directory Entry was reloaded to a level 3 page walk cache from the core's L3 cache. If MMCR1[16] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. #49,u,g,n,n,n,y,PM_DATA_RADIX_L4_PTE_FROM_L3,A data Page Table Entry was reloaded to a level 4 page walk cache from the core's L3 cache. If MMCR1[16] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. ##2404A A data Page Table Entry was reloaded to a level 4 page walk cache from the core's L3 cache. If MMCR1[16] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. #50,u,g,n,n,n,y,PM_INST_RADIX_L2_PTE_FROM_L3,An instruction Page Table Entry was reloaded to a level 2 page walk cache from the core's L3 cache. If MMCR1[17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[17] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. ##2404E An instruction Page Table Entry was reloaded to a level 2 page walk cache from the core's L3 cache. If MMCR1[17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[17] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. #51,u,g,n,n,n,y,PM_INST_RADIX_L3_PTE_FROM_L3,An instruction Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 cache. If MMCR1[17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[17] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. ##25042 An instruction Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 cache. If MMCR1[17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[17] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. #52,u,g,n,n,n,y,PM_INST_RADIX_L3_PDE_FROM_L3,An instruction Page Directory Entry was reloaded to a level 3 page walk cache from the core's L3 cache. If MMCR1[17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[17] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. ##25044 An instruction Page Directory Entry was reloaded to a level 3 page walk cache from the core's L3 cache. If MMCR1[17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[17] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. #53,u,g,n,n,n,y,PM_INST_RADIX_L4_PTE_FROM_L3,An instruction Page Table Entry was reloaded to a level 4 page walk cache from the core's L3 cache. If MMCR1[17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[17] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. ##25046 An instruction Page Table Entry was reloaded to a level 4 page walk cache from the core's L3 cache. If MMCR1[17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[17] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. #54,u,g,n,n,n,y,PM_PMC4_HELD_CYC,Cycles when the speculative counter for PMC4 is frozen. ##2504C Cycles when the speculative counter for PMC4 is frozen. #55,u,g,n,n,n,y,PM_XFER_FROM_SRC_PMC2,The processor's L1 data cache was reloaded from the source specified in MMCR3[15:27]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads. ##2C040 The processor's L1 data cache was reloaded from the source specified in MMCR3[15:27]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads. #56,u,g,n,n,m,y,PM_MRK_XFER_FROM_SRC_PMC2,For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[15:27]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads. ##2C142 For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[15:27]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads. #57,u,g,n,n,m,y,PM_MRK_XFER_FROM_SRC_CYC_PMC2,Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[15:27]. ##2C144 Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[15:27]. #58,u,g,n,n,m,y,PM_MRK_DATA_FLUSHED_FROM_SRC_PMC2,Marked demand loads that attempted a reload, but were flushed ##2C146 Marked demand loads that attempted a reload, but were flushed #59,u,g,n,n,m,y,PM_MRK_DATA_FLUSHED_FROM_SRC_CYC_PMC2,Cycles spent attempting to reload a line from any source for a marked demand miss that was later flushed ##2C148 Cycles spent attempting to reload a line from any source for a marked demand miss that was later flushed #60,u,g,n,n,n,u,PM_SDAR_LOADED,SDAR writes per thread ##2C04E SDAR writes per thread #61,u,g,n,n,n,u,PM_ICBI_FIN,An ICBI instruction finished ##2F04C An ICBI instruction finished #62,u,g,n,n,n,y,PM_HPT_RELOAD,A page was reloaded for an HPT translation ##20050 A page was reloaded for an HPT translation #63,u,g,n,n,n,y,PM_GRP_PUMP_MPRED_TOO_BIG,A bus operation was sent as a system pump and group pump was the accurate scope. The scope could have been smaller but no retry was needed. Includes data, instruction and translation operations. Set MMCR1[16] and MMCR1[17] to 0b11 to include instruction and data prefetch respectively. ##20052 A bus operation was sent as a system pump and group pump was the accurate scope. The scope could have been smaller but no retry was needed. Includes data, instruction and translation operations. Set MMCR1[16] and MMCR1[17] to 0b11 to include instruction and data prefetch respectively. #64,u,g,n,n,n,y,PM_LD_CACHE_INHIBITED,A data line was brought in from the nest to fulfill a request initiated by a non-cacheable load instruction. The data will not be written to the L1 ##20058 A data line was brought in from the nest to fulfill a request initiated by a non-cacheable load instruction. The data will not be written to the L1 #65,u,g,n,n,m,y,PM_MRK_FAB_RSP_RWITM_RTY,Sampled store did a rwitm and got a rty ##2015E Sampled store did a rwitm and got a rty #66,u,g,n,n,n,y,PM_IOPS_DISP,Internal Operations dispatched. PM_IOPS_DISP / PM_INST_DISP will show the average number of internal operations per PowerPC instruction. ##24050 Internal Operations dispatched. PM_IOPS_DISP / PM_INST_DISP will show the average number of internal operations per PowerPC instruction. #67,u,g,n,n,m,y,PM_MRK_STCX_FIN,Marked conditional store instruction (STCX) finished. LARX and STCX are instructions used to acquire a lock ##24156 Marked conditional store instruction (STCX) finished. LARX and STCX are instructions used to acquire a lock #68,u,g,n,n,m,y,PM_MRK_INST,An instruction was marked. Includes both Random Instruction Sampling (RIS) at decode time and Random Event Sampling (RES) at the time the configured event happens ##24158 An instruction was marked. Includes both Random Instruction Sampling (RIS) at decode time and Random Event Sampling (RES) at the time the configured event happens #69,u,g,n,n,n,y,PM_NTC_FIN,Cycles in which the oldest instruction in the pipeline (NTC) finishes. Note that instructions can finish out of order, therefore not all the instructions that finish have a Next-to-complete status. ##2405A Cycles in which the oldest instruction in the pipeline (NTC) finishes. Note that instructions can finish out of order, therefore not all the instructions that finish have a Next-to-complete status. #70,u,g,n,n,m,n,PM_MRK_BR_CMPL,A marked branch completed. All branches are included. ##2415C A marked branch completed. All branches are included. #71,u,g,n,n,n,y,PM_ISSUE_CANCEL,An instruction issued and the issue was later cancelled. Only one cancel per PowerPC instruction ##2405E An instruction issued and the issue was later cancelled. Only one cancel per PowerPC instruction #72,u,g,n,n,n,y,PM_VSU_ISSUE,At least one VSU instruction was issued to one of the VSU pipes. Up to 4 per cycle. Includes fixed point operations. ##2505C At least one VSU instruction was issued to one of the VSU pipes. Up to 4 per cycle. Includes fixed point operations. #73,u,g,n,n,n,y,PM_DATA_GRP_PUMP_CPRED,Initial and Final Pump Scope was group pump (prediction=correct) for a demand load ##2C050 Initial and Final Pump Scope was group pump (prediction=correct) for a demand load #74,u,g,n,n,n,y,PM_DATA_GRP_PUMP_MPRED_TOO_BIG,Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for a demand load ##2C052 Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for a demand load #75,u,g,n,n,n,y,PM_DERAT_MISS_64K,Data ERAT Miss (Data TLB Access) page size 64K. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches ##2C054 Data ERAT Miss (Data TLB Access) page size 64K. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches #76,u,g,n,n,n,y,PM_DTLB_MISS_4K,Data TLB reload (after a miss) page size 4K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches ##2C056 Data TLB reload (after a miss) page size 4K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches #77,u,g,n,n,n,y,PM_MEM_PREF,Memory prefetch for this thread. Includes instruction and data. This event count should be divided by two since the event is sourced from 2:1 clock domain. ##2C058 Memory prefetch for this thread. Includes instruction and data. This event count should be divided by two since the event is sourced from 2:1 clock domain. #78,u,g,n,n,n,y,PM_DERAT_MISS_1G,Data ERAT Miss (Data TLB Access) page size 1G. Implies radix translation. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches ##2C05A Data ERAT Miss (Data TLB Access) page size 1G. Implies radix translation. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches #79,u,g,n,n,n,y,PM_INST_GRP_PUMP_CPRED,Initial and Final Pump Scope was group pump (prediction=correct) for an instruction fetch (demand only) ##2C05C Initial and Final Pump Scope was group pump (prediction=correct) for an instruction fetch (demand only) #80,u,g,n,n,n,y,PM_INST_GRP_PUMP_MPRED_TOO_BIG,Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for an instruction fetch (demand only) ##2C05E Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for an instruction fetch (demand only) #81,u,g,n,n,m,y,PM_MRK_DERAT_MISS_4K,Data ERAT Miss (Data TLB Access) page size 4K for a marked instruction. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches ##2D150 Data ERAT Miss (Data TLB Access) page size 4K for a marked instruction. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches #82,u,g,n,n,m,y,PM_MRK_DERAT_MISS_64K,Data ERAT Miss (Data TLB Access) page size 64K for a marked instruction. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches ##2D154 Data ERAT Miss (Data TLB Access) page size 64K for a marked instruction. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches #83,u,g,n,n,m,y,PM_MRK_DTLB_MISS_16M,Marked Data TLB reload (after a miss) page size 16M. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches ##2D156 Marked Data TLB reload (after a miss) page size 16M. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches #84,u,g,n,n,n,y,PM_ITLB_MISS_2M,Instruction TLB reload (after a miss) page size 2M, which implies Radix Page Table translation is in use. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches. ##2D058 Instruction TLB reload (after a miss) page size 2M, which implies Radix Page Table translation is in use. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches. #85,u,g,n,n,n,y,PM_ITLB_MISS_16M,Instruction TLB reload (after a miss) page size 16M. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches. ##2D05A Instruction TLB reload (after a miss) page size 16M. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches. #86,u,g,n,n,m,y,PM_MRK_DTLB_MISS_16G,Marked Data TLB reload (after a miss) page size 16G. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches ##2D15E Marked Data TLB reload (after a miss) page size 16G. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches #87,u,g,n,n,n,y,PM_DTLB_HIT_4K,Data TLB hit (DERAT reload) page size 64K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches ##2E050 Data TLB hit (DERAT reload) page size 64K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches #88,u,g,n,n,n,y,PM_ITLB_HIT_2M,Instruction TLB hit (IERAT reload) page size 2M, which implies Radix Page Table translation is in use. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches. ##2E054 Instruction TLB hit (IERAT reload) page size 2M, which implies Radix Page Table translation is in use. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches. #89,u,g,n,n,n,y,PM_ITLB_HIT_16M,Instruction TLB hit (IERAT reload) page size 16M. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches. ##2E056 Instruction TLB hit (IERAT reload) page size 16M. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches. #90,u,g,n,n,n,y,PM_LD_REJECT_TIQ,Internal LSU reject from LRQ. Rejects cause the load to go back to LRQ, but it stays contained within the LSU once it gets issued. This event counts the number of times the LRQ attempts to relaunch an instruction after a reject. Any load can suffer multiple rejects ##2E05A Internal LSU reject from LRQ. Rejects cause the load to go back to LRQ, but it stays contained within the LSU once it gets issued. This event counts the number of times the LRQ attempts to relaunch an instruction after a reject. Any load can suffer multiple rejects #91,u,g,n,n,m,y,PM_MRK_FAB_RSP_DCLAIM_CYC,Cycles L2 RC took for a dclaim ##2F152 Cycles L2 RC took for a dclaim #92,u,g,n,n,n,y,PM_DISP_SS1_2_INSTR_CYC,Cycles in which Superslice 1 dispatches either 1 or 2 instructions ##2F054 Cycles in which Superslice 1 dispatches either 1 or 2 instructions #93,u,g,n,n,n,y,PM_DISP_SS1_4_INSTR_CYC,Cycles in which Superslice 1 dispatches either 3 or 4 instructions ##2F056 Cycles in which Superslice 1 dispatches either 3 or 4 instructions #94,u,g,n,n,n,y,PM_DISP_HELD_OTHER_CYC,Cycles dispatch is held for any other reason ##20066 Cycles dispatch is held for any other reason #95,u,g,n,n,n,y,PM_DISP_HELD_HALT_CYC,Cycles dispatch is held because of power management ##20068 Cycles dispatch is held because of power management #96,u,g,n,n,n,y,PM_DISP_HELD_STF_MAPPER_CYC,Cycles dispatch is held because the STF mapper/SRB was full. Includes GPR (count, link, tar), VSR, VMR, FPR ##2006A Cycles dispatch is held because the STF mapper/SRB was full. Includes GPR (count, link, tar), VSR, VMR, FPR #97,u,g,n,n,n,y,PM_RUN_CYC_SMT4_MODE,Cycles when this thread's run latch is set and the core is in SMT4 mode ##2006C Cycles when this thread's run latch is set and the core is in SMT4 mode #98,u,g,n,n,m,y,PM_MRK_DATA_FROM_MEMORY,The processor's data cache was reloaded from local, remote, or distant memory due to a demand miss for a marked load ##201E0 The processor's data cache was reloaded from local, remote, or distant memory due to a demand miss for a marked load #99,u,g,n,n,m,y,PM_MRK_LD_MISS_L1,Marked demand data load miss counted at finish time ##201E2 Marked demand data load miss counted at finish time #100,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3MISS,The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction. ##201E4 The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction. #101,u,g,t,n,m,y,PM_THRESH_EXC_32,Threshold counter exceeded a value of 32 ##201E6 Threshold counter exceeded a value of 32 #102,u,g,t,n,m,y,PM_THRESH_EXC_512,Threshold counter exceeded a value of 512 ##201E8 Threshold counter exceeded a value of 512 #103,u,g,n,n,n,n,PM_ST_CMPL,Stores completed from S2Q (2nd-level store queue). This event includes regular stores, stcx and cache inhibited stores. The following operations are excluded (pteupdate, snoop tlbie complete, store atomics, miso, load atomic payloads, tlbie, tlbsync, slbieg, isync, msgsnd, slbiag, cpabort, copy, tcheck, tend, stsync, dcbst, icbi, dcbf, hwsync, lwsync, ptesync, eieio, msgsync) ##200F0 Stores completed from S2Q (2nd-level store queue). This event includes regular stores, stcx and cache inhibited stores. The following operations are excluded (pteupdate, snoop tlbie complete, store atomics, miso, load atomic payloads, tlbie, tlbsync, slbieg, isync, msgsnd, slbiag, cpabort, copy, tcheck, tend, stsync, dcbst, icbi, dcbf, hwsync, lwsync, ptesync, eieio, msgsync) #104,u,g,n,n,n,y,PM_INST_DISP,PowerPC instruction dispatched ##200F2 PowerPC instruction dispatched #105,u,g,n,n,n,n,PM_RUN_CYC,Processor cycles gated by the run latch ##200F4 Processor cycles gated by the run latch #106,u,g,n,n,n,y,PM_DERAT_MISS,DERAT Reloaded to satisfy a DERAT miss. All page sizes are counted by this event. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches ##200F6 DERAT Reloaded to satisfy a DERAT miss. All page sizes are counted by this event. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches #107,u,g,n,n,n,n,PM_EXT_INT,Cycles an external interrupt was active ##200F8 Cycles an external interrupt was active #108,u,g,n,n,n,n,PM_BR_TAKEN_CMPL,Branch Taken instruction completed ##200FA Branch Taken instruction completed #109,u,g,n,n,n,y,PM_L1_ICACHE_MISS,Demand instruction cache miss ##200FD Demand instruction cache miss #110,u,g,n,n,n,u,PM_DATA_FROM_L2MISS,The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss. ##200FE The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss. #111,u,g,n,n,n,u,PM_INST_FROM_L3MISS,The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss. ##000780000002C040 The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss. #112,u,g,n,n,n,u,PM_DATA_FROM_L3MISS,The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss. ##0007C0000002C040 The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss. #113,u,g,n,n,m,u,PM_MRK_INST_FROM_L3MISS,The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction. ##000780000002C142 The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction. #114,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2MISS,The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction. ##0003C0000002C142 The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction. #115,u,g,n,n,n,u,PM_EE_OFF_EXT_INT_CYC,Cycles in which MSR[EE] is off and external interrupts are active ##0000002080 Cycles in which MSR[EE] is off and external interrupts are active #116,u,g,n,n,n,u,PM_ISU_FLUSH,All flushes initiated by the Instruction Sequencing Unit (ISU). Excludes LSU NTC+1 flushes ##0000002880 All flushes initiated by the Instruction Sequencing Unit (ISU). Excludes LSU NTC+1 flushes #117,u,g,n,n,n,u,PM_ISU_FLUSH_DISP,Dispatch flushes occur when one thread is causing other threads to stall ##0000002084 Dispatch flushes occur when one thread is causing other threads to stall #118,u,g,n,n,n,u,PM_ISU_FLUSH_BALANCE,A balance flush occurred. Balance flushes are triggered when excessive L3 or TLB misses occur ##0000002884 A balance flush occurred. Balance flushes are triggered when excessive L3 or TLB misses occur #119,u,g,n,n,n,u,PM_ISU_FLUSH_PARTIAL,A flush occurred only to the odd ITAG of a pair. This type of flush requires an additional 10 cycles to process. More pairs of instructions can be included in this count. ##0000002088 A flush occurred only to the odd ITAG of a pair. This type of flush requires an additional 10 cycles to process. More pairs of instructions can be included in this count. #120,u,g,n,n,n,u,PM_ISU_FLUSH_DISP_SRQ_EMPTY,Dispatch flush while waiting for the SRQ to become empty: TLBIE, SLBIEG, SLBIET, EIEIO, TLBSYNC. ##0000002888 Dispatch flush while waiting for the SRQ to become empty: TLBIE, SLBIEG, SLBIET, EIEIO, TLBSYNC. #121,u,g,n,n,n,u,PM_ISU_FLUSH_LD_ECC_ERROR,A load instruction that accessed early data from memory and finished speculatively before the ECC was returned, gets flushed because of a later ECC error ##000000208C A load instruction that accessed early data from memory and finished speculatively before the ECC was returned, gets flushed because of a later ECC error #122,u,g,n,n,n,u,PM_ISU_FLUSH_LWSYNC,A flush to a lightweight synchronizing or barrier instruction (LWSYNC) instruction that had trouble. This event includes NTC flushes and NTC+1 flushes. ##000000288C A flush to a lightweight synchronizing or barrier instruction (LWSYNC) instruction that had trouble. This event includes NTC flushes and NTC+1 flushes. #123,u,g,n,n,n,u,PM_ISU_FLUSH_ISYNC,A flush to an isync instruction that had trouble. This event includes NTC flushes and NTC+1 flushes. ##0000002090 A flush to an isync instruction that had trouble. This event includes NTC flushes and NTC+1 flushes. #124,u,g,n,n,n,u,PM_ISU_FLUSH_HWSYNC,A flush to a heavyweight synchronizing or barrier instruction (HWSYNC) instruction that had trouble. This event includes NTC flushes and NTC+1 flushes. ##0000002094 A flush to a heavyweight synchronizing or barrier instruction (HWSYNC) instruction that had trouble. This event includes NTC flushes and NTC+1 flushes. #125,u,g,n,n,n,u,PM_ISU_FLUSH_MMA_OFF_CYC,If the MMA engine is off when an MMA instruction is issued, the instruction will issue and finish as a nop. It will then get flushed when it becomes NTC and it will not be refetched until the MMA engine is on. This event counts the number of cycles between the flush and the MMA engine turning on. ##0000002894 If the MMA engine is off when an MMA instruction is issued, the instruction will issue and finish as a nop. It will then get flushed when it becomes NTC and it will not be refetched until the MMA engine is on. This event counts the number of cycles between the flush and the MMA engine turning on. #126,u,g,n,n,n,u,PM_ISU_FLUSH_DISP_STF_REBAL,The Sliced Target File (STF) is the register file for GPRs, VSRs, LR, CTR, and TAR. This event indicates that an execution unit attempted to write to a slice that was full. In this case, the instruction gets flushed and the slices get rebalanced. ##00000028AC The Sliced Target File (STF) is the register file for GPRs, VSRs, LR, CTR, and TAR. This event indicates that an execution unit attempted to write to a slice that was full. In this case, the instruction gets flushed and the slices get rebalanced. #127,u,g,n,n,n,u,PM_START_PROBE_NOP_DISP,A start probe nop was dispatched. Instruction AND 0,0,0 ##00000020B0 A start probe nop was dispatched. Instruction AND 0,0,0 #128,u,g,n,n,n,u,PM_STOP_PROBE_NOP_DISP,A stop probe nop was dispatched. Instruction AND 1,1,1 ##00000028B0 A stop probe nop was dispatched. Instruction AND 1,1,1 #129,u,g,n,n,m,u,PM_MRK_STOP_PROBE_NOP_DISP,A stop probe nop was marked at dispatch. Instruction AND 1,1,1 ##00000021B4 A stop probe nop was marked at dispatch. Instruction AND 1,1,1 #130,u,g,n,n,n,u,PM_FUNCTION_CALL_DISP,bl instruction dispatched. Only one reported per cycle. It is possible to dispatch 8 instructions per cycle in single thread mode. ##00000020B8 bl instruction dispatched. Only one reported per cycle. It is possible to dispatch 8 instructions per cycle in single thread mode. #131,u,g,n,n,n,u,PM_FUNCTION_RETURN_DISP,blr instruction dispatched. Only one reported per cycle. It is possible to dispatch 8 instructions per cycle in single thread mode. ##00000028B8 blr instruction dispatched. Only one reported per cycle. It is possible to dispatch 8 instructions per cycle in single thread mode. #132,u,g,n,n,n,u,PM_0CYC_CONST_DISP,Xxor instruction dispatched. ##00000020BC Xxor instruction dispatched. #133,u,g,n,n,n,u,PM_ISSUE_HOLD_STAGS_CYC,Cycles in which one or more instructions are being held at issue while waiting for Store Tags to become available. These instructions could also be held simultaneously for other conditions. Other non-store instructions are allowed to issue while the store is being held. ##0000003080 Cycles in which one or more instructions are being held at issue while waiting for Store Tags to become available. These instructions could also be held simultaneously for other conditions. Other non-store instructions are allowed to issue while the store is being held. #134,u,g,n,n,n,u,PM_ISSUE_HOLD_LTAGS_CYC,Cycles in which one or more instructions are being held at issue while waiting for Load Tags to become available. These instructions could also be held simultaneously for other conditions. Other non-load instructions are allowed to issue while the load is being held. ##0000003880 Cycles in which one or more instructions are being held at issue while waiting for Load Tags to become available. These instructions could also be held simultaneously for other conditions. Other non-load instructions are allowed to issue while the load is being held. #135,u,g,n,n,n,u,PM_ISSUE_KILL_DL_MISS,An instruction was primed to issue but was killed before being written because one of the sources takes a data load miss. I.e. dependent data from a load does not get valid data ##0000003084 An instruction was primed to issue but was killed before being written because one of the sources takes a data load miss. I.e. dependent data from a load does not get valid data #136,u,g,n,n,n,u,PM_ISSUE_KILL_RESOURCE,An instruction was primed to issue but was killed before being written because a resource is unavailable. Includes BFU, FX-DIV, DFU, BRU and SFX instructions that would collide at finish with a store AGEN. ##0000003884 An instruction was primed to issue but was killed before being written because a resource is unavailable. Includes BFU, FX-DIV, DFU, BRU and SFX instructions that would collide at finish with a store AGEN. #137,u,g,n,n,n,u,PM_ISSUE_KILL_THROTTLE,An instruction was primed to issue but was killed before being written because power throttling was enabled ##0000003088 An instruction was primed to issue but was killed before being written because power throttling was enabled #138,u,g,n,n,n,u,PM_SHL_HIT,A dependency was created when a dispatched store matched the address for a load in the Store-Hit-Load Table. ##000000388C A dependency was created when a dispatched store matched the address for a load in the Store-Hit-Load Table. #139,u,g,n,n,n,u,PM_LHS_HIT,A dependency was created when a dispatched load matched the address for a store instruction in the Load-Hit-Store table. ##0000003890 A dependency was created when a dispatched load matched the address for a store instruction in the Load-Hit-Store table. #140,u,g,n,n,n,u,PM_LHS_CREATED,New entry added to the Load-Hit-Store table. ##0000003094 New entry added to the Load-Hit-Store table. #141,u,g,n,n,n,u,PM_LARX_HIT_LARX_HIT,A dependency was created for a LARX instruction that was dispatched and matched an older LARX in the Larx-hit-larx table. ##0000003894 A dependency was created for a LARX instruction that was dispatched and matched an older LARX in the Larx-hit-larx table. #142,u,g,n,n,n,u,PM_LARX_HIT_LARX_CREATED,New entry added to the Larx-hit-larx table. LARX and STCX are instructions used to acquire a lock.  ##0000003098 New entry added to the Larx-hit-larx table. LARX and STCX are instructions used to acquire a lock.  #143,u,g,n,n,n,u,PM_MMA_VSR_CONFLICT_FLUSH,A VSR operation references an ACC that has been primed. This is indicative of a context switch ##0000003898 A VSR operation references an ACC that has been primed. This is indicative of a context switch #144,u,g,n,n,n,u,PM_MMA_ACC_CONFLICT_FLUSH,An MMA instruction references an ACC that has not been primed. This is indicative of faulty software ##000000309C An MMA instruction references an ACC that has not been primed. This is indicative of faulty software #145,u,g,n,n,m,u,PM_MRK_MMA_ACC_VSR_CONFLICT,Either a marked MMA instruction references an ACC that has not been primed or a marked VSR operation references an ACC that has been primed ##000000399C Either a marked MMA instruction references an ACC that has not been primed or a marked VSR operation references an ACC that has been primed #146,u,g,n,n,n,u,PM_MMA_IN_USE_CYC,Cycles in which the MMA engine is actively being used by this thread. This is measured by counting the cycles in which at least one ACC register is primed for MMA use. ##00000030A0 Cycles in which the MMA engine is actively being used by this thread. This is measured by counting the cycles in which at least one ACC register is primed for MMA use. #147,u,g,n,n,n,u,PM_MMA_ON_CYC,Cycles in which this core's MMA engine is enabled. ##00000038A0 Cycles in which this core's MMA engine is enabled. #148,u,g,n,n,n,u,PM_DISP_HELD_OUT_OF_LTAGS_CYC,Cycles in which dispatch is held because the LRQ is full. No LTAGS are available. There are twice as many LTAGS as there are LRQ entries. The signal should be on if less than 8 tags, and should be off if greater than 24 tags, and could be on if in-between. In ST/SMT2, if less than 24 tags, signal can come on, and if less than 8 it will be on. In SMT4, if less than 12 tags, it can come on, if less than 4 tags it will be on. ##00000030B4 Cycles in which dispatch is held because the LRQ is full. No LTAGS are available. There are twice as many LTAGS as there are LRQ entries. The signal should be on if less than 8 tags, and should be off if greater than 24 tags, and could be on if in-between. In ST/SMT2, if less than 24 tags, signal can come on, and if less than 8 it will be on. In SMT4, if less than 12 tags, it can come on, if less than 4 tags it will be on. #149,u,g,n,n,n,u,PM_DISP_HELD_OUT_OF_STAGS_CYC,Cycles in which dispatch is held because the SRQ is full. No STAGS are available. There are twice as many STAGS as there are SRQ entries. The signal should be on if less than 8 tags, should be off is greater than 24 tags, and could be on if in-between. In ST/SMT2, if less than 24 tags, signal can come on, if less than 8 tags it will be on. In SMT4, if less than 12 tags, it can come on, if less than 4 tags it will be on. ##00000038B4 Cycles in which dispatch is held because the SRQ is full. No STAGS are available. There are twice as many STAGS as there are SRQ entries. The signal should be on if less than 8 tags, should be off is greater than 24 tags, and could be on if in-between. In ST/SMT2, if less than 24 tags, signal can come on, if less than 8 tags it will be on. In SMT4, if less than 12 tags, it can come on, if less than 4 tags it will be on. #150,u,g,n,n,n,u,PM_DISP_CLB_HELD_BALANCE_CYC,Dispatch/CLB Hold as cause of Balance Flush. ##00000030B8 Dispatch/CLB Hold as cause of Balance Flush. #151,u,g,n,n,n,u,PM_DISP_CLB_HELD_SRQ_EMPTY_CYC,Dispatch Hold: waiting for the SRQ to become empty: TLBIE, SLBIEG, SLBIET, EIEIO, TLBSYNC. This should exclude cycles when it is only waiting for the ICT to become empty. ##00000038B8 Dispatch Hold: waiting for the SRQ to become empty: TLBIE, SLBIEG, SLBIET, EIEIO, TLBSYNC. This should exclude cycles when it is only waiting for the ICT to become empty. #152,u,g,n,n,n,u,PM_DISP_PARTIAL,Dispatches in which the Instruction Sequencing Unit (ISU) dispatches instructions at either half rate or quarter rate. This can happen when some of the queues (or mapper subblocks) are either full, or close to full. ##00000030BC Dispatches in which the Instruction Sequencing Unit (ISU) dispatches instructions at either half rate or quarter rate. This can happen when some of the queues (or mapper subblocks) are either full, or close to full. #153,u,g,n,n,n,u,PM_ISYNC_CMPL,Isync completion count per thread ##00000038BC Isync completion count per thread #154,u,g,n,n,n,u,PM_LD0_8B_FIN,64-bit or smaller load finished in the LD0 load execution unit. ##000000C080 64-bit or smaller load finished in the LD0 load execution unit. #155,u,g,n,n,n,u,PM_LD1_8B_FIN,64-bit or smaller load finished in the LD1 load execution unit. ##000000C880 64-bit or smaller load finished in the LD1 load execution unit. #156,u,g,n,n,n,u,PM_LD0_16B_FIN,128-bit load finished in the LD0 load execution unit. ##000000C084 128-bit load finished in the LD0 load execution unit. #157,u,g,n,n,n,u,PM_LD1_16B_FIN,128-bit load finished in the LD1 load execution unit. ##000000C884 128-bit load finished in the LD1 load execution unit. #158,u,g,n,n,n,u,PM_LD0_32B_FIN,256-bit load finished in the LD0 load execution unit. ##000000C088 256-bit load finished in the LD0 load execution unit. #159,u,g,n,n,n,u,PM_LD1_32B_FIN,256-bit load finished in the LD1 load execution unit. ##000000C888 256-bit load finished in the LD1 load execution unit. #160,u,g,n,n,n,u,PM_LD0_VECTOR_FIN,Any vector load operation finished in the LD0 execution unit. Excludes load quad, larx quad, fused load double, load float double-pair. ##000000C08C Any vector load operation finished in the LD0 execution unit. Excludes load quad, larx quad, fused load double, load float double-pair. #161,u,g,n,n,n,u,PM_LD1_VECTOR_FIN,Any vector load operation finished in the LD1 execution unit. Excludes load quad, larx quad, fused load double, load float double-pair. ##000000C88C Any vector load operation finished in the LD1 execution unit. Excludes load quad, larx quad, fused load double, load float double-pair. #162,u,g,n,n,n,u,PM_LD0_UNALIGNED_FIN,Load instructions in LD0 port that are either unaligned, or treated as unaligned and require an additional recycle through the pipeline using the load gather buffer. This typically adds about 10 cycles to the latency of the instruction. This includes loads that cross the 128 byte boundary, octword loads that are not aligned, and a special forward progress case of a load that does not hit in the L1 and crosses the 32 byte boundary and is launched NTC. Counted at finish time. ##000000C090 Load instructions in LD0 port that are either unaligned, or treated as unaligned and require an additional recycle through the pipeline using the load gather buffer. This typically adds about 10 cycles to the latency of the instruction. This includes loads that cross the 128 byte boundary, octword loads that are not aligned, and a special forward progress case of a load that does not hit in the L1 and crosses the 32 byte boundary and is launched NTC. Counted at finish time. #163,u,g,n,n,n,u,PM_LD1_UNALIGNED_FIN,Load instructions in LD1 port that are either unaligned, or treated as unaligned and require an additional recycle through the pipeline using the load gather buffer. This typically adds about 10 cycles to the latency of the instruction. This includes loads that cross the 128 byte boundary, octword loads that are not aligned, and a special forward progress case of a load that does not hit in the L1 and crosses the 32 byte boundary and is launched NTC. Counted at finish time. ##000000C890 Load instructions in LD1 port that are either unaligned, or treated as unaligned and require an additional recycle through the pipeline using the load gather buffer. This typically adds about 10 cycles to the latency of the instruction. This includes loads that cross the 128 byte boundary, octword loads that are not aligned, and a special forward progress case of a load that does not hit in the L1 and crosses the 32 byte boundary and is launched NTC. Counted at finish time. #164,u,g,n,n,n,u,PM_ST0_8B_FIN,8-byte or smaller store finished in the ST0 store execution unit. ##000000C094 8-byte or smaller store finished in the ST0 store execution unit. #165,u,g,n,n,n,u,PM_ST1_8B_FIN,8-byte or smaller store finished in the ST1 store execution unit. ##000000C894 8-byte or smaller store finished in the ST1 store execution unit. #166,u,g,n,n,n,u,PM_ST0_16B_FIN,16-byte store finished in the ST0 store execution unit. ##000000C098 16-byte store finished in the ST0 store execution unit. #167,u,g,n,n,n,u,PM_ST1_16B_FIN,16-byte store finished in the ST1 store execution unit. ##000000C898 16-byte store finished in the ST1 store execution unit. #168,u,g,n,n,n,u,PM_ST0_32B_FIN,32-byte store finished in the ST0 store execution unit. ##000000C09C 32-byte store finished in the ST0 store execution unit. #169,u,g,n,n,n,u,PM_ST1_32B_FIN,32-byte store finished in the ST1 store execution unit. ##000000C89C 32-byte store finished in the ST1 store execution unit. #170,u,g,n,n,n,u,PM_ST0_VECTOR_FIN,Any vector store operation finished in the ST0 store execution unit. Excludes store quad, stcx quad, store float double-pair, fused store double. ##000000C0A0 Any vector store operation finished in the ST0 store execution unit. Excludes store quad, stcx quad, store float double-pair, fused store double. #171,u,g,n,n,n,u,PM_ST1_VECTOR_FIN,Any vector store operation finished in the ST1 store execution unit. Excludes store quad, stcx quad, store float double-pair, fused store double. ##000000C8A0 Any vector store operation finished in the ST1 store execution unit. Excludes store quad, stcx quad, store float double-pair, fused store double. #172,u,g,n,n,n,u,PM_ST0_UNALIGNED_FIN,Store instructions in ST0 port that are either unaligned, or treated as unaligned and require an additional recycle through the pipeline. This typically adds about 10 cycles to the latency of the instruction. This only includes stores that cross the 128 byte boundary. Counted at finish time. ##000000C0A4 Store instructions in ST0 port that are either unaligned, or treated as unaligned and require an additional recycle through the pipeline. This typically adds about 10 cycles to the latency of the instruction. This only includes stores that cross the 128 byte boundary. Counted at finish time. #173,u,g,n,n,n,u,PM_ST1_UNALIGNED_FIN,Store instructions in ST1 port that are either unaligned, or treated as unaligned and require an additional recycle through the pipeline. This typically adds about 10 cycles to the latency of the instruction. This only includes stores that cross the 128 byte boundary. Counted at finish time. ##000000C8A4 Store instructions in ST1 port that are either unaligned, or treated as unaligned and require an additional recycle through the pipeline. This typically adds about 10 cycles to the latency of the instruction. This only includes stores that cross the 128 byte boundary. Counted at finish time. #174,u,g,n,n,n,u,PM_FALSE_LHS,False Load-Hit-Store (LHS) match detected. Load and store have a partial Effective Address (EA) match but they are actually independent of each other. The other cases of false LHS cause flushes and they are instrumented with separate PMU events. ##000000C0A8 False Load-Hit-Store (LHS) match detected. Load and store have a partial Effective Address (EA) match but they are actually independent of each other. The other cases of false LHS cause flushes and they are instrumented with separate PMU events. #175,u,g,n,n,n,u,PM_LD0_LHS_REJECT,On the LD0 load execution unit, the real address of a load matched the real address of an earlier store and it is not possible to store forward because not all bytes required by the load are available on the store entry that was hit. In this case, the load must wait for the store to drain or for the store data to issue. ##000000C8A8 On the LD0 load execution unit, the real address of a load matched the real address of an earlier store and it is not possible to store forward because not all bytes required by the load are available on the store entry that was hit. In this case, the load must wait for the store to drain or for the store data to issue. #176,u,g,n,n,n,u,PM_LD1_LHS_REJECT,On the LD1 load execution unit, the real address of a load matched the real address of an earlier store and it is not possible to store forward because not all bytes required by the load are available on the store entry that was hit. In this case, the load must wait for the store to drain or for the store data to issue. ##000000C0AC On the LD1 load execution unit, the real address of a load matched the real address of an earlier store and it is not possible to store forward because not all bytes required by the load are available on the store entry that was hit. In this case, the load must wait for the store to drain or for the store data to issue. #177,u,g,n,n,n,u,PM_ST0_STORE_REJECT,Store reject on the ST0 store execution unit. All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up, to try again after the condition has been met. ##000000C8AC Store reject on the ST0 store execution unit. All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up, to try again after the condition has been met. #178,u,g,n,n,n,u,PM_ST1_STORE_REJECT,Store reject on the ST1 store execution unit. All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up, to try again after the condition has been met. ##000000C0B0 Store reject on the ST1 store execution unit. All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up, to try again after the condition has been met. #179,u,g,n,n,n,u,PM_ST_DRAIN_MERGE,Two stores drain together. Use PM_ST_CMPL as a divider. If one of the stores crosses a cache-line boundary, a store drain can be counted for each half. In this case, if there are three stores they will count as two merges. ##000000C8B0 Two stores drain together. Use PM_ST_CMPL as a divider. If one of the stores crosses a cache-line boundary, a store drain can be counted for each half. In this case, if there are three stores they will count as two merges. #180,u,g,n,n,n,u,PM_LMQ_MERGE,A load-hit-reload occurred. A load launched in the LSU and hit an existing LMQ entry which is fetching data for the same cacheline. ##000000C0B4 A load-hit-reload occurred. A load launched in the LSU and hit an existing LMQ entry which is fetching data for the same cacheline. #181,u,g,n,n,n,u,PM_STCX_CMPL,STCX data was sent to nest, i.e. total count of stcx. stcx instructions are not allowed to gather before the final drain-out to the L1 and L2, so this count is always accurate. ##000000C8B4 STCX data was sent to nest, i.e. total count of stcx. stcx instructions are not allowed to gather before the final drain-out to the L1 and L2, so this count is always accurate. #182,u,g,n,n,n,u,PM_NCST_CMPL,Counts when an I=1 store op is sent to the nest. This event counts at drain time and it may include up to 3 stores that have gathered for the same cache line before drain. ##000000C0B8 Counts when an I=1 store op is sent to the nest. This event counts at drain time and it may include up to 3 stores that have gathered for the same cache line before drain. #183,u,g,n,n,n,u,PM_STCX_SUCCESS_CMPL,STCX instructions that completed successfully. Specifically, counts only when a pass status is returned from the nest. ##000000C8B8 STCX instructions that completed successfully. Specifically, counts only when a pass status is returned from the nest. #184,u,g,n,n,n,u,PM_DC_RELOAD_COLLISIONS,A load reading the L1 cache has a bank collision with another load reading the same bank, or due to a cache-line reload writing to that bank of the L1 cache. ##000000C0BC A load reading the L1 cache has a bank collision with another load reading the same bank, or due to a cache-line reload writing to that bank of the L1 cache. #185,u,g,n,n,n,u,PM_DC_STORE_WRITE_COLLISIONS,A store writing the L1 cache at the same time as a reload or dkill writing the L1 cache that results in a bank collision. ##000000C8BC A store writing the L1 cache at the same time as a reload or dkill writing the L1 cache that results in a bank collision. #186,u,g,n,n,n,u,PM_LSU_SET_MPRED,Set prediction(set-p) miss. The entry was not found in the Set prediction table. The set-p table contains a hash of the EA and it helps access the L1 cache. ##000000D080 Set prediction(set-p) miss. The entry was not found in the Set prediction table. The set-p table contains a hash of the EA and it helps access the L1 cache. #187,u,g,n,n,n,u,PM_DERAT_HIT,A load or store instruction missed the data cache and hit in the primary ERAT. There is no secondary ERAT ##000000D880 A load or store instruction missed the data cache and hit in the primary ERAT. There is no secondary ERAT #188,u,g,n,n,n,u,PM_IERAT_HIT,An instruction fetch missed in the instruction cache and hit in the primary ERAT. There is no secondary ERAT ##000000D084 An instruction fetch missed in the instruction cache and hit in the primary ERAT. There is no secondary ERAT #189,u,g,n,n,n,u,PM_TIQ_BYPASS,A translation request bypasses the TIQ either because the TIQ is completely empty at the time of the request. ##000000D884 A translation request bypasses the TIQ either because the TIQ is completely empty at the time of the request. #190,u,g,n,n,n,u,PM_TIQ_ALLOC_CYC,Cycles when one or more operations on that thread allocated one or more TIQ entries ##000000D088 Cycles when one or more operations on that thread allocated one or more TIQ entries #191,u,g,n,n,n,u,PM_TIQ_HALF_FULL_CYC,Cycles in which the TIQ has 4 or less active entries ##000000D888 Cycles in which the TIQ has 4 or less active entries #192,u,g,n,n,n,u,PM_TIQ_ERAT_MISS_EMB_FULL_RESPIN,A load or store missed in the ERAT and found no space in the EMB. ##000000D08C A load or store missed in the ERAT and found no space in the EMB. #193,u,g,n,n,n,u,PM_EMB_FULL_CYC,Cycles in which the ERAT miss buffer is full. When the ERAT miss buffer is full the operation will go to the TIQ ##000000D88C Cycles in which the ERAT miss buffer is full. When the ERAT miss buffer is full the operation will go to the TIQ #194,u,g,n,n,n,u,PM_LSU_FLUSH_CYC,LSU flushes: includes all LSU flushes. This event only counts one flush per cycle but the hardware can flush up to 5 instructions per cycle. In general, multiple flushes for the same thread get consolidated into a single flush operation. ##000000D090 LSU flushes: includes all LSU flushes. This event only counts one flush per cycle but the hardware can flush up to 5 instructions per cycle. In general, multiple flushes for the same thread get consolidated into a single flush operation. #195,u,g,n,n,n,u,PM_LSU_FLUSH_CI,Load was not initially issued to the LSU as a cache inhibited (non-cacheable) load, but it was later determined to be cache inhibited. ##000000D890 Load was not initially issued to the LSU as a cache inhibited (non-cacheable) load, but it was later determined to be cache inhibited. #196,u,g,n,n,n,u,PM_LSU_FLUSH_ALL_WAYS_LOCKED,Non-speculative stores have locked all ways in the data cache and a newly-issued older store is not able to allocate a way for a given congruence class. ##000000D094 Non-speculative stores have locked all ways in the data cache and a newly-issued older store is not able to allocate a way for a given congruence class. #197,u,g,n,n,n,u,PM_LSU_FLUSH_LHL,If a load hits on an older load of the same address that has been snooped, or two loads of the same thread and address execute out of order and a store of another thread occurs to that address, the younger load will be flushed. The LSU only checks the out-of-orderness of the two loads and ignores the address in detecting this condition. ##000000D894 If a load hits on an older load of the same address that has been snooped, or two loads of the same thread and address execute out of order and a store of another thread occurs to that address, the younger load will be flushed. The LSU only checks the out-of-orderness of the two loads and ignores the address in detecting this condition. #198,u,g,n,n,n,u,PM_LSU_FLUSH_SAME_ICT_GRP,This flush happens if an ICT pair contains a store followed by a load to the same address with at least one byte of overlap between the two. ##000000D098 This flush happens if an ICT pair contains a store followed by a load to the same address with at least one byte of overlap between the two. #199,u,g,n,n,n,u,PM_LSU_REJECT_LHS,Effective Address (EA) alias reject: no EA match but Real Addresses do match. ##000000D898 Effective Address (EA) alias reject: no EA match but Real Addresses do match. #200,u,g,n,n,n,u,PM_LSU_FLUSH_SPECIAL,LSU workaround flush. These flushes are setup with programmable scan-only latches to perform various actions when the flush macro receives a trigger from the debug macros. These actions include things like flushing the next op encountered for a particular thread, or flushing the next op that is the Next To Complete (NTC) op that is encountered on a particular slice. The kind of flush that the workaround is setup to perform is highly variable. ##000000D09C LSU workaround flush. These flushes are setup with programmable scan-only latches to perform various actions when the flush macro receives a trigger from the debug macros. These actions include things like flushing the next op encountered for a particular thread, or flushing the next op that is the Next To Complete (NTC) op that is encountered on a particular slice. The kind of flush that the workaround is setup to perform is highly variable. #201,u,g,n,n,n,u,PM_LSU_FLUSH_SHL,The instruction was flushed because of a sequential load/store consistency issue. If a load or store hits on an older load that has either been snooped (for loads) or has stale data (for stores), a flush will occur. ##000000D89C The instruction was flushed because of a sequential load/store consistency issue. If a load or store hits on an older load that has either been snooped (for loads) or has stale data (for stores), a flush will occur. #202,u,g,n,n,n,u,PM_LSU_FLUSH_SAO,A Load-Hit-Load condition with Strong Address Ordering (SAO) will have address compare disabled and will flush. ##000000D0A0 A Load-Hit-Load condition with Strong Address Ordering (SAO) will have address compare disabled and will flush. #203,u,g,n,n,n,u,PM_LSU_FLUSH_LARX_STCX,A LARX is flushed because an older LARX has an LMQ reservation for the same thread. A STCX is flushed because an older STCX is in the STQ. The flush happens when the older LARX/STCX relaunches ##000000D8A0 A LARX is flushed because an older LARX has an LMQ reservation for the same thread. A STCX is flushed because an older STCX is in the STQ. The flush happens when the older LARX/STCX relaunches #204,u,g,n,n,n,u,PM_LSU_FLUSH_OTHER,Other LSU flushes, including: * Sync - a sync acknowledge from the L2 caused a search of the LRQ for the oldest snooped load. This will either signal a Precise Flush of the oldest snooped load, or a Flush Next PPC. * Data Valid Flush Next - several cases of this, one example is store and reload are lined up such that a store-hit-reload scenario exists and the CDF has already launched and has gotten bad/stale data. * Bad Data Valid (DVAL) Flush Next - might be a few cases of this, one example is a larxa (D-cache hit) return data and DVAL signal, but can't allocate to the LMQ (either the LMQ is full, or some other reason). Already signaled DVAL but can't watch it for snoop_hit_larx. Need to take the “bad dval” back and flush all younger ops). ##000000D0A4 Other LSU flushes, including: * Sync - a sync acknowledge from the L2 caused a search of the LRQ for the oldest snooped load. This will either signal a Precise Flush of the oldest snooped load, or a Flush Next PPC. * Data Valid Flush Next - several cases of this, one example is store and reload are lined up such that a store-hit-reload scenario exists and the CDF has already launched and has gotten bad/stale data. * Bad Data Valid (DVAL) Flush Next - might be a few cases of this, one example is a larxa (D-cache hit) return data and DVAL signal, but can't allocate to the LMQ (either the LMQ is full, or some other reason). Already signaled DVAL but can't watch it for snoop_hit_larx. Need to take the “bad dval” back and flush all younger ops). #205,u,g,n,n,n,u,PM_DC_PREF_HW_ALLOC,Prefetch stream allocated by the hardware prefetch mechanism ##000000D8A4 Prefetch stream allocated by the hardware prefetch mechanism #206,u,g,n,n,n,u,PM_DC_PREF_SW_ALLOC,Prefetch stream allocated by software prefetching ##000000D0A8 Prefetch stream allocated by software prefetching #207,u,g,n,n,n,u,PM_DC_PREF_STRIDED_ALLOC,Strided prefetch stream allocated by either the software or hardware mechanisms ##000000D8A8 Strided prefetch stream allocated by either the software or hardware mechanisms #208,u,g,n,n,n,u,PM_DC_PREF_CONS_ALLOC,Prefetch stream allocated in the conservative phase by either the hardware prefetch mechanism or software prefetch. The sum of this pair subtracted from the total number of allocs will give the total allocs in normal phase ##000000D0AC Prefetch stream allocated in the conservative phase by either the hardware prefetch mechanism or software prefetch. The sum of this pair subtracted from the total number of allocs will give the total allocs in normal phase #209,u,g,n,n,n,u,PM_DC_PREF_XCONS_ALLOC,Prefetch stream allocated in the Ultra conservative phase by either the hardware prefetch mechanism or software prefetch ##000000D8AC Prefetch stream allocated in the Ultra conservative phase by either the hardware prefetch mechanism or software prefetch #210,u,g,n,n,n,u,PM_DC_PREF_CONF,A demand load referenced a line in an active prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. Includes forwards and backwards streams ##000000D0B0 A demand load referenced a line in an active prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. Includes forwards and backwards streams #211,u,g,n,n,n,u,PM_DC_PREF_FUZZY_CONF,A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up) ##000000D8B0 A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up) #212,u,g,n,n,n,u,PM_DC_PREF_STRIDED_CONF,A demand load referenced a line in an active strided prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. ##000000D0B4 A demand load referenced a line in an active strided prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. #213,u,g,n,n,n,u,PM_DC_PREF_DEALLOC_NO_CONF,A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up) ##000000D8B4 A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up) #214,u,g,n,n,n,u,PM_L1_SW_PREF,Software L1 Prefetches, including SW Transient Prefetches ##000000D0B8 Software L1 Prefetches, including SW Transient Prefetches #215,u,g,n,n,n,u,PM_L3_SW_PREF,L3 load prefetch, sourced from a software prefetch stream, was sent to the nest ##000000D0BC L3 load prefetch, sourced from a software prefetch stream, was sent to the nest #216,u,g,n,n,n,u,PM_SNOOP_TLBIE_MY_LPAR_CYC,TLBIE snoops executed in the LSU ##000000F080 TLBIE snoops executed in the LSU #217,u,g,n,n,n,u,PM_SNOOP_TLBIE_CYC,Cycles in which TLBIE snoops are executed in the LSU ##000000F880 Cycles in which TLBIE snoops are executed in the LSU #218,u,g,n,n,n,u,PM_SNOOP_TLBIE_CACHE_WALK_CYC,TLBIE snoop cycles in which the data cache is being walked ##000000F084 TLBIE snoop cycles in which the data cache is being walked #219,u,g,n,n,n,u,PM_SNOOP_TLBIE_WAIT_ST_CYC,TLBIE snoop cycles in which older stores are still draining ##000000F884 TLBIE snoop cycles in which older stores are still draining #220,u,g,n,n,n,u,PM_SNOOP_TLBIE_WAIT_LD_CYC,TLBIE snoop cycles in which older loads are still draining ##000000F088 TLBIE snoop cycles in which older loads are still draining #221,u,g,n,n,n,u,PM_SNOOP_TLBIE_WAIT_IFU_CYC,TLBIE snoop cycles in which the Load-Store unit is waiting for the instruction cache to be walked ##000000F888 TLBIE snoop cycles in which the Load-Store unit is waiting for the instruction cache to be walked #222,u,g,n,n,n,u,PM_SNOOP_TLBIE_WAIT_MMU_CYC,TLBIE snoop cycles in which the Load-Store unit is waiting for the MMU to finish invalidation ##000000F08C TLBIE snoop cycles in which the Load-Store unit is waiting for the MMU to finish invalidation #223,u,g,n,n,n,u,PM_LD0_SETP_HIT_EADIR_MISS,A load in the LD0 execution unit matched the setp Effective Address (EA) hash function for one of the ways in the L1. But the full EA does not match the L1 directory, so the request is sent to the L1 miss pipe. ##000000F094 A load in the LD0 execution unit matched the setp Effective Address (EA) hash function for one of the ways in the L1. But the full EA does not match the L1 directory, so the request is sent to the L1 miss pipe. #224,u,g,n,n,n,u,PM_SAME_EA_DIFF_CTXTAG_RADIR_HIT,A load or store did not get a full Effective Address (EA) plus Context match in the EA directory, so it is sent to the L1 miss pipe. In particular, a full EA match, but a context miss occurred. In the L1 miss pipe, the Real Address (RA) directory lookup finds that the real address is in the L1, but allocated in the EA directory with a different context. ##000000F898 A load or store did not get a full Effective Address (EA) plus Context match in the EA directory, so it is sent to the L1 miss pipe. In particular, a full EA match, but a context miss occurred. In the L1 miss pipe, the Real Address (RA) directory lookup finds that the real address is in the L1, but allocated in the EA directory with a different context. #225,u,g,n,n,n,u,PM_CTXT_MP4_ALLOC,A new entry is created in the 4 entry Context Alias Table due to a load or store that L1 missed due to same EA/different context, but whose Real Address (RA) was found in the L1 during (RA) directory lookup in the miss pipe. ##000000F09C A new entry is created in the 4 entry Context Alias Table due to a load or store that L1 missed due to same EA/different context, but whose Real Address (RA) was found in the L1 during (RA) directory lookup in the miss pipe. #226,u,g,n,n,n,u,PM_CTXT_ALIAS_HIT_CONTRIB,A load or a store in the miss pipe hits in the Real Address (RA) directory and also on one of the 4 entries of the Context Alias Table. The index and way getting an RA directory hit is written with a context alias tag to allow future L1 hits. ##000000F89C A load or a store in the miss pipe hits in the Real Address (RA) directory and also on one of the 4 entries of the Context Alias Table. The index and way getting an RA directory hit is written with a context alias tag to allow future L1 hits. #227,u,g,n,n,n,u,PM_START_NEW_RENAME,Upon creation of a new Context Alias Table entry, a 4k walk is initiated to set the Alias Tag valid for the 31 other congruence classes. The walk is only initiated after it is confirmed that at least 2 other congruence classes detected a context alias situation.  ##000000F0A0 Upon creation of a new Context Alias Table entry, a 4k walk is initiated to set the Alias Tag valid for the 31 other congruence classes. The walk is only initiated after it is confirmed that at least 2 other congruence classes detected a context alias situation.  #228,u,g,n,n,n,u,PM_STORE_ALLOCATE,A store misses the L1 Effective Address (EA) Directory and allocates an L1 index and way with its address for use in tracking the store address in the Load-Store Unit (LSU) during the SRQ lifetime of the store. ##000000F8A0 A store misses the L1 Effective Address (EA) Directory and allocates an L1 index and way with its address for use in tracking the store address in the Load-Store Unit (LSU) during the SRQ lifetime of the store. #229,u,g,n,n,n,u,PM_LOAD_ALLOC_DEPRA_FOR_ALL_WAYS_LOCKED,A load miss allocates an Load Miss Queue (LMQ) entry however it is not able to allocate an L1 index and way for load hazard detection in the LRQ because all 8 ways are locked, either by stores in the SRQ or other loads in the LMQ. The current load is instead marked deprecated. CDF will occur but it will be marked deprecated in the LRQ and ordering hazard checking will be pessimistic. ##000000F0A4 A load miss allocates an Load Miss Queue (LMQ) entry however it is not able to allocate an L1 index and way for load hazard detection in the LRQ because all 8 ways are locked, either by stores in the SRQ or other loads in the LMQ. The current load is instead marked deprecated. CDF will occur but it will be marked deprecated in the LRQ and ordering hazard checking will be pessimistic. #230,u,g,n,n,n,u,PM_STORE_REJECT_FOR_ALL_WAYS_LOCKED,A store misses the L1 Effective Address (EA) Directory, but cannot allocates an L1 index and way with its address due to all 8 ways being locked, either by stores already in the SRQ or by loads in the LMQ. The store is rejected and relaunched immediately. ##000000F8A4 A store misses the L1 Effective Address (EA) Directory, but cannot allocates an L1 index and way with its address due to all 8 ways being locked, either by stores already in the SRQ or by loads in the LMQ. The store is rejected and relaunched immediately. #231,u,g,n,n,n,u,PM_DERAT_HIT_4K,A load or store instruction missed the data cache and hit in the primary ERAT. Page size = 4K ##000000F0B0 A load or store instruction missed the data cache and hit in the primary ERAT. Page size = 4K #232,u,g,n,n,n,u,PM_IERAT_HIT_4K,An instruction fetch missed in the instruction cache and hit in the primary ERAT. Page size = 4k ##000000F8B0 An instruction fetch missed in the instruction cache and hit in the primary ERAT. Page size = 4k #233,u,g,n,n,n,u,PM_DERAT_HIT_64K,A load or store instruction missed the data cache and hit in the primary ERAT. Page size =64k ##000000F0B4 A load or store instruction missed the data cache and hit in the primary ERAT. Page size =64k #234,u,g,n,n,n,u,PM_IERAT_HIT_64K,An instruction fetch missed in the instruction cache and hit in the primary ERAT. Page size = 64k ##000000F8B4 An instruction fetch missed in the instruction cache and hit in the primary ERAT. Page size = 64k #235,u,g,n,n,n,u,PM_DERAT_HIT_2M,A load or store instruction missed the data cache and hit in the primary ERAT. Page size = 2M ##000000F0B8 A load or store instruction missed the data cache and hit in the primary ERAT. Page size = 2M #236,u,g,n,n,n,u,PM_IERAT_HIT_2M,An instruction fetch missed in the instruction cache and hit in the primary ERAT. Page size = 2M ##000000F8B8 An instruction fetch missed in the instruction cache and hit in the primary ERAT. Page size = 2M #237,u,g,n,n,n,u,PM_DERAT_HIT_1G,A load or store instruction missed the data cache and hit in the primary ERAT. Page size = 1G ##000000F0BC A load or store instruction missed the data cache and hit in the primary ERAT. Page size = 1G #238,u,g,n,n,n,u,PM_IERAT_HIT_1G,An instruction fetch missed in the instruction cache and hit in the primary ERAT. Page size = 1G ##000000F8BC An instruction fetch missed in the instruction cache and hit in the primary ERAT. Page size = 1G #239,u,g,n,n,n,u,PM_INST_FROM_L1,An instruction fetch hit in the L1. Each fetch group contains 8 instructions. The same line can hit 4 times if 32 sequential instructions are fetched. ##0000004080 An instruction fetch hit in the L1. Each fetch group contains 8 instructions. The same line can hit 4 times if 32 sequential instructions are fetched. #240,u,g,n,n,n,u,PM_NO_FETCH_BANK_CONFLICT_CYC,Cycles in which no instructions are fetched because of an interleave conflict. The ifar logic will detect an interleave conflict and kill the data that was read that cycle. ##0000004880 Cycles in which no instructions are fetched because of an interleave conflict. The ifar logic will detect an interleave conflict and kill the data that was read that cycle. #241,u,g,n,n,n,u,PM_NO_FETCH_EAT_FULL_CYC,Cycles in which no instructions are fetched because there is no room in EAT ##0000004084 Cycles in which no instructions are fetched because there is no room in EAT #242,u,g,n,n,n,u,PM_NO_FETCH_IBUF_FULL_CYC,Cycles in which no instructions are fetched because there is no room in the instruction buffers ##0000004884 Cycles in which no instructions are fetched because there is no room in the instruction buffers #243,u,g,n,n,n,u,PM_NO_FETCH_THROTTLE_CYC,Cycles in which no instructions are fetched for this thread because it is being throttled ##0000004088 Cycles in which no instructions are fetched for this thread because it is being throttled #244,u,g,n,n,n,u,PM_FETCH_CYC,Cycles in which instructions are successfully fetched from the instruction cache ##0000004888 Cycles in which instructions are successfully fetched from the instruction cache #245,u,g,n,n,n,u,PM_NO_FETCH_THROTTLE_POWMAN_CYC,Cycles in which the thread is throttled because of power management ##000000408C Cycles in which the thread is throttled because of power management #246,u,g,n,n,n,u,PM_NO_FETCH_THROTTLE_OTHER_CYC,Cycles in which the thread is throttled for a reason other than power management, relative priority and dynamic priority. This includes throttles for speculation for power or performance, independently decided by the IFAR ##000000488C Cycles in which the thread is throttled for a reason other than power management, relative priority and dynamic priority. This includes throttles for speculation for power or performance, independently decided by the IFAR #247,u,g,n,n,n,u,PM_NO_FETCH_THROTTLE_REL_PRIO_CYC,Cycles in which the thread is throttled because of relative priority. This is thread arbitration based on the Relative Priority Register (RPR). ##0000004090 Cycles in which the thread is throttled because of relative priority. This is thread arbitration based on the Relative Priority Register (RPR). #248,u,g,n,n,n,u,PM_NO_FETCH_THROTTLE_DYN_PRIO_CYC,Cycles in which the thread is throttled because of dynamic priority. This is the generic thread arbitration without relative thread priority. A thread may also be throttled if an instruction cache reload for a different thread occurs in the same cycle. ##0000004890 Cycles in which the thread is throttled because of dynamic priority. This is the generic thread arbitration without relative thread priority. A thread may also be throttled if an instruction cache reload for a different thread occurs in the same cycle. #249,u,g,n,n,n,u,PM_DECODE_THROTTLE_IIF_CYC,Cycles in which decode was held for a thread due to an Instruction-In-Flight throttle (WOF). This event will increment regardless of other decode holds being present ##0000004894 Cycles in which decode was held for a thread due to an Instruction-In-Flight throttle (WOF). This event will increment regardless of other decode holds being present #250,u,g,n,n,n,u,PM_DECODE_HOLD_NO_ITAGS,Cycles in which the IFU was not able to decode and transmit one or more instructions because all itags were in use. This means the ICT is full for this thread. This event will only increment when no other hold is present. ##0000004098 Cycles in which the IFU was not able to decode and transmit one or more instructions because all itags were in use. This means the ICT is full for this thread. This event will only increment when no other hold is present. #251,u,g,n,n,n,u,PM_DECODE_THROTTLE_IPC_CYC,Cycles in which decode is throttled because M over N throttle is active (WOF). This event will increment regardless of other decode holds being present ##0000004898 Cycles in which decode is throttled because M over N throttle is active (WOF). This event will increment regardless of other decode holds being present #252,u,g,n,n,n,u,PM_IC_INVALIDATE,A line in the instruction cache has been invalidated by an ICBI ##000000409C A line in the instruction cache has been invalidated by an ICBI #253,u,g,n,n,n,u,PM_IC_RELOAD_PRIVATE,An instruction cache line was brought in private for a specific thread. Most lines are brought in shared for all four threads. ##000000489C An instruction cache line was brought in private for a specific thread. Most lines are brought in shared for all four threads. #254,u,g,n,n,n,u,PM_IC_PREF_REQ,Instruction prefetch requests ##00000040A0 Instruction prefetch requests #255,u,g,n,n,n,u,PM_FUSED_BACK_TO_BACK,Back to back two-cycle execution. Counted at decode time ##00000048A0 Back to back two-cycle execution. Counted at decode time #256,u,g,n,n,n,u,PM_FUSED_DESTRUCTIVE,The first and second instruction have the same target register. Counted at decode time ##00000040A4 The first and second instruction have the same target register. Counted at decode time #257,u,g,n,n,n,u,PM_FUSED_RESULT,Two fused PowerPC (PPC set) instructions: the first PPC instruction, in age order, is the result of the second PPC instruction. Counted at decode time. ##00000048A4 Two fused PowerPC (PPC set) instructions: the first PPC instruction, in age order, is the result of the second PPC instruction. Counted at decode time. #258,u,g,n,n,n,u,PM_FUSED_TOGETHER,Produce 2 results together. Ex instruction having a fusable compare: fabs f3,f1 ##00000040A8 Produce 2 results together. Ex instruction having a fusable compare: fabs f3,f1 #259,u,g,n,n,n,u,PM_FUSED_LOADCOMPARE,Fusion of a load and a compare immediate referencing the load's data. Ex: ldx r3,r1,r2 ##00000048A8 Fusion of a load and a compare immediate referencing the load's data. Ex: ldx r3,r1,r2 #260,u,g,n,n,n,u,PM_FUSED_LOAD_LOAD,Fusion of two displacement loads (meeting the requirements for load-load fusion). ##00000040AC Fusion of two displacement loads (meeting the requirements for load-load fusion). #261,u,g,n,n,n,u,PM_BCQ_FULL_CYC,Cycles in which all 12 entries of the BCQ are full ##00000040B0 Cycles in which all 12 entries of the BCQ are full #262,u,g,n,n,n,u,PM_BR_FIN_FROM_BCQ,Branches that were issued with sources not ready (CR=0), counted at finish time. Branches go to the BCQ when their sources are not ready. ##00000048B0 Branches that were issued with sources not ready (CR=0), counted at finish time. Branches go to the BCQ when their sources are not ready. #263,u,g,n,n,n,u,PM_BR_TKN_FIN,A taken branch (conditional or unconditional) finished ##00000040B4 A taken branch (conditional or unconditional) finished #264,u,g,n,n,n,u,PM_BR_TKN_UNCOND_FIN,An unconditional branch finished. All unconditional branches are taken. ##00000048B4 An unconditional branch finished. All unconditional branches are taken. #265,u,g,n,n,n,u,PM_PRED_BR_TKN_COND_DIR,A conditional branch finished with correctly predicted direction. Resolved taken ##00000040B8 A conditional branch finished with correctly predicted direction. Resolved taken #266,u,g,n,n,n,u,PM_PRED_BR_NTKN_COND_DIR,A conditional branch finished with correctly predicted direction. Resolved not taken ##00000048B8 A conditional branch finished with correctly predicted direction. Resolved not taken #267,u,g,n,n,n,u,PM_MPRED_BR_TKN_COND_DIR,A conditional branch finished with mispredicted direction. Resolved taken ##00000040BC A conditional branch finished with mispredicted direction. Resolved taken #268,u,g,n,n,n,u,PM_MPRED_BR_NTKN_COND_DIR,A conditional branch finished with mispredicted direction. Resolved not taken ##00000048BC A conditional branch finished with mispredicted direction. Resolved not taken #269,u,g,n,n,n,u,PM_PRED_BR_TKN_COND_TGT_DIR,A conditional branch finished with correctly predicted target and direction. Resolved taken ##0000005080 A conditional branch finished with correctly predicted target and direction. Resolved taken #270,u,g,n,n,n,u,PM_PRED_BR_NTKN_COND_TGT_DIR,A conditional branch finished with correctly predicted target and direction. Resolved not taken ##0000005880 A conditional branch finished with correctly predicted target and direction. Resolved not taken #271,u,g,n,n,n,u,PM_MPRED_BR_NTKN_COND_TGT_DIR,A conditional branch finished with mispredicted target and direction. Resolved not taken ##0000005884 A conditional branch finished with mispredicted target and direction. Resolved not taken #272,u,g,n,n,n,u,PM_BR_PRED_TKN_COND_DIR_LBHT_LSEL,A conditional branch finished with correctly predicted direction using the Local Branch History Table selected by the local selector. Resolved taken ##0000005088 A conditional branch finished with correctly predicted direction using the Local Branch History Table selected by the local selector. Resolved taken #273,u,g,n,n,n,u,PM_BR_PRED_TKN_COND_DIR_LBHT_GSEL,A conditional branch finished with correctly predicted direction using the Local Branch History Table selected with the global selector. Resolved taken ##0000005888 A conditional branch finished with correctly predicted direction using the Local Branch History Table selected with the global selector. Resolved taken #274,u,g,n,n,n,u,PM_BR_PRED_TKN_COND_DIR_GBHT,A conditional branch finished with correctly predicted direction using the Global Branch History Table. Resolved taken ##000000508C A conditional branch finished with correctly predicted direction using the Global Branch History Table. Resolved taken #275,u,g,n,n,n,u,PM_BR_PRED_TKN_COND_DIR_TAGE,A conditional branch finished with correctly predicted direction using a TAGE override. Resolved taken ##000000588C A conditional branch finished with correctly predicted direction using a TAGE override. Resolved taken #276,u,g,n,n,n,u,PM_BR_PRED_TKN_COND_DIR_TOP,A conditional branch finished with correctly predicted direction using a TOP override to the BHT. Resolved taken ##0000005090 A conditional branch finished with correctly predicted direction using a TOP override to the BHT. Resolved taken #277,u,g,n,n,n,u,PM_BR_PRED_TKN_COND_TGT_COUNT_LCC,A conditional branch finished with correctly predicted target using the local count cache. Resolved taken ##0000005890 A conditional branch finished with correctly predicted target using the local count cache. Resolved taken #278,u,g,n,n,n,u,PM_BR_PRED_TKN_COND_TGT_COUNT_GCC,A conditional branch finished with correctly predicted target using the global count cache. Resolved taken ##0000005094 A conditional branch finished with correctly predicted target using the global count cache. Resolved taken #279,u,g,n,n,n,u,PM_BR_PRED_TKN_COND_TGT_COUNT_TIP,A conditional branch finished with correctly predicted target using the count TIP override to the count cache. Resolved taken ##0000005894 A conditional branch finished with correctly predicted target using the count TIP override to the count cache. Resolved taken #280,u,g,n,n,n,u,PM_BR_PRED_TKN_TGT_LINK,A conditional or unconditional branch finished with correctly predicted target using the Link register (bclr[l]) and predicted by Link Stack (BH(1)=0). Resolved taken ##0000005098 A conditional or unconditional branch finished with correctly predicted target using the Link register (bclr[l]) and predicted by Link Stack (BH(1)=0). Resolved taken #281,u,g,n,n,n,u,PM_BR_PRED_NTKN_COND_DIR_LBHT_LSEL,A conditional branch finished with correctly predicted direction using the Local Branch History Table selected by the local selector. Resolved not taken ##0000005898 A conditional branch finished with correctly predicted direction using the Local Branch History Table selected by the local selector. Resolved not taken #282,u,g,n,n,n,u,PM_BR_PRED_NTKN_COND_DIR_LBHT_GSEL,A conditional branch finished with correctly predicted direction using the Local Branch History Table selected with the global selector. Resolved not taken ##000000509C A conditional branch finished with correctly predicted direction using the Local Branch History Table selected with the global selector. Resolved not taken #283,u,g,n,n,n,u,PM_BR_PRED_NTKN_COND_DIR_GBHT,A conditional branch finished with correctly predicted direction using the Global Branch History Table. Resolved not taken ##000000589C A conditional branch finished with correctly predicted direction using the Global Branch History Table. Resolved not taken #284,u,g,n,n,n,u,PM_BR_PRED_NTKN_COND_DIR_TAGE,A conditional branch finished with correctly predicted direction using a TAGE override. Resolved not taken ##00000050A0 A conditional branch finished with correctly predicted direction using a TAGE override. Resolved not taken #285,u,g,n,n,n,u,PM_BR_PRED_NTKN_COND_DIR_TOP,A conditional branch finished with correctly predicted direction using a TOP override to the BHT. Resolved not taken ##00000058A0 A conditional branch finished with correctly predicted direction using a TOP override to the BHT. Resolved not taken #286,u,g,n,n,n,u,PM_SHL_CREATED,An Store-Hit-Load Table entry was created as a result of an SHL Flush. ##00000050A4 An Store-Hit-Load Table entry was created as a result of an SHL Flush. #287,u,g,n,n,n,u,PM_SHL_ST_DEPENDENCY,A fetched instruction hit in the Store-Hit-Load Table. ##00000058A4 A fetched instruction hit in the Store-Hit-Load Table. #288,u,g,n,n,n,u,PM_IEADIR_HIT_IDIR_MISS,A fetch hit in the IEADIR but missed in the IDIR. This is usually due to IEADIR aliasing, but could be due to an IDIR invalidate that did not invalidate the corresponding IEADIR entry. ##00000050A8 A fetch hit in the IEADIR but missed in the IDIR. This is usually due to IEADIR aliasing, but could be due to an IDIR invalidate that did not invalidate the corresponding IEADIR entry. #289,u,g,n,n,n,u,PM_ICACHE_MISS_DUE_TO_CTXTTAG,A fetch missed the instruction cache due to a context tag miscompare. All other fields matched. This is similar to PM_IEA_TRACKING_TABLE_WRITE but is not restricted to context tags restricted to IEA Sharing and does not require IEA Sharing to be enabled. ##00000058A8 A fetch missed the instruction cache due to a context tag miscompare. All other fields matched. This is similar to PM_IEA_TRACKING_TABLE_WRITE but is not restricted to context tags restricted to IEA Sharing and does not require IEA Sharing to be enabled. #290,u,g,n,n,n,u,PM_BR_MPRED_TKN_COND_DIR_LBHT_LSEL,A conditional branch finished with mispredicted direction using the Local Branch History Table selected by the local selector. Resolved taken ##00000050AC A conditional branch finished with mispredicted direction using the Local Branch History Table selected by the local selector. Resolved taken #291,u,g,n,n,n,u,PM_BR_MPRED_TKN_COND_DIR_LBHT_GSEL,A conditional branch finished with mispredicted direction using the Local Branch History Table selected with the global selector. Resolved taken ##00000058AC A conditional branch finished with mispredicted direction using the Local Branch History Table selected with the global selector. Resolved taken #292,u,g,n,n,n,u,PM_BR_MPRED_TKN_COND_DIR_GBHT,A conditional branch finished with mispredicted direction using the Global Branch History Table. Resolved taken ##00000050B0 A conditional branch finished with mispredicted direction using the Global Branch History Table. Resolved taken #293,u,g,n,n,n,u,PM_BR_MPRED_TKN_COND_DIR_TAGE,A conditional branch finished with mispredicted direction using a TAGE override. Resolved taken ##00000058B0 A conditional branch finished with mispredicted direction using a TAGE override. Resolved taken #294,u,g,n,n,n,u,PM_BR_MPRED_TKN_COND_DIR_TOP,A conditional branch finished with mispredicted direction using a TOP override to the BHT. Resolved taken ##00000050B4 A conditional branch finished with mispredicted direction using a TOP override to the BHT. Resolved taken #295,u,g,n,n,n,u,PM_BR_MPRED_TKN_COND_TGT_COUNT_LCC,A conditional branch finished with mispredicted target using the local count cache. Resolved taken ##00000058B4 A conditional branch finished with mispredicted target using the local count cache. Resolved taken #296,u,g,n,n,n,u,PM_BR_MPRED_TKN_COND_TGT_COUNT_GCC,A conditional branch finished with mispredicted target using the global count cache. Resolved taken ##00000050B8 A conditional branch finished with mispredicted target using the global count cache. Resolved taken #297,u,g,n,n,n,u,PM_BR_MPRED_TKN_COND_TGT_COUNT_TIP,A conditional branch finished with mispredicted target using the count TIP override to the count cache. Resolved taken ##00000058B8 A conditional branch finished with mispredicted target using the count TIP override to the count cache. Resolved taken #298,u,g,n,n,n,u,PM_BR_MPRED_TKN_TGT_LINK,A conditional or unconditional branch finished with mispredicted target using the Link register. Resolved taken ##00000050BC A conditional or unconditional branch finished with mispredicted target using the Link register. Resolved taken #299,u,g,n,n,n,u,PM_BR_MPRED_NTKN_COND_DIR_LBHT_LSEL,A conditional branch finished with mispredicted direction using the Local Branch History Table selected by the local selector. Resolved not taken ##00000058BC A conditional branch finished with mispredicted direction using the Local Branch History Table selected by the local selector. Resolved not taken #300,u,g,n,n,n,u,PM_BR_MPRED_NTKN_COND_DIR_LBHT_GSEL,A conditional branch finished with mispredicted direction using the Local Branch History Table selected with the global selector. Resolved not taken ##000000E080 A conditional branch finished with mispredicted direction using the Local Branch History Table selected with the global selector. Resolved not taken #301,u,g,n,n,n,u,PM_BR_MPRED_NTKN_COND_DIR_GBHT,A conditional branch finished with mispredicted direction using the Global Branch History Table. Resolved not taken ##000000E880 A conditional branch finished with mispredicted direction using the Global Branch History Table. Resolved not taken #302,u,g,n,n,n,u,PM_BR_MPRED_NTKN_COND_DIR_TAGE,A conditional branch finished with mispredicted direction using a TAGE override. Resolved not taken ##000000E084 A conditional branch finished with mispredicted direction using a TAGE override. Resolved not taken #303,u,g,n,n,n,u,PM_BR_MPRED_NTKN_COND_DIR_TOP,A conditional branch finished with mispredicted direction using a TOP override to the BHT. Resolved not taken ##000000E884 A conditional branch finished with mispredicted direction using a TOP override to the BHT. Resolved not taken #304,u,g,n,n,n,u,PM_IEA_ALIAS_TABLE_WRITE,IFU EA Sharing was detected and the sharing info was written to the IFU Alias Table. ##000000E088 IFU EA Sharing was detected and the sharing info was written to the IFU Alias Table. #305,u,g,n,n,n,u,PM_IEA_ALIAS_TABLE_HIT,Instruction cache reload hit on the Alias Table and was written to the ICache as an IEA Shared entry. ##000000E888 Instruction cache reload hit on the Alias Table and was written to the ICache as an IEA Shared entry. #306,u,g,n,n,n,u,PM_IEA_TRACKING_TABLE_WRITE,Instruction cache miss occurred where ICache EA Sharing may be possible. i.e. All IDIR fields matched except the context tag and the incumbent context tag is compatible with IEA Sharing. ##000000E08C Instruction cache miss occurred where ICache EA Sharing may be possible. i.e. All IDIR fields matched except the context tag and the incumbent context tag is compatible with IEA Sharing. #307,u,g,n,n,n,u,PM_IEA_ICACHE_SHARED_HIT,Instruction cache hit occurred on an entry that is marked as IEA Sharing. This does not include ICache reload bypasses. ##000000E88C Instruction cache hit occurred on an entry that is marked as IEA Sharing. This does not include ICache reload bypasses. #308,u,g,n,n,n,u,PM_BR_BTAC_INV_TGT,BTAC predicts a target that is different from what the BHT and count cache predict. The BTAC entry is invalidated. Reported at fetch time ##000000E890 BTAC predicts a target that is different from what the BHT and count cache predict. The BTAC entry is invalidated. Reported at fetch time #309,u,g,n,n,n,u,PM_BR_BTAC_INV_DIR,BTAC predicts taken for a branch that the BHT predicts not taken, so that BTAC entry is invalidated. Reported at fetch time ##000000E094 BTAC predicts taken for a branch that the BHT predicts not taken, so that BTAC entry is invalidated. Reported at fetch time #310,u,g,n,n,n,u,PM_BR_PRED_COND_BTAC,A conditional branch finished with correctly predicted target or direction using the BTAC. Reported at fetch time ##000000E894 A conditional branch finished with correctly predicted target or direction using the BTAC. Reported at fetch time #311,u,g,n,n,n,u,PM_MPRED_BR_FIN,A conditional branch mispredicted its direction or target address. Counted at finish time ##000000E098 A conditional branch mispredicted its direction or target address. Counted at finish time #312,u,g,n,n,n,u,PM_BR_PRED_TKN_SWHINT,A software hinted branch finished and the branch resolved taken and the hint was correct. ##000000E898 A software hinted branch finished and the branch resolved taken and the hint was correct. #313,u,g,n,n,n,u,PM_BR_PRED_NTKN_SWHINT,A software hinted branch finished and the branch resolved not taken and the hint was correct. ##000000E09C A software hinted branch finished and the branch resolved not taken and the hint was correct. #314,u,g,n,n,n,u,PM_BR_MPRED_TKN_SWHINT,A software hinted branch finished and the branch resolved taken and the hint was incorrect. ##000000E89C A software hinted branch finished and the branch resolved taken and the hint was incorrect. #315,u,g,n,n,n,u,PM_BR_MPRED_NTKN_SWHINT,A software hinted branch finished and the branch resolved not taken and the hint was incorrect. ##000000E0A0 A software hinted branch finished and the branch resolved not taken and the hint was incorrect. #316,u,g,n,n,n,u,PM_BACK_BRANCH,Branch whose target address is lower than the program counter ##000000E0A4 Branch whose target address is lower than the program counter #317,u,g,n,n,n,u,PM_TLB_ACCESS_L3PREF,Incoming L3 prefetches that access the TLB (there is no L3 instruction prefetching in POWER10). L3 prefetches access the TLB directly, without accessing the ERAT ##0000008080 Incoming L3 prefetches that access the TLB (there is no L3 instruction prefetching in POWER10). L3 prefetches access the TLB directly, without accessing the ERAT #318,u,g,n,n,n,u,PM_TLB_CHILD_PURGE_CYC,Cycles spent in a TLB scrub. Counted for radix or HPT translations. Implies a parent eviction ##0000008880 Cycles spent in a TLB scrub. Counted for radix or HPT translations. Implies a parent eviction #319,u,g,n,n,n,u,PM_REJ_MMU,The MMU rejects a translation for any reason. This includes loads/stores/ifetches. ##0000008884 The MMU rejects a translation for any reason. This includes loads/stores/ifetches. #320,u,g,n,n,n,u,PM_REJ_EXEC_NTC_SLEEP_SELECT,The operation is rejected because it must be NTC to translate. This includes loads/stores/ifetches. ##0000008088 The operation is rejected because it must be NTC to translate. This includes loads/stores/ifetches. #321,u,g,n,n,n,u,PM_RDXWALK_INSTR_CYC,Cycles when an instruction(MMU type fetch) tablewalk is active. ##000000808C Cycles when an instruction(MMU type fetch) tablewalk is active. #322,u,g,n,n,n,u,PM_RDXWALK_DATA_CYC,Data Tablewalk Cycles. Cycles in which at least one tablewalk is in progress. This event includes data, demand and prefetch(MMU type LD, ST, L1 Prefetch). There can be up to 4 tablewalks in one cycle. ##000000888C Data Tablewalk Cycles. Cycles in which at least one tablewalk is in progress. This event includes data, demand and prefetch(MMU type LD, ST, L1 Prefetch). There can be up to 4 tablewalks in one cycle. #323,u,g,n,n,n,u,PM_REJ_TABLEWALK_L2_PDE_MERGE,A translation is rejected on a level 2 PDE boundary. This is only valid for radix. This is when the incoming translation matches on the 1G address boundary, but not a 2M address boundary. ##0000008090 A translation is rejected on a level 2 PDE boundary. This is only valid for radix. This is when the incoming translation matches on the 1G address boundary, but not a 2M address boundary. #324,u,g,n,n,n,u,PM_REJ_TABLEWALK_L3_PDE_MERGE,A translation is rejected on a level 3 PDE boundary. This is when the incoming translation matches on the 2M address boundary, but not the 64k address boundary. This is only valid in radix translations. ##0000008890 A translation is rejected on a level 3 PDE boundary. This is when the incoming translation matches on the 2M address boundary, but not the 64k address boundary. This is only valid in radix translations. #325,u,g,n,n,n,u,PM_REJ_TABLEWALK_PTE_MERGE,A translation is rejected on a PTE boundary. This indicates that the table walk merged due to a full 4k or 64k address match. This is valid for both Radix and HPT. In HPT this is both the parent hit, child miss case, and the parent miss case. ##0000008094 A translation is rejected on a PTE boundary. This indicates that the table walk merged due to a full 4k or 64k address match. This is valid for both Radix and HPT. In HPT this is both the parent hit, child miss case, and the parent miss case. #326,u,g,n,n,m,u,PM_MRK_DTABLEWALK_CYC,Cycles a data(MMU type LD, ST, L1 PF) tablewalk is in progress for a marked instruction. ##0000008894 Cycles a data(MMU type LD, ST, L1 PF) tablewalk is in progress for a marked instruction. #327,u,g,n,n,n,u,PM_XLATE_HPT_MODE_CYC,MMU reports every cycle the thread is in HPT translation mode (as opposed to radix mode) ##0000008098 MMU reports every cycle the thread is in HPT translation mode (as opposed to radix mode) #328,u,g,n,n,n,u,PM_XLATE_RADIX_MODE_CYC,MMU reports every cycle the thread is in radix translation mode (as opposed to HPT mode) ##0000008898 MMU reports every cycle the thread is in radix translation mode (as opposed to HPT mode) #329,u,g,n,n,n,u,PM_XLATE_L2_REQ,The MMU requested a line from L2 for translation. It may be satisfied from L2 and beyond. Includes speculative instructions. Includes instruction, prefetch and demand. ##000000809C The MMU requested a line from L2 for translation. It may be satisfied from L2 and beyond. Includes speculative instructions. Includes instruction, prefetch and demand. #330,u,g,n,n,n,u,PM_RDXTLB_ANY_NSTD_ANY_HST_HIT,Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup. If this event increments, one and only one of the following must also increment: PM_RDXTLB_ANY_NSTD_64K_HST_HIT, PM_RDXTLB_ANY_NSTD_2M_HST_HIT, or PM_RDXTLB_ANY_NSTD_1G_HST_HIT ##00000080A0 Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup. If this event increments, one and only one of the following must also increment: PM_RDXTLB_ANY_NSTD_64K_HST_HIT, PM_RDXTLB_ANY_NSTD_2M_HST_HIT, or PM_RDXTLB_ANY_NSTD_1G_HST_HIT #331,u,g,n,n,n,u,PM_RDXTLB_ANY_NSTD_4K_HST_HIT,Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup w/ the 4K page size. Due to P10 microarchitecture, this event will never increment. ##00000088A0 Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup w/ the 4K page size. Due to P10 microarchitecture, this event will never increment. #332,u,g,n,n,n,u,PM_RDXTLB_ANY_NSTD_64K_HST_HIT,Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup w/ the 64K page size. ##00000080A4 Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup w/ the 64K page size. #333,u,g,n,n,n,u,PM_RDXTLB_ANY_NSTD_2M_HST_HIT,Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup w/ the 2M page size. ##00000088A4 Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup w/ the 2M page size. #334,u,g,n,n,n,u,PM_RDXTLB_ANY_NSTD_1G_HST_HIT,Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup w/ the 1G page size. ##00000080A8 Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup w/ the 1G page size. #335,u,g,n,n,n,u,PM_RDXTLB_ANY_NSTD_ACC,Qualified as nested radix translations. There was a TLB lookup for any nested radix partition scoped translation. ##00000088A8 Qualified as nested radix translations. There was a TLB lookup for any nested radix partition scoped translation. #336,u,g,n,n,n,u,PM_RDXTLB_ANY_NSTD_MISS,Qualified as nested radix translations. There was a complete TLB miss on any intermediate TLB lookup. ##00000080AC Qualified as nested radix translations. There was a complete TLB miss on any intermediate TLB lookup. #337,u,g,n,n,n,u,PM_SNOOP_TLBIE_ARB_CYC,Cycles the MMU is in the process of arbitrating an incoming TLBIE snoop, but the snoop has not yet acquired the MML lock. ##0000009080 Cycles the MMU is in the process of arbitrating an incoming TLBIE snoop, but the snoop has not yet acquired the MML lock. #338,u,g,n,n,n,u,PM_SNOOP_TLBIE_TLB_INV_CYC,Cycles the MMU is in the process of walking the TLB for a TLBIE. From the time the probe is installed to the time the probe is uninstalled. ##0000009880 Cycles the MMU is in the process of walking the TLB for a TLBIE. From the time the probe is installed to the time the probe is uninstalled. #339,u,g,n,n,n,u,PM_SNOOP_TLBIE_NOT_MY_LPAR_CONTEXT_TABLE_HIT_CYC,Total duration of the snoop TLBIE when there is a context table hit, but a not-my-lpar (LSU is counting my-lpar case). ##0000009084 Total duration of the snoop TLBIE when there is a context table hit, but a not-my-lpar (LSU is counting my-lpar case). #340,u,g,n,n,n,u,PM_SNOOP_TLBIE_NOT_MY_LPAR_CONTEXT_TABLE_MISS_CYC,Total duration of the snoop TLBIE when there is a context table miss. ##0000009884 Total duration of the snoop TLBIE when there is a context table miss. #341,u,g,n,n,n,u,PM_SNOOP_TLBIE,Total number of TLBIE snoops ##0000009088 Total number of TLBIE snoops #342,u,g,n,n,n,u,PM_DTLB_ACCESS_ERAT_MISS,The TLB was read to satisfy a load or store ERAT miss. This includes demands and L1 prefetching data(MMU type LD, ST, L1PF) ##000000908C The TLB was read to satisfy a load or store ERAT miss. This includes demands and L1 prefetching data(MMU type LD, ST, L1PF) #343,u,g,n,n,n,u,PM_ITLB_ACCESS_ERAT_MISS,The TLB was read to satisfy an instruction ERAT miss. This includes demands and L1 prefetching for instruction (MMU Type Fetch) ##000000988C The TLB was read to satisfy an instruction ERAT miss. This includes demands and L1 prefetching for instruction (MMU Type Fetch) #344,u,g,n,n,n,u,PM_HPTWALK_INSTR_CYC,Cycles when an instruction tablewalk is active. This is qualified for HPT translations. ##0000009090 Cycles when an instruction tablewalk is active. This is qualified for HPT translations. #345,u,g,n,n,n,u,PM_HPTWALK_DATA_CYC,Data Tablewalk Cycles. Cycles in which at least one tablewalk is in progress. This event includes data and instruction, demand and prefetch. There can be up to 4 tablewalks in one cycle. (MMU Type LD, ST, L1PF) ##0000009890 Data Tablewalk Cycles. Cycles in which at least one tablewalk is in progress. This event includes data and instruction, demand and prefetch. There can be up to 4 tablewalks in one cycle. (MMU Type LD, ST, L1PF) #346,u,g,n,n,n,u,PM_REJ_PROBE_MATCH_PRS0,A load/store, fetch, or prefetch was rejected because it matched on a partition scoped probe. This is set for both Radix and HPT ##0000009094 A load/store, fetch, or prefetch was rejected because it matched on a partition scoped probe. This is set for both Radix and HPT #347,u,g,n,n,n,u,PM_REJ_PROBE_MATCH_PRS1,A load/store, fetch, or prefetch was rejected because it matched on a process scoped probe. This is Radix only ##0000009894 A load/store, fetch, or prefetch was rejected because it matched on a process scoped probe. This is Radix only #348,u,g,n,n,n,u,PM_REJ_PROBE_MATCH_MML,A load/store, fetch, or prefetch was rejected because it matched on the MML lock. This is set for both Radix and HPT ##0000009098 A load/store, fetch, or prefetch was rejected because it matched on the MML lock. This is set for both Radix and HPT #349,u,g,n,n,n,u,PM_REJ_PIPE_COLLISION_2ND_RELOAD,A load/store or fetch was rejected because there was a collision in the MMU pipeline with a 2nd pass & a reload. ##0000009898 A load/store or fetch was rejected because there was a collision in the MMU pipeline with a 2nd pass & a reload. #350,u,g,n,n,n,u,PM_REJ_XMQ_FULL,A translation was rejected because the MMU was full. ##000000909C A translation was rejected because the MMU was full. #351,u,g,n,n,n,u,PM_BLOCK_ERAT_WRITE,A valid translation reloaded the ERAT with block write enabled. ##000000989C A valid translation reloaded the ERAT with block write enabled. #352,u,g,n,n,n,u,PM_2ND_PASS_RADIX,The 2nd pass for Radix was initiated. ##00000090A0 The 2nd pass for Radix was initiated. #353,u,g,n,n,n,u,PM_2ND_PASS_HPT,The 2nd pass for HPT was initiated. This doesn't include VA hash mispredicts. ##00000098A0 The 2nd pass for HPT was initiated. This doesn't include VA hash mispredicts. #354,u,g,n,n,n,u,PM_VA_HASH_MPRED,The 1st pass for HPT was rejected due to VA hash mispredicts. ##00000090A4 The 1st pass for HPT was rejected due to VA hash mispredicts. #355,u,g,n,n,n,u,PM_CHILD_PURGE_HIT,Total amount of congruence classes that found at least 1 invalidation match for a child purge. ##000000A080 Total amount of congruence classes that found at least 1 invalidation match for a child purge. #356,u,g,n,n,n,u,PM_TLBIE_INV_CC_PRS0_COMPOSITE_CHILD_HASH,Congruence classes that found at least 1 invalidation match for a partition scoped hash match. ##000000A084 Congruence classes that found at least 1 invalidation match for a partition scoped hash match. #357,u,g,n,n,n,u,PM_TLBIE_INV_CC_PRS0_COMPOSITE_PARENT_HASH,Congruence classes that found at least 1 invalidation match for a partition scoped parent hash match. ##000000A884 Congruence classes that found at least 1 invalidation match for a partition scoped parent hash match. #358,u,g,n,n,n,u,PM_TLBIE_INV_ATTEMPT_CC_PRS0_COMPOSITE_CHILD,A partition scoped child hash invalidation was sent to the TLB. ##000000A088 A partition scoped child hash invalidation was sent to the TLB. #359,u,g,n,n,n,u,PM_TLBIE_INV_ATTEMPT_CC_PRS0_COMPOSITE_PARENT,A partition scoped parent hash invalidation was sent to the TLB. ##000000A888 A partition scoped parent hash invalidation was sent to the TLB. #360,u,g,n,n,n,u,PM_TLBIE_INV_ATTEMPT_HPT_PRECISE,Precise TLBIES sent to TLB in HPT. ##000000A08C Precise TLBIES sent to TLB in HPT. #361,u,g,n,n,n,u,PM_TLBIE_INV_CC_HPT_PRECISE,Precise TLBIEs sent to TLB for HPT invalidations and had at least 1 matching entry in the congruence class. ##000000A88C Precise TLBIEs sent to TLB for HPT invalidations and had at least 1 matching entry in the congruence class. #362,u,g,n,n,n,u,PM_CASE_A_HIT_MTPID,mtpid instruction found a Case A Context Table Hit. ##000000A090 mtpid instruction found a Case A Context Table Hit. #363,u,g,n,n,n,u,PM_CASE_A_HIT_MTLPID,mtlpid instruction found a Case A Context Table Hit. ##000000A890 mtlpid instruction found a Case A Context Table Hit. #364,u,g,n,n,n,u,PM_CASE_B_HIT_MTLPID,A mtlpid instruction found a Case B Context table hit. ##000000A094 A mtlpid instruction found a Case B Context table hit. #365,u,g,n,n,n,u,PM_CASE_C_HIT_MTPID,A mtpid instruction found a Case C Context table hit. ##000000A894 A mtpid instruction found a Case C Context table hit. #366,u,g,n,n,n,u,PM_CASE_A_MISS_MTPID,A mtpid instruction found a Case A context table miss ##000000A098 A mtpid instruction found a Case A context table miss #367,u,g,n,n,n,u,PM_CASE_A_MISS_MTLPID,A mtlpid instruction found a Case A Context table miss ##000000A898 A mtlpid instruction found a Case A Context table miss #368,u,g,n,n,n,u,PM_CASE_B_MISS_MTLPID,A mtlpid instruction found a Case B Context table miss ##000000A09C A mtlpid instruction found a Case B Context table miss #369,u,g,n,n,n,u,PM_CASE_C_MISS_MTPID,A mtpid instruction found a Case C Context table miss. ##000000A89C A mtpid instruction found a Case C Context table miss. #370,u,g,n,n,n,u,PM_MTPID,The thread executed a mtpid instruction. ##000000A0A0 The thread executed a mtpid instruction. #371,u,g,n,n,n,u,PM_MTLPID,The thread executed a mtlpid instruction. ##000000A8A0 The thread executed a mtlpid instruction. #372,u,g,n,n,n,u,PM_CASE_A_SNOOP_TLBIE_HIT,A snoop hit on a Case A context tag. ##000000A0A4 A snoop hit on a Case A context tag. #373,u,g,n,n,n,u,PM_CASE_B_SNOOP_TLBIE_HIT,A snoop hit on a Case B Context tag. ##000000A8A4 A snoop hit on a Case B Context tag. #374,u,g,n,n,n,u,PM_CASE_C_SNOOP_TLBIE_HIT,A snoop hit on a Case C context tag. ##000000A0A8 A snoop hit on a Case C context tag. #375,u,g,n,n,n,u,PM_CASE_D_SNOOP_TLBIE_HIT,A snoop hit on a Case D context tag. ##000000A8A8 A snoop hit on a Case D context tag. #376,u,g,n,n,n,u,PM_SNOOP_TLBIE_NOT_MY_LPAR_CONTEXT_TABLE_HIT,A snoop found a not-my-lpar but found a context table hit. ##000000A0AC A snoop found a not-my-lpar but found a context table hit. #377,u,g,n,n,n,u,PM_SNOOP_TLBIE_NOT_MY_LPAR_CONTEXT_TABLE_MISS,A snoop found a not-my-lpar but found a context table miss. ##000000A8AC A snoop found a not-my-lpar but found a context table miss. #378,u,g,n,n,n,u,PM_LPAR_SNOOP_HIT,A snoop found a "my-lpar" match. ##000000A0B0 A snoop found a "my-lpar" match. #379,u,g,n,n,n,u,PM_L3_CO_MEM,L3 CO to memory. L3 castout a line to memory and it was accepted (CRESP=good) by the memory controller. Lossy - increments only once when two CO's receive CRESP=good simultaneously, thus may undercount. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##100000026080 L3 CO to memory. L3 castout a line to memory and it was accepted (CRESP=good) by the memory controller. Lossy - increments only once when two CO's receive CRESP=good simultaneously, thus may undercount. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #380,u,g,n,n,n,u,PM_L3_CO_L31,L3 CO to L3.1 Lossy. L3 castout a line as an LCO (L3.1) and it was accepted (CRESP=good) by a destination L3. Lossy - increments only once when two LCO receive CRESP=good simultaneously, thus may undercount. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##100000026880 L3 CO to L3.1 Lossy. L3 castout a line as an LCO (L3.1) and it was accepted (CRESP=good) by a destination L3. Lossy - increments only once when two LCO receive CRESP=good simultaneously, thus may undercount. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #381,u,g,n,n,n,u,PM_L3_CI_HIT,L3 Castins hit L3. L3 inserted a line due to an L2 castout, an incoming LCO or a successful L3PF and the line was already in the L3 (a "hit"). Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##110000026080 L3 Castins hit L3. L3 inserted a line due to an L2 castout, an incoming LCO or a successful L3PF and the line was already in the L3 (a "hit"). Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #382,u,g,n,n,n,u,PM_L3_CI_MISS,L3 castins miss L3. L3 inserted a line due to an L2 castout, an incoming LCO or a successful L3PF and the line was new to the L3 (a "miss"). Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##110000026880 L3 castins miss L3. L3 inserted a line due to an L2 castout, an incoming LCO or a successful L3PF and the line was new to the L3 (a "miss"). Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #383,u,g,n,n,n,u,PM_L3_LD_HIT,L3 Hits for for loads, but not stores. Any L2 load (but not store) that hits in the L3, including data load, instruction load or translate load. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##120000026080 L3 Hits for for loads, but not stores. Any L2 load (but not store) that hits in the L3, including data load, instruction load or translate load. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #384,u,g,n,n,n,u,PM_L3_LD_MISS,L3 Misses for loads, but not stores. Any L2 load (but not store) to the L3 that misses in the L3, including data load, instruction load or translate load. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##120000026880 L3 Misses for loads, but not stores. Any L2 load (but not store) to the L3 that misses in the L3, including data load, instruction load or translate load. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #385,u,g,n,n,n,u,PM_NON_TM_RST_SC,Non-TM snoop hits line in L3 that is TM_SC state and causes it to be invalidated. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##130000026080 Non-TM snoop hits line in L3 that is TM_SC state and causes it to be invalidated. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #386,u,g,n,n,n,u,PM_TM_RST_SC,TM snoop hits line in L3 that is TM_SC state and causes it to be invalidated. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##130000026880 TM snoop hits line in L3 that is TM_SC state and causes it to be invalidated. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #387,u,g,n,n,n,u,PM_L3_PF_HIT_L3,L3 PF hit in L3 (abandoned). Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##140000026080 L3 PF hit in L3 (abandoned). Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #388,u,g,n,n,n,u,PM_RD_HIT_PF,L3 RD machine hit L3 PF machine. L3 RD machine, which is running an L2 read, including data load and store, instruction load or translate load, hit an active L3 prefetch machine. Thus an L2 read occurred before the previously queued L3 prefetch request completed. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##140000026880 L3 RD machine hit L3 PF machine. L3 RD machine, which is running an L2 read, including data load and store, instruction load or translate load, hit an active L3 prefetch machine. Thus an L2 read occurred before the previously queued L3 prefetch request completed. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #389,u,g,n,n,n,u,PM_L3_P0_LCO_DATA,LCO sent with data port 0. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##150000026080 LCO sent with data port 0. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #390,u,g,n,n,n,u,PM_L3_P1_LCO_DATA,LCO sent with data port 1. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##150000026880 LCO sent with data port 1. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #391,u,g,n,n,n,u,PM_L3_PF_USAGE,Rotating sample of 48 PF actives. Increments when selected L3 PF machine is active. Every 48 clocks, switches among the 48 PF machines. Thus, indicates overall utilization of the PF machines. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##160000026080 Rotating sample of 48 PF actives. Increments when selected L3 PF machine is active. Every 48 clocks, switches among the 48 PF machines. Thus, indicates overall utilization of the PF machines. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #392,u,g,n,n,n,u,PM_L3_RD_USAGE,Rotating sample of 16 RD actives. Increments when selected L3 RD machine is active. Every 48 clocks, switches among the 16 RD machines. Thus, indicates overall utilization of the RD machines. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##160000026880 Rotating sample of 16 RD actives. Increments when selected L3 RD machine is active. Every 48 clocks, switches among the 16 RD machines. Thus, indicates overall utilization of the RD machines. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #393,u,g,n,n,n,u,PM_L3_P2_PF_RTY,L3 PF received retry on fabric CRESP port 2, every retry counted. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##170000026080 L3 PF received retry on fabric CRESP port 2, every retry counted. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #394,u,g,n,n,n,u,PM_L3_P3_PF_RTY,L3 PF received retry on fabric CRESP port 3, every retry counted. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##170000026880 L3 PF received retry on fabric CRESP port 3, every retry counted. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #395,u,g,n,n,n,u,PM_L3_P0_GRP_PUMP,L3 PF sent with grp or nn scope from PF machine 0-23, counts even retried requests. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##180000026080 L3 PF sent with grp or nn scope from PF machine 0-23, counts even retried requests. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #396,u,g,n,n,n,u,PM_L3_P1_GRP_PUMP,L3 PF sent with grp or nn scope from PF machine 24-47, counts even retried requests. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##180000026880 L3 PF sent with grp or nn scope from PF machine 24-47, counts even retried requests. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #397,u,g,n,n,n,u,PM_L3_SYS_GUESS_CORRECT,L3 Prefetch scope predictor selected VGS or RNS and was correct. Increments when data received for L3 PF machine 0 or 24. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##190000026080 L3 Prefetch scope predictor selected VGS or RNS and was correct. Increments when data received for L3 PF machine 0 or 24. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #398,u,g,n,n,n,u,PM_L3_LOC_GUESS_WRONG,L3 Prefetch scope predictor selected LNS, but was wrong. Increments when data received for L3 PF machine 0 or 24. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##190000026880 L3 Prefetch scope predictor selected LNS, but was wrong. Increments when data received for L3 PF machine 0 or 24. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #399,u,g,n,n,n,u,PM_L3_P2_LCO_RTY,L3 initiated LCO received retry on fabric CRESP port 2 (can try 4 times). Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##1A0000026080 L3 initiated LCO received retry on fabric CRESP port 2 (can try 4 times). Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #400,u,g,n,n,n,u,PM_L3_P3_LCO_RTY,L3 initiated LCO received retry on fabric CRESP port 3 (can try 4 times). Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##1A0000026880 L3 initiated LCO received retry on fabric CRESP port 3 (can try 4 times). Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #401,u,g,n,n,n,u,PM_L3_WI0_BUSY,Rotating sample of 16 WI valid. Increments when selected L3 WI machine is valid. Every 48 clocks, switches among the 16 WI machines. Thus, indicates overall utilization of the WI machines. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##1B0000026080 Rotating sample of 16 WI valid. Increments when selected L3 WI machine is valid. Every 48 clocks, switches among the 16 WI machines. Thus, indicates overall utilization of the WI machines. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #402,u,g,n,n,n,u,PM_L2_LD_MISS,All successful D-Side Load dispatches for this thread that missed in the L2. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##000000026080 All successful D-Side Load dispatches for this thread that missed in the L2. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #403,u,g,n,n,n,u,PM_L2_ST_MISS,All successful D-Side Store dispatches for this thread that missed in the L2. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##000000026880 All successful D-Side Store dispatches for this thread that missed in the L2. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #404,u,g,n,n,n,u,PM_L2_IC_INV,Instruction cache invalidates sent over the reload bus to the core. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##010000026080 Instruction cache invalidates sent over the reload bus to the core. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #405,u,g,n,n,n,u,PM_L2_DC_INV,Data cache invalidates sent over the reload bus to the core. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##010000026880 Data cache invalidates sent over the reload bus to the core. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #406,u,g,n,n,n,u,PM_L2_ST_HIT,All successful D-side store dispatches for this thread that were L2 hits. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##0F0000026880 All successful D-side store dispatches for this thread that were L2 hits. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #407,u,g,n,n,n,u,PM_L2_ISIDE_DSIDE_FAIL_OTHER,All D-side-Ld or I-side-instruction-fetch dispatch attempts for this thread that failed due to reasons other than an address collision conflicts with an L2 machine (e.g. Read-Claim/Snoop machine not available). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##020000026080 All D-side-Ld or I-side-instruction-fetch dispatch attempts for this thread that failed due to reasons other than an address collision conflicts with an L2 machine (e.g. Read-Claim/Snoop machine not available). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #408,u,g,n,n,n,u,PM_L2_CO_TM_SC_FOOTPRINT,L2 did a cleanifdirty CO to the L3 (ie created an SC line in the L3) OR L2 TM_store hit dirty HPC line and L3 indicated SC line formed in L3 on RDR bus. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##030000026080 L2 did a cleanifdirty CO to the L3 (ie created an SC line in the L3) OR L2 TM_store hit dirty HPC line and L3 indicated SC line formed in L3 on RDR bus. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #409,u,g,n,n,n,u,PM_L2_GRP_GUESS_CORRECT,L2 guess grp (GS or NNS) and guess was correct (data intra-group AND ^on-chip). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##040000026080 L2 guess grp (GS or NNS) and guess was correct (data intra-group AND ^on-chip). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #410,u,g,n,n,n,u,PM_L2_GRP_GUESS_WRONG,L2 guess grp (GS or NNS) and guess was not correct (ie data on-chip OR beyond-group). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##040000026880 L2 guess grp (GS or NNS) and guess was not correct (ie data on-chip OR beyond-group). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #411,u,g,n,n,n,u,PM_ISIDE_FAIL_ADDR,All I-side-instruction-fetch dispatch attempts for this thread that failed due to an address collision conflict with an L2 machine already working on this line (e.g. ld-hit-stq or RC/CO/SN machines). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##050000026080 All I-side-instruction-fetch dispatch attempts for this thread that failed due to an address collision conflict with an L2 machine already working on this line (e.g. ld-hit-stq or RC/CO/SN machines). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #412,u,g,n,n,n,u,PM_ISIDE_FAIL_OTHER,All I-side-instruction-fetch dispatch attempts for this thread that failed due to reasons other than an address collision conflict with an L2 machine (e.g. no available RC/CO machines). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##050000026880 All I-side-instruction-fetch dispatch attempts for this thread that failed due to reasons other than an address collision conflict with an L2 machine (e.g. no available RC/CO machines). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #413,u,g,n,n,n,u,PM_L2_RC0_BUSY,RC mach 0 Busy. Used by PMU to sample ave RC lifetime (mach0 used as sample point). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##060000026080 RC mach 0 Busy. Used by PMU to sample ave RC lifetime (mach0 used as sample point). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #414,u,g,n,n,n,u,PM_L2_CO_USAGE,Continuous 16 cycle (2to1) window where this signals rotates thru sampling each CO machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##060000026880 Continuous 16 cycle (2to1) window where this signals rotates thru sampling each CO machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #415,u,g,n,n,n,u,PM_TM_LD_FAIL,TM Load (fav or non-fav) ran into conflict (failed). Event count should be multiplied by 2 since the data is coming from a 2:1 clock domain and the data is time sliced across all 4 threads. ##070000026080 TM Load (fav or non-fav) ran into conflict (failed). Event count should be multiplied by 2 since the data is coming from a 2:1 clock domain and the data is time sliced across all 4 threads. #416,u,g,n,n,n,u,PM_TM_FAV_CAUSED_FAIL,TM Load (fav) caused another thread to fail. Event count should be multiplied by 2 since the data is coming from a 2:1 clock domain and the data is time sliced across all 4 threads. ##070000026880 TM Load (fav) caused another thread to fail. Event count should be multiplied by 2 since the data is coming from a 2:1 clock domain and the data is time sliced across all 4 threads. #417,u,g,n,n,n,u,PM_L2_SN0_BUSY,SN mach 0 Busy. Used by PMU to sample ave SN lifetime (mach0 used as sample point). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##080000026080 SN mach 0 Busy. Used by PMU to sample ave SN lifetime (mach0 used as sample point). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #418,u,g,n,n,n,u,PM_L2_ISIDE_READ,Valid when first beat of data comes in for an I-side fetch where data came from memory or L4. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##080000026880 Valid when first beat of data comes in for an I-side fetch where data came from memory or L4. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #419,u,g,n,n,n,u,PM_L2_ISIDE_DSIDE_ST_SUCCESS,All D-side-Ld, D-side-St or I-side-instruction-fetch successful dispatches for this thread. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##090000026080 All D-side-Ld, D-side-St or I-side-instruction-fetch successful dispatches for this thread. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #420,u,g,n,n,n,u,PM_L2_TM_FOOTPR_OVERFLOW_ST,One TM thread was running and Store footprint was lost due to capacity Cast Out or full TMDIR/LVDIR. Event count should be multiplied by 2 since the data is coming from a 2:1 clock domain and the data is time sliced across all 4 threads. ##0A0000026080 One TM thread was running and Store footprint was lost due to capacity Cast Out or full TMDIR/LVDIR. Event count should be multiplied by 2 since the data is coming from a 2:1 clock domain and the data is time sliced across all 4 threads. #421,u,g,n,n,n,u,PM_L2_TM_FOOTPR_LD_LINES,Total number of Load Footprint cachelines formed. Divide this cnt by PM_L2_TM_END to get average Ld footprint size. Counts stop when thread gets DeadThreadWalking for two reasons: 1) once a thread TM Overflows, each Ld/St attempt would otherwise inflate this cnt 2) useful to get size cap size of footprint at point transaction first failed(ie Overflow fails) to get a sense of if other threads were present Event count should be multiplied by 2 since the data is coming from a 2:1 clock domain and the data is time sliced across all 4 threads. ##0A0000026880 Total number of Load Footprint cachelines formed. Divide this cnt by PM_L2_TM_END to get average Ld footprint size. Counts stop when thread gets DeadThreadWalking for two reasons: 1) once a thread TM Overflows, each Ld/St attempt would otherwise inflate this cnt 2) useful to get size cap size of footprint at point transaction first failed(ie Overflow fails) to get a sense of if other threads were present Event count should be multiplied by 2 since the data is coming from a 2:1 clock domain and the data is time sliced across all 4 threads. #422,u,g,n,n,n,u,PM_L2_SNP_TLBIE_SLBIE_START,The NCU Snooper snooped a TLBIE/SLBIEG/SLBIAG operation that targets this thread's LPAR and has sent it to the core. Event count should be multiplied by 2 since the data is coming from a 2:1 clock domain and the data is time sliced across all 4 threads. ##0B0000026080 The NCU Snooper snooped a TLBIE/SLBIEG/SLBIAG operation that targets this thread's LPAR and has sent it to the core. Event count should be multiplied by 2 since the data is coming from a 2:1 clock domain and the data is time sliced across all 4 threads. #423,u,g,n,n,n,u,PM_L2_SNP_TLBIE_SLBIE_DELAY,Cycles when a TLBIE/SLBIEG/SLBIAG that targets this thread's LPAR was in flight while in a hottemp condition. Multiply this count by 1000 to obtain the total number of cycles. This can be divided by PM_L2_SNP_TLBIE_SLBIE_START to obtain the overall efficiency. Note: ’inflight’ means SnpTLB has been sent to core(ie doesn’t include when SnpTLB is in NCU waiting to be launched serially behind different SnpTLB). The NCU Snooper gets in a ’hottemp’ delay window when it detects it is above its TLBIE/SLBIE threshold for process SnpTLBIE/SLBIE with this core. Event count should be multiplied by 2 since the data is coming from a 2:1 clock domain and the data is time sliced across all 4 threads. ##0B0000026880 Cycles when a TLBIE/SLBIEG/SLBIAG that targets this thread's LPAR was in flight while in a hottemp condition. Multiply this count by 1000 to obtain the total number of cycles. This can be divided by PM_L2_SNP_TLBIE_SLBIE_START to obtain the overall efficiency. Note: ’inflight’ means SnpTLB has been sent to core(ie doesn’t include when SnpTLB is in NCU waiting to be launched serially behind different SnpTLB). The NCU Snooper gets in a ’hottemp’ delay window when it detects it is above its TLBIE/SLBIE threshold for process SnpTLBIE/SLBIE with this core. Event count should be multiplied by 2 since the data is coming from a 2:1 clock domain and the data is time sliced across all 4 threads. #424,u,g,n,n,n,u,PM_ST_DATA_FROM_L21_L31,Store data line missed in the local chiplet and was found in a neighbor L2 or L3 (on-chip L2/L3 intervention). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##0C0000026080 Store data line missed in the local chiplet and was found in a neighbor L2 or L3 (on-chip L2/L3 intervention). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #425,u,g,n,n,n,u,PM_ST_DATA_FROM_LMEM,Store data line missed in the local chiplet and was found in local memory. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##0C0000026880 Store data line missed in the local chiplet and was found in local memory. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #426,u,g,n,n,n,u,PM_L2_LD_HIT,All successful D-side-Ld or I-side-instruction-fetch dispatches for this thread that were L2 hits. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##0F0000026080 All successful D-side-Ld or I-side-instruction-fetch dispatches for this thread that were L2 hits. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #427,u,g,n,n,n,u,PM_DATA_RADIX_PROCESS_L2_PTE_FROM_L3,A data Page Table Entry was reloaded to a level 2 page walk cache from the core's L3 data cache due to a process scoped demand miss. ##000000000024242 A data Page Table Entry was reloaded to a level 2 page walk cache from the core's L3 data cache due to a process scoped demand miss. #428,u,g,n,n,n,u,PM_DATA_RADIX_PROCESS_L2_PDE_FROM_L3,A data Page Directory Entry was reloaded to a level 2 page walk cache from the core's L3 data cache due to a process scoped demand miss. ##000000000024244 A data Page Directory Entry was reloaded to a level 2 page walk cache from the core's L3 data cache due to a process scoped demand miss. #429,u,g,n,n,n,u,PM_DATA_RADIX_PROCESS_L3_PTE_FROM_L3,A data Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 data cache due to a process scoped demand miss. ##000000000024246 A data Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 data cache due to a process scoped demand miss. #430,u,g,n,n,n,u,PM_DATA_RADIX_PROCESS_L3_PDE_FROM_L3,A data Page Directory Entry was reloaded to a level 3 page walk cache from the core's L3 data cache due to a process scoped demand miss. ##000000000024248 A data Page Directory Entry was reloaded to a level 3 page walk cache from the core's L3 data cache due to a process scoped demand miss. #431,u,g,n,n,n,u,PM_DATA_RADIX_PROCESS_L4_PTE_FROM_L3,A data Page Table Entry was reloaded to a level 4 page walk cache from the core's L3 data cache due to a process scoped demand miss. ##00000000002424A A data Page Table Entry was reloaded to a level 4 page walk cache from the core's L3 data cache due to a process scoped demand miss. #432,u,g,n,n,n,u,PM_INST_RADIX_PROCESS_L2_PTE_FROM_L3,An instruction Page Table Entry was reloaded to a level 2 page walk cache from the core's L3 data cache due to a process scoped demand miss. ##00000000002424E An instruction Page Table Entry was reloaded to a level 2 page walk cache from the core's L3 data cache due to a process scoped demand miss. #433,u,g,n,n,n,u,PM_INST_RADIX_PROCESS_L3_PTE_FROM_L3,An instruction Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 data cache due to a process scoped demand miss. ##000000000025242 An instruction Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 data cache due to a process scoped demand miss. #434,u,g,n,n,n,u,PM_INST_RADIX_PROCESS_L3_PDE_FROM_L3,An instruction Page Directory Entry was reloaded to a level 3 page walk cache from the core's L3 data cache due to a process scoped demand miss. ##000000000025244 An instruction Page Directory Entry was reloaded to a level 3 page walk cache from the core's L3 data cache due to a process scoped demand miss. #435,u,g,n,n,n,u,PM_INST_RADIX_PROCESS_L4_PTE_FROM_L3,An instruction Page Table Entry was reloaded to a level 4 page walk cache from the core's L3 data cache due to a process scoped demand miss. ##000000000025246 An instruction Page Table Entry was reloaded to a level 4 page walk cache from the core's L3 data cache due to a process scoped demand miss. #436,u,g,n,n,n,u,PM_DATA_RADIX_PROCESS_L2_PTE_FROM_L3_ALL,A data Page Table Entry was reloaded to a level 2 page walk cache from the core's L3 data cache due to a process scoped demand or prefetch miss. ##000000000224242 A data Page Table Entry was reloaded to a level 2 page walk cache from the core's L3 data cache due to a process scoped demand or prefetch miss. #437,u,g,n,n,n,u,PM_DATA_RADIX_PROCESS_L2_PDE_FROM_L3_ALL,A data Page Directory Entry was reloaded to a level 2 page walk cache from the core's L3 data cache due to a process scoped demand or prefetch miss. ##000000000224244 A data Page Directory Entry was reloaded to a level 2 page walk cache from the core's L3 data cache due to a process scoped demand or prefetch miss. #438,u,g,n,n,n,u,PM_DATA_RADIX_PROCESS_L3_PTE_FROM_L3_ALL,A data Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 data cache due to a process scoped demand or prefetch miss. ##000000000224246 A data Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 data cache due to a process scoped demand or prefetch miss. #439,u,g,n,n,n,u,PM_DATA_RADIX_PROCESS_L3_PDE_FROM_L3_ALL,A data Page Directory Entry was reloaded to a level 3 page walk cache from the core's L3 data cache due to a process scoped demand or prefetch miss. ##000000000224248 A data Page Directory Entry was reloaded to a level 3 page walk cache from the core's L3 data cache due to a process scoped demand or prefetch miss. #440,u,g,n,n,n,u,PM_DATA_RADIX_PROCESS_L4_PTE_FROM_L3_ALL,A data Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 data cache due to a process scoped demand or prefetch miss. ##00000000022424A A data Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 data cache due to a process scoped demand or prefetch miss. #441,u,g,n,n,n,u,PM_INST_RADIX_PROCESS_L2_PTE_FROM_L3_ALL,An instruction Page Table Entry was reloaded to a level 2 page walk cache from the core's L3 data cache due to a process scoped demand or prefetch miss. ##00000000012424E An instruction Page Table Entry was reloaded to a level 2 page walk cache from the core's L3 data cache due to a process scoped demand or prefetch miss. #442,u,g,n,n,n,u,PM_INST_RADIX_PROCESS_L3_PTE_FROM_L3_ALL,An instruction Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 data cache due to a process scoped demand or prefetch miss. ##000000000125242 An instruction Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 data cache due to a process scoped demand or prefetch miss. #443,u,g,n,n,n,u,PM_INST_RADIX_PROCESS_L3_PDE_FROM_L3_ALL,An instruction Page Directory Entry was reloaded to a level 3 page walk cache from the core's L3 data cache due to a process scoped demand or prefetch miss. ##000000000125244 An instruction Page Directory Entry was reloaded to a level 3 page walk cache from the core's L3 data cache due to a process scoped demand or prefetch miss. #444,u,g,n,n,n,u,PM_INST_RADIX_PROCESS_L4_PTE_FROM_L3_ALL,An instruction Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 data cache due to a process scoped demand or prefetch miss. ##000000000125246 An instruction Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 data cache due to a process scoped demand or prefetch miss. #445,u,g,n,n,n,u,PM_INST_FROM_L2,The processor's instruction cache was reloaded from the local core's L2 due to a demand miss. ##000300000002C040 The processor's instruction cache was reloaded from the local core's L2 due to a demand miss. #446,u,g,n,n,n,u,PM_IPTEG_FROM_L2,The processor's instruction page table entry was reloaded from the local core's L2 due to a demand miss. ##000320000002C040 The processor's instruction page table entry was reloaded from the local core's L2 due to a demand miss. #447,u,g,n,n,n,u,PM_DATA_FROM_L2,The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss. ##000340000002C040 The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss. #448,u,g,n,n,n,u,PM_DPTEG_FROM_L2,The processor's data page table entry was reloaded from the local core's L2 due to a demand miss. ##000360000002C040 The processor's data page table entry was reloaded from the local core's L2 due to a demand miss. #449,u,g,n,n,n,u,PM_INST_FROM_L2_ALL,The processor's instruction cache was reloaded from the local core's L2 due to a demand miss or prefetch reload. ##000300000012C040 The processor's instruction cache was reloaded from the local core's L2 due to a demand miss or prefetch reload. #450,u,g,n,n,n,u,PM_IPTEG_FROM_L2_ALL,The processor's instruction page table entry was reloaded from the local core's L2 due to a demand miss or prefetch reload. ##000320000012C040 The processor's instruction page table entry was reloaded from the local core's L2 due to a demand miss or prefetch reload. #451,u,g,n,n,n,u,PM_DATA_FROM_L2_ALL,The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss or prefetch reload. ##000340000022C040 The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss or prefetch reload. #452,u,g,n,n,n,u,PM_DPTEG_FROM_L2_ALL,The processor's data page table entry was reloaded from the local core's L2 due to a demand miss or prefetch reload. ##000360000022C040 The processor's data page table entry was reloaded from the local core's L2 due to a demand miss or prefetch reload. #453,u,g,n,n,n,u,PM_INST_FROM_L1MISS,The processor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss. ##003F00000002C040 The processor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss. #454,u,g,n,n,n,u,PM_IPTEG_FROM_L1MISS,The processor's instruction page table entry was reloaded from a source beyond the local core's L1 due to a demand miss. ##003F20000002C040 The processor's instruction page table entry was reloaded from a source beyond the local core's L1 due to a demand miss. #455,u,g,n,n,n,u,PM_DATA_FROM_L1MISS,The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss. ##003F40000002C040 The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss. #456,u,g,n,n,n,u,PM_DPTEG_FROM_L1MISS,The processor's data page table entry was reloaded from a source beyond the local core's L1 due to a demand miss. ##003F60000002C040 The processor's data page table entry was reloaded from a source beyond the local core's L1 due to a demand miss. #457,u,g,n,n,n,u,PM_INST_FROM_L1MISS_ALL,The processor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. ##003F00000012C040 The processor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. #458,u,g,n,n,n,u,PM_IPTEG_FROM_L1MISS_ALL,The processor's instruction page table entry was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. ##003F20000012C040 The processor's instruction page table entry was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. #459,u,g,n,n,n,u,PM_DATA_FROM_L1MISS_ALL,The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. ##003F40000022C040 The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. #460,u,g,n,n,n,u,PM_DPTEG_FROM_L1MISS_ALL,The processor's data page table entry was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. ##003F60000022C040 The processor's data page table entry was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. #461,u,g,n,n,n,u,PM_IPTEG_FROM_L2_NO_CONFLICT,The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. ##000020000002C040 The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. #462,u,g,n,n,n,u,PM_DATA_FROM_L2_NO_CONFLICT,The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. ##000040000002C040 The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. #463,u,g,n,n,n,u,PM_DPTEG_FROM_L2_NO_CONFLICT,The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. ##000060000002C040 The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. #464,u,g,n,n,n,u,PM_IPTEG_FROM_L2_NO_CONFLICT_ALL,The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. ##000020000012C040 The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. #465,u,g,n,n,n,u,PM_DATA_FROM_L2_NO_CONFLICT_ALL,The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. ##000040000022C040 The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. #466,u,g,n,n,n,u,PM_DPTEG_FROM_L2_NO_CONFLICT_ALL,The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. ##000060000022C040 The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. #467,u,g,n,n,n,u,PM_IPTEG_FROM_L2_MEPF,The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. ##004020000002C040 The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. #468,u,g,n,n,n,u,PM_DATA_FROM_L2_MEPF,The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. ##004040000002C040 The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. #469,u,g,n,n,n,u,PM_DPTEG_FROM_L2_MEPF,The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. ##004060000002C040 The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. #470,u,g,n,n,n,u,PM_IPTEG_FROM_L2_MEPF_ALL,The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. ##004020000012C040 The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. #471,u,g,n,n,n,u,PM_DATA_FROM_L2_MEPF_ALL,The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. ##004040000022C040 The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. #472,u,g,n,n,n,u,PM_DPTEG_FROM_L2_MEPF_ALL,The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. ##004060000022C040 The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. #473,u,g,n,n,n,u,PM_IPTEG_FROM_L2_LDHITST_CONFLICT,The processor's instruction page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. ##008020000002C040 The processor's instruction page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. #474,u,g,n,n,n,u,PM_DATA_FROM_L2_LDHITST_CONFLICT,The processor's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. ##008040000002C040 The processor's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. #475,u,g,n,n,n,u,PM_DPTEG_FROM_L2_LDHITST_CONFLICT,The processor's data page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. ##008060000002C040 The processor's data page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. #476,u,g,n,n,n,u,PM_IPTEG_FROM_L2_LDHITST_CONFLICT_ALL,The processor's instruction page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. ##008020000012C040 The processor's instruction page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. #477,u,g,n,n,n,u,PM_DATA_FROM_L2_LDHITST_CONFLICT_ALL,The processor's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. ##008040000022C040 The processor's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. #478,u,g,n,n,n,u,PM_DPTEG_FROM_L2_LDHITST_CONFLICT_ALL,The processor's data page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. ##008060000022C040 The processor's data page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. #479,u,g,n,n,n,u,PM_IPTEG_FROM_L2_OTHER_CONFLICT,The processor's instruction page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. ##00C020000002C040 The processor's instruction page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. #480,u,g,n,n,n,u,PM_DATA_FROM_L2_OTHER_CONFLICT,The processor's L1 data cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. ##00C040000002C040 The processor's L1 data cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. #481,u,g,n,n,n,u,PM_DPTEG_FROM_L2_OTHER_CONFLICT,The processor's data page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. ##00C060000002C040 The processor's data page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. #482,u,g,n,n,n,u,PM_IPTEG_FROM_L2_OTHER_CONFLICT_ALL,The processor's instruction page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. ##00C020000012C040 The processor's instruction page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. #483,u,g,n,n,n,u,PM_DATA_FROM_L2_OTHER_CONFLICT_ALL,The processor's L1 data cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. ##00C040000022C040 The processor's L1 data cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. #484,u,g,n,n,n,u,PM_DPTEG_FROM_L2_OTHER_CONFLICT_ALL,The processor's data page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. ##00C060000022C040 The processor's data page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. #485,u,g,n,n,n,u,PM_INST_FROM_L2MISS,The processor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss. ##000380000002C040 The processor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss. #486,u,g,n,n,n,u,PM_IPTEG_FROM_L2MISS,The processor's instruction page table entry was reloaded from a source beyond the local core's L2 due to a demand miss. ##0003A0000002C040 The processor's instruction page table entry was reloaded from a source beyond the local core's L2 due to a demand miss. #487,u,g,n,n,n,u,PM_DPTEG_FROM_L2MISS,The processor's data page table entry was reloaded from a source beyond the local core's L2 due to a demand miss. ##0003E0000002C040 The processor's data page table entry was reloaded from a source beyond the local core's L2 due to a demand miss. #488,u,g,n,n,n,u,PM_INST_FROM_L2MISS_ALL,The processor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. ##000380000012C040 The processor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. #489,u,g,n,n,n,u,PM_IPTEG_FROM_L2MISS_ALL,The processor's instruction page table entry was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. ##0003A0000012C040 The processor's instruction page table entry was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. #490,u,g,n,n,n,u,PM_DATA_FROM_L2MISS_ALL,The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. ##0003C0000022C040 The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. #491,u,g,n,n,n,u,PM_DPTEG_FROM_L2MISS_ALL,The processor's data page table entry was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. ##0003E0000022C040 The processor's data page table entry was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. #492,u,g,n,n,n,u,PM_INST_FROM_L3,The processor's instruction cache was reloaded from the local core's L3 due to a demand miss. ##010300000002C040 The processor's instruction cache was reloaded from the local core's L3 due to a demand miss. #493,u,g,n,n,n,u,PM_IPTEG_FROM_L3,The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss. ##010320000002C040 The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss. #494,u,g,n,n,n,u,PM_DATA_FROM_L3,The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss. ##010340000002C040 The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss. #495,u,g,n,n,n,u,PM_DPTEG_FROM_L3,The processor's data page table entry was reloaded from the local core's L3 due to a demand miss. ##010360000002C040 The processor's data page table entry was reloaded from the local core's L3 due to a demand miss. #496,u,g,n,n,n,u,PM_INST_FROM_L3_ALL,The processor's instruction cache was reloaded from the local core's L3 due to a demand miss or prefetch reload. ##010300000012C040 The processor's instruction cache was reloaded from the local core's L3 due to a demand miss or prefetch reload. #497,u,g,n,n,n,u,PM_IPTEG_FROM_L3_ALL,The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload. ##010320000012C040 The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload. #498,u,g,n,n,n,u,PM_DATA_FROM_L3_ALL,The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload. ##010340000022C040 The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload. #499,u,g,n,n,n,u,PM_DPTEG_FROM_L3_ALL,The processor's data page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload. ##010360000022C040 The processor's data page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload. #500,u,g,n,n,n,u,PM_IPTEG_FROM_L3_NO_CONFLICT,The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. ##010020000002C040 The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. #501,u,g,n,n,n,u,PM_DATA_FROM_L3_NO_CONFLICT,The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. ##010040000002C040 The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. #502,u,g,n,n,n,u,PM_DPTEG_FROM_L3_NO_CONFLICT,The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. ##010060000002C040 The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. #503,u,g,n,n,n,u,PM_IPTEG_FROM_L3_NO_CONFLICT_ALL,The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. ##010020000012C040 The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. #504,u,g,n,n,n,u,PM_DATA_FROM_L3_NO_CONFLICT_ALL,The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. ##010040000022C040 The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. #505,u,g,n,n,n,u,PM_DPTEG_FROM_L3_NO_CONFLICT_ALL,The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. ##010060000022C040 The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. #506,u,g,n,n,n,u,PM_IPTEG_FROM_L3_MEPF,The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. ##014020000002C040 The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. #507,u,g,n,n,n,u,PM_DATA_FROM_L3_MEPF,The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. ##014040000002C040 The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. #508,u,g,n,n,n,u,PM_DPTEG_FROM_L3_MEPF,The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. ##014060000002C040 The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. #509,u,g,n,n,n,u,PM_IPTEG_FROM_L3_MEPF_ALL,The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. ##014020000012C040 The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. #510,u,g,n,n,n,u,PM_DATA_FROM_L3_MEPF_ALL,The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. ##014040000022C040 The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. #511,u,g,n,n,n,u,PM_DPTEG_FROM_L3_MEPF_ALL,The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. ##014060000022C040 The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. #512,u,g,n,n,n,u,PM_IPTEG_FROM_L3_CONFLICT,The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss. ##01C020000002C040 The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss. #513,u,g,n,n,n,u,PM_DATA_FROM_L3_CONFLICT,The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss. ##01C040000002C040 The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss. #514,u,g,n,n,n,u,PM_DPTEG_FROM_L3_CONFLICT,The processor's data page table entry was reloaded from the local core's L3 due to a demand miss. ##01C060000002C040 The processor's data page table entry was reloaded from the local core's L3 due to a demand miss. #515,u,g,n,n,n,u,PM_IPTEG_FROM_L3_CONFLICT_ALL,The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload. ##01C020000012C040 The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload. #516,u,g,n,n,n,u,PM_DATA_FROM_L3_CONFLICT_ALL,The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload. ##01C040000022C040 The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload. #517,u,g,n,n,n,u,PM_DPTEG_FROM_L3_CONFLICT_ALL,The processor's data page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload. ##01C060000022C040 The processor's data page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload. #518,u,g,n,n,n,u,PM_IPTEG_FROM_L3MISS,The processor's instruction page table entry was reloaded from beyond the local core's L3 due to a demand miss. ##0007A0000002C040 The processor's instruction page table entry was reloaded from beyond the local core's L3 due to a demand miss. #519,u,g,n,n,n,u,PM_DPTEG_FROM_L3MISS,The processor's data page table entry was reloaded from beyond the local core's L3 due to a demand miss. ##0007E0000002C040 The processor's data page table entry was reloaded from beyond the local core's L3 due to a demand miss. #520,u,g,n,n,n,u,PM_INST_FROM_L3MISS_ALL,The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. ##000780000012C040 The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. #521,u,g,n,n,n,u,PM_IPTEG_FROM_L3MISS_ALL,The processor's instruction page table entry was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. ##0007A0000012C040 The processor's instruction page table entry was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. #522,u,g,n,n,n,u,PM_DATA_FROM_L3MISS_ALL,The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. ##0007C0000022C040 The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. #523,u,g,n,n,n,u,PM_DPTEG_FROM_L3MISS_ALL,The processor's data page table entry was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. ##0007E0000022C040 The processor's data page table entry was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. #524,u,g,n,n,n,u,PM_IPTEG_FROM_L21_REGENT_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. ##080020000002C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. #525,u,g,n,n,n,u,PM_DATA_FROM_L21_REGENT_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. ##080040000002C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. #526,u,g,n,n,n,u,PM_DPTEG_FROM_L21_REGENT_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. ##080060000002C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. #527,u,g,n,n,n,u,PM_IPTEG_FROM_L21_REGENT_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. ##080020000012C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. #528,u,g,n,n,n,u,PM_DATA_FROM_L21_REGENT_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. ##080040000022C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. #529,u,g,n,n,n,u,PM_DPTEG_FROM_L21_REGENT_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. ##080060000022C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. #530,u,g,n,n,n,u,PM_IPTEG_FROM_L21_REGENT_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. ##084020000002C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. #531,u,g,n,n,n,u,PM_DATA_FROM_L21_REGENT_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. ##084040000002C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. #532,u,g,n,n,n,u,PM_DPTEG_FROM_L21_REGENT_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. ##084060000002C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. #533,u,g,n,n,n,u,PM_IPTEG_FROM_L21_REGENT_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. ##084020000012C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. #534,u,g,n,n,n,u,PM_DATA_FROM_L21_REGENT_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. ##084040000022C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. #535,u,g,n,n,n,u,PM_DPTEG_FROM_L21_REGENT_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. ##084060000022C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. #536,u,g,n,n,n,u,PM_INST_FROM_L21_REGENT,The processor's instruction cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. ##080100000002C040 The processor's instruction cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. #537,u,g,n,n,n,u,PM_IPTEG_FROM_L21_REGENT,The processor's instruction page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. ##080120000002C040 The processor's instruction page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. #538,u,g,n,n,n,u,PM_DATA_FROM_L21_REGENT,The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. ##080140000002C040 The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. #539,u,g,n,n,n,u,PM_DPTEG_FROM_L21_REGENT,The processor's data page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. ##080160000002C040 The processor's data page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. #540,u,g,n,n,n,u,PM_INST_FROM_L21_REGENT_ALL,The processor's instruction cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. ##080100000012C040 The processor's instruction cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. #541,u,g,n,n,n,u,PM_IPTEG_FROM_L21_REGENT_ALL,The processor's instruction page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. ##080120000012C040 The processor's instruction page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. #542,u,g,n,n,n,u,PM_DATA_FROM_L21_REGENT_ALL,The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. ##080140000022C040 The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. #543,u,g,n,n,n,u,PM_DPTEG_FROM_L21_REGENT_ALL,The processor's data page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. ##080160000022C040 The processor's data page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. #544,u,g,n,n,n,u,PM_IPTEG_FROM_L31_REGENT_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. ##088020000002C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. #545,u,g,n,n,n,u,PM_DATA_FROM_L31_REGENT_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. ##088040000002C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. #546,u,g,n,n,n,u,PM_DPTEG_FROM_L31_REGENT_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. ##088060000002C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. #547,u,g,n,n,n,u,PM_IPTEG_FROM_L31_REGENT_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##088020000012C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. #548,u,g,n,n,n,u,PM_DATA_FROM_L31_REGENT_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##088040000022C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. #549,u,g,n,n,n,u,PM_DPTEG_FROM_L31_REGENT_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##088060000022C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. #550,u,g,n,n,n,u,PM_IPTEG_FROM_L31_REGENT_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. ##08C020000002C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. #551,u,g,n,n,n,u,PM_DATA_FROM_L31_REGENT_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. ##08C040000002C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. #552,u,g,n,n,n,u,PM_DPTEG_FROM_L31_REGENT_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. ##08C060000002C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. #553,u,g,n,n,n,u,PM_IPTEG_FROM_L31_REGENT_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##08C020000012C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. #554,u,g,n,n,n,u,PM_DATA_FROM_L31_REGENT_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##08C040000022C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. #555,u,g,n,n,n,u,PM_DPTEG_FROM_L31_REGENT_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##08C060000022C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. #556,u,g,n,n,n,u,PM_INST_FROM_L31_REGENT,The processor's instruction cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. ##088100000002C040 The processor's instruction cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. #557,u,g,n,n,n,u,PM_IPTEG_FROM_L31_REGENT,The processor's instruction page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. ##088120000002C040 The processor's instruction page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. #558,u,g,n,n,n,u,PM_DATA_FROM_L31_REGENT,The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. ##088140000002C040 The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. #559,u,g,n,n,n,u,PM_DPTEG_FROM_L31_REGENT,The processor's data page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. ##088160000002C040 The processor's data page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. #560,u,g,n,n,n,u,PM_INST_FROM_L31_REGENT_ALL,The processor's instruction cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##088100000012C040 The processor's instruction cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. #561,u,g,n,n,n,u,PM_IPTEG_FROM_L31_REGENT_ALL,The processor's instruction page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##088120000012C040 The processor's instruction page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. #562,u,g,n,n,n,u,PM_DATA_FROM_L31_REGENT_ALL,The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##088140000022C040 The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. #563,u,g,n,n,n,u,PM_DPTEG_FROM_L31_REGENT_ALL,The processor's data page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##088160000022C040 The processor's data page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. #564,u,g,n,n,n,u,PM_IPTEG_FROM_REGENT_L2L3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. ##080220000002C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. #565,u,g,n,n,n,u,PM_DATA_FROM_REGENT_L2L3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. ##080240000002C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. #566,u,g,n,n,n,u,PM_DPTEG_FROM_REGENT_L2L3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. ##080260000002C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. #567,u,g,n,n,n,u,PM_IPTEG_FROM_REGENT_L2L3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##080220000012C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. #568,u,g,n,n,n,u,PM_DATA_FROM_REGENT_L2L3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##080240000022C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. #569,u,g,n,n,n,u,PM_DPTEG_FROM_REGENT_L2L3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##080260000022C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. #570,u,g,n,n,n,u,PM_IPTEG_FROM_REGENT_L2L3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. ##084220000002C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. #571,u,g,n,n,n,u,PM_DATA_FROM_REGENT_L2L3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. ##084240000002C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. #572,u,g,n,n,n,u,PM_DPTEG_FROM_REGENT_L2L3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. ##084260000002C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. #573,u,g,n,n,n,u,PM_IPTEG_FROM_REGENT_L2L3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##084220000012C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. #574,u,g,n,n,n,u,PM_DATA_FROM_REGENT_L2L3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##084240000022C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. #575,u,g,n,n,n,u,PM_DPTEG_FROM_REGENT_L2L3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##084260000022C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. #576,u,g,n,n,n,u,PM_INST_FROM_REGENT_L2L3,The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. ##080300000002C040 The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. #577,u,g,n,n,n,u,PM_IPTEG_FROM_REGENT_L2L3,The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. ##080320000002C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. #578,u,g,n,n,n,u,PM_DATA_FROM_REGENT_L2L3,The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. ##080340000002C040 The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. #579,u,g,n,n,n,u,PM_DPTEG_FROM_REGENT_L2L3,The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. ##080360000002C040 The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. #580,u,g,n,n,n,u,PM_INST_FROM_REGENT_L2L3_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##080300000012C040 The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. #581,u,g,n,n,n,u,PM_IPTEG_FROM_REGENT_L2L3_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##080320000012C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. #582,u,g,n,n,n,u,PM_DATA_FROM_REGENT_L2L3_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##080340000022C040 The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. #583,u,g,n,n,n,u,PM_DPTEG_FROM_REGENT_L2L3_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##080360000022C040 The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. #584,u,g,n,n,n,u,PM_IPTEG_FROM_L21_NON_REGENT_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. ##0A0020000002C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. #585,u,g,n,n,n,u,PM_DATA_FROM_L21_NON_REGENT_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. ##0A0040000002C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. #586,u,g,n,n,n,u,PM_DPTEG_FROM_L21_NON_REGENT_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. ##0A0060000002C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. #587,u,g,n,n,n,u,PM_IPTEG_FROM_L21_NON_REGENT_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0020000012C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. #588,u,g,n,n,n,u,PM_DATA_FROM_L21_NON_REGENT_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0040000022C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. #589,u,g,n,n,n,u,PM_DPTEG_FROM_L21_NON_REGENT_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0060000022C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. #590,u,g,n,n,n,u,PM_IPTEG_FROM_L21_NON_REGENT_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. ##0A4020000002C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. #591,u,g,n,n,n,u,PM_DATA_FROM_L21_NON_REGENT_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. ##0A4040000002C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. #592,u,g,n,n,n,u,PM_DPTEG_FROM_L21_NON_REGENT_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. ##0A4060000002C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. #593,u,g,n,n,n,u,PM_IPTEG_FROM_L21_NON_REGENT_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A4020000012C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. #594,u,g,n,n,n,u,PM_DATA_FROM_L21_NON_REGENT_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A4040000022C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. #595,u,g,n,n,n,u,PM_DPTEG_FROM_L21_NON_REGENT_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A4060000022C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. #596,u,g,n,n,n,u,PM_INST_FROM_L21_NON_REGENT,The processor's instruction cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. ##0A0100000002C040 The processor's instruction cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. #597,u,g,n,n,n,u,PM_IPTEG_FROM_L21_NON_REGENT,The processor's instruction page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. ##0A0120000002C040 The processor's instruction page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. #598,u,g,n,n,n,u,PM_DATA_FROM_L21_NON_REGENT,The processor's L1 data cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. ##0A0140000002C040 The processor's L1 data cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. #599,u,g,n,n,n,u,PM_DPTEG_FROM_L21_NON_REGENT,The processor's data page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. ##0A0160000002C040 The processor's data page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. #600,u,g,n,n,n,u,PM_INST_FROM_L21_NON_REGENT_ALL,The processor's instruction cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0100000012C040 The processor's instruction cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. #601,u,g,n,n,n,u,PM_IPTEG_FROM_L21_NON_REGENT_ALL,The processor's instruction page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0120000012C040 The processor's instruction page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. #602,u,g,n,n,n,u,PM_DATA_FROM_L21_NON_REGENT_ALL,The processor's L1 data cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0140000022C040 The processor's L1 data cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. #603,u,g,n,n,n,u,PM_DPTEG_FROM_L21_NON_REGENT_ALL,The processor's data page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0160000022C040 The processor's data page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. #604,u,g,n,n,n,u,PM_IPTEG_FROM_L31_NON_REGENT_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. ##0A8020000002C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. #605,u,g,n,n,n,u,PM_DATA_FROM_L31_NON_REGENT_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. ##0A8040000002C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. #606,u,g,n,n,n,u,PM_DPTEG_FROM_L31_NON_REGENT_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. ##0A8060000002C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. #607,u,g,n,n,n,u,PM_IPTEG_FROM_L31_NON_REGENT_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A8020000012C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. #608,u,g,n,n,n,u,PM_DATA_FROM_L31_NON_REGENT_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A8040000022C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. #609,u,g,n,n,n,u,PM_DPTEG_FROM_L31_NON_REGENT_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A8060000022C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. #610,u,g,n,n,n,u,PM_IPTEG_FROM_L31_NON_REGENT_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. ##0AC020000002C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. #611,u,g,n,n,n,u,PM_DATA_FROM_L31_NON_REGENT_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. ##0AC040000002C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. #612,u,g,n,n,n,u,PM_DPTEG_FROM_L31_NON_REGENT_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. ##0AC060000002C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. #613,u,g,n,n,n,u,PM_IPTEG_FROM_L31_NON_REGENT_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0AC020000012C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. #614,u,g,n,n,n,u,PM_DATA_FROM_L31_NON_REGENT_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0AC040000022C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. #615,u,g,n,n,n,u,PM_DPTEG_FROM_L31_NON_REGENT_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0AC060000022C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. #616,u,g,n,n,n,u,PM_INST_FROM_L31_NON_REGENT,The processor's instruction cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. ##0A8100000002C040 The processor's instruction cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. #617,u,g,n,n,n,u,PM_IPTEG_FROM_L31_NON_REGENT,The processor's instruction page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. ##0A8120000002C040 The processor's instruction page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. #618,u,g,n,n,n,u,PM_DATA_FROM_L31_NON_REGENT,The processor's L1 data cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. ##0A8140000002C040 The processor's L1 data cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. #619,u,g,n,n,n,u,PM_DPTEG_FROM_L31_NON_REGENT,The processor's data page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. ##0A8160000002C040 The processor's data page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. #620,u,g,n,n,n,u,PM_INST_FROM_L31_NON_REGENT_ALL,The processor's instruction cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A8100000012C040 The processor's instruction cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. #621,u,g,n,n,n,u,PM_IPTEG_FROM_L31_NON_REGENT_ALL,The processor's instruction page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A8120000012C040 The processor's instruction page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. #622,u,g,n,n,n,u,PM_DATA_FROM_L31_NON_REGENT_ALL,The processor's L1 data cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A8140000022C040 The processor's L1 data cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. #623,u,g,n,n,n,u,PM_DPTEG_FROM_L31_NON_REGENT_ALL,The processor's data page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A8160000022C040 The processor's data page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. #624,u,g,n,n,n,u,PM_IPTEG_FROM_NON_REGENT_L2L3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. ##0A0220000002C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. #625,u,g,n,n,n,u,PM_DATA_FROM_NON_REGENT_L2L3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. ##0A0240000002C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. #626,u,g,n,n,n,u,PM_DPTEG_FROM_NON_REGENT_L2L3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. ##0A0260000002C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. #627,u,g,n,n,n,u,PM_IPTEG_FROM_NON_REGENT_L2L3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0220000012C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. #628,u,g,n,n,n,u,PM_DATA_FROM_NON_REGENT_L2L3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0240000022C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. #629,u,g,n,n,n,u,PM_DPTEG_FROM_NON_REGENT_L2L3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0260000022C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. #630,u,g,n,n,n,u,PM_IPTEG_FROM_NON_REGENT_L2L3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. ##0A4220000002C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. #631,u,g,n,n,n,u,PM_DATA_FROM_NON_REGENT_L2L3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. ##0A4240000002C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. #632,u,g,n,n,n,u,PM_DPTEG_FROM_NON_REGENT_L2L3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. ##0A4260000002C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. #633,u,g,n,n,n,u,PM_IPTEG_FROM_NON_REGENT_L2L3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A4220000012C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. #634,u,g,n,n,n,u,PM_DATA_FROM_NON_REGENT_L2L3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A4240000022C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. #635,u,g,n,n,n,u,PM_DPTEG_FROM_NON_REGENT_L2L3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A4260000022C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. #636,u,g,n,n,n,u,PM_INST_FROM_NON_REGENT_L2L3,The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. ##0A0300000002C040 The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. #637,u,g,n,n,n,u,PM_IPTEG_FROM_NON_REGENT_L2L3,The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. ##0A0320000002C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. #638,u,g,n,n,n,u,PM_DATA_FROM_NON_REGENT_L2L3,The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. ##0A0340000002C040 The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. #639,u,g,n,n,n,u,PM_DPTEG_FROM_NON_REGENT_L2L3,The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. ##0A0360000002C040 The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. #640,u,g,n,n,n,u,PM_INST_FROM_NON_REGENT_L2L3_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0300000012C040 The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. #641,u,g,n,n,n,u,PM_IPTEG_FROM_NON_REGENT_L2L3_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0320000012C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. #642,u,g,n,n,n,u,PM_DATA_FROM_NON_REGENT_L2L3_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0340000022C040 The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. #643,u,g,n,n,n,u,PM_DPTEG_FROM_NON_REGENT_L2L3_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0360000022C040 The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. #644,u,g,n,n,n,u,PM_INST_FROM_LMEM,The processor's instruction cache was reloaded from the local chip's memory due to a demand miss. ##094100000002C040 The processor's instruction cache was reloaded from the local chip's memory due to a demand miss. #645,u,g,n,n,n,u,PM_IPTEG_FROM_LMEM,The processor's instruction page table entry was reloaded from the local chip's memory due to a demand miss. ##094020000002C040 The processor's instruction page table entry was reloaded from the local chip's memory due to a demand miss. #646,u,g,n,n,n,u,PM_DATA_FROM_LMEM,The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss. ##094040000002C040 The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss. #647,u,g,n,n,n,u,PM_DPTEG_FROM_LMEM,The processor's data page table entry was reloaded from the local chip's memory due to a demand miss. ##094060000002C040 The processor's data page table entry was reloaded from the local chip's memory due to a demand miss. #648,u,g,n,n,n,u,PM_INST_FROM_LMEM_ALL,The processor's instruction cache was reloaded from the local chip's memory due to a demand miss or prefetch reload. ##094100000012C040 The processor's instruction cache was reloaded from the local chip's memory due to a demand miss or prefetch reload. #649,u,g,n,n,n,u,PM_IPTEG_FROM_LMEM_ALL,The processor's instruction page table entry was reloaded from the local chip's memory due to a demand miss or prefetch reload. ##094020000012C040 The processor's instruction page table entry was reloaded from the local chip's memory due to a demand miss or prefetch reload. #650,u,g,n,n,n,u,PM_DATA_FROM_LMEM_ALL,The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss or prefetch reload. ##094040000022C040 The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss or prefetch reload. #651,u,g,n,n,n,u,PM_DPTEG_FROM_LMEM_ALL,The processor's data page table entry was reloaded from the local chip's memory due to a demand miss or prefetch reload. ##094060000022C040 The processor's data page table entry was reloaded from the local chip's memory due to a demand miss or prefetch reload. #652,u,g,n,n,n,u,PM_IPTEG_FROM_L_OC_CACHE,The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss. ##098020000002C040 The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss. #653,u,g,n,n,n,u,PM_DATA_FROM_L_OC_CACHE,The processor's L1 data cache was reloaded from the local chip's OpenCapp cache due to a demand miss. ##098040000002C040 The processor's L1 data cache was reloaded from the local chip's OpenCapp cache due to a demand miss. #654,u,g,n,n,n,u,PM_DPTEG_FROM_L_OC_CACHE,The processor's data page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss. ##098060000002C040 The processor's data page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss. #655,u,g,n,n,n,u,PM_IPTEG_FROM_L_OC_CACHE_ALL,The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. ##098020000012C040 The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. #656,u,g,n,n,n,u,PM_DATA_FROM_L_OC_CACHE_ALL,The processor's L1 data cache was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. ##098040000022C040 The processor's L1 data cache was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. #657,u,g,n,n,n,u,PM_DPTEG_FROM_L_OC_CACHE_ALL,The processor's data page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. ##098060000022C040 The processor's data page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. #658,u,g,n,n,n,u,PM_IPTEG_FROM_L_OC_MEM,The processor's instruction page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss. ##09C020000002C040 The processor's instruction page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss. #659,u,g,n,n,n,u,PM_DATA_FROM_L_OC_MEM,The processor's L1 data cache was reloaded from the local chip's OpenCapp memory due to a demand miss. ##09C040000002C040 The processor's L1 data cache was reloaded from the local chip's OpenCapp memory due to a demand miss. #660,u,g,n,n,n,u,PM_DPTEG_FROM_L_OC_MEM,The processor's data page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss. ##09C060000002C040 The processor's data page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss. #661,u,g,n,n,n,u,PM_IPTEG_FROM_L_OC_MEM_ALL,The processor's instruction page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. ##09C020000012C040 The processor's instruction page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. #662,u,g,n,n,n,u,PM_DATA_FROM_L_OC_MEM_ALL,The processor's L1 data cache was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. ##09C040000022C040 The processor's L1 data cache was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. #663,u,g,n,n,n,u,PM_DPTEG_FROM_L_OC_MEM_ALL,The processor's data page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. ##09C060000022C040 The processor's data page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. #664,u,g,n,n,n,u,PM_INST_FROM_L_OC_ANY,The processor's instruction cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. ##098100000002C040 The processor's instruction cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. #665,u,g,n,n,n,u,PM_IPTEG_FROM_L_OC_ANY,The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. ##098120000002C040 The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. #666,u,g,n,n,n,u,PM_DATA_FROM_L_OC_ANY,The processor's L1 data cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. ##098140000002C040 The processor's L1 data cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. #667,u,g,n,n,n,u,PM_DPTEG_FROM_L_OC_ANY,The processor's data page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. ##098160000002C040 The processor's data page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. #668,u,g,n,n,n,u,PM_INST_FROM_L_OC_ANY_ALL,The processor's instruction cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##098100000012C040 The processor's instruction cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #669,u,g,n,n,n,u,PM_IPTEG_FROM_L_OC_ANY_ALL,The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##098120000012C040 The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #670,u,g,n,n,n,u,PM_DATA_FROM_L_OC_ANY_ALL,The processor's L1 data cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##098140000022C040 The processor's L1 data cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #671,u,g,n,n,n,u,PM_DPTEG_FROM_L_OC_ANY_ALL,The processor's data page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##098160000022C040 The processor's data page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #672,u,g,n,n,n,u,PM_IPTEG_FROM_RL2_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. ##0C0020000002C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. #673,u,g,n,n,n,u,PM_DATA_FROM_RL2_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. ##0C0040000002C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. #674,u,g,n,n,n,u,PM_DPTEG_FROM_RL2_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. ##0C0060000002C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. #675,u,g,n,n,n,u,PM_IPTEG_FROM_RL2_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. ##0C0020000012C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. #676,u,g,n,n,n,u,PM_DATA_FROM_RL2_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. ##0C0040000022C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. #677,u,g,n,n,n,u,PM_DPTEG_FROM_RL2_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. ##0C0060000022C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. #678,u,g,n,n,n,u,PM_IPTEG_FROM_RL2_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. ##0C4020000002C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. #679,u,g,n,n,n,u,PM_DATA_FROM_RL2_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. ##0C4040000002C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. #680,u,g,n,n,n,u,PM_DPTEG_FROM_RL2_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. ##0C4060000002C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. #681,u,g,n,n,n,u,PM_IPTEG_FROM_RL2_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. ##0C4020000012C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. #682,u,g,n,n,n,u,PM_DATA_FROM_RL2_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. ##0C4040000022C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. #683,u,g,n,n,n,u,PM_DPTEG_FROM_RL2_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. ##0C4060000022C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. #684,u,g,n,n,n,u,PM_INST_FROM_RL2,The processor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss. ##0C0100000002C040 The processor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss. #685,u,g,n,n,n,u,PM_IPTEG_FROM_RL2,The processor's instruction page table entry was reloaded from another core's L2 from a remote chip due to a demand miss. ##0C0120000002C040 The processor's instruction page table entry was reloaded from another core's L2 from a remote chip due to a demand miss. #686,u,g,n,n,n,u,PM_DATA_FROM_RL2,The processor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss. ##0C0140000002C040 The processor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss. #687,u,g,n,n,n,u,PM_DPTEG_FROM_RL2,The processor's data page table entry was reloaded from another core's L2 from a remote chip due to a demand miss. ##0C0160000002C040 The processor's data page table entry was reloaded from another core's L2 from a remote chip due to a demand miss. #688,u,g,n,n,n,u,PM_INST_FROM_RL2_ALL,The processor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. ##0C0100000012C040 The processor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. #689,u,g,n,n,n,u,PM_IPTEG_FROM_RL2_ALL,The processor's instruction page table entry was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. ##0C0120000012C040 The processor's instruction page table entry was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. #690,u,g,n,n,n,u,PM_DATA_FROM_RL2_ALL,The processor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. ##0C0140000022C040 The processor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. #691,u,g,n,n,n,u,PM_DPTEG_FROM_RL2_ALL,The processor's data page table entry was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. ##0C0160000022C040 The processor's data page table entry was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. #692,u,g,n,n,n,u,PM_IPTEG_FROM_RL3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. ##0C8020000002C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. #693,u,g,n,n,n,u,PM_DATA_FROM_RL3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. ##0C8040000002C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. #694,u,g,n,n,n,u,PM_DPTEG_FROM_RL3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. ##0C8060000002C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. #695,u,g,n,n,n,u,PM_IPTEG_FROM_RL3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. ##0C8020000012C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. #696,u,g,n,n,n,u,PM_DATA_FROM_RL3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. ##0C8040000022C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. #697,u,g,n,n,n,u,PM_DPTEG_FROM_RL3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. ##0C8060000022C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. #698,u,g,n,n,n,u,PM_IPTEG_FROM_RL3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. ##0CC020000002C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. #699,u,g,n,n,n,u,PM_DATA_FROM_RL3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. ##0CC040000002C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. #700,u,g,n,n,n,u,PM_DPTEG_FROM_RL3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. ##0CC060000002C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. #701,u,g,n,n,n,u,PM_IPTEG_FROM_RL3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. ##0CC020000012C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. #702,u,g,n,n,n,u,PM_DATA_FROM_RL3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. ##0CC040000022C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. #703,u,g,n,n,n,u,PM_DPTEG_FROM_RL3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. ##0CC060000022C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. #704,u,g,n,n,n,u,PM_INST_FROM_RL3,The processor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss. ##0C8100000002C040 The processor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss. #705,u,g,n,n,n,u,PM_IPTEG_FROM_RL3,The processor's instruction page table entry was reloaded from another core's L3 from a remote chip due to a demand miss. ##0C8120000002C040 The processor's instruction page table entry was reloaded from another core's L3 from a remote chip due to a demand miss. #706,u,g,n,n,n,u,PM_DATA_FROM_RL3,The processor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss. ##0C8140000002C040 The processor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss. #707,u,g,n,n,n,u,PM_DPTEG_FROM_RL3,The processor's data page table entry was reloaded from another core's L3 from a remote chip due to a demand miss. ##0C8160000002C040 The processor's data page table entry was reloaded from another core's L3 from a remote chip due to a demand miss. #708,u,g,n,n,n,u,PM_INST_FROM_RL3_ALL,The processor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. ##0C8100000012C040 The processor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. #709,u,g,n,n,n,u,PM_IPTEG_FROM_RL3_ALL,The processor's instruction page table entry was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. ##0C8120000012C040 The processor's instruction page table entry was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. #710,u,g,n,n,n,u,PM_DATA_FROM_RL3_ALL,The processor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. ##0C8140000022C040 The processor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. #711,u,g,n,n,n,u,PM_DPTEG_FROM_RL3_ALL,The processor's data page table entry was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. ##0C8160000022C040 The processor's data page table entry was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. #712,u,g,n,n,n,u,PM_IPTEG_FROM_RL2L3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. ##0C0220000002C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. #713,u,g,n,n,n,u,PM_DATA_FROM_RL2L3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. ##0C0240000002C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. #714,u,g,n,n,n,u,PM_DPTEG_FROM_RL2L3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. ##0C0260000002C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. #715,u,g,n,n,n,u,PM_IPTEG_FROM_RL2L3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. ##0C0220000012C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. #716,u,g,n,n,n,u,PM_DATA_FROM_RL2L3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. ##0C0240000022C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. #717,u,g,n,n,n,u,PM_DPTEG_FROM_RL2L3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. ##0C0260000022C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. #718,u,g,n,n,n,u,PM_IPTEG_FROM_RL2L3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. ##0C4220000002C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. #719,u,g,n,n,n,u,PM_DATA_FROM_RL2L3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. ##0C4240000002C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. #720,u,g,n,n,n,u,PM_DPTEG_FROM_RL2L3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. ##0C4260000002C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. #721,u,g,n,n,n,u,PM_IPTEG_FROM_RL2L3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. ##0C4220000012C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. #722,u,g,n,n,n,u,PM_DATA_FROM_RL2L3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. ##0C4240000022C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. #723,u,g,n,n,n,u,PM_DPTEG_FROM_RL2L3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. ##0C4260000022C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. #724,u,g,n,n,n,u,PM_INST_FROM_RL2L3,The processor's instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. ##0C0300000002C040 The processor's instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. #725,u,g,n,n,n,u,PM_IPTEG_FROM_RL2L3,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. ##0C0320000002C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. #726,u,g,n,n,n,u,PM_DATA_FROM_RL2L3,The processor's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. ##0C0340000002C040 The processor's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. #727,u,g,n,n,n,u,PM_DPTEG_FROM_RL2L3,The processor's data page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. ##0C0360000002C040 The processor's data page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. #728,u,g,n,n,n,u,PM_INST_FROM_RL2L3_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. ##0C0300000012C040 The processor's instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. #729,u,g,n,n,n,u,PM_IPTEG_FROM_RL2L3_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. ##0C0320000012C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. #730,u,g,n,n,n,u,PM_DATA_FROM_RL2L3_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. ##0C0340000022C040 The processor's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. #731,u,g,n,n,n,u,PM_DPTEG_FROM_RL2L3_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. ##0C0360000022C040 The processor's data page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. #732,u,g,n,n,n,u,PM_INST_FROM_RMEM,The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss. ##0D4100000002C040 The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss. #733,u,g,n,n,n,u,PM_IPTEG_FROM_RMEM,The processor's instruction page table entry was reloaded from remote memory (MC slow) due to a demand miss. ##0D4020000002C040 The processor's instruction page table entry was reloaded from remote memory (MC slow) due to a demand miss. #734,u,g,n,n,n,u,PM_DATA_FROM_RMEM,The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss. ##0D4040000002C040 The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss. #735,u,g,n,n,n,u,PM_DPTEG_FROM_RMEM,The processor's data page table entry was reloaded from remote memory (MC slow) due to a demand miss. ##0D4060000002C040 The processor's data page table entry was reloaded from remote memory (MC slow) due to a demand miss. #736,u,g,n,n,n,u,PM_INST_FROM_RMEM_ALL,The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. ##0D4100000012C040 The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. #737,u,g,n,n,n,u,PM_IPTEG_FROM_RMEM_ALL,The processor's instruction page table entry was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. ##0D4020000012C040 The processor's instruction page table entry was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. #738,u,g,n,n,n,u,PM_DATA_FROM_RMEM_ALL,The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. ##0D4040000022C040 The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. #739,u,g,n,n,n,u,PM_DPTEG_FROM_RMEM_ALL,The processor's data page table entry was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. ##0D4060000022C040 The processor's data page table entry was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. #740,u,g,n,n,n,u,PM_IPTEG_FROM_R_OC_CACHE,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss. ##0D8020000002C040 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss. #741,u,g,n,n,n,u,PM_DATA_FROM_R_OC_CACHE,The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache due to a demand miss. ##0D8040000002C040 The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache due to a demand miss. #742,u,g,n,n,n,u,PM_DPTEG_FROM_R_OC_CACHE,The processor's data page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss. ##0D8060000002C040 The processor's data page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss. #743,u,g,n,n,n,u,PM_IPTEG_FROM_R_OC_CACHE_ALL,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. ##0D8020000012C040 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. #744,u,g,n,n,n,u,PM_DATA_FROM_R_OC_CACHE_ALL,The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. ##0D8040000022C040 The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. #745,u,g,n,n,n,u,PM_DPTEG_FROM_R_OC_CACHE_ALL,The processor's data page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. ##0D8060000022C040 The processor's data page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. #746,u,g,n,n,n,u,PM_IPTEG_FROM_R_OC_MEM,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss. ##0DC020000002C040 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss. #747,u,g,n,n,n,u,PM_DATA_FROM_R_OC_MEM,The processor's L1 data cache was reloaded from a remote chip's OpenCapp memory due to a demand miss. ##0DC040000002C040 The processor's L1 data cache was reloaded from a remote chip's OpenCapp memory due to a demand miss. #748,u,g,n,n,n,u,PM_DPTEG_FROM_R_OC_MEM,The processor's data page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss. ##0DC060000002C040 The processor's data page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss. #749,u,g,n,n,n,u,PM_IPTEG_FROM_R_OC_MEM_ALL,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. ##0DC020000012C040 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. #750,u,g,n,n,n,u,PM_DATA_FROM_R_OC_MEM_ALL,The processor's L1 data cache was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. ##0DC040000022C040 The processor's L1 data cache was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. #751,u,g,n,n,n,u,PM_DPTEG_FROM_R_OC_MEM_ALL,The processor's data page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. ##0DC060000022C040 The processor's data page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. #752,u,g,n,n,n,u,PM_INST_FROM_R_OC_ANY,The processor's instruction cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. ##0D8100000002C040 The processor's instruction cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. #753,u,g,n,n,n,u,PM_IPTEG_FROM_R_OC_ANY,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. ##0D8120000002C040 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. #754,u,g,n,n,n,u,PM_DATA_FROM_R_OC_ANY,The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. ##0D8140000002C040 The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. #755,u,g,n,n,n,u,PM_DPTEG_FROM_R_OC_ANY,The processor's data page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. ##0D8160000002C040 The processor's data page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. #756,u,g,n,n,n,u,PM_INST_FROM_R_OC_ANY_ALL,The processor's instruction cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##0D8100000012C040 The processor's instruction cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #757,u,g,n,n,n,u,PM_IPTEG_FROM_R_OC_ANY_ALL,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##0D8120000012C040 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #758,u,g,n,n,n,u,PM_DATA_FROM_R_OC_ANY_ALL,The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##0D8140000022C040 The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #759,u,g,n,n,n,u,PM_DPTEG_FROM_R_OC_ANY_ALL,The processor's data page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##0D8160000022C040 The processor's data page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #760,u,g,n,n,n,u,PM_IPTEG_FROM_DL2_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. ##0E0020000002C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. #761,u,g,n,n,n,u,PM_DATA_FROM_DL2_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. ##0E0040000002C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. #762,u,g,n,n,n,u,PM_DPTEG_FROM_DL2_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. ##0E0060000002C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. #763,u,g,n,n,n,u,PM_IPTEG_FROM_DL2_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. ##0E0020000012C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. #764,u,g,n,n,n,u,PM_DATA_FROM_DL2_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. ##0E0040000022C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. #765,u,g,n,n,n,u,PM_DPTEG_FROM_DL2_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. ##0E0060000022C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. #766,u,g,n,n,n,u,PM_IPTEG_FROM_DL2_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. ##0E4020000002C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. #767,u,g,n,n,n,u,PM_DATA_FROM_DL2_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. ##0E4040000002C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. #768,u,g,n,n,n,u,PM_DPTEG_FROM_DL2_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. ##0E4060000002C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. #769,u,g,n,n,n,u,PM_IPTEG_FROM_DL2_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. ##0E4020000012C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. #770,u,g,n,n,n,u,PM_DATA_FROM_DL2_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. ##0E4040000022C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. #771,u,g,n,n,n,u,PM_DPTEG_FROM_DL2_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. ##0E4060000022C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. #772,u,g,n,n,n,u,PM_INST_FROM_DL2,The processor's instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss. ##0E0100000002C040 The processor's instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss. #773,u,g,n,n,n,u,PM_IPTEG_FROM_DL2,The processor's instruction page table entry was reloaded from another core's L2 from a distant chip due to a demand miss. ##0E0120000002C040 The processor's instruction page table entry was reloaded from another core's L2 from a distant chip due to a demand miss. #774,u,g,n,n,n,u,PM_DATA_FROM_DL2,The processor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss. ##0E0140000002C040 The processor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss. #775,u,g,n,n,n,u,PM_DPTEG_FROM_DL2,The processor's data page table entry was reloaded from another core's L2 from a distant chip due to a demand miss. ##0E0160000002C040 The processor's data page table entry was reloaded from another core's L2 from a distant chip due to a demand miss. #776,u,g,n,n,n,u,PM_INST_FROM_DL2_ALL,The processor's instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. ##0E0100000012C040 The processor's instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. #777,u,g,n,n,n,u,PM_IPTEG_FROM_DL2_ALL,The processor's instruction page table entry was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. ##0E0120000012C040 The processor's instruction page table entry was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. #778,u,g,n,n,n,u,PM_DATA_FROM_DL2_ALL,The processor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. ##0E0140000022C040 The processor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. #779,u,g,n,n,n,u,PM_DPTEG_FROM_DL2_ALL,The processor's data page table entry was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. ##0E0160000022C040 The processor's data page table entry was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. #780,u,g,n,n,n,u,PM_IPTEG_FROM_DL3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. ##0E8020000002C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. #781,u,g,n,n,n,u,PM_DATA_FROM_DL3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. ##0E8040000002C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. #782,u,g,n,n,n,u,PM_DPTEG_FROM_DL3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. ##0E8060000002C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. #783,u,g,n,n,n,u,PM_IPTEG_FROM_DL3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. ##0E8020000012C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. #784,u,g,n,n,n,u,PM_DATA_FROM_DL3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. ##0E8040000022C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. #785,u,g,n,n,n,u,PM_DPTEG_FROM_DL3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. ##0E8060000022C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. #786,u,g,n,n,n,u,PM_IPTEG_FROM_DL3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. ##0EC020000002C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. #787,u,g,n,n,n,u,PM_DATA_FROM_DL3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. ##0EC040000002C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. #788,u,g,n,n,n,u,PM_DPTEG_FROM_DL3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. ##0EC060000002C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. #789,u,g,n,n,n,u,PM_IPTEG_FROM_DL3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. ##0EC020000012C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. #790,u,g,n,n,n,u,PM_DATA_FROM_DL3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. ##0EC040000022C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. #791,u,g,n,n,n,u,PM_DPTEG_FROM_DL3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. ##0EC060000022C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. #792,u,g,n,n,n,u,PM_INST_FROM_DL3,The processor's instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss. ##0E8100000002C040 The processor's instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss. #793,u,g,n,n,n,u,PM_IPTEG_FROM_DL3,The processor's instruction page table entry was reloaded from another core's L3 from a distant chip due to a demand miss. ##0E8120000002C040 The processor's instruction page table entry was reloaded from another core's L3 from a distant chip due to a demand miss. #794,u,g,n,n,n,u,PM_DATA_FROM_DL3,The processor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss. ##0E8140000002C040 The processor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss. #795,u,g,n,n,n,u,PM_DPTEG_FROM_DL3,The processor's data page table entry was reloaded from another core's L3 from a distant chip due to a demand miss. ##0E8160000002C040 The processor's data page table entry was reloaded from another core's L3 from a distant chip due to a demand miss. #796,u,g,n,n,n,u,PM_INST_FROM_DL3_ALL,The processor's instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. ##0E8100000012C040 The processor's instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. #797,u,g,n,n,n,u,PM_IPTEG_FROM_DL3_ALL,The processor's instruction page table entry was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. ##0E8120000012C040 The processor's instruction page table entry was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. #798,u,g,n,n,n,u,PM_DATA_FROM_DL3_ALL,The processor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. ##0E8140000022C040 The processor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. #799,u,g,n,n,n,u,PM_DPTEG_FROM_DL3_ALL,The processor's data page table entry was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. ##0E8160000022C040 The processor's data page table entry was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. #800,u,g,n,n,n,u,PM_IPTEG_FROM_DL2L3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. ##0E0220000002C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. #801,u,g,n,n,n,u,PM_DATA_FROM_DL2L3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. ##0E0240000002C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. #802,u,g,n,n,n,u,PM_DPTEG_FROM_DL2L3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. ##0E0260000002C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. #803,u,g,n,n,n,u,PM_IPTEG_FROM_DL2L3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. ##0E0220000012C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. #804,u,g,n,n,n,u,PM_DATA_FROM_DL2L3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. ##0E0240000022C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. #805,u,g,n,n,n,u,PM_DPTEG_FROM_DL2L3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. ##0E0260000022C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. #806,u,g,n,n,n,u,PM_IPTEG_FROM_DL2L3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. ##0E4220000002C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. #807,u,g,n,n,n,u,PM_DATA_FROM_DL2L3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. ##0E4240000002C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. #808,u,g,n,n,n,u,PM_DPTEG_FROM_DL2L3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. ##0E4260000002C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. #809,u,g,n,n,n,u,PM_IPTEG_FROM_DL2L3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. ##0E4220000012C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. #810,u,g,n,n,n,u,PM_DATA_FROM_DL2L3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. ##0E4240000022C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. #811,u,g,n,n,n,u,PM_DPTEG_FROM_DL2L3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. ##0E4260000022C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. #812,u,g,n,n,n,u,PM_INST_FROM_DL2L3,The processor's instruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. ##0E0300000002C040 The processor's instruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. #813,u,g,n,n,n,u,PM_IPTEG_FROM_DL2L3,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. ##0E0320000002C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. #814,u,g,n,n,n,u,PM_DATA_FROM_DL2L3,The processor's L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. ##0E0340000002C040 The processor's L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. #815,u,g,n,n,n,u,PM_DPTEG_FROM_DL2L3,The processor's data page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. ##0E0360000002C040 The processor's data page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. #816,u,g,n,n,n,u,PM_INST_FROM_DL2L3_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. ##0E0300000012C040 The processor's instruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. #817,u,g,n,n,n,u,PM_IPTEG_FROM_DL2L3_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. ##0E0320000012C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. #818,u,g,n,n,n,u,PM_DATA_FROM_DL2L3_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. ##0E0340000022C040 The processor's L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. #819,u,g,n,n,n,u,PM_DPTEG_FROM_DL2L3_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. ##0E0360000022C040 The processor's data page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. #820,u,g,n,n,n,u,PM_INST_FROM_DMEM,The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss. ##0F4100000002C040 The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss. #821,u,g,n,n,n,u,PM_IPTEG_FROM_DMEM,The processor's instruction page table entry was reloaded from distant memory (MC slow) due to a demand miss. ##0F4020000002C040 The processor's instruction page table entry was reloaded from distant memory (MC slow) due to a demand miss. #822,u,g,n,n,n,u,PM_DATA_FROM_DMEM,The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss. ##0F4040000002C040 The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss. #823,u,g,n,n,n,u,PM_DPTEG_FROM_DMEM,The processor's data page table entry was reloaded from distant memory (MC slow) due to a demand miss. ##0F4060000002C040 The processor's data page table entry was reloaded from distant memory (MC slow) due to a demand miss. #824,u,g,n,n,n,u,PM_INST_FROM_DMEM_ALL,The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. ##0F4100000012C040 The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. #825,u,g,n,n,n,u,PM_IPTEG_FROM_DMEM_ALL,The processor's instruction page table entry was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. ##0F4020000012C040 The processor's instruction page table entry was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. #826,u,g,n,n,n,u,PM_DATA_FROM_DMEM_ALL,The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. ##0F4040000022C040 The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. #827,u,g,n,n,n,u,PM_DPTEG_FROM_DMEM_ALL,The processor's data page table entry was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. ##0F4060000022C040 The processor's data page table entry was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. #828,u,g,n,n,n,u,PM_IPTEG_FROM_D_OC_CACHE,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss. ##0F8020000002C040 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss. #829,u,g,n,n,n,u,PM_DATA_FROM_D_OC_CACHE,The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache due to a demand miss. ##0F8040000002C040 The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache due to a demand miss. #830,u,g,n,n,n,u,PM_DPTEG_FROM_D_OC_CACHE,The processor's data page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss. ##0F8060000002C040 The processor's data page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss. #831,u,g,n,n,n,u,PM_IPTEG_FROM_D_OC_CACHE_ALL,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. ##0F8020000012C040 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. #832,u,g,n,n,n,u,PM_DATA_FROM_D_OC_CACHE_ALL,The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. ##0F8040000022C040 The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. #833,u,g,n,n,n,u,PM_DPTEG_FROM_D_OC_CACHE_ALL,The processor's data page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. ##0F8060000022C040 The processor's data page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. #834,u,g,n,n,n,u,PM_IPTEG_FROM_D_OC_MEM,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss. ##0FC020000002C040 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss. #835,u,g,n,n,n,u,PM_DATA_FROM_D_OC_MEM,The processor's L1 data cache was reloaded from a distant chip's OpenCapp memory due to a demand miss. ##0FC040000002C040 The processor's L1 data cache was reloaded from a distant chip's OpenCapp memory due to a demand miss. #836,u,g,n,n,n,u,PM_DPTEG_FROM_D_OC_MEM,The processor's data page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss. ##0FC060000002C040 The processor's data page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss. #837,u,g,n,n,n,u,PM_IPTEG_FROM_D_OC_MEM_ALL,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. ##0FC020000012C040 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. #838,u,g,n,n,n,u,PM_DATA_FROM_D_OC_MEM_ALL,The processor's L1 data cache was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. ##0FC040000022C040 The processor's L1 data cache was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. #839,u,g,n,n,n,u,PM_DPTEG_FROM_D_OC_MEM_ALL,The processor's data page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. ##0FC060000022C040 The processor's data page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. #840,u,g,n,n,n,u,PM_INST_FROM_D_OC_ANY,The processor's instruction cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. ##0F8100000002C040 The processor's instruction cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. #841,u,g,n,n,n,u,PM_IPTEG_FROM_D_OC_ANY,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. ##0F8120000002C040 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. #842,u,g,n,n,n,u,PM_DATA_FROM_D_OC_ANY,The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. ##0F8140000002C040 The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. #843,u,g,n,n,n,u,PM_DPTEG_FROM_D_OC_ANY,The processor's data page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. ##0F8160000002C040 The processor's data page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. #844,u,g,n,n,n,u,PM_INST_FROM_D_OC_ANY_ALL,The processor's instruction cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##0F8100000012C040 The processor's instruction cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #845,u,g,n,n,n,u,PM_IPTEG_FROM_D_OC_ANY_ALL,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##0F8120000012C040 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #846,u,g,n,n,n,u,PM_DATA_FROM_D_OC_ANY_ALL,The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##0F8140000022C040 The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #847,u,g,n,n,n,u,PM_DPTEG_FROM_D_OC_ANY_ALL,The processor's data page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##0F8160000022C040 The processor's data page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #848,u,g,n,n,n,u,PM_INST_FROM_ONCHIP_CACHE,The processor's instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss. ##080B00000002C040 The processor's instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss. #849,u,g,n,n,n,u,PM_IPTEG_FROM_ONCHIP_CACHE,The processor's instruction page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss. ##080B20000002C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss. #850,u,g,n,n,n,u,PM_DATA_FROM_ONCHIP_CACHE,The processor's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss. ##080B40000002C040 The processor's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss. #851,u,g,n,n,n,u,PM_DPTEG_FROM_ONCHIP_CACHE,The processor's data page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss. ##080B60000002C040 The processor's data page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss. #852,u,g,n,n,n,u,PM_INST_FROM_ONCHIP_CACHE_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. ##080B00000012C040 The processor's instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. #853,u,g,n,n,n,u,PM_IPTEG_FROM_ONCHIP_CACHE_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. ##080B20000012C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. #854,u,g,n,n,n,u,PM_DATA_FROM_ONCHIP_CACHE_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. ##080B40000022C040 The processor's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. #855,u,g,n,n,n,u,PM_DPTEG_FROM_ONCHIP_CACHE_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. ##080B60000022C040 The processor's data page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. #856,u,g,n,n,n,u,PM_INST_FROM_OFFCHIP_CACHE,The processor's instruction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss. ##0C0B00000002C040 The processor's instruction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss. #857,u,g,n,n,n,u,PM_IPTEG_FROM_OFFCHIP_CACHE,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss. ##0C0B20000002C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss. #858,u,g,n,n,n,u,PM_DATA_FROM_OFFCHIP_CACHE,The processor's L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss. ##0C0B40000002C040 The processor's L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss. #859,u,g,n,n,n,u,PM_DPTEG_FROM_OFFCHIP_CACHE,The processor's data page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss. ##0C0B60000002C040 The processor's data page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss. #860,u,g,n,n,n,u,PM_INST_FROM_OFFCHIP_CACHE_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. ##0C0B00000012C040 The processor's instruction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. #861,u,g,n,n,n,u,PM_IPTEG_FROM_OFFCHIP_CACHE_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. ##0C0B20000012C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. #862,u,g,n,n,n,u,PM_DATA_FROM_OFFCHIP_CACHE_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. ##0C0B40000022C040 The processor's L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. #863,u,g,n,n,n,u,PM_DPTEG_FROM_OFFCHIP_CACHE_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. ##0C0B60000022C040 The processor's data page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. #864,u,g,n,n,n,u,PM_INST_FROM_ANY_MEMORY,The processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss. ##095900000002C040 The processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss. #865,u,g,n,n,n,u,PM_IPTEG_FROM_ANY_MEMORY,The processor's instruction page table entry was reloaded from any chip's memory (MC slow) due to a demand miss. ##095820000002C040 The processor's instruction page table entry was reloaded from any chip's memory (MC slow) due to a demand miss. #866,u,g,n,n,n,u,PM_DATA_FROM_ANY_MEMORY,The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss. ##095840000002C040 The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss. #867,u,g,n,n,n,u,PM_DPTEG_FROM_ANY_MEMORY,The processor's data page table entry was reloaded from any chip's memory (MC slow) due to a demand miss. ##095860000002C040 The processor's data page table entry was reloaded from any chip's memory (MC slow) due to a demand miss. #868,u,g,n,n,n,u,PM_INST_FROM_ANY_MEMORY_ALL,The processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. ##095900000012C040 The processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. #869,u,g,n,n,n,u,PM_IPTEG_FROM_ANY_MEMORY_ALL,The processor's instruction page table entry was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. ##095820000012C040 The processor's instruction page table entry was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. #870,u,g,n,n,n,u,PM_DATA_FROM_ANY_MEMORY_ALL,The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. ##095840000022C040 The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. #871,u,g,n,n,n,u,PM_DPTEG_FROM_ANY_MEMORY_ALL,The processor's data page table entry was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. ##095860000022C040 The processor's data page table entry was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. #872,u,g,n,n,m,u,PM_MRK_INST_FROM_L2,The processor's instruction cache was reloaded from the local core's L2 due to a demand miss for a marked instruction. ##000300000002C142 The processor's instruction cache was reloaded from the local core's L2 due to a demand miss for a marked instruction. #873,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2,The processor's instruction page table entry was reloaded from the local core's L2 due to a demand miss for a marked instruction. ##000320000002C142 The processor's instruction page table entry was reloaded from the local core's L2 due to a demand miss for a marked instruction. #874,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2,The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss for a marked instruction. ##000340000002C142 The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss for a marked instruction. #875,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2,The processor's data page table entry was reloaded from the local core's L2 due to a demand miss for a marked instruction. ##000360000002C142 The processor's data page table entry was reloaded from the local core's L2 due to a demand miss for a marked instruction. #876,u,g,n,n,m,u,PM_MRK_INST_FROM_L2_ALL,The processor's instruction cache was reloaded from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##000300000012C142 The processor's instruction cache was reloaded from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #877,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_ALL,The processor's instruction page table entry was reloaded from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##000320000012C142 The processor's instruction page table entry was reloaded from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #878,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_ALL,The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##000340000022C142 The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #879,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_ALL,The processor's data page table entry was reloaded from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##000360000022C142 The processor's data page table entry was reloaded from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #880,u,g,n,n,m,u,PM_MRK_INST_FROM_L1MISS,The processor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss for a marked instruction. ##003F00000002C142 The processor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss for a marked instruction. #881,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L1MISS,The processor's instruction page table entry was reloaded from a source beyond the local core's L1 due to a demand miss for a marked instruction. ##003F20000002C142 The processor's instruction page table entry was reloaded from a source beyond the local core's L1 due to a demand miss for a marked instruction. #882,u,g,n,n,m,u,PM_MRK_DATA_FROM_L1MISS,The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss for a marked instruction. ##003F40000002C142 The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss for a marked instruction. #883,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L1MISS,The processor's data page table entry was reloaded from a source beyond the local core's L1 due to a demand miss for a marked instruction. ##003F60000002C142 The processor's data page table entry was reloaded from a source beyond the local core's L1 due to a demand miss for a marked instruction. #884,u,g,n,n,m,u,PM_MRK_INST_FROM_L1MISS_ALL,The processor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload for a marked instruction. ##003F00000012C142 The processor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload for a marked instruction. #885,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L1MISS_ALL,The processor's instruction page table entry was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload for a marked instruction. ##003F20000012C142 The processor's instruction page table entry was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload for a marked instruction. #886,u,g,n,n,m,u,PM_MRK_DATA_FROM_L1MISS_ALL,The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload for a marked instruction. ##003F40000022C142 The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload for a marked instruction. #887,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L1MISS_ALL,The processor's data page table entry was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload for a marked instruction. ##003F60000022C142 The processor's data page table entry was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload for a marked instruction. #888,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_NO_CONFLICT,The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss for a marked instruction. ##000020000002C142 The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss for a marked instruction. #889,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_NO_CONFLICT,The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss for a marked instruction. ##000040000002C142 The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss for a marked instruction. #890,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_NO_CONFLICT,The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss for a marked instruction. ##000060000002C142 The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss for a marked instruction. #891,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_NO_CONFLICT_ALL,The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##000020000012C142 The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #892,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_NO_CONFLICT_ALL,The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##000040000022C142 The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #893,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_NO_CONFLICT_ALL,The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##000060000022C142 The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #894,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_MEPF,The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss for a marked instruction. ##004020000002C142 The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss for a marked instruction. #895,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_MEPF,The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss for a marked instruction. ##004040000002C142 The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss for a marked instruction. #896,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_MEPF,The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss for a marked instruction. ##004060000002C142 The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss for a marked instruction. #897,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_MEPF_ALL,The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##004020000012C142 The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #898,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_MEPF_ALL,The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##004040000022C142 The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #899,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_MEPF_ALL,The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##004060000022C142 The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #900,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_LDHITST_CONFLICT,The processor's instruction page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. ##008020000002C142 The processor's instruction page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. #901,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_LDHITST_CONFLICT,The processor's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. ##008040000002C142 The processor's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. #902,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_LDHITST_CONFLICT,The processor's data page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. ##008060000002C142 The processor's data page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. #903,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_LDHITST_CONFLICT_ALL,The processor's instruction page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##008020000012C142 The processor's instruction page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #904,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_LDHITST_CONFLICT_ALL,The processor's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##008040000022C142 The processor's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #905,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_LDHITST_CONFLICT_ALL,The processor's data page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##008060000022C142 The processor's data page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #906,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_OTHER_CONFLICT,The processor's instruction page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. ##00C020000002C142 The processor's instruction page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. #907,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_OTHER_CONFLICT,The processor's L1 data cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. ##00C040000002C142 The processor's L1 data cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. #908,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_OTHER_CONFLICT,The processor's data page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. ##00C060000002C142 The processor's data page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. #909,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_OTHER_CONFLICT_ALL,The processor's instruction page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##00C020000012C142 The processor's instruction page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #910,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_OTHER_CONFLICT_ALL,The processor's L1 data cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##00C040000022C142 The processor's L1 data cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #911,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_OTHER_CONFLICT_ALL,The processor's data page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##00C060000022C142 The processor's data page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #912,u,g,n,n,m,u,PM_MRK_INST_FROM_L2MISS,The processor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction. ##000380000002C142 The processor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction. #913,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2MISS,The processor's instruction page table entry was reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction. ##0003A0000002C142 The processor's instruction page table entry was reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction. #914,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2MISS,The processor's data page table entry was reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction. ##0003E0000002C142 The processor's data page table entry was reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction. #915,u,g,n,n,m,u,PM_MRK_INST_FROM_L2MISS_ALL,The processor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##000380000012C142 The processor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #916,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2MISS_ALL,The processor's instruction page table entry was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##0003A0000012C142 The processor's instruction page table entry was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #917,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2MISS_ALL,The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##0003C0000022C142 The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #918,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2MISS_ALL,The processor's data page table entry was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##0003E0000022C142 The processor's data page table entry was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #919,u,g,n,n,m,u,PM_MRK_INST_FROM_L3,The processor's instruction cache was reloaded from the local core's L3 due to a demand miss for a marked instruction. ##010300000002C142 The processor's instruction cache was reloaded from the local core's L3 due to a demand miss for a marked instruction. #920,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3,The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss for a marked instruction. ##010320000002C142 The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss for a marked instruction. #921,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3,The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss for a marked instruction. ##010340000002C142 The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss for a marked instruction. #922,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3,The processor's data page table entry was reloaded from the local core's L3 due to a demand miss for a marked instruction. ##010360000002C142 The processor's data page table entry was reloaded from the local core's L3 due to a demand miss for a marked instruction. #923,u,g,n,n,m,u,PM_MRK_INST_FROM_L3_ALL,The processor's instruction cache was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##010300000012C142 The processor's instruction cache was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #924,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_ALL,The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##010320000012C142 The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #925,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_ALL,The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##010340000022C142 The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #926,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_ALL,The processor's data page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##010360000022C142 The processor's data page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #927,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_NO_CONFLICT,The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss for a marked instruction. ##010020000002C142 The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss for a marked instruction. #928,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_NO_CONFLICT,The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss for a marked instruction. ##010040000002C142 The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss for a marked instruction. #929,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_NO_CONFLICT,The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss for a marked instruction. ##010060000002C142 The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss for a marked instruction. #930,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_NO_CONFLICT_ALL,The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##010020000012C142 The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #931,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_NO_CONFLICT_ALL,The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##010040000022C142 The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #932,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_NO_CONFLICT_ALL,The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##010060000022C142 The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #933,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_MEPF,The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss for a marked instruction. ##014020000002C142 The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss for a marked instruction. #934,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_MEPF,The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss for a marked instruction. ##014040000002C142 The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss for a marked instruction. #935,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_MEPF,The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss for a marked instruction. ##014060000002C142 The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss for a marked instruction. #936,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_MEPF_ALL,The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##014020000012C142 The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #937,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_MEPF_ALL,The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##014040000022C142 The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #938,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_MEPF_ALL,The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##014060000022C142 The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #939,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_CONFLICT,The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss for a marked instruction. ##01C020000002C142 The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss for a marked instruction. #940,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_CONFLICT,The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss for a marked instruction. ##01C040000002C142 The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss for a marked instruction. #941,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_CONFLICT,The processor's data page table entry was reloaded from the local core's L3 due to a demand miss for a marked instruction. ##01C060000002C142 The processor's data page table entry was reloaded from the local core's L3 due to a demand miss for a marked instruction. #942,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_CONFLICT_ALL,The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##01C020000012C142 The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #943,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_CONFLICT_ALL,The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##01C040000022C142 The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #944,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_CONFLICT_ALL,The processor's data page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##01C060000022C142 The processor's data page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #945,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3MISS,The processor's instruction page table entry was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction. ##0007A0000002C142 The processor's instruction page table entry was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction. #946,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3MISS,The processor's data page table entry was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction. ##0007E0000002C142 The processor's data page table entry was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction. #947,u,g,n,n,m,u,PM_MRK_INST_FROM_L3MISS_ALL,The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##000780000012C142 The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #948,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3MISS_ALL,The processor's instruction page table entry was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##0007A0000012C142 The processor's instruction page table entry was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #949,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3MISS_ALL,The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##0007C0000022C142 The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #950,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3MISS_ALL,The processor's data page table entry was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##0007E0000022C142 The processor's data page table entry was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #951,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. ##080020000002C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. #952,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. ##080040000002C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. #953,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. ##080060000002C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. #954,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080020000012C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #955,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080040000022C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #956,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080060000022C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #957,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. ##084020000002C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. #958,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. ##084040000002C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. #959,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. ##084060000002C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. #960,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##084020000012C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #961,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##084040000022C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #962,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##084060000022C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #963,u,g,n,n,m,u,PM_MRK_INST_FROM_L21_REGENT,The processor's instruction cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. ##080100000002C142 The processor's instruction cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. #964,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT,The processor's instruction page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. ##080120000002C142 The processor's instruction page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. #965,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT,The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. ##080140000002C142 The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. #966,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT,The processor's data page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. ##080160000002C142 The processor's data page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. #967,u,g,n,n,m,u,PM_MRK_INST_FROM_L21_REGENT_ALL,The processor's instruction cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080100000012C142 The processor's instruction cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #968,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_ALL,The processor's instruction page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080120000012C142 The processor's instruction page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #969,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_ALL,The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080140000022C142 The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #970,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_ALL,The processor's data page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080160000022C142 The processor's data page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #971,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##088020000002C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. #972,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##088040000002C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. #973,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##088060000002C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. #974,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##088020000012C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #975,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##088040000022C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #976,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##088060000022C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #977,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##08C020000002C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. #978,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##08C040000002C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. #979,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##08C060000002C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. #980,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##08C020000012C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #981,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##08C040000022C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #982,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##08C060000022C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #983,u,g,n,n,m,u,PM_MRK_INST_FROM_L31_REGENT,The processor's instruction cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##088100000002C142 The processor's instruction cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. #984,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT,The processor's instruction page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##088120000002C142 The processor's instruction page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. #985,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT,The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##088140000002C142 The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. #986,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT,The processor's data page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##088160000002C142 The processor's data page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. #987,u,g,n,n,m,u,PM_MRK_INST_FROM_L31_REGENT_ALL,The processor's instruction cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##088100000012C142 The processor's instruction cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #988,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_ALL,The processor's instruction page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##088120000012C142 The processor's instruction page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #989,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_ALL,The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##088140000022C142 The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #990,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_ALL,The processor's data page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##088160000022C142 The processor's data page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #991,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##080220000002C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. #992,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##080240000002C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. #993,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##080260000002C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. #994,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080220000012C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #995,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080240000022C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #996,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080260000022C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #997,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##084220000002C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. #998,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##084240000002C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. #999,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##084260000002C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. #1000,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##084220000012C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #1001,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##084240000022C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #1002,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##084260000022C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #1003,u,g,n,n,m,u,PM_MRK_INST_FROM_REGENT_L2L3,The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##080300000002C142 The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. #1004,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3,The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##080320000002C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. #1005,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3,The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##080340000002C142 The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. #1006,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3,The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##080360000002C142 The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. #1007,u,g,n,n,m,u,PM_MRK_INST_FROM_REGENT_L2L3_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080300000012C142 The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #1008,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080320000012C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #1009,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080340000022C142 The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #1010,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080360000022C142 The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #1011,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0020000002C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. #1012,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0040000002C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. #1013,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0060000002C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. #1014,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0020000012C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1015,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0040000022C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1016,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0060000022C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1017,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A4020000002C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. #1018,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A4040000002C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. #1019,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A4060000002C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. #1020,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A4020000012C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1021,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A4040000022C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1022,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A4060000022C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1023,u,g,n,n,m,u,PM_MRK_INST_FROM_L21_NON_REGENT,The processor's instruction cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0100000002C142 The processor's instruction cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. #1024,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT,The processor's instruction page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0120000002C142 The processor's instruction page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. #1025,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT,The processor's L1 data cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0140000002C142 The processor's L1 data cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. #1026,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT,The processor's data page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0160000002C142 The processor's data page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. #1027,u,g,n,n,m,u,PM_MRK_INST_FROM_L21_NON_REGENT_ALL,The processor's instruction cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0100000012C142 The processor's instruction cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1028,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_ALL,The processor's instruction page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0120000012C142 The processor's instruction page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1029,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_ALL,The processor's L1 data cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0140000022C142 The processor's L1 data cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1030,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_ALL,The processor's data page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0160000022C142 The processor's data page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1031,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A8020000002C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1032,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A8040000002C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1033,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A8060000002C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1034,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A8020000012C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1035,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A8040000022C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1036,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A8060000022C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1037,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0AC020000002C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1038,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0AC040000002C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1039,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0AC060000002C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1040,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0AC020000012C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1041,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0AC040000022C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1042,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0AC060000022C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1043,u,g,n,n,m,u,PM_MRK_INST_FROM_L31_NON_REGENT,The processor's instruction cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A8100000002C142 The processor's instruction cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1044,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT,The processor's instruction page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A8120000002C142 The processor's instruction page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1045,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT,The processor's L1 data cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A8140000002C142 The processor's L1 data cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1046,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT,The processor's data page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A8160000002C142 The processor's data page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1047,u,g,n,n,m,u,PM_MRK_INST_FROM_L31_NON_REGENT_ALL,The processor's instruction cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A8100000012C142 The processor's instruction cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1048,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_ALL,The processor's instruction page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A8120000012C142 The processor's instruction page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1049,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_ALL,The processor's L1 data cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A8140000022C142 The processor's L1 data cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1050,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_ALL,The processor's data page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A8160000022C142 The processor's data page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1051,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0220000002C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1052,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0240000002C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1053,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0260000002C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1054,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0220000012C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1055,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0240000022C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1056,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0260000022C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1057,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A4220000002C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1058,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A4240000002C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1059,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A4260000002C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1060,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A4220000012C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1061,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A4240000022C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1062,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A4260000022C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1063,u,g,n,n,m,u,PM_MRK_INST_FROM_NON_REGENT_L2L3,The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0300000002C142 The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1064,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3,The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0320000002C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1065,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3,The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0340000002C142 The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1066,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3,The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0360000002C142 The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1067,u,g,n,n,m,u,PM_MRK_INST_FROM_NON_REGENT_L2L3_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0300000012C142 The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1068,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0320000012C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1069,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0340000022C142 The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1070,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0360000022C142 The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1071,u,g,n,n,m,u,PM_MRK_INST_FROM_LMEM,The processor's instruction cache was reloaded from the local chip's memory due to a demand miss for a marked instruction. ##094100000002C142 The processor's instruction cache was reloaded from the local chip's memory due to a demand miss for a marked instruction. #1072,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_LMEM,The processor's instruction page table entry was reloaded from the local chip's memory due to a demand miss for a marked instruction. ##094020000002C142 The processor's instruction page table entry was reloaded from the local chip's memory due to a demand miss for a marked instruction. #1073,u,g,n,n,m,u,PM_MRK_DATA_FROM_LMEM,The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss for a marked instruction. ##094040000002C142 The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss for a marked instruction. #1074,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_LMEM,The processor's data page table entry was reloaded from the local chip's memory due to a demand miss for a marked instruction. ##094060000002C142 The processor's data page table entry was reloaded from the local chip's memory due to a demand miss for a marked instruction. #1075,u,g,n,n,m,u,PM_MRK_INST_FROM_LMEM_ALL,The processor's instruction cache was reloaded from the local chip's memory due to a demand miss or prefetch reload for a marked instruction. ##094100000012C142 The processor's instruction cache was reloaded from the local chip's memory due to a demand miss or prefetch reload for a marked instruction. #1076,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_LMEM_ALL,The processor's instruction page table entry was reloaded from the local chip's memory due to a demand miss or prefetch reload for a marked instruction. ##094020000012C142 The processor's instruction page table entry was reloaded from the local chip's memory due to a demand miss or prefetch reload for a marked instruction. #1077,u,g,n,n,m,u,PM_MRK_DATA_FROM_LMEM_ALL,The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss or prefetch reload for a marked instruction. ##094040000022C142 The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss or prefetch reload for a marked instruction. #1078,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_LMEM_ALL,The processor's data page table entry was reloaded from the local chip's memory due to a demand miss or prefetch reload for a marked instruction. ##094060000022C142 The processor's data page table entry was reloaded from the local chip's memory due to a demand miss or prefetch reload for a marked instruction. #1079,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_CACHE,The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss for a marked instruction. ##098020000002C142 The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss for a marked instruction. #1080,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_CACHE,The processor's L1 data cache was reloaded from the local chip's OpenCapp cache due to a demand miss for a marked instruction. ##098040000002C142 The processor's L1 data cache was reloaded from the local chip's OpenCapp cache due to a demand miss for a marked instruction. #1081,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_CACHE,The processor's data page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss for a marked instruction. ##098060000002C142 The processor's data page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss for a marked instruction. #1082,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_CACHE_ALL,The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. ##098020000012C142 The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. #1083,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_CACHE_ALL,The processor's L1 data cache was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. ##098040000022C142 The processor's L1 data cache was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. #1084,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_CACHE_ALL,The processor's data page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. ##098060000022C142 The processor's data page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. #1085,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_MEM,The processor's instruction page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss for a marked instruction. ##09C020000002C142 The processor's instruction page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss for a marked instruction. #1086,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_MEM,The processor's L1 data cache was reloaded from the local chip's OpenCapp memory due to a demand miss for a marked instruction. ##09C040000002C142 The processor's L1 data cache was reloaded from the local chip's OpenCapp memory due to a demand miss for a marked instruction. #1087,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_MEM,The processor's data page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss for a marked instruction. ##09C060000002C142 The processor's data page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss for a marked instruction. #1088,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_MEM_ALL,The processor's instruction page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. ##09C020000012C142 The processor's instruction page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. #1089,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_MEM_ALL,The processor's L1 data cache was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. ##09C040000022C142 The processor's L1 data cache was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. #1090,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_MEM_ALL,The processor's data page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. ##09C060000022C142 The processor's data page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. #1091,u,g,n,n,m,u,PM_MRK_INST_FROM_L_OC_ANY,The processor's instruction cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##098100000002C142 The processor's instruction cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1092,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_ANY,The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##098120000002C142 The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1093,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_ANY,The processor's L1 data cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##098140000002C142 The processor's L1 data cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1094,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_ANY,The processor's data page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##098160000002C142 The processor's data page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1095,u,g,n,n,m,u,PM_MRK_INST_FROM_L_OC_ANY_ALL,The processor's instruction cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##098100000012C142 The processor's instruction cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1096,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_ANY_ALL,The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##098120000012C142 The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1097,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_ANY_ALL,The processor's L1 data cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##098140000022C142 The processor's L1 data cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1098,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_ANY_ALL,The processor's data page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##098160000022C142 The processor's data page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1099,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. ##0C0020000002C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. #1100,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. ##0C0040000002C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. #1101,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. ##0C0060000002C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. #1102,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0020000012C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1103,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0040000022C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1104,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0060000022C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1105,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. ##0C4020000002C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. #1106,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. ##0C4040000002C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. #1107,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. ##0C4060000002C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. #1108,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C4020000012C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1109,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C4040000022C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1110,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C4060000022C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1111,u,g,n,n,m,u,PM_MRK_INST_FROM_RL2,The processor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss for a marked instruction. ##0C0100000002C142 The processor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss for a marked instruction. #1112,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2,The processor's instruction page table entry was reloaded from another core's L2 from a remote chip due to a demand miss for a marked instruction. ##0C0120000002C142 The processor's instruction page table entry was reloaded from another core's L2 from a remote chip due to a demand miss for a marked instruction. #1113,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2,The processor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss for a marked instruction. ##0C0140000002C142 The processor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss for a marked instruction. #1114,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2,The processor's data page table entry was reloaded from another core's L2 from a remote chip due to a demand miss for a marked instruction. ##0C0160000002C142 The processor's data page table entry was reloaded from another core's L2 from a remote chip due to a demand miss for a marked instruction. #1115,u,g,n,n,m,u,PM_MRK_INST_FROM_RL2_ALL,The processor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0100000012C142 The processor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1116,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_ALL,The processor's instruction page table entry was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0120000012C142 The processor's instruction page table entry was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1117,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_ALL,The processor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0140000022C142 The processor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1118,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_ALL,The processor's data page table entry was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0160000022C142 The processor's data page table entry was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1119,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. ##0C8020000002C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. #1120,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. ##0C8040000002C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. #1121,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. ##0C8060000002C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. #1122,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C8020000012C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1123,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C8040000022C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1124,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C8060000022C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1125,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. ##0CC020000002C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. #1126,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. ##0CC040000002C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. #1127,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. ##0CC060000002C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. #1128,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0CC020000012C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1129,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0CC040000022C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1130,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0CC060000022C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1131,u,g,n,n,m,u,PM_MRK_INST_FROM_RL3,The processor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss for a marked instruction. ##0C8100000002C142 The processor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss for a marked instruction. #1132,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3,The processor's instruction page table entry was reloaded from another core's L3 from a remote chip due to a demand miss for a marked instruction. ##0C8120000002C142 The processor's instruction page table entry was reloaded from another core's L3 from a remote chip due to a demand miss for a marked instruction. #1133,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3,The processor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss for a marked instruction. ##0C8140000002C142 The processor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss for a marked instruction. #1134,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3,The processor's data page table entry was reloaded from another core's L3 from a remote chip due to a demand miss for a marked instruction. ##0C8160000002C142 The processor's data page table entry was reloaded from another core's L3 from a remote chip due to a demand miss for a marked instruction. #1135,u,g,n,n,m,u,PM_MRK_INST_FROM_RL3_ALL,The processor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C8100000012C142 The processor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1136,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_ALL,The processor's instruction page table entry was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C8120000012C142 The processor's instruction page table entry was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1137,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_ALL,The processor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C8140000022C142 The processor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1138,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_ALL,The processor's data page table entry was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C8160000022C142 The processor's data page table entry was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1139,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. ##0C0220000002C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. #1140,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. ##0C0240000002C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. #1141,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. ##0C0260000002C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. #1142,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0220000012C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1143,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0240000022C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1144,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0260000022C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1145,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. ##0C4220000002C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. #1146,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. ##0C4240000002C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. #1147,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. ##0C4260000002C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. #1148,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C4220000012C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1149,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C4240000022C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1150,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C4260000022C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1151,u,g,n,n,m,u,PM_MRK_INST_FROM_RL2L3,The processor's instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. ##0C0300000002C142 The processor's instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. #1152,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. ##0C0320000002C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. #1153,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3,The processor's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. ##0C0340000002C142 The processor's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. #1154,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3,The processor's data page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. ##0C0360000002C142 The processor's data page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. #1155,u,g,n,n,m,u,PM_MRK_INST_FROM_RL2L3_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0300000012C142 The processor's instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1156,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0320000012C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1157,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0340000022C142 The processor's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1158,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0360000022C142 The processor's data page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1159,u,g,n,n,m,u,PM_MRK_INST_FROM_RMEM,The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss for a marked instruction. ##0D4100000002C142 The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss for a marked instruction. #1160,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RMEM,The processor's instruction page table entry was reloaded from remote memory (MC slow) due to a demand miss for a marked instruction. ##0D4020000002C142 The processor's instruction page table entry was reloaded from remote memory (MC slow) due to a demand miss for a marked instruction. #1161,u,g,n,n,m,u,PM_MRK_DATA_FROM_RMEM,The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss for a marked instruction. ##0D4040000002C142 The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss for a marked instruction. #1162,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RMEM,The processor's data page table entry was reloaded from remote memory (MC slow) due to a demand miss for a marked instruction. ##0D4060000002C142 The processor's data page table entry was reloaded from remote memory (MC slow) due to a demand miss for a marked instruction. #1163,u,g,n,n,m,u,PM_MRK_INST_FROM_RMEM_ALL,The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##0D4100000012C142 The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1164,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RMEM_ALL,The processor's instruction page table entry was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##0D4020000012C142 The processor's instruction page table entry was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1165,u,g,n,n,m,u,PM_MRK_DATA_FROM_RMEM_ALL,The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##0D4040000022C142 The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1166,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RMEM_ALL,The processor's data page table entry was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##0D4060000022C142 The processor's data page table entry was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1167,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_CACHE,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss for a marked instruction. ##0D8020000002C142 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss for a marked instruction. #1168,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_CACHE,The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache due to a demand miss for a marked instruction. ##0D8040000002C142 The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache due to a demand miss for a marked instruction. #1169,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_CACHE,The processor's data page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss for a marked instruction. ##0D8060000002C142 The processor's data page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss for a marked instruction. #1170,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_CACHE_ALL,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. ##0D8020000012C142 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. #1171,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_CACHE_ALL,The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. ##0D8040000022C142 The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. #1172,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_CACHE_ALL,The processor's data page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. ##0D8060000022C142 The processor's data page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. #1173,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_MEM,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss for a marked instruction. ##0DC020000002C142 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss for a marked instruction. #1174,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_MEM,The processor's L1 data cache was reloaded from a remote chip's OpenCapp memory due to a demand miss for a marked instruction. ##0DC040000002C142 The processor's L1 data cache was reloaded from a remote chip's OpenCapp memory due to a demand miss for a marked instruction. #1175,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_MEM,The processor's data page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss for a marked instruction. ##0DC060000002C142 The processor's data page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss for a marked instruction. #1176,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_MEM_ALL,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. ##0DC020000012C142 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. #1177,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_MEM_ALL,The processor's L1 data cache was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. ##0DC040000022C142 The processor's L1 data cache was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. #1178,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_MEM_ALL,The processor's data page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. ##0DC060000022C142 The processor's data page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. #1179,u,g,n,n,m,u,PM_MRK_INST_FROM_R_OC_ANY,The processor's instruction cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##0D8100000002C142 The processor's instruction cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1180,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_ANY,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##0D8120000002C142 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1181,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_ANY,The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##0D8140000002C142 The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1182,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_ANY,The processor's data page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##0D8160000002C142 The processor's data page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1183,u,g,n,n,m,u,PM_MRK_INST_FROM_R_OC_ANY_ALL,The processor's instruction cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##0D8100000012C142 The processor's instruction cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1184,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_ANY_ALL,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##0D8120000012C142 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1185,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_ANY_ALL,The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##0D8140000022C142 The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1186,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_ANY_ALL,The processor's data page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##0D8160000022C142 The processor's data page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1187,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. ##0E0020000002C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. #1188,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. ##0E0040000002C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. #1189,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. ##0E0060000002C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. #1190,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0020000012C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1191,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0040000022C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1192,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0060000022C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1193,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. ##0E4020000002C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. #1194,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. ##0E4040000002C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. #1195,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. ##0E4060000002C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. #1196,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E4020000012C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1197,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E4040000022C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1198,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E4060000022C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1199,u,g,n,n,m,u,PM_MRK_INST_FROM_DL2,The processor's instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss for a marked instruction. ##0E0100000002C142 The processor's instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss for a marked instruction. #1200,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2,The processor's instruction page table entry was reloaded from another core's L2 from a distant chip due to a demand miss for a marked instruction. ##0E0120000002C142 The processor's instruction page table entry was reloaded from another core's L2 from a distant chip due to a demand miss for a marked instruction. #1201,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2,The processor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss for a marked instruction. ##0E0140000002C142 The processor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss for a marked instruction. #1202,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2,The processor's data page table entry was reloaded from another core's L2 from a distant chip due to a demand miss for a marked instruction. ##0E0160000002C142 The processor's data page table entry was reloaded from another core's L2 from a distant chip due to a demand miss for a marked instruction. #1203,u,g,n,n,m,u,PM_MRK_INST_FROM_DL2_ALL,The processor's instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0100000012C142 The processor's instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1204,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_ALL,The processor's instruction page table entry was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0120000012C142 The processor's instruction page table entry was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1205,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_ALL,The processor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0140000022C142 The processor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1206,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_ALL,The processor's data page table entry was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0160000022C142 The processor's data page table entry was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1207,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. ##0E8020000002C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. #1208,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. ##0E8040000002C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. #1209,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. ##0E8060000002C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. #1210,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E8020000012C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1211,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E8040000022C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1212,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E8060000022C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1213,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. ##0EC020000002C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. #1214,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. ##0EC040000002C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. #1215,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. ##0EC060000002C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. #1216,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0EC020000012C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1217,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0EC040000022C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1218,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0EC060000022C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1219,u,g,n,n,m,u,PM_MRK_INST_FROM_DL3,The processor's instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss for a marked instruction. ##0E8100000002C142 The processor's instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss for a marked instruction. #1220,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3,The processor's instruction page table entry was reloaded from another core's L3 from a distant chip due to a demand miss for a marked instruction. ##0E8120000002C142 The processor's instruction page table entry was reloaded from another core's L3 from a distant chip due to a demand miss for a marked instruction. #1221,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3,The processor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss for a marked instruction. ##0E8140000002C142 The processor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss for a marked instruction. #1222,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3,The processor's data page table entry was reloaded from another core's L3 from a distant chip due to a demand miss for a marked instruction. ##0E8160000002C142 The processor's data page table entry was reloaded from another core's L3 from a distant chip due to a demand miss for a marked instruction. #1223,u,g,n,n,m,u,PM_MRK_INST_FROM_DL3_ALL,The processor's instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E8100000012C142 The processor's instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1224,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_ALL,The processor's instruction page table entry was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E8120000012C142 The processor's instruction page table entry was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1225,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_ALL,The processor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E8140000022C142 The processor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1226,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_ALL,The processor's data page table entry was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E8160000022C142 The processor's data page table entry was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1227,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. ##0E0220000002C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. #1228,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. ##0E0240000002C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. #1229,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. ##0E0260000002C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. #1230,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0220000012C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1231,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0240000022C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1232,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0260000022C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1233,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. ##0E4220000002C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. #1234,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. ##0E4240000002C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. #1235,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. ##0E4260000002C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. #1236,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E4220000012C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1237,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E4240000022C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1238,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E4260000022C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1239,u,g,n,n,m,u,PM_MRK_INST_FROM_DL2L3,The processor's instruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. ##0E0300000002C142 The processor's instruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. #1240,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. ##0E0320000002C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. #1241,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3,The processor's L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. ##0E0340000002C142 The processor's L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. #1242,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3,The processor's data page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. ##0E0360000002C142 The processor's data page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. #1243,u,g,n,n,m,u,PM_MRK_INST_FROM_DL2L3_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0300000012C142 The processor's instruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1244,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0320000012C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1245,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0340000022C142 The processor's L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1246,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0360000022C142 The processor's data page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1247,u,g,n,n,m,u,PM_MRK_INST_FROM_DMEM,The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss for a marked instruction. ##0F4100000002C142 The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss for a marked instruction. #1248,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DMEM,The processor's instruction page table entry was reloaded from distant memory (MC slow) due to a demand miss for a marked instruction. ##0F4020000002C142 The processor's instruction page table entry was reloaded from distant memory (MC slow) due to a demand miss for a marked instruction. #1249,u,g,n,n,m,u,PM_MRK_DATA_FROM_DMEM,The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss for a marked instruction. ##0F4040000002C142 The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss for a marked instruction. #1250,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DMEM,The processor's data page table entry was reloaded from distant memory (MC slow) due to a demand miss for a marked instruction. ##0F4060000002C142 The processor's data page table entry was reloaded from distant memory (MC slow) due to a demand miss for a marked instruction. #1251,u,g,n,n,m,u,PM_MRK_INST_FROM_DMEM_ALL,The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##0F4100000012C142 The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1252,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DMEM_ALL,The processor's instruction page table entry was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##0F4020000012C142 The processor's instruction page table entry was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1253,u,g,n,n,m,u,PM_MRK_DATA_FROM_DMEM_ALL,The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##0F4040000022C142 The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1254,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DMEM_ALL,The processor's data page table entry was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##0F4060000022C142 The processor's data page table entry was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1255,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_CACHE,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss for a marked instruction. ##0F8020000002C142 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss for a marked instruction. #1256,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_CACHE,The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache due to a demand miss for a marked instruction. ##0F8040000002C142 The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache due to a demand miss for a marked instruction. #1257,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_CACHE,The processor's data page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss for a marked instruction. ##0F8060000002C142 The processor's data page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss for a marked instruction. #1258,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_CACHE_ALL,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. ##0F8020000012C142 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. #1259,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_CACHE_ALL,The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. ##0F8040000022C142 The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. #1260,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_CACHE_ALL,The processor's data page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. ##0F8060000022C142 The processor's data page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. #1261,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_MEM,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss for a marked instruction. ##0FC020000002C142 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss for a marked instruction. #1262,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_MEM,The processor's L1 data cache was reloaded from a distant chip's OpenCapp memory due to a demand miss for a marked instruction. ##0FC040000002C142 The processor's L1 data cache was reloaded from a distant chip's OpenCapp memory due to a demand miss for a marked instruction. #1263,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_MEM,The processor's data page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss for a marked instruction. ##0FC060000002C142 The processor's data page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss for a marked instruction. #1264,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_MEM_ALL,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. ##0FC020000012C142 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. #1265,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_MEM_ALL,The processor's L1 data cache was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. ##0FC040000022C142 The processor's L1 data cache was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. #1266,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_MEM_ALL,The processor's data page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. ##0FC060000022C142 The processor's data page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. #1267,u,g,n,n,m,u,PM_MRK_INST_FROM_D_OC_ANY,The processor's instruction cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##0F8100000002C142 The processor's instruction cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1268,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_ANY,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##0F8120000002C142 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1269,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_ANY,The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##0F8140000002C142 The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1270,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_ANY,The processor's data page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##0F8160000002C142 The processor's data page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1271,u,g,n,n,m,u,PM_MRK_INST_FROM_D_OC_ANY_ALL,The processor's instruction cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##0F8100000012C142 The processor's instruction cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1272,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_ANY_ALL,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##0F8120000012C142 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1273,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_ANY_ALL,The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##0F8140000022C142 The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1274,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_ANY_ALL,The processor's data page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##0F8160000022C142 The processor's data page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1275,u,g,n,n,m,u,PM_MRK_INST_FROM_ONCHIP_CACHE,The processor's instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss for a marked instruction. ##080B00000002C142 The processor's instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss for a marked instruction. #1276,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_ONCHIP_CACHE,The processor's instruction page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss for a marked instruction. ##080B20000002C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss for a marked instruction. #1277,u,g,n,n,m,u,PM_MRK_DATA_FROM_ONCHIP_CACHE,The processor's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss for a marked instruction. ##080B40000002C142 The processor's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss for a marked instruction. #1278,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_ONCHIP_CACHE,The processor's data page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss for a marked instruction. ##080B60000002C142 The processor's data page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss for a marked instruction. #1279,u,g,n,n,m,u,PM_MRK_INST_FROM_ONCHIP_CACHE_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload for a marked instruction. ##080B00000012C142 The processor's instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload for a marked instruction. #1280,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_ONCHIP_CACHE_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload for a marked instruction. ##080B20000012C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload for a marked instruction. #1281,u,g,n,n,m,u,PM_MRK_DATA_FROM_ONCHIP_CACHE_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload for a marked instruction. ##080B40000022C142 The processor's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload for a marked instruction. #1282,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_ONCHIP_CACHE_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload for a marked instruction. ##080B60000022C142 The processor's data page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload for a marked instruction. #1283,u,g,n,n,m,u,PM_MRK_INST_FROM_OFFCHIP_CACHE,The processor's instruction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss for a marked instruction. ##0C0B00000002C142 The processor's instruction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss for a marked instruction. #1284,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_OFFCHIP_CACHE,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss for a marked instruction. ##0C0B20000002C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss for a marked instruction. #1285,u,g,n,n,m,u,PM_MRK_DATA_FROM_OFFCHIP_CACHE,The processor's L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss for a marked instruction. ##0C0B40000002C142 The processor's L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss for a marked instruction. #1286,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_OFFCHIP_CACHE,The processor's data page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss for a marked instruction. ##0C0B60000002C142 The processor's data page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss for a marked instruction. #1287,u,g,n,n,m,u,PM_MRK_INST_FROM_OFFCHIP_CACHE_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload for a marked instruction. ##0C0B00000012C142 The processor's instruction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload for a marked instruction. #1288,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_OFFCHIP_CACHE_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload for a marked instruction. ##0C0B20000012C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload for a marked instruction. #1289,u,g,n,n,m,u,PM_MRK_DATA_FROM_OFFCHIP_CACHE_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload for a marked instruction. ##0C0B40000022C142 The processor's L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload for a marked instruction. #1290,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_OFFCHIP_CACHE_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload for a marked instruction. ##0C0B60000022C142 The processor's data page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload for a marked instruction. #1291,u,g,n,n,m,u,PM_MRK_INST_FROM_ANY_MEMORY,The processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss for a marked instruction. ##095900000002C142 The processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss for a marked instruction. #1292,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_ANY_MEMORY,The processor's instruction page table entry was reloaded from any chip's memory (MC slow) due to a demand miss for a marked instruction. ##095820000002C142 The processor's instruction page table entry was reloaded from any chip's memory (MC slow) due to a demand miss for a marked instruction. #1293,u,g,n,n,m,u,PM_MRK_DATA_FROM_ANY_MEMORY,The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss for a marked instruction. ##095840000002C142 The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss for a marked instruction. #1294,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_ANY_MEMORY,The processor's data page table entry was reloaded from any chip's memory (MC slow) due to a demand miss for a marked instruction. ##095860000002C142 The processor's data page table entry was reloaded from any chip's memory (MC slow) due to a demand miss for a marked instruction. #1295,u,g,n,n,m,u,PM_MRK_INST_FROM_ANY_MEMORY_ALL,The processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##095900000012C142 The processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1296,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_ANY_MEMORY_ALL,The processor's instruction page table entry was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##095820000012C142 The processor's instruction page table entry was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1297,u,g,n,n,m,u,PM_MRK_DATA_FROM_ANY_MEMORY_ALL,The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##095840000022C142 The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1298,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_ANY_MEMORY_ALL,The processor's data page table entry was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##095860000022C142 The processor's data page table entry was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1299,u,g,n,n,m,u,PM_MRK_INST_FROM_L2_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local core's L2 due to a demand miss. Divide this count by PM_MRK_INST_FROM_L2 to obtain the average L2 latency for instruction reloads. ##000300000002C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local core's L2 due to a demand miss. Divide this count by PM_MRK_INST_FROM_L2 to obtain the average L2 latency for instruction reloads. #1300,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2 to obtain the average L2 latency for instruction page table reloads. ##000320000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2 to obtain the average L2 latency for instruction page table reloads. #1301,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2 to obtain the average L2 latency for data reloads. ##000340000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2 to obtain the average L2 latency for data reloads. #1302,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2 to obtain the average L2 latency for data page table reloads. ##000360000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2 to obtain the average L2 latency for data page table reloads. #1303,u,g,n,n,m,u,PM_MRK_INST_FROM_L2_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L2_ALL to obtain the average L2_ALL latency for instruction reloads. ##000300000012C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L2_ALL to obtain the average L2_ALL latency for instruction reloads. #1304,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2_ALL to obtain the average L2_ALL latency for instruction page table reloads. ##000320000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2_ALL to obtain the average L2_ALL latency for instruction page table reloads. #1305,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2_ALL to obtain the average L2_ALL latency for data reloads. ##000340000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2_ALL to obtain the average L2_ALL latency for data reloads. #1306,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2_ALL to obtain the average L2_ALL latency for data page table reloads. ##000360000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2_ALL to obtain the average L2_ALL latency for data page table reloads. #1307,u,g,n,n,m,u,PM_MRK_INST_FROM_L1MISS_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a source beyond the local core's L1 due to a demand miss. Divide this count by PM_MRK_INST_FROM_L1MISS to obtain the average L1MISS latency for instruction reloads. ##003F00000002C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a source beyond the local core's L1 due to a demand miss. Divide this count by PM_MRK_INST_FROM_L1MISS to obtain the average L1MISS latency for instruction reloads. #1308,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L1MISS_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a source beyond the local core's L1 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L1MISS to obtain the average L1MISS latency for instruction page table reloads. ##003F20000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a source beyond the local core's L1 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L1MISS to obtain the average L1MISS latency for instruction page table reloads. #1309,u,g,n,n,m,u,PM_MRK_DATA_FROM_L1MISS_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a source beyond the local core's L1 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L1MISS to obtain the average L1MISS latency for data reloads. ##003F40000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a source beyond the local core's L1 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L1MISS to obtain the average L1MISS latency for data reloads. #1310,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L1MISS_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a source beyond the local core's L1 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L1MISS to obtain the average L1MISS latency for data page table reloads. ##003F60000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a source beyond the local core's L1 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L1MISS to obtain the average L1MISS latency for data page table reloads. #1311,u,g,n,n,m,u,PM_MRK_INST_FROM_L1MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L1MISS_ALL to obtain the average L1MISS_ALL latency for instruction reloads. ##003F00000012C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L1MISS_ALL to obtain the average L1MISS_ALL latency for instruction reloads. #1312,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L1MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L1MISS_ALL to obtain the average L1MISS_ALL latency for instruction page table reloads. ##003F20000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L1MISS_ALL to obtain the average L1MISS_ALL latency for instruction page table reloads. #1313,u,g,n,n,m,u,PM_MRK_DATA_FROM_L1MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L1MISS_ALL to obtain the average L1MISS_ALL latency for data reloads. ##003F40000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L1MISS_ALL to obtain the average L1MISS_ALL latency for data reloads. #1314,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L1MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L1MISS_ALL to obtain the average L1MISS_ALL latency for data page table reloads. ##003F60000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L1MISS_ALL to obtain the average L1MISS_ALL latency for data page table reloads. #1315,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_NO_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2_NO_CONFLICT to obtain the average L2_NO_CONFLICT latency for instruction page table reloads. ##000020000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2_NO_CONFLICT to obtain the average L2_NO_CONFLICT latency for instruction page table reloads. #1316,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2_NO_CONFLICT to obtain the average L2_NO_CONFLICT latency for data reloads. ##000040000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2_NO_CONFLICT to obtain the average L2_NO_CONFLICT latency for data reloads. #1317,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_NO_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2_NO_CONFLICT to obtain the average L2_NO_CONFLICT latency for data page table reloads. ##000060000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2_NO_CONFLICT to obtain the average L2_NO_CONFLICT latency for data page table reloads. #1318,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_NO_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2_NO_CONFLICT_ALL to obtain the average L2_NO_CONFLICT_ALL latency for instruction page table reloads. ##000020000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2_NO_CONFLICT_ALL to obtain the average L2_NO_CONFLICT_ALL latency for instruction page table reloads. #1319,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_NO_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2_NO_CONFLICT_ALL to obtain the average L2_NO_CONFLICT_ALL latency for data reloads. ##000040000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2_NO_CONFLICT_ALL to obtain the average L2_NO_CONFLICT_ALL latency for data reloads. #1320,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_NO_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2_NO_CONFLICT_ALL to obtain the average L2_NO_CONFLICT_ALL latency for data page table reloads. ##000060000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2_NO_CONFLICT_ALL to obtain the average L2_NO_CONFLICT_ALL latency for data page table reloads. #1321,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_MEPF_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2_MEPF to obtain the average L2_MEPF latency for instruction page table reloads. ##004020000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2_MEPF to obtain the average L2_MEPF latency for instruction page table reloads. #1322,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_MEPF_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2_MEPF to obtain the average L2_MEPF latency for data reloads. ##004040000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2_MEPF to obtain the average L2_MEPF latency for data reloads. #1323,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_MEPF_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2_MEPF to obtain the average L2_MEPF latency for data page table reloads. ##004060000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2_MEPF to obtain the average L2_MEPF latency for data page table reloads. #1324,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_MEPF_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2_MEPF_ALL to obtain the average L2_MEPF_ALL latency for instruction page table reloads. ##004020000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2_MEPF_ALL to obtain the average L2_MEPF_ALL latency for instruction page table reloads. #1325,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_MEPF_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2_MEPF_ALL to obtain the average L2_MEPF_ALL latency for data reloads. ##004040000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2_MEPF_ALL to obtain the average L2_MEPF_ALL latency for data reloads. #1326,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_MEPF_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2_MEPF_ALL to obtain the average L2_MEPF_ALL latency for data page table reloads. ##004060000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2_MEPF_ALL to obtain the average L2_MEPF_ALL latency for data page table reloads. #1327,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_LDHITST_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2_LDHITST_CONFLICT to obtain the average L2_LDHITST_CONFLICT latency for instruction page table reloads. ##008020000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2_LDHITST_CONFLICT to obtain the average L2_LDHITST_CONFLICT latency for instruction page table reloads. #1328,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_LDHITST_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2_LDHITST_CONFLICT to obtain the average L2_LDHITST_CONFLICT latency for data reloads. ##008040000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2_LDHITST_CONFLICT to obtain the average L2_LDHITST_CONFLICT latency for data reloads. #1329,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_LDHITST_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2_LDHITST_CONFLICT to obtain the average L2_LDHITST_CONFLICT latency for data page table reloads. ##008060000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2_LDHITST_CONFLICT to obtain the average L2_LDHITST_CONFLICT latency for data page table reloads. #1330,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_LDHITST_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2_LDHITST_CONFLICT_ALL to obtain the average L2_LDHITST_CONFLICT_ALL latency for instruction page table reloads. ##008020000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2_LDHITST_CONFLICT_ALL to obtain the average L2_LDHITST_CONFLICT_ALL latency for instruction page table reloads. #1331,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_LDHITST_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2_LDHITST_CONFLICT_ALL to obtain the average L2_LDHITST_CONFLICT_ALL latency for data reloads. ##008040000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2_LDHITST_CONFLICT_ALL to obtain the average L2_LDHITST_CONFLICT_ALL latency for data reloads. #1332,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_LDHITST_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2_LDHITST_CONFLICT_ALL to obtain the average L2_LDHITST_CONFLICT_ALL latency for data page table reloads. ##008060000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2_LDHITST_CONFLICT_ALL to obtain the average L2_LDHITST_CONFLICT_ALL latency for data page table reloads. #1333,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_OTHER_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2_OTHER_CONFLICT to obtain the average L2_OTHER_CONFLICT latency for instruction page table reloads. ##00C020000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2_OTHER_CONFLICT to obtain the average L2_OTHER_CONFLICT latency for instruction page table reloads. #1334,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_OTHER_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2_OTHER_CONFLICT to obtain the average L2_OTHER_CONFLICT latency for data reloads. ##00C040000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2_OTHER_CONFLICT to obtain the average L2_OTHER_CONFLICT latency for data reloads. #1335,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_OTHER_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2_OTHER_CONFLICT to obtain the average L2_OTHER_CONFLICT latency for data page table reloads. ##00C060000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2_OTHER_CONFLICT to obtain the average L2_OTHER_CONFLICT latency for data page table reloads. #1336,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_OTHER_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2_OTHER_CONFLICT_ALL to obtain the average L2_OTHER_CONFLICT_ALL latency for instruction page table reloads. ##00C020000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2_OTHER_CONFLICT_ALL to obtain the average L2_OTHER_CONFLICT_ALL latency for instruction page table reloads. #1337,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_OTHER_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2_OTHER_CONFLICT_ALL to obtain the average L2_OTHER_CONFLICT_ALL latency for data reloads. ##00C040000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2_OTHER_CONFLICT_ALL to obtain the average L2_OTHER_CONFLICT_ALL latency for data reloads. #1338,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_OTHER_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2_OTHER_CONFLICT_ALL to obtain the average L2_OTHER_CONFLICT_ALL latency for data page table reloads. ##00C060000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2_OTHER_CONFLICT_ALL to obtain the average L2_OTHER_CONFLICT_ALL latency for data page table reloads. #1339,u,g,n,n,m,u,PM_MRK_INST_FROM_L2MISS_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a source beyond the local core's L2 due to a demand miss. Divide this count by PM_MRK_INST_FROM_L2MISS to obtain the average L2MISS latency for instruction reloads. ##000380000002C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a source beyond the local core's L2 due to a demand miss. Divide this count by PM_MRK_INST_FROM_L2MISS to obtain the average L2MISS latency for instruction reloads. #1340,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2MISS_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a source beyond the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2MISS to obtain the average L2MISS latency for instruction page table reloads. ##0003A0000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a source beyond the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2MISS to obtain the average L2MISS latency for instruction page table reloads. #1341,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2MISS_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a source beyond the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2MISS to obtain the average L2MISS latency for data reloads. ##0003C0000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a source beyond the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2MISS to obtain the average L2MISS latency for data reloads. #1342,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2MISS_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a source beyond the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2MISS to obtain the average L2MISS latency for data page table reloads. ##0003E0000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a source beyond the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2MISS to obtain the average L2MISS latency for data page table reloads. #1343,u,g,n,n,m,u,PM_MRK_INST_FROM_L2MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L2MISS_ALL to obtain the average L2MISS_ALL latency for instruction reloads. ##000380000012C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L2MISS_ALL to obtain the average L2MISS_ALL latency for instruction reloads. #1344,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2MISS_ALL to obtain the average L2MISS_ALL latency for instruction page table reloads. ##0003A0000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2MISS_ALL to obtain the average L2MISS_ALL latency for instruction page table reloads. #1345,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2MISS_ALL to obtain the average L2MISS_ALL latency for data reloads. ##0003C0000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2MISS_ALL to obtain the average L2MISS_ALL latency for data reloads. #1346,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2MISS_ALL to obtain the average L2MISS_ALL latency for data page table reloads. ##0003E0000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2MISS_ALL to obtain the average L2MISS_ALL latency for data page table reloads. #1347,u,g,n,n,m,u,PM_MRK_INST_FROM_L3_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_INST_FROM_L3 to obtain the average L3 latency for instruction reloads. ##010300000002C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_INST_FROM_L3 to obtain the average L3 latency for instruction reloads. #1348,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L3 to obtain the average L3 latency for instruction page table reloads. ##010320000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L3 to obtain the average L3 latency for instruction page table reloads. #1349,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L3 to obtain the average L3 latency for data reloads. ##010340000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L3 to obtain the average L3 latency for data reloads. #1350,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L3 to obtain the average L3 latency for data page table reloads. ##010360000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L3 to obtain the average L3 latency for data page table reloads. #1351,u,g,n,n,m,u,PM_MRK_INST_FROM_L3_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L3_ALL to obtain the average L3_ALL latency for instruction reloads. ##010300000012C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L3_ALL to obtain the average L3_ALL latency for instruction reloads. #1352,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L3_ALL to obtain the average L3_ALL latency for instruction page table reloads. ##010320000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L3_ALL to obtain the average L3_ALL latency for instruction page table reloads. #1353,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L3_ALL to obtain the average L3_ALL latency for data reloads. ##010340000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L3_ALL to obtain the average L3_ALL latency for data reloads. #1354,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L3_ALL to obtain the average L3_ALL latency for data page table reloads. ##010360000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L3_ALL to obtain the average L3_ALL latency for data page table reloads. #1355,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_NO_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L3_NO_CONFLICT to obtain the average L3_NO_CONFLICT latency for instruction page table reloads. ##010020000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L3_NO_CONFLICT to obtain the average L3_NO_CONFLICT latency for instruction page table reloads. #1356,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L3_NO_CONFLICT to obtain the average L3_NO_CONFLICT latency for data reloads. ##010040000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L3_NO_CONFLICT to obtain the average L3_NO_CONFLICT latency for data reloads. #1357,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_NO_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L3_NO_CONFLICT to obtain the average L3_NO_CONFLICT latency for data page table reloads. ##010060000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L3_NO_CONFLICT to obtain the average L3_NO_CONFLICT latency for data page table reloads. #1358,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_NO_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L3_NO_CONFLICT_ALL to obtain the average L3_NO_CONFLICT_ALL latency for instruction page table reloads. ##010020000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L3_NO_CONFLICT_ALL to obtain the average L3_NO_CONFLICT_ALL latency for instruction page table reloads. #1359,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_NO_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L3_NO_CONFLICT_ALL to obtain the average L3_NO_CONFLICT_ALL latency for data reloads. ##010040000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L3_NO_CONFLICT_ALL to obtain the average L3_NO_CONFLICT_ALL latency for data reloads. #1360,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_NO_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L3_NO_CONFLICT_ALL to obtain the average L3_NO_CONFLICT_ALL latency for data page table reloads. ##010060000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L3_NO_CONFLICT_ALL to obtain the average L3_NO_CONFLICT_ALL latency for data page table reloads. #1361,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_MEPF_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L3_MEPF to obtain the average L3_MEPF latency for instruction page table reloads. ##014020000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L3_MEPF to obtain the average L3_MEPF latency for instruction page table reloads. #1362,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_MEPF_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L3_MEPF to obtain the average L3_MEPF latency for data reloads. ##014040000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L3_MEPF to obtain the average L3_MEPF latency for data reloads. #1363,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_MEPF_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L3_MEPF to obtain the average L3_MEPF latency for data page table reloads. ##014060000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L3_MEPF to obtain the average L3_MEPF latency for data page table reloads. #1364,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_MEPF_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L3_MEPF_ALL to obtain the average L3_MEPF_ALL latency for instruction page table reloads. ##014020000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L3_MEPF_ALL to obtain the average L3_MEPF_ALL latency for instruction page table reloads. #1365,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_MEPF_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L3_MEPF_ALL to obtain the average L3_MEPF_ALL latency for data reloads. ##014040000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L3_MEPF_ALL to obtain the average L3_MEPF_ALL latency for data reloads. #1366,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_MEPF_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L3_MEPF_ALL to obtain the average L3_MEPF_ALL latency for data page table reloads. ##014060000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L3_MEPF_ALL to obtain the average L3_MEPF_ALL latency for data page table reloads. #1367,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L3_CONFLICT to obtain the average L3_CONFLICT latency for instruction page table reloads. ##01C020000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L3_CONFLICT to obtain the average L3_CONFLICT latency for instruction page table reloads. #1368,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L3_CONFLICT to obtain the average L3_CONFLICT latency for data reloads. ##01C040000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L3_CONFLICT to obtain the average L3_CONFLICT latency for data reloads. #1369,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L3_CONFLICT to obtain the average L3_CONFLICT latency for data page table reloads. ##01C060000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L3_CONFLICT to obtain the average L3_CONFLICT latency for data page table reloads. #1370,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L3_CONFLICT_ALL to obtain the average L3_CONFLICT_ALL latency for instruction page table reloads. ##01C020000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L3_CONFLICT_ALL to obtain the average L3_CONFLICT_ALL latency for instruction page table reloads. #1371,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L3_CONFLICT_ALL to obtain the average L3_CONFLICT_ALL latency for data reloads. ##01C040000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L3_CONFLICT_ALL to obtain the average L3_CONFLICT_ALL latency for data reloads. #1372,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L3_CONFLICT_ALL to obtain the average L3_CONFLICT_ALL latency for data page table reloads. ##01C060000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L3_CONFLICT_ALL to obtain the average L3_CONFLICT_ALL latency for data page table reloads. #1373,u,g,n,n,m,u,PM_MRK_INST_FROM_L3MISS_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from beyond the local core's L3 due to a demand miss. Divide this count by PM_MRK_INST_FROM_L3MISS to obtain the average L3MISS latency for instruction reloads. ##000780000002C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from beyond the local core's L3 due to a demand miss. Divide this count by PM_MRK_INST_FROM_L3MISS to obtain the average L3MISS latency for instruction reloads. #1374,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3MISS_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from beyond the local core's L3 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L3MISS to obtain the average L3MISS latency for instruction page table reloads. ##0007A0000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from beyond the local core's L3 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L3MISS to obtain the average L3MISS latency for instruction page table reloads. #1375,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3MISS_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from beyond the local core's L3 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L3MISS to obtain the average L3MISS latency for data reloads. ##0007C0000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from beyond the local core's L3 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L3MISS to obtain the average L3MISS latency for data reloads. #1376,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3MISS_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from beyond the local core's L3 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L3MISS to obtain the average L3MISS latency for data page table reloads. ##0007E0000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from beyond the local core's L3 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L3MISS to obtain the average L3MISS latency for data page table reloads. #1377,u,g,n,n,m,u,PM_MRK_INST_FROM_L3MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L3MISS_ALL to obtain the average L3MISS_ALL latency for instruction reloads. ##000780000012C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L3MISS_ALL to obtain the average L3MISS_ALL latency for instruction reloads. #1378,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L3MISS_ALL to obtain the average L3MISS_ALL latency for instruction page table reloads. ##0007A0000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L3MISS_ALL to obtain the average L3MISS_ALL latency for instruction page table reloads. #1379,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L3MISS_ALL to obtain the average L3MISS_ALL latency for data reloads. ##0007C0000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L3MISS_ALL to obtain the average L3MISS_ALL latency for data reloads. #1380,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L3MISS_ALL to obtain the average L3MISS_ALL latency for data page table reloads. ##0007E0000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L3MISS_ALL to obtain the average L3MISS_ALL latency for data page table reloads. #1381,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT_SHR to obtain the average L21_REGENT_SHR latency for instruction page table reloads. ##080020000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT_SHR to obtain the average L21_REGENT_SHR latency for instruction page table reloads. #1382,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_REGENT_SHR to obtain the average L21_REGENT_SHR latency for data reloads. ##080040000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_REGENT_SHR to obtain the average L21_REGENT_SHR latency for data reloads. #1383,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT_SHR to obtain the average L21_REGENT_SHR latency for data page table reloads. ##080060000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT_SHR to obtain the average L21_REGENT_SHR latency for data page table reloads. #1384,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT_SHR_ALL to obtain the average L21_REGENT_SHR_ALL latency for instruction page table reloads. ##080020000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT_SHR_ALL to obtain the average L21_REGENT_SHR_ALL latency for instruction page table reloads. #1385,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_REGENT_SHR_ALL to obtain the average L21_REGENT_SHR_ALL latency for data reloads. ##080040000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_REGENT_SHR_ALL to obtain the average L21_REGENT_SHR_ALL latency for data reloads. #1386,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT_SHR_ALL to obtain the average L21_REGENT_SHR_ALL latency for data page table reloads. ##080060000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT_SHR_ALL to obtain the average L21_REGENT_SHR_ALL latency for data page table reloads. #1387,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT_MOD to obtain the average L21_REGENT_MOD latency for instruction page table reloads. ##084020000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT_MOD to obtain the average L21_REGENT_MOD latency for instruction page table reloads. #1388,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_REGENT_MOD to obtain the average L21_REGENT_MOD latency for data reloads. ##084040000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_REGENT_MOD to obtain the average L21_REGENT_MOD latency for data reloads. #1389,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT_MOD to obtain the average L21_REGENT_MOD latency for data page table reloads. ##084060000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT_MOD to obtain the average L21_REGENT_MOD latency for data page table reloads. #1390,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT_MOD_ALL to obtain the average L21_REGENT_MOD_ALL latency for instruction page table reloads. ##084020000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT_MOD_ALL to obtain the average L21_REGENT_MOD_ALL latency for instruction page table reloads. #1391,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_REGENT_MOD_ALL to obtain the average L21_REGENT_MOD_ALL latency for data reloads. ##084040000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_REGENT_MOD_ALL to obtain the average L21_REGENT_MOD_ALL latency for data reloads. #1392,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT_MOD_ALL to obtain the average L21_REGENT_MOD_ALL latency for data page table reloads. ##084060000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT_MOD_ALL to obtain the average L21_REGENT_MOD_ALL latency for data page table reloads. #1393,u,g,n,n,m,u,PM_MRK_INST_FROM_L21_REGENT_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_L21_REGENT to obtain the average L21_REGENT latency for instruction reloads. ##080100000002C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_L21_REGENT to obtain the average L21_REGENT latency for instruction reloads. #1394,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT to obtain the average L21_REGENT latency for instruction page table reloads. ##080120000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT to obtain the average L21_REGENT latency for instruction page table reloads. #1395,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_REGENT to obtain the average L21_REGENT latency for data reloads. ##080140000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_REGENT to obtain the average L21_REGENT latency for data reloads. #1396,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT to obtain the average L21_REGENT latency for data page table reloads. ##080160000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT to obtain the average L21_REGENT latency for data page table reloads. #1397,u,g,n,n,m,u,PM_MRK_INST_FROM_L21_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L21_REGENT_ALL to obtain the average L21_REGENT_ALL latency for instruction reloads. ##080100000012C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L21_REGENT_ALL to obtain the average L21_REGENT_ALL latency for instruction reloads. #1398,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT_ALL to obtain the average L21_REGENT_ALL latency for instruction page table reloads. ##080120000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT_ALL to obtain the average L21_REGENT_ALL latency for instruction page table reloads. #1399,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_REGENT_ALL to obtain the average L21_REGENT_ALL latency for data reloads. ##080140000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_REGENT_ALL to obtain the average L21_REGENT_ALL latency for data reloads. #1400,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT_ALL to obtain the average L21_REGENT_ALL latency for data page table reloads. ##080160000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT_ALL to obtain the average L21_REGENT_ALL latency for data page table reloads. #1401,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT_SHR to obtain the average L31_REGENT_SHR latency for instruction page table reloads. ##088020000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT_SHR to obtain the average L31_REGENT_SHR latency for instruction page table reloads. #1402,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_REGENT_SHR to obtain the average L31_REGENT_SHR latency for data reloads. ##088040000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_REGENT_SHR to obtain the average L31_REGENT_SHR latency for data reloads. #1403,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT_SHR to obtain the average L31_REGENT_SHR latency for data page table reloads. ##088060000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT_SHR to obtain the average L31_REGENT_SHR latency for data page table reloads. #1404,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT_SHR_ALL to obtain the average L31_REGENT_SHR_ALL latency for instruction page table reloads. ##088020000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT_SHR_ALL to obtain the average L31_REGENT_SHR_ALL latency for instruction page table reloads. #1405,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_REGENT_SHR_ALL to obtain the average L31_REGENT_SHR_ALL latency for data reloads. ##088040000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_REGENT_SHR_ALL to obtain the average L31_REGENT_SHR_ALL latency for data reloads. #1406,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT_SHR_ALL to obtain the average L31_REGENT_SHR_ALL latency for data page table reloads. ##088060000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT_SHR_ALL to obtain the average L31_REGENT_SHR_ALL latency for data page table reloads. #1407,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT_MOD to obtain the average L31_REGENT_MOD latency for instruction page table reloads. ##08C020000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT_MOD to obtain the average L31_REGENT_MOD latency for instruction page table reloads. #1408,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_REGENT_MOD to obtain the average L31_REGENT_MOD latency for data reloads. ##08C040000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_REGENT_MOD to obtain the average L31_REGENT_MOD latency for data reloads. #1409,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT_MOD to obtain the average L31_REGENT_MOD latency for data page table reloads. ##08C060000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT_MOD to obtain the average L31_REGENT_MOD latency for data page table reloads. #1410,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT_MOD_ALL to obtain the average L31_REGENT_MOD_ALL latency for instruction page table reloads. ##08C020000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT_MOD_ALL to obtain the average L31_REGENT_MOD_ALL latency for instruction page table reloads. #1411,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_REGENT_MOD_ALL to obtain the average L31_REGENT_MOD_ALL latency for data reloads. ##08C040000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_REGENT_MOD_ALL to obtain the average L31_REGENT_MOD_ALL latency for data reloads. #1412,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT_MOD_ALL to obtain the average L31_REGENT_MOD_ALL latency for data page table reloads. ##08C060000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT_MOD_ALL to obtain the average L31_REGENT_MOD_ALL latency for data page table reloads. #1413,u,g,n,n,m,u,PM_MRK_INST_FROM_L31_REGENT_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_L31_REGENT to obtain the average L31_REGENT latency for instruction reloads. ##088100000002C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_L31_REGENT to obtain the average L31_REGENT latency for instruction reloads. #1414,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT to obtain the average L31_REGENT latency for instruction page table reloads. ##088120000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT to obtain the average L31_REGENT latency for instruction page table reloads. #1415,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_REGENT to obtain the average L31_REGENT latency for data reloads. ##088140000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_REGENT to obtain the average L31_REGENT latency for data reloads. #1416,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT to obtain the average L31_REGENT latency for data page table reloads. ##088160000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT to obtain the average L31_REGENT latency for data page table reloads. #1417,u,g,n,n,m,u,PM_MRK_INST_FROM_L31_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L31_REGENT_ALL to obtain the average L31_REGENT_ALL latency for instruction reloads. ##088100000012C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L31_REGENT_ALL to obtain the average L31_REGENT_ALL latency for instruction reloads. #1418,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT_ALL to obtain the average L31_REGENT_ALL latency for instruction page table reloads. ##088120000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT_ALL to obtain the average L31_REGENT_ALL latency for instruction page table reloads. #1419,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_REGENT_ALL to obtain the average L31_REGENT_ALL latency for data reloads. ##088140000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_REGENT_ALL to obtain the average L31_REGENT_ALL latency for data reloads. #1420,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT_ALL to obtain the average L31_REGENT_ALL latency for data page table reloads. ##088160000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT_ALL to obtain the average L31_REGENT_ALL latency for data page table reloads. #1421,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3_SHR to obtain the average REGENT_L2L3_SHR latency for instruction page table reloads. ##080220000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3_SHR to obtain the average REGENT_L2L3_SHR latency for instruction page table reloads. #1422,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3_SHR to obtain the average REGENT_L2L3_SHR latency for data reloads. ##080240000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3_SHR to obtain the average REGENT_L2L3_SHR latency for data reloads. #1423,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3_SHR to obtain the average REGENT_L2L3_SHR latency for data page table reloads. ##080260000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3_SHR to obtain the average REGENT_L2L3_SHR latency for data page table reloads. #1424,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3_SHR_ALL to obtain the average REGENT_L2L3_SHR_ALL latency for instruction page table reloads. ##080220000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3_SHR_ALL to obtain the average REGENT_L2L3_SHR_ALL latency for instruction page table reloads. #1425,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3_SHR_ALL to obtain the average REGENT_L2L3_SHR_ALL latency for data reloads. ##080240000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3_SHR_ALL to obtain the average REGENT_L2L3_SHR_ALL latency for data reloads. #1426,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3_SHR_ALL to obtain the average REGENT_L2L3_SHR_ALL latency for data page table reloads. ##080260000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3_SHR_ALL to obtain the average REGENT_L2L3_SHR_ALL latency for data page table reloads. #1427,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3_MOD to obtain the average REGENT_L2L3_MOD latency for instruction page table reloads. ##084220000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3_MOD to obtain the average REGENT_L2L3_MOD latency for instruction page table reloads. #1428,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3_MOD to obtain the average REGENT_L2L3_MOD latency for data reloads. ##084240000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3_MOD to obtain the average REGENT_L2L3_MOD latency for data reloads. #1429,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3_MOD to obtain the average REGENT_L2L3_MOD latency for data page table reloads. ##084260000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3_MOD to obtain the average REGENT_L2L3_MOD latency for data page table reloads. #1430,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3_MOD_ALL to obtain the average REGENT_L2L3_MOD_ALL latency for instruction page table reloads. ##084220000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3_MOD_ALL to obtain the average REGENT_L2L3_MOD_ALL latency for instruction page table reloads. #1431,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3_MOD_ALL to obtain the average REGENT_L2L3_MOD_ALL latency for data reloads. ##084240000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3_MOD_ALL to obtain the average REGENT_L2L3_MOD_ALL latency for data reloads. #1432,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3_MOD_ALL to obtain the average REGENT_L2L3_MOD_ALL latency for data page table reloads. ##084260000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3_MOD_ALL to obtain the average REGENT_L2L3_MOD_ALL latency for data page table reloads. #1433,u,g,n,n,m,u,PM_MRK_INST_FROM_REGENT_L2L3_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_REGENT_L2L3 to obtain the average REGENT_L2L3 latency for instruction reloads. ##080300000002C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_REGENT_L2L3 to obtain the average REGENT_L2L3 latency for instruction reloads. #1434,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3 to obtain the average REGENT_L2L3 latency for instruction page table reloads. ##080320000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3 to obtain the average REGENT_L2L3 latency for instruction page table reloads. #1435,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3 to obtain the average REGENT_L2L3 latency for data reloads. ##080340000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3 to obtain the average REGENT_L2L3 latency for data reloads. #1436,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3 to obtain the average REGENT_L2L3 latency for data page table reloads. ##080360000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3 to obtain the average REGENT_L2L3 latency for data page table reloads. #1437,u,g,n,n,m,u,PM_MRK_INST_FROM_REGENT_L2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_REGENT_L2L3_ALL to obtain the average REGENT_L2L3_ALL latency for instruction reloads. ##080300000012C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_REGENT_L2L3_ALL to obtain the average REGENT_L2L3_ALL latency for instruction reloads. #1438,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3_ALL to obtain the average REGENT_L2L3_ALL latency for instruction page table reloads. ##080320000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3_ALL to obtain the average REGENT_L2L3_ALL latency for instruction page table reloads. #1439,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3_ALL to obtain the average REGENT_L2L3_ALL latency for data reloads. ##080340000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3_ALL to obtain the average REGENT_L2L3_ALL latency for data reloads. #1440,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3_ALL to obtain the average REGENT_L2L3_ALL latency for data page table reloads. ##080360000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3_ALL to obtain the average REGENT_L2L3_ALL latency for data page table reloads. #1441,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT_SHR to obtain the average L21_NON_REGENT_SHR latency for instruction page table reloads. ##0A0020000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT_SHR to obtain the average L21_NON_REGENT_SHR latency for instruction page table reloads. #1442,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT_SHR to obtain the average L21_NON_REGENT_SHR latency for data reloads. ##0A0040000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT_SHR to obtain the average L21_NON_REGENT_SHR latency for data reloads. #1443,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT_SHR to obtain the average L21_NON_REGENT_SHR latency for data page table reloads. ##0A0060000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT_SHR to obtain the average L21_NON_REGENT_SHR latency for data page table reloads. #1444,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT_SHR_ALL to obtain the average L21_NON_REGENT_SHR_ALL latency for instruction page table reloads. ##0A0020000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT_SHR_ALL to obtain the average L21_NON_REGENT_SHR_ALL latency for instruction page table reloads. #1445,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT_SHR_ALL to obtain the average L21_NON_REGENT_SHR_ALL latency for data reloads. ##0A0040000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT_SHR_ALL to obtain the average L21_NON_REGENT_SHR_ALL latency for data reloads. #1446,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT_SHR_ALL to obtain the average L21_NON_REGENT_SHR_ALL latency for data page table reloads. ##0A0060000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT_SHR_ALL to obtain the average L21_NON_REGENT_SHR_ALL latency for data page table reloads. #1447,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT_MOD to obtain the average L21_NON_REGENT_MOD latency for instruction page table reloads. ##0A4020000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT_MOD to obtain the average L21_NON_REGENT_MOD latency for instruction page table reloads. #1448,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT_MOD to obtain the average L21_NON_REGENT_MOD latency for data reloads. ##0A4040000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT_MOD to obtain the average L21_NON_REGENT_MOD latency for data reloads. #1449,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT_MOD to obtain the average L21_NON_REGENT_MOD latency for data page table reloads. ##0A4060000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT_MOD to obtain the average L21_NON_REGENT_MOD latency for data page table reloads. #1450,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT_MOD_ALL to obtain the average L21_NON_REGENT_MOD_ALL latency for instruction page table reloads. ##0A4020000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT_MOD_ALL to obtain the average L21_NON_REGENT_MOD_ALL latency for instruction page table reloads. #1451,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT_MOD_ALL to obtain the average L21_NON_REGENT_MOD_ALL latency for data reloads. ##0A4040000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT_MOD_ALL to obtain the average L21_NON_REGENT_MOD_ALL latency for data reloads. #1452,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT_MOD_ALL to obtain the average L21_NON_REGENT_MOD_ALL latency for data page table reloads. ##0A4060000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT_MOD_ALL to obtain the average L21_NON_REGENT_MOD_ALL latency for data page table reloads. #1453,u,g,n,n,m,u,PM_MRK_INST_FROM_L21_NON_REGENT_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_L21_NON_REGENT to obtain the average L21_NON_REGENT latency for instruction reloads. ##0A0100000002C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_L21_NON_REGENT to obtain the average L21_NON_REGENT latency for instruction reloads. #1454,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT to obtain the average L21_NON_REGENT latency for instruction page table reloads. ##0A0120000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT to obtain the average L21_NON_REGENT latency for instruction page table reloads. #1455,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT to obtain the average L21_NON_REGENT latency for data reloads. ##0A0140000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT to obtain the average L21_NON_REGENT latency for data reloads. #1456,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT to obtain the average L21_NON_REGENT latency for data page table reloads. ##0A0160000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT to obtain the average L21_NON_REGENT latency for data page table reloads. #1457,u,g,n,n,m,u,PM_MRK_INST_FROM_L21_NON_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L21_NON_REGENT_ALL to obtain the average L21_NON_REGENT_ALL latency for instruction reloads. ##0A0100000012C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L21_NON_REGENT_ALL to obtain the average L21_NON_REGENT_ALL latency for instruction reloads. #1458,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT_ALL to obtain the average L21_NON_REGENT_ALL latency for instruction page table reloads. ##0A0120000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT_ALL to obtain the average L21_NON_REGENT_ALL latency for instruction page table reloads. #1459,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT_ALL to obtain the average L21_NON_REGENT_ALL latency for data reloads. ##0A0140000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT_ALL to obtain the average L21_NON_REGENT_ALL latency for data reloads. #1460,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT_ALL to obtain the average L21_NON_REGENT_ALL latency for data page table reloads. ##0A0160000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT_ALL to obtain the average L21_NON_REGENT_ALL latency for data page table reloads. #1461,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT_SHR to obtain the average L31_NON_REGENT_SHR latency for instruction page table reloads. ##0A8020000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT_SHR to obtain the average L31_NON_REGENT_SHR latency for instruction page table reloads. #1462,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT_SHR to obtain the average L31_NON_REGENT_SHR latency for data reloads. ##0A8040000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT_SHR to obtain the average L31_NON_REGENT_SHR latency for data reloads. #1463,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT_SHR to obtain the average L31_NON_REGENT_SHR latency for data page table reloads. ##0A8060000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT_SHR to obtain the average L31_NON_REGENT_SHR latency for data page table reloads. #1464,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT_SHR_ALL to obtain the average L31_NON_REGENT_SHR_ALL latency for instruction page table reloads. ##0A8020000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT_SHR_ALL to obtain the average L31_NON_REGENT_SHR_ALL latency for instruction page table reloads. #1465,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT_SHR_ALL to obtain the average L31_NON_REGENT_SHR_ALL latency for data reloads. ##0A8040000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT_SHR_ALL to obtain the average L31_NON_REGENT_SHR_ALL latency for data reloads. #1466,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT_SHR_ALL to obtain the average L31_NON_REGENT_SHR_ALL latency for data page table reloads. ##0A8060000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT_SHR_ALL to obtain the average L31_NON_REGENT_SHR_ALL latency for data page table reloads. #1467,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT_MOD to obtain the average L31_NON_REGENT_MOD latency for instruction page table reloads. ##0AC020000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT_MOD to obtain the average L31_NON_REGENT_MOD latency for instruction page table reloads. #1468,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT_MOD to obtain the average L31_NON_REGENT_MOD latency for data reloads. ##0AC040000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT_MOD to obtain the average L31_NON_REGENT_MOD latency for data reloads. #1469,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT_MOD to obtain the average L31_NON_REGENT_MOD latency for data page table reloads. ##0AC060000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT_MOD to obtain the average L31_NON_REGENT_MOD latency for data page table reloads. #1470,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT_MOD_ALL to obtain the average L31_NON_REGENT_MOD_ALL latency for instruction page table reloads. ##0AC020000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT_MOD_ALL to obtain the average L31_NON_REGENT_MOD_ALL latency for instruction page table reloads. #1471,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT_MOD_ALL to obtain the average L31_NON_REGENT_MOD_ALL latency for data reloads. ##0AC040000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT_MOD_ALL to obtain the average L31_NON_REGENT_MOD_ALL latency for data reloads. #1472,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT_MOD_ALL to obtain the average L31_NON_REGENT_MOD_ALL latency for data page table reloads. ##0AC060000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT_MOD_ALL to obtain the average L31_NON_REGENT_MOD_ALL latency for data page table reloads. #1473,u,g,n,n,m,u,PM_MRK_INST_FROM_L31_NON_REGENT_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_L31_NON_REGENT to obtain the average L31_NON_REGENT latency for instruction reloads. ##0A8100000002C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_L31_NON_REGENT to obtain the average L31_NON_REGENT latency for instruction reloads. #1474,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT to obtain the average L31_NON_REGENT latency for instruction page table reloads. ##0A8120000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT to obtain the average L31_NON_REGENT latency for instruction page table reloads. #1475,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT to obtain the average L31_NON_REGENT latency for data reloads. ##0A8140000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT to obtain the average L31_NON_REGENT latency for data reloads. #1476,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT to obtain the average L31_NON_REGENT latency for data page table reloads. ##0A8160000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT to obtain the average L31_NON_REGENT latency for data page table reloads. #1477,u,g,n,n,m,u,PM_MRK_INST_FROM_L31_NON_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L31_NON_REGENT_ALL to obtain the average L31_NON_REGENT_ALL latency for instruction reloads. ##0A8100000012C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L31_NON_REGENT_ALL to obtain the average L31_NON_REGENT_ALL latency for instruction reloads. #1478,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT_ALL to obtain the average L31_NON_REGENT_ALL latency for instruction page table reloads. ##0A8120000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT_ALL to obtain the average L31_NON_REGENT_ALL latency for instruction page table reloads. #1479,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT_ALL to obtain the average L31_NON_REGENT_ALL latency for data reloads. ##0A8140000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT_ALL to obtain the average L31_NON_REGENT_ALL latency for data reloads. #1480,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT_ALL to obtain the average L31_NON_REGENT_ALL latency for data page table reloads. ##0A8160000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT_ALL to obtain the average L31_NON_REGENT_ALL latency for data page table reloads. #1481,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_SHR to obtain the average NON_REGENT_L2L3_SHR latency for instruction page table reloads. ##0A0220000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_SHR to obtain the average NON_REGENT_L2L3_SHR latency for instruction page table reloads. #1482,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3_SHR to obtain the average NON_REGENT_L2L3_SHR latency for data reloads. ##0A0240000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3_SHR to obtain the average NON_REGENT_L2L3_SHR latency for data reloads. #1483,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_SHR to obtain the average NON_REGENT_L2L3_SHR latency for data page table reloads. ##0A0260000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_SHR to obtain the average NON_REGENT_L2L3_SHR latency for data page table reloads. #1484,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_SHR_ALL to obtain the average NON_REGENT_L2L3_SHR_ALL latency for instruction page table reloads. ##0A0220000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_SHR_ALL to obtain the average NON_REGENT_L2L3_SHR_ALL latency for instruction page table reloads. #1485,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3_SHR_ALL to obtain the average NON_REGENT_L2L3_SHR_ALL latency for data reloads. ##0A0240000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3_SHR_ALL to obtain the average NON_REGENT_L2L3_SHR_ALL latency for data reloads. #1486,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_SHR_ALL to obtain the average NON_REGENT_L2L3_SHR_ALL latency for data page table reloads. ##0A0260000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_SHR_ALL to obtain the average NON_REGENT_L2L3_SHR_ALL latency for data page table reloads. #1487,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_MOD to obtain the average NON_REGENT_L2L3_MOD latency for instruction page table reloads. ##0A4220000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_MOD to obtain the average NON_REGENT_L2L3_MOD latency for instruction page table reloads. #1488,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3_MOD to obtain the average NON_REGENT_L2L3_MOD latency for data reloads. ##0A4240000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3_MOD to obtain the average NON_REGENT_L2L3_MOD latency for data reloads. #1489,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_MOD to obtain the average NON_REGENT_L2L3_MOD latency for data page table reloads. ##0A4260000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_MOD to obtain the average NON_REGENT_L2L3_MOD latency for data page table reloads. #1490,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_MOD_ALL to obtain the average NON_REGENT_L2L3_MOD_ALL latency for instruction page table reloads. ##0A4220000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_MOD_ALL to obtain the average NON_REGENT_L2L3_MOD_ALL latency for instruction page table reloads. #1491,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3_MOD_ALL to obtain the average NON_REGENT_L2L3_MOD_ALL latency for data reloads. ##0A4240000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3_MOD_ALL to obtain the average NON_REGENT_L2L3_MOD_ALL latency for data reloads. #1492,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_MOD_ALL to obtain the average NON_REGENT_L2L3_MOD_ALL latency for data page table reloads. ##0A4260000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_MOD_ALL to obtain the average NON_REGENT_L2L3_MOD_ALL latency for data page table reloads. #1493,u,g,n,n,m,u,PM_MRK_INST_FROM_NON_REGENT_L2L3_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_NON_REGENT_L2L3 to obtain the average NON_REGENT_L2L3 latency for instruction reloads. ##0A0300000002C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_NON_REGENT_L2L3 to obtain the average NON_REGENT_L2L3 latency for instruction reloads. #1494,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3 to obtain the average NON_REGENT_L2L3 latency for instruction page table reloads. ##0A0320000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3 to obtain the average NON_REGENT_L2L3 latency for instruction page table reloads. #1495,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3 to obtain the average NON_REGENT_L2L3 latency for data reloads. ##0A0340000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3 to obtain the average NON_REGENT_L2L3 latency for data reloads. #1496,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3 to obtain the average NON_REGENT_L2L3 latency for data page table reloads. ##0A0360000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3 to obtain the average NON_REGENT_L2L3 latency for data page table reloads. #1497,u,g,n,n,m,u,PM_MRK_INST_FROM_NON_REGENT_L2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_NON_REGENT_L2L3_ALL to obtain the average NON_REGENT_L2L3_ALL latency for instruction reloads. ##0A0300000012C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_NON_REGENT_L2L3_ALL to obtain the average NON_REGENT_L2L3_ALL latency for instruction reloads. #1498,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_ALL to obtain the average NON_REGENT_L2L3_ALL latency for instruction page table reloads. ##0A0320000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_ALL to obtain the average NON_REGENT_L2L3_ALL latency for instruction page table reloads. #1499,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3_ALL to obtain the average NON_REGENT_L2L3_ALL latency for data reloads. ##0A0340000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3_ALL to obtain the average NON_REGENT_L2L3_ALL latency for data reloads. #1500,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_ALL to obtain the average NON_REGENT_L2L3_ALL latency for data page table reloads. ##0A0360000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_ALL to obtain the average NON_REGENT_L2L3_ALL latency for data page table reloads. #1501,u,g,n,n,m,u,PM_MRK_INST_FROM_LMEM_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local chip's memory due to a demand miss. Divide this count by PM_MRK_INST_FROM_LMEM to obtain the average LMEM latency for instruction reloads. ##094100000002C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local chip's memory due to a demand miss. Divide this count by PM_MRK_INST_FROM_LMEM to obtain the average LMEM latency for instruction reloads. #1502,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_LMEM_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_LMEM to obtain the average LMEM latency for instruction page table reloads. ##094020000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_LMEM to obtain the average LMEM latency for instruction page table reloads. #1503,u,g,n,n,m,u,PM_MRK_DATA_FROM_LMEM_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_LMEM to obtain the average LMEM latency for data reloads. ##094040000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_LMEM to obtain the average LMEM latency for data reloads. #1504,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_LMEM_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_LMEM to obtain the average LMEM latency for data page table reloads. ##094060000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_LMEM to obtain the average LMEM latency for data page table reloads. #1505,u,g,n,n,m,u,PM_MRK_INST_FROM_LMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local chip's memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_LMEM_ALL to obtain the average LMEM_ALL latency for instruction reloads. ##094100000012C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local chip's memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_LMEM_ALL to obtain the average LMEM_ALL latency for instruction reloads. #1506,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_LMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_LMEM_ALL to obtain the average LMEM_ALL latency for instruction page table reloads. ##094020000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_LMEM_ALL to obtain the average LMEM_ALL latency for instruction page table reloads. #1507,u,g,n,n,m,u,PM_MRK_DATA_FROM_LMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_LMEM_ALL to obtain the average LMEM_ALL latency for data reloads. ##094040000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_LMEM_ALL to obtain the average LMEM_ALL latency for data reloads. #1508,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_LMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_LMEM_ALL to obtain the average LMEM_ALL latency for data page table reloads. ##094060000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_LMEM_ALL to obtain the average LMEM_ALL latency for data page table reloads. #1509,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_CACHE_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L_OC_CACHE to obtain the average L_OC_CACHE latency for instruction page table reloads. ##098020000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L_OC_CACHE to obtain the average L_OC_CACHE latency for instruction page table reloads. #1510,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_CACHE_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L_OC_CACHE to obtain the average L_OC_CACHE latency for data reloads. ##098040000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L_OC_CACHE to obtain the average L_OC_CACHE latency for data reloads. #1511,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_CACHE_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L_OC_CACHE to obtain the average L_OC_CACHE latency for data page table reloads. ##098060000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L_OC_CACHE to obtain the average L_OC_CACHE latency for data page table reloads. #1512,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L_OC_CACHE_ALL to obtain the average L_OC_CACHE_ALL latency for instruction page table reloads. ##098020000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L_OC_CACHE_ALL to obtain the average L_OC_CACHE_ALL latency for instruction page table reloads. #1513,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L_OC_CACHE_ALL to obtain the average L_OC_CACHE_ALL latency for data reloads. ##098040000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L_OC_CACHE_ALL to obtain the average L_OC_CACHE_ALL latency for data reloads. #1514,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L_OC_CACHE_ALL to obtain the average L_OC_CACHE_ALL latency for data page table reloads. ##098060000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L_OC_CACHE_ALL to obtain the average L_OC_CACHE_ALL latency for data page table reloads. #1515,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_MEM_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L_OC_MEM to obtain the average L_OC_MEM latency for instruction page table reloads. ##09C020000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L_OC_MEM to obtain the average L_OC_MEM latency for instruction page table reloads. #1516,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_MEM_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L_OC_MEM to obtain the average L_OC_MEM latency for data reloads. ##09C040000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L_OC_MEM to obtain the average L_OC_MEM latency for data reloads. #1517,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_MEM_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L_OC_MEM to obtain the average L_OC_MEM latency for data page table reloads. ##09C060000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L_OC_MEM to obtain the average L_OC_MEM latency for data page table reloads. #1518,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_MEM_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L_OC_MEM_ALL to obtain the average L_OC_MEM_ALL latency for instruction page table reloads. ##09C020000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L_OC_MEM_ALL to obtain the average L_OC_MEM_ALL latency for instruction page table reloads. #1519,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_MEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L_OC_MEM_ALL to obtain the average L_OC_MEM_ALL latency for data reloads. ##09C040000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L_OC_MEM_ALL to obtain the average L_OC_MEM_ALL latency for data reloads. #1520,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_MEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L_OC_MEM_ALL to obtain the average L_OC_MEM_ALL latency for data page table reloads. ##09C060000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L_OC_MEM_ALL to obtain the average L_OC_MEM_ALL latency for data page table reloads. #1521,u,g,n,n,m,u,PM_MRK_INST_FROM_L_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_INST_FROM_L_OC_ANY to obtain the average L_OC_ANY latency for instruction reloads. ##098100000002C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_INST_FROM_L_OC_ANY to obtain the average L_OC_ANY latency for instruction reloads. #1522,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L_OC_ANY to obtain the average L_OC_ANY latency for instruction page table reloads. ##098120000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L_OC_ANY to obtain the average L_OC_ANY latency for instruction page table reloads. #1523,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L_OC_ANY to obtain the average L_OC_ANY latency for data reloads. ##098140000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L_OC_ANY to obtain the average L_OC_ANY latency for data reloads. #1524,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L_OC_ANY to obtain the average L_OC_ANY latency for data page table reloads. ##098160000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L_OC_ANY to obtain the average L_OC_ANY latency for data page table reloads. #1525,u,g,n,n,m,u,PM_MRK_INST_FROM_L_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L_OC_ANY_ALL to obtain the average L_OC_ANY_ALL latency for instruction reloads. ##098100000012C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L_OC_ANY_ALL to obtain the average L_OC_ANY_ALL latency for instruction reloads. #1526,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L_OC_ANY_ALL to obtain the average L_OC_ANY_ALL latency for instruction page table reloads. ##098120000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L_OC_ANY_ALL to obtain the average L_OC_ANY_ALL latency for instruction page table reloads. #1527,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L_OC_ANY_ALL to obtain the average L_OC_ANY_ALL latency for data reloads. ##098140000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L_OC_ANY_ALL to obtain the average L_OC_ANY_ALL latency for data reloads. #1528,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L_OC_ANY_ALL to obtain the average L_OC_ANY_ALL latency for data page table reloads. ##098160000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L_OC_ANY_ALL to obtain the average L_OC_ANY_ALL latency for data page table reloads. #1529,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2_SHR to obtain the average RL2_SHR latency for instruction page table reloads. ##0C0020000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2_SHR to obtain the average RL2_SHR latency for instruction page table reloads. #1530,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2_SHR to obtain the average RL2_SHR latency for data reloads. ##0C0040000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2_SHR to obtain the average RL2_SHR latency for data reloads. #1531,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2_SHR to obtain the average RL2_SHR latency for data page table reloads. ##0C0060000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2_SHR to obtain the average RL2_SHR latency for data page table reloads. #1532,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2_SHR_ALL to obtain the average RL2_SHR_ALL latency for instruction page table reloads. ##0C0020000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2_SHR_ALL to obtain the average RL2_SHR_ALL latency for instruction page table reloads. #1533,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2_SHR_ALL to obtain the average RL2_SHR_ALL latency for data reloads. ##0C0040000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2_SHR_ALL to obtain the average RL2_SHR_ALL latency for data reloads. #1534,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2_SHR_ALL to obtain the average RL2_SHR_ALL latency for data page table reloads. ##0C0060000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2_SHR_ALL to obtain the average RL2_SHR_ALL latency for data page table reloads. #1535,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2_MOD to obtain the average RL2_MOD latency for instruction page table reloads. ##0C4020000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2_MOD to obtain the average RL2_MOD latency for instruction page table reloads. #1536,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2_MOD to obtain the average RL2_MOD latency for data reloads. ##0C4040000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2_MOD to obtain the average RL2_MOD latency for data reloads. #1537,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2_MOD to obtain the average RL2_MOD latency for data page table reloads. ##0C4060000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2_MOD to obtain the average RL2_MOD latency for data page table reloads. #1538,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2_MOD_ALL to obtain the average RL2_MOD_ALL latency for instruction page table reloads. ##0C4020000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2_MOD_ALL to obtain the average RL2_MOD_ALL latency for instruction page table reloads. #1539,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2_MOD_ALL to obtain the average RL2_MOD_ALL latency for data reloads. ##0C4040000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2_MOD_ALL to obtain the average RL2_MOD_ALL latency for data reloads. #1540,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2_MOD_ALL to obtain the average RL2_MOD_ALL latency for data page table reloads. ##0C4060000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2_MOD_ALL to obtain the average RL2_MOD_ALL latency for data page table reloads. #1541,u,g,n,n,m,u,PM_MRK_INST_FROM_RL2_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_RL2 to obtain the average RL2 latency for instruction reloads. ##0C0100000002C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_RL2 to obtain the average RL2 latency for instruction reloads. #1542,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2 to obtain the average RL2 latency for instruction page table reloads. ##0C0120000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2 to obtain the average RL2 latency for instruction page table reloads. #1543,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2 to obtain the average RL2 latency for data reloads. ##0C0140000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2 to obtain the average RL2 latency for data reloads. #1544,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2 to obtain the average RL2 latency for data page table reloads. ##0C0160000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2 to obtain the average RL2 latency for data page table reloads. #1545,u,g,n,n,m,u,PM_MRK_INST_FROM_RL2_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_RL2_ALL to obtain the average RL2_ALL latency for instruction reloads. ##0C0100000012C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_RL2_ALL to obtain the average RL2_ALL latency for instruction reloads. #1546,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2_ALL to obtain the average RL2_ALL latency for instruction page table reloads. ##0C0120000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2_ALL to obtain the average RL2_ALL latency for instruction page table reloads. #1547,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2_ALL to obtain the average RL2_ALL latency for data reloads. ##0C0140000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2_ALL to obtain the average RL2_ALL latency for data reloads. #1548,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2_ALL to obtain the average RL2_ALL latency for data page table reloads. ##0C0160000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2_ALL to obtain the average RL2_ALL latency for data page table reloads. #1549,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL3_SHR to obtain the average RL3_SHR latency for instruction page table reloads. ##0C8020000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL3_SHR to obtain the average RL3_SHR latency for instruction page table reloads. #1550,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL3_SHR to obtain the average RL3_SHR latency for data reloads. ##0C8040000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL3_SHR to obtain the average RL3_SHR latency for data reloads. #1551,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL3_SHR to obtain the average RL3_SHR latency for data page table reloads. ##0C8060000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL3_SHR to obtain the average RL3_SHR latency for data page table reloads. #1552,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL3_SHR_ALL to obtain the average RL3_SHR_ALL latency for instruction page table reloads. ##0C8020000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL3_SHR_ALL to obtain the average RL3_SHR_ALL latency for instruction page table reloads. #1553,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL3_SHR_ALL to obtain the average RL3_SHR_ALL latency for data reloads. ##0C8040000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL3_SHR_ALL to obtain the average RL3_SHR_ALL latency for data reloads. #1554,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL3_SHR_ALL to obtain the average RL3_SHR_ALL latency for data page table reloads. ##0C8060000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL3_SHR_ALL to obtain the average RL3_SHR_ALL latency for data page table reloads. #1555,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL3_MOD to obtain the average RL3_MOD latency for instruction page table reloads. ##0CC020000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL3_MOD to obtain the average RL3_MOD latency for instruction page table reloads. #1556,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL3_MOD to obtain the average RL3_MOD latency for data reloads. ##0CC040000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL3_MOD to obtain the average RL3_MOD latency for data reloads. #1557,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL3_MOD to obtain the average RL3_MOD latency for data page table reloads. ##0CC060000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL3_MOD to obtain the average RL3_MOD latency for data page table reloads. #1558,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL3_MOD_ALL to obtain the average RL3_MOD_ALL latency for instruction page table reloads. ##0CC020000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL3_MOD_ALL to obtain the average RL3_MOD_ALL latency for instruction page table reloads. #1559,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL3_MOD_ALL to obtain the average RL3_MOD_ALL latency for data reloads. ##0CC040000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL3_MOD_ALL to obtain the average RL3_MOD_ALL latency for data reloads. #1560,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL3_MOD_ALL to obtain the average RL3_MOD_ALL latency for data page table reloads. ##0CC060000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL3_MOD_ALL to obtain the average RL3_MOD_ALL latency for data page table reloads. #1561,u,g,n,n,m,u,PM_MRK_INST_FROM_RL3_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_RL3 to obtain the average RL3 latency for instruction reloads. ##0C8100000002C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_RL3 to obtain the average RL3 latency for instruction reloads. #1562,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL3 to obtain the average RL3 latency for instruction page table reloads. ##0C8120000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL3 to obtain the average RL3 latency for instruction page table reloads. #1563,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL3 to obtain the average RL3 latency for data reloads. ##0C8140000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL3 to obtain the average RL3 latency for data reloads. #1564,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL3 to obtain the average RL3 latency for data page table reloads. ##0C8160000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL3 to obtain the average RL3 latency for data page table reloads. #1565,u,g,n,n,m,u,PM_MRK_INST_FROM_RL3_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_RL3_ALL to obtain the average RL3_ALL latency for instruction reloads. ##0C8100000012C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_RL3_ALL to obtain the average RL3_ALL latency for instruction reloads. #1566,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL3_ALL to obtain the average RL3_ALL latency for instruction page table reloads. ##0C8120000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL3_ALL to obtain the average RL3_ALL latency for instruction page table reloads. #1567,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL3_ALL to obtain the average RL3_ALL latency for data reloads. ##0C8140000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL3_ALL to obtain the average RL3_ALL latency for data reloads. #1568,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL3_ALL to obtain the average RL3_ALL latency for data page table reloads. ##0C8160000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL3_ALL to obtain the average RL3_ALL latency for data page table reloads. #1569,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2L3_SHR to obtain the average RL2L3_SHR latency for instruction page table reloads. ##0C0220000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2L3_SHR to obtain the average RL2L3_SHR latency for instruction page table reloads. #1570,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2L3_SHR to obtain the average RL2L3_SHR latency for data reloads. ##0C0240000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2L3_SHR to obtain the average RL2L3_SHR latency for data reloads. #1571,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2L3_SHR to obtain the average RL2L3_SHR latency for data page table reloads. ##0C0260000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2L3_SHR to obtain the average RL2L3_SHR latency for data page table reloads. #1572,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2L3_SHR_ALL to obtain the average RL2L3_SHR_ALL latency for instruction page table reloads. ##0C0220000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2L3_SHR_ALL to obtain the average RL2L3_SHR_ALL latency for instruction page table reloads. #1573,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2L3_SHR_ALL to obtain the average RL2L3_SHR_ALL latency for data reloads. ##0C0240000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2L3_SHR_ALL to obtain the average RL2L3_SHR_ALL latency for data reloads. #1574,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2L3_SHR_ALL to obtain the average RL2L3_SHR_ALL latency for data page table reloads. ##0C0260000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2L3_SHR_ALL to obtain the average RL2L3_SHR_ALL latency for data page table reloads. #1575,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2L3_MOD to obtain the average RL2L3_MOD latency for instruction page table reloads. ##0C4220000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2L3_MOD to obtain the average RL2L3_MOD latency for instruction page table reloads. #1576,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2L3_MOD to obtain the average RL2L3_MOD latency for data reloads. ##0C4240000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2L3_MOD to obtain the average RL2L3_MOD latency for data reloads. #1577,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2L3_MOD to obtain the average RL2L3_MOD latency for data page table reloads. ##0C4260000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2L3_MOD to obtain the average RL2L3_MOD latency for data page table reloads. #1578,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2L3_MOD_ALL to obtain the average RL2L3_MOD_ALL latency for instruction page table reloads. ##0C4220000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2L3_MOD_ALL to obtain the average RL2L3_MOD_ALL latency for instruction page table reloads. #1579,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2L3_MOD_ALL to obtain the average RL2L3_MOD_ALL latency for data reloads. ##0C4240000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2L3_MOD_ALL to obtain the average RL2L3_MOD_ALL latency for data reloads. #1580,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2L3_MOD_ALL to obtain the average RL2L3_MOD_ALL latency for data page table reloads. ##0C4260000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2L3_MOD_ALL to obtain the average RL2L3_MOD_ALL latency for data page table reloads. #1581,u,g,n,n,m,u,PM_MRK_INST_FROM_RL2L3_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_RL2L3 to obtain the average RL2L3 latency for instruction reloads. ##0C0300000002C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_RL2L3 to obtain the average RL2L3 latency for instruction reloads. #1582,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2L3 to obtain the average RL2L3 latency for instruction page table reloads. ##0C0320000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2L3 to obtain the average RL2L3 latency for instruction page table reloads. #1583,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2L3 to obtain the average RL2L3 latency for data reloads. ##0C0340000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2L3 to obtain the average RL2L3 latency for data reloads. #1584,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2L3 to obtain the average RL2L3 latency for data page table reloads. ##0C0360000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2L3 to obtain the average RL2L3 latency for data page table reloads. #1585,u,g,n,n,m,u,PM_MRK_INST_FROM_RL2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_RL2L3_ALL to obtain the average RL2L3_ALL latency for instruction reloads. ##0C0300000012C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_RL2L3_ALL to obtain the average RL2L3_ALL latency for instruction reloads. #1586,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2L3_ALL to obtain the average RL2L3_ALL latency for instruction page table reloads. ##0C0320000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2L3_ALL to obtain the average RL2L3_ALL latency for instruction page table reloads. #1587,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2L3_ALL to obtain the average RL2L3_ALL latency for data reloads. ##0C0340000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2L3_ALL to obtain the average RL2L3_ALL latency for data reloads. #1588,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2L3_ALL to obtain the average RL2L3_ALL latency for data page table reloads. ##0C0360000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2L3_ALL to obtain the average RL2L3_ALL latency for data page table reloads. #1589,u,g,n,n,m,u,PM_MRK_INST_FROM_RMEM_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from remote memory (MC slow) due to a demand miss. Divide this count by PM_MRK_INST_FROM_RMEM to obtain the average RMEM latency for instruction reloads. ##0D4100000002C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from remote memory (MC slow) due to a demand miss. Divide this count by PM_MRK_INST_FROM_RMEM to obtain the average RMEM latency for instruction reloads. #1590,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RMEM_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from remote memory (MC slow) due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RMEM to obtain the average RMEM latency for instruction page table reloads. ##0D4020000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from remote memory (MC slow) due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RMEM to obtain the average RMEM latency for instruction page table reloads. #1591,u,g,n,n,m,u,PM_MRK_DATA_FROM_RMEM_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from remote memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RMEM to obtain the average RMEM latency for data reloads. ##0D4040000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from remote memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RMEM to obtain the average RMEM latency for data reloads. #1592,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RMEM_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from remote memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RMEM to obtain the average RMEM latency for data page table reloads. ##0D4060000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from remote memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RMEM to obtain the average RMEM latency for data page table reloads. #1593,u,g,n,n,m,u,PM_MRK_INST_FROM_RMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_RMEM_ALL to obtain the average RMEM_ALL latency for instruction reloads. ##0D4100000012C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_RMEM_ALL to obtain the average RMEM_ALL latency for instruction reloads. #1594,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RMEM_ALL to obtain the average RMEM_ALL latency for instruction page table reloads. ##0D4020000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RMEM_ALL to obtain the average RMEM_ALL latency for instruction page table reloads. #1595,u,g,n,n,m,u,PM_MRK_DATA_FROM_RMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RMEM_ALL to obtain the average RMEM_ALL latency for data reloads. ##0D4040000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RMEM_ALL to obtain the average RMEM_ALL latency for data reloads. #1596,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RMEM_ALL to obtain the average RMEM_ALL latency for data page table reloads. ##0D4060000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RMEM_ALL to obtain the average RMEM_ALL latency for data page table reloads. #1597,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_CACHE_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_R_OC_CACHE to obtain the average R_OC_CACHE latency for instruction page table reloads. ##0D8020000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_R_OC_CACHE to obtain the average R_OC_CACHE latency for instruction page table reloads. #1598,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_CACHE_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DATA_FROM_R_OC_CACHE to obtain the average R_OC_CACHE latency for data reloads. ##0D8040000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DATA_FROM_R_OC_CACHE to obtain the average R_OC_CACHE latency for data reloads. #1599,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_CACHE_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_R_OC_CACHE to obtain the average R_OC_CACHE latency for data page table reloads. ##0D8060000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_R_OC_CACHE to obtain the average R_OC_CACHE latency for data page table reloads. #1600,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_R_OC_CACHE_ALL to obtain the average R_OC_CACHE_ALL latency for instruction page table reloads. ##0D8020000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_R_OC_CACHE_ALL to obtain the average R_OC_CACHE_ALL latency for instruction page table reloads. #1601,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_R_OC_CACHE_ALL to obtain the average R_OC_CACHE_ALL latency for data reloads. ##0D8040000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_R_OC_CACHE_ALL to obtain the average R_OC_CACHE_ALL latency for data reloads. #1602,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_R_OC_CACHE_ALL to obtain the average R_OC_CACHE_ALL latency for data page table reloads. ##0D8060000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_R_OC_CACHE_ALL to obtain the average R_OC_CACHE_ALL latency for data page table reloads. #1603,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_MEM_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_R_OC_MEM to obtain the average R_OC_MEM latency for instruction page table reloads. ##0DC020000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_R_OC_MEM to obtain the average R_OC_MEM latency for instruction page table reloads. #1604,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_MEM_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_R_OC_MEM to obtain the average R_OC_MEM latency for data reloads. ##0DC040000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_R_OC_MEM to obtain the average R_OC_MEM latency for data reloads. #1605,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_MEM_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_R_OC_MEM to obtain the average R_OC_MEM latency for data page table reloads. ##0DC060000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_R_OC_MEM to obtain the average R_OC_MEM latency for data page table reloads. #1606,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_MEM_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_R_OC_MEM_ALL to obtain the average R_OC_MEM_ALL latency for instruction page table reloads. ##0DC020000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_R_OC_MEM_ALL to obtain the average R_OC_MEM_ALL latency for instruction page table reloads. #1607,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_MEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_R_OC_MEM_ALL to obtain the average R_OC_MEM_ALL latency for data reloads. ##0DC040000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_R_OC_MEM_ALL to obtain the average R_OC_MEM_ALL latency for data reloads. #1608,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_MEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_R_OC_MEM_ALL to obtain the average R_OC_MEM_ALL latency for data page table reloads. ##0DC060000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_R_OC_MEM_ALL to obtain the average R_OC_MEM_ALL latency for data page table reloads. #1609,u,g,n,n,m,u,PM_MRK_INST_FROM_R_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_INST_FROM_R_OC_ANY to obtain the average R_OC_ANY latency for instruction reloads. ##0D8100000002C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_INST_FROM_R_OC_ANY to obtain the average R_OC_ANY latency for instruction reloads. #1610,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_R_OC_ANY to obtain the average R_OC_ANY latency for instruction page table reloads. ##0D8120000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_R_OC_ANY to obtain the average R_OC_ANY latency for instruction page table reloads. #1611,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_R_OC_ANY to obtain the average R_OC_ANY latency for data reloads. ##0D8140000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_R_OC_ANY to obtain the average R_OC_ANY latency for data reloads. #1612,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_R_OC_ANY to obtain the average R_OC_ANY latency for data page table reloads. ##0D8160000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_R_OC_ANY to obtain the average R_OC_ANY latency for data page table reloads. #1613,u,g,n,n,m,u,PM_MRK_INST_FROM_R_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_R_OC_ANY_ALL to obtain the average R_OC_ANY_ALL latency for instruction reloads. ##0D8100000012C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_R_OC_ANY_ALL to obtain the average R_OC_ANY_ALL latency for instruction reloads. #1614,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_R_OC_ANY_ALL to obtain the average R_OC_ANY_ALL latency for instruction page table reloads. ##0D8120000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_R_OC_ANY_ALL to obtain the average R_OC_ANY_ALL latency for instruction page table reloads. #1615,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_R_OC_ANY_ALL to obtain the average R_OC_ANY_ALL latency for data reloads. ##0D8140000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_R_OC_ANY_ALL to obtain the average R_OC_ANY_ALL latency for data reloads. #1616,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_R_OC_ANY_ALL to obtain the average R_OC_ANY_ALL latency for data page table reloads. ##0D8160000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_R_OC_ANY_ALL to obtain the average R_OC_ANY_ALL latency for data page table reloads. #1617,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2_SHR to obtain the average DL2_SHR latency for instruction page table reloads. ##0E0020000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2_SHR to obtain the average DL2_SHR latency for instruction page table reloads. #1618,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2_SHR to obtain the average DL2_SHR latency for data reloads. ##0E0040000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2_SHR to obtain the average DL2_SHR latency for data reloads. #1619,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2_SHR to obtain the average DL2_SHR latency for data page table reloads. ##0E0060000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2_SHR to obtain the average DL2_SHR latency for data page table reloads. #1620,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2_SHR_ALL to obtain the average DL2_SHR_ALL latency for instruction page table reloads. ##0E0020000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2_SHR_ALL to obtain the average DL2_SHR_ALL latency for instruction page table reloads. #1621,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2_SHR_ALL to obtain the average DL2_SHR_ALL latency for data reloads. ##0E0040000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2_SHR_ALL to obtain the average DL2_SHR_ALL latency for data reloads. #1622,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2_SHR_ALL to obtain the average DL2_SHR_ALL latency for data page table reloads. ##0E0060000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2_SHR_ALL to obtain the average DL2_SHR_ALL latency for data page table reloads. #1623,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2_MOD to obtain the average DL2_MOD latency for instruction page table reloads. ##0E4020000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2_MOD to obtain the average DL2_MOD latency for instruction page table reloads. #1624,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2_MOD to obtain the average DL2_MOD latency for data reloads. ##0E4040000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2_MOD to obtain the average DL2_MOD latency for data reloads. #1625,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2_MOD to obtain the average DL2_MOD latency for data page table reloads. ##0E4060000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2_MOD to obtain the average DL2_MOD latency for data page table reloads. #1626,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2_MOD_ALL to obtain the average DL2_MOD_ALL latency for instruction page table reloads. ##0E4020000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2_MOD_ALL to obtain the average DL2_MOD_ALL latency for instruction page table reloads. #1627,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2_MOD_ALL to obtain the average DL2_MOD_ALL latency for data reloads. ##0E4040000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2_MOD_ALL to obtain the average DL2_MOD_ALL latency for data reloads. #1628,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2_MOD_ALL to obtain the average DL2_MOD_ALL latency for data page table reloads. ##0E4060000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2_MOD_ALL to obtain the average DL2_MOD_ALL latency for data page table reloads. #1629,u,g,n,n,m,u,PM_MRK_INST_FROM_DL2_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_DL2 to obtain the average DL2 latency for instruction reloads. ##0E0100000002C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_DL2 to obtain the average DL2 latency for instruction reloads. #1630,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2 to obtain the average DL2 latency for instruction page table reloads. ##0E0120000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2 to obtain the average DL2 latency for instruction page table reloads. #1631,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2 to obtain the average DL2 latency for data reloads. ##0E0140000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2 to obtain the average DL2 latency for data reloads. #1632,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2 to obtain the average DL2 latency for data page table reloads. ##0E0160000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2 to obtain the average DL2 latency for data page table reloads. #1633,u,g,n,n,m,u,PM_MRK_INST_FROM_DL2_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_DL2_ALL to obtain the average DL2_ALL latency for instruction reloads. ##0E0100000012C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_DL2_ALL to obtain the average DL2_ALL latency for instruction reloads. #1634,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2_ALL to obtain the average DL2_ALL latency for instruction page table reloads. ##0E0120000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2_ALL to obtain the average DL2_ALL latency for instruction page table reloads. #1635,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2_ALL to obtain the average DL2_ALL latency for data reloads. ##0E0140000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2_ALL to obtain the average DL2_ALL latency for data reloads. #1636,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2_ALL to obtain the average DL2_ALL latency for data page table reloads. ##0E0160000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2_ALL to obtain the average DL2_ALL latency for data page table reloads. #1637,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL3_SHR to obtain the average DL3_SHR latency for instruction page table reloads. ##0E8020000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL3_SHR to obtain the average DL3_SHR latency for instruction page table reloads. #1638,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL3_SHR to obtain the average DL3_SHR latency for data reloads. ##0E8040000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL3_SHR to obtain the average DL3_SHR latency for data reloads. #1639,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL3_SHR to obtain the average DL3_SHR latency for data page table reloads. ##0E8060000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL3_SHR to obtain the average DL3_SHR latency for data page table reloads. #1640,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL3_SHR_ALL to obtain the average DL3_SHR_ALL latency for instruction page table reloads. ##0E8020000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL3_SHR_ALL to obtain the average DL3_SHR_ALL latency for instruction page table reloads. #1641,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL3_SHR_ALL to obtain the average DL3_SHR_ALL latency for data reloads. ##0E8040000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL3_SHR_ALL to obtain the average DL3_SHR_ALL latency for data reloads. #1642,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL3_SHR_ALL to obtain the average DL3_SHR_ALL latency for data page table reloads. ##0E8060000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL3_SHR_ALL to obtain the average DL3_SHR_ALL latency for data page table reloads. #1643,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL3_MOD to obtain the average DL3_MOD latency for instruction page table reloads. ##0EC020000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL3_MOD to obtain the average DL3_MOD latency for instruction page table reloads. #1644,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL3_MOD to obtain the average DL3_MOD latency for data reloads. ##0EC040000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL3_MOD to obtain the average DL3_MOD latency for data reloads. #1645,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL3_MOD to obtain the average DL3_MOD latency for data page table reloads. ##0EC060000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL3_MOD to obtain the average DL3_MOD latency for data page table reloads. #1646,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL3_MOD_ALL to obtain the average DL3_MOD_ALL latency for instruction page table reloads. ##0EC020000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL3_MOD_ALL to obtain the average DL3_MOD_ALL latency for instruction page table reloads. #1647,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL3_MOD_ALL to obtain the average DL3_MOD_ALL latency for data reloads. ##0EC040000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL3_MOD_ALL to obtain the average DL3_MOD_ALL latency for data reloads. #1648,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL3_MOD_ALL to obtain the average DL3_MOD_ALL latency for data page table reloads. ##0EC060000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL3_MOD_ALL to obtain the average DL3_MOD_ALL latency for data page table reloads. #1649,u,g,n,n,m,u,PM_MRK_INST_FROM_DL3_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_DL3 to obtain the average DL3 latency for instruction reloads. ##0E8100000002C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_DL3 to obtain the average DL3 latency for instruction reloads. #1650,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL3 to obtain the average DL3 latency for instruction page table reloads. ##0E8120000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL3 to obtain the average DL3 latency for instruction page table reloads. #1651,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL3 to obtain the average DL3 latency for data reloads. ##0E8140000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL3 to obtain the average DL3 latency for data reloads. #1652,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL3 to obtain the average DL3 latency for data page table reloads. ##0E8160000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL3 to obtain the average DL3 latency for data page table reloads. #1653,u,g,n,n,m,u,PM_MRK_INST_FROM_DL3_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_DL3_ALL to obtain the average DL3_ALL latency for instruction reloads. ##0E8100000012C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_DL3_ALL to obtain the average DL3_ALL latency for instruction reloads. #1654,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL3_ALL to obtain the average DL3_ALL latency for instruction page table reloads. ##0E8120000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL3_ALL to obtain the average DL3_ALL latency for instruction page table reloads. #1655,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL3_ALL to obtain the average DL3_ALL latency for data reloads. ##0E8140000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL3_ALL to obtain the average DL3_ALL latency for data reloads. #1656,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL3_ALL to obtain the average DL3_ALL latency for data page table reloads. ##0E8160000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL3_ALL to obtain the average DL3_ALL latency for data page table reloads. #1657,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2L3_SHR to obtain the average DL2L3_SHR latency for instruction page table reloads. ##0E0220000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2L3_SHR to obtain the average DL2L3_SHR latency for instruction page table reloads. #1658,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2L3_SHR to obtain the average DL2L3_SHR latency for data reloads. ##0E0240000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2L3_SHR to obtain the average DL2L3_SHR latency for data reloads. #1659,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2L3_SHR to obtain the average DL2L3_SHR latency for data page table reloads. ##0E0260000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2L3_SHR to obtain the average DL2L3_SHR latency for data page table reloads. #1660,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2L3_SHR_ALL to obtain the average DL2L3_SHR_ALL latency for instruction page table reloads. ##0E0220000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2L3_SHR_ALL to obtain the average DL2L3_SHR_ALL latency for instruction page table reloads. #1661,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2L3_SHR_ALL to obtain the average DL2L3_SHR_ALL latency for data reloads. ##0E0240000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2L3_SHR_ALL to obtain the average DL2L3_SHR_ALL latency for data reloads. #1662,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2L3_SHR_ALL to obtain the average DL2L3_SHR_ALL latency for data page table reloads. ##0E0260000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2L3_SHR_ALL to obtain the average DL2L3_SHR_ALL latency for data page table reloads. #1663,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2L3_MOD to obtain the average DL2L3_MOD latency for instruction page table reloads. ##0E4220000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2L3_MOD to obtain the average DL2L3_MOD latency for instruction page table reloads. #1664,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2L3_MOD to obtain the average DL2L3_MOD latency for data reloads. ##0E4240000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2L3_MOD to obtain the average DL2L3_MOD latency for data reloads. #1665,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2L3_MOD to obtain the average DL2L3_MOD latency for data page table reloads. ##0E4260000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2L3_MOD to obtain the average DL2L3_MOD latency for data page table reloads. #1666,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2L3_MOD_ALL to obtain the average DL2L3_MOD_ALL latency for instruction page table reloads. ##0E4220000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2L3_MOD_ALL to obtain the average DL2L3_MOD_ALL latency for instruction page table reloads. #1667,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2L3_MOD_ALL to obtain the average DL2L3_MOD_ALL latency for data reloads. ##0E4240000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2L3_MOD_ALL to obtain the average DL2L3_MOD_ALL latency for data reloads. #1668,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2L3_MOD_ALL to obtain the average DL2L3_MOD_ALL latency for data page table reloads. ##0E4260000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2L3_MOD_ALL to obtain the average DL2L3_MOD_ALL latency for data page table reloads. #1669,u,g,n,n,m,u,PM_MRK_INST_FROM_DL2L3_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_DL2L3 to obtain the average DL2L3 latency for instruction reloads. ##0E0300000002C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_DL2L3 to obtain the average DL2L3 latency for instruction reloads. #1670,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2L3 to obtain the average DL2L3 latency for instruction page table reloads. ##0E0320000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2L3 to obtain the average DL2L3 latency for instruction page table reloads. #1671,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2L3 to obtain the average DL2L3 latency for data reloads. ##0E0340000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2L3 to obtain the average DL2L3 latency for data reloads. #1672,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2L3 to obtain the average DL2L3 latency for data page table reloads. ##0E0360000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2L3 to obtain the average DL2L3 latency for data page table reloads. #1673,u,g,n,n,m,u,PM_MRK_INST_FROM_DL2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_DL2L3_ALL to obtain the average DL2L3_ALL latency for instruction reloads. ##0E0300000012C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_DL2L3_ALL to obtain the average DL2L3_ALL latency for instruction reloads. #1674,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2L3_ALL to obtain the average DL2L3_ALL latency for instruction page table reloads. ##0E0320000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2L3_ALL to obtain the average DL2L3_ALL latency for instruction page table reloads. #1675,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2L3_ALL to obtain the average DL2L3_ALL latency for data reloads. ##0E0340000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2L3_ALL to obtain the average DL2L3_ALL latency for data reloads. #1676,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2L3_ALL to obtain the average DL2L3_ALL latency for data page table reloads. ##0E0360000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2L3_ALL to obtain the average DL2L3_ALL latency for data page table reloads. #1677,u,g,n,n,m,u,PM_MRK_INST_FROM_DMEM_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from distant memory (MC slow) due to a demand miss. Divide this count by PM_MRK_INST_FROM_DMEM to obtain the average DMEM latency for instruction reloads. ##0F4100000002C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from distant memory (MC slow) due to a demand miss. Divide this count by PM_MRK_INST_FROM_DMEM to obtain the average DMEM latency for instruction reloads. #1678,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DMEM_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from distant memory (MC slow) due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DMEM to obtain the average DMEM latency for instruction page table reloads. ##0F4020000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from distant memory (MC slow) due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DMEM to obtain the average DMEM latency for instruction page table reloads. #1679,u,g,n,n,m,u,PM_MRK_DATA_FROM_DMEM_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from distant memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DMEM to obtain the average DMEM latency for data reloads. ##0F4040000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from distant memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DMEM to obtain the average DMEM latency for data reloads. #1680,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DMEM_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from distant memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DMEM to obtain the average DMEM latency for data page table reloads. ##0F4060000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from distant memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DMEM to obtain the average DMEM latency for data page table reloads. #1681,u,g,n,n,m,u,PM_MRK_INST_FROM_DMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_DMEM_ALL to obtain the average DMEM_ALL latency for instruction reloads. ##0F4100000012C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_DMEM_ALL to obtain the average DMEM_ALL latency for instruction reloads. #1682,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DMEM_ALL to obtain the average DMEM_ALL latency for instruction page table reloads. ##0F4020000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DMEM_ALL to obtain the average DMEM_ALL latency for instruction page table reloads. #1683,u,g,n,n,m,u,PM_MRK_DATA_FROM_DMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DMEM_ALL to obtain the average DMEM_ALL latency for data reloads. ##0F4040000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DMEM_ALL to obtain the average DMEM_ALL latency for data reloads. #1684,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DMEM_ALL to obtain the average DMEM_ALL latency for data page table reloads. ##0F4060000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DMEM_ALL to obtain the average DMEM_ALL latency for data page table reloads. #1685,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_CACHE_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_D_OC_CACHE to obtain the average D_OC_CACHE latency for instruction page table reloads. ##0F8020000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_D_OC_CACHE to obtain the average D_OC_CACHE latency for instruction page table reloads. #1686,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_CACHE_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DATA_FROM_D_OC_CACHE to obtain the average D_OC_CACHE latency for data reloads. ##0F8040000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DATA_FROM_D_OC_CACHE to obtain the average D_OC_CACHE latency for data reloads. #1687,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_CACHE_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_D_OC_CACHE to obtain the average D_OC_CACHE latency for data page table reloads. ##0F8060000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_D_OC_CACHE to obtain the average D_OC_CACHE latency for data page table reloads. #1688,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_D_OC_CACHE_ALL to obtain the average D_OC_CACHE_ALL latency for instruction page table reloads. ##0F8020000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_D_OC_CACHE_ALL to obtain the average D_OC_CACHE_ALL latency for instruction page table reloads. #1689,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_D_OC_CACHE_ALL to obtain the average D_OC_CACHE_ALL latency for data reloads. ##0F8040000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_D_OC_CACHE_ALL to obtain the average D_OC_CACHE_ALL latency for data reloads. #1690,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_D_OC_CACHE_ALL to obtain the average D_OC_CACHE_ALL latency for data page table reloads. ##0F8060000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_D_OC_CACHE_ALL to obtain the average D_OC_CACHE_ALL latency for data page table reloads. #1691,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_MEM_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_D_OC_MEM to obtain the average D_OC_MEM latency for instruction page table reloads. ##0FC020000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_D_OC_MEM to obtain the average D_OC_MEM latency for instruction page table reloads. #1692,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_MEM_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_D_OC_MEM to obtain the average D_OC_MEM latency for data reloads. ##0FC040000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_D_OC_MEM to obtain the average D_OC_MEM latency for data reloads. #1693,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_MEM_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_D_OC_MEM to obtain the average D_OC_MEM latency for data page table reloads. ##0FC060000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_D_OC_MEM to obtain the average D_OC_MEM latency for data page table reloads. #1694,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_MEM_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_D_OC_MEM_ALL to obtain the average D_OC_MEM_ALL latency for instruction page table reloads. ##0FC020000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_D_OC_MEM_ALL to obtain the average D_OC_MEM_ALL latency for instruction page table reloads. #1695,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_MEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_D_OC_MEM_ALL to obtain the average D_OC_MEM_ALL latency for data reloads. ##0FC040000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_D_OC_MEM_ALL to obtain the average D_OC_MEM_ALL latency for data reloads. #1696,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_MEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_D_OC_MEM_ALL to obtain the average D_OC_MEM_ALL latency for data page table reloads. ##0FC060000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_D_OC_MEM_ALL to obtain the average D_OC_MEM_ALL latency for data page table reloads. #1697,u,g,n,n,m,u,PM_MRK_INST_FROM_D_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_INST_FROM_D_OC_ANY to obtain the average D_OC_ANY latency for instruction reloads. ##0F8100000002C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_INST_FROM_D_OC_ANY to obtain the average D_OC_ANY latency for instruction reloads. #1698,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_D_OC_ANY to obtain the average D_OC_ANY latency for instruction page table reloads. ##0F8120000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_D_OC_ANY to obtain the average D_OC_ANY latency for instruction page table reloads. #1699,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_D_OC_ANY to obtain the average D_OC_ANY latency for data reloads. ##0F8140000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_D_OC_ANY to obtain the average D_OC_ANY latency for data reloads. #1700,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_D_OC_ANY to obtain the average D_OC_ANY latency for data page table reloads. ##0F8160000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_D_OC_ANY to obtain the average D_OC_ANY latency for data page table reloads. #1701,u,g,n,n,m,u,PM_MRK_INST_FROM_D_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_D_OC_ANY_ALL to obtain the average D_OC_ANY_ALL latency for instruction reloads. ##0F8100000012C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_D_OC_ANY_ALL to obtain the average D_OC_ANY_ALL latency for instruction reloads. #1702,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_D_OC_ANY_ALL to obtain the average D_OC_ANY_ALL latency for instruction page table reloads. ##0F8120000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_D_OC_ANY_ALL to obtain the average D_OC_ANY_ALL latency for instruction page table reloads. #1703,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_D_OC_ANY_ALL to obtain the average D_OC_ANY_ALL latency for data reloads. ##0F8140000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_D_OC_ANY_ALL to obtain the average D_OC_ANY_ALL latency for data reloads. #1704,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_D_OC_ANY_ALL to obtain the average D_OC_ANY_ALL latency for data page table reloads. ##0F8160000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_D_OC_ANY_ALL to obtain the average D_OC_ANY_ALL latency for data page table reloads. #1705,u,g,n,n,m,u,PM_MRK_INST_FROM_ONCHIP_CACHE_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_ONCHIP_CACHE to obtain the average ONCHIP_CACHE latency for instruction reloads. ##080B00000002C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_ONCHIP_CACHE to obtain the average ONCHIP_CACHE latency for instruction reloads. #1706,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_ONCHIP_CACHE_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_ONCHIP_CACHE to obtain the average ONCHIP_CACHE latency for instruction page table reloads. ##080B20000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_ONCHIP_CACHE to obtain the average ONCHIP_CACHE latency for instruction page table reloads. #1707,u,g,n,n,m,u,PM_MRK_DATA_FROM_ONCHIP_CACHE_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_ONCHIP_CACHE to obtain the average ONCHIP_CACHE latency for data reloads. ##080B40000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_ONCHIP_CACHE to obtain the average ONCHIP_CACHE latency for data reloads. #1708,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_ONCHIP_CACHE_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_ONCHIP_CACHE to obtain the average ONCHIP_CACHE latency for data page table reloads. ##080B60000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_ONCHIP_CACHE to obtain the average ONCHIP_CACHE latency for data page table reloads. #1709,u,g,n,n,m,u,PM_MRK_INST_FROM_ONCHIP_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_ONCHIP_CACHE_ALL to obtain the average ONCHIP_CACHE_ALL latency for instruction reloads. ##080B00000012C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_ONCHIP_CACHE_ALL to obtain the average ONCHIP_CACHE_ALL latency for instruction reloads. #1710,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_ONCHIP_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_ONCHIP_CACHE_ALL to obtain the average ONCHIP_CACHE_ALL latency for instruction page table reloads. ##080B20000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_ONCHIP_CACHE_ALL to obtain the average ONCHIP_CACHE_ALL latency for instruction page table reloads. #1711,u,g,n,n,m,u,PM_MRK_DATA_FROM_ONCHIP_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_ONCHIP_CACHE_ALL to obtain the average ONCHIP_CACHE_ALL latency for data reloads. ##080B40000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_ONCHIP_CACHE_ALL to obtain the average ONCHIP_CACHE_ALL latency for data reloads. #1712,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_ONCHIP_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_ONCHIP_CACHE_ALL to obtain the average ONCHIP_CACHE_ALL latency for data page table reloads. ##080B60000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_ONCHIP_CACHE_ALL to obtain the average ONCHIP_CACHE_ALL latency for data page table reloads. #1713,u,g,n,n,m,u,PM_MRK_INST_FROM_OFFCHIP_CACHE_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_OFFCHIP_CACHE to obtain the average OFFCHIP_CACHE latency for instruction reloads. ##0C0B00000002C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_OFFCHIP_CACHE to obtain the average OFFCHIP_CACHE latency for instruction reloads. #1714,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_OFFCHIP_CACHE_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_OFFCHIP_CACHE to obtain the average OFFCHIP_CACHE latency for instruction page table reloads. ##0C0B20000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_OFFCHIP_CACHE to obtain the average OFFCHIP_CACHE latency for instruction page table reloads. #1715,u,g,n,n,m,u,PM_MRK_DATA_FROM_OFFCHIP_CACHE_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_OFFCHIP_CACHE to obtain the average OFFCHIP_CACHE latency for data reloads. ##0C0B40000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_OFFCHIP_CACHE to obtain the average OFFCHIP_CACHE latency for data reloads. #1716,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_OFFCHIP_CACHE_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_OFFCHIP_CACHE to obtain the average OFFCHIP_CACHE latency for data page table reloads. ##0C0B60000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_OFFCHIP_CACHE to obtain the average OFFCHIP_CACHE latency for data page table reloads. #1717,u,g,n,n,m,u,PM_MRK_INST_FROM_OFFCHIP_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_OFFCHIP_CACHE_ALL to obtain the average OFFCHIP_CACHE_ALL latency for instruction reloads. ##0C0B00000012C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_OFFCHIP_CACHE_ALL to obtain the average OFFCHIP_CACHE_ALL latency for instruction reloads. #1718,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_OFFCHIP_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_OFFCHIP_CACHE_ALL to obtain the average OFFCHIP_CACHE_ALL latency for instruction page table reloads. ##0C0B20000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_OFFCHIP_CACHE_ALL to obtain the average OFFCHIP_CACHE_ALL latency for instruction page table reloads. #1719,u,g,n,n,m,u,PM_MRK_DATA_FROM_OFFCHIP_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_OFFCHIP_CACHE_ALL to obtain the average OFFCHIP_CACHE_ALL latency for data reloads. ##0C0B40000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_OFFCHIP_CACHE_ALL to obtain the average OFFCHIP_CACHE_ALL latency for data reloads. #1720,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_OFFCHIP_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_OFFCHIP_CACHE_ALL to obtain the average OFFCHIP_CACHE_ALL latency for data page table reloads. ##0C0B60000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_OFFCHIP_CACHE_ALL to obtain the average OFFCHIP_CACHE_ALL latency for data page table reloads. #1721,u,g,n,n,m,u,PM_MRK_INST_FROM_ANY_MEMORY_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from any chip's memory (MC slow) due to a demand miss. Divide this count by PM_MRK_INST_FROM_ANY_MEMORY to obtain the average ANY_MEMORY latency for instruction reloads. ##095900000002C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from any chip's memory (MC slow) due to a demand miss. Divide this count by PM_MRK_INST_FROM_ANY_MEMORY to obtain the average ANY_MEMORY latency for instruction reloads. #1722,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_ANY_MEMORY_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from any chip's memory (MC slow) due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_ANY_MEMORY to obtain the average ANY_MEMORY latency for instruction page table reloads. ##095820000002C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from any chip's memory (MC slow) due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_ANY_MEMORY to obtain the average ANY_MEMORY latency for instruction page table reloads. #1723,u,g,n,n,m,u,PM_MRK_DATA_FROM_ANY_MEMORY_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from any chip's memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DATA_FROM_ANY_MEMORY to obtain the average ANY_MEMORY latency for data reloads. ##095840000002C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from any chip's memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DATA_FROM_ANY_MEMORY to obtain the average ANY_MEMORY latency for data reloads. #1724,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_ANY_MEMORY_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from any chip's memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_ANY_MEMORY to obtain the average ANY_MEMORY latency for data page table reloads. ##095860000002C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from any chip's memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_ANY_MEMORY to obtain the average ANY_MEMORY latency for data page table reloads. #1725,u,g,n,n,m,u,PM_MRK_INST_FROM_ANY_MEMORY_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_ANY_MEMORY_ALL to obtain the average ANY_MEMORY_ALL latency for instruction reloads. ##095900000012C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_ANY_MEMORY_ALL to obtain the average ANY_MEMORY_ALL latency for instruction reloads. #1726,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_ANY_MEMORY_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_ANY_MEMORY_ALL to obtain the average ANY_MEMORY_ALL latency for instruction page table reloads. ##095820000012C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_ANY_MEMORY_ALL to obtain the average ANY_MEMORY_ALL latency for instruction page table reloads. #1727,u,g,n,n,m,u,PM_MRK_DATA_FROM_ANY_MEMORY_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_ANY_MEMORY_ALL to obtain the average ANY_MEMORY_ALL latency for data reloads. ##095840000022C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_ANY_MEMORY_ALL to obtain the average ANY_MEMORY_ALL latency for data reloads. #1728,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_ANY_MEMORY_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_ANY_MEMORY_ALL to obtain the average ANY_MEMORY_ALL latency for data page table reloads. ##095860000022C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_ANY_MEMORY_ALL to obtain the average ANY_MEMORY_ALL latency for data page table reloads. $$$$$$$$ { counter 3} #0,u,g,n,n,n,n,PM_SUSPENDED,Counter off ##30000 Counter off #1,u,g,n,n,n,n,PM_INST_CMPL,PowerPC instruction completed ##30002 PowerPC instruction completed #2,u,g,n,n,n,n,PM_CYC,Processor cycles ##3001E Processor cycles #3,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3MISS,The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction. ##0007C0000003C142 The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction. #4,u,g,n,n,n,y,PM_INST_DISP,PowerPC instruction dispatched ##300F2 PowerPC instruction dispatched #5,u,g,n,n,n,u,PM_DATA_FROM_L2MISS,The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss. ##0003C0000003C040 The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss. #6,u,g,n,n,n,y,PM_DISP_STALL_FLUSH,Cycles when dispatch was stalled because of a flush that happened to an instruction(s) that was not yet next-to-complete (NTC). PM_EXEC_STALL_NTC_FLUSH only includes instructions that were flushed after becoming NTC ##30004 Cycles when dispatch was stalled because of a flush that happened to an instruction(s) that was not yet next-to-complete (NTC). PM_EXEC_STALL_NTC_FLUSH only includes instructions that were flushed after becoming NTC #7,u,g,n,n,n,u,PM_MMA_ACTIVE_NAVAIL,MMA instructions are being held and not executed as the MMA is not powered up and available ##30006 MMA instructions are being held and not executed as the MMA is not powered up and available #8,u,g,n,n,n,y,PM_EXEC_STALL,Cycles in which the oldest instruction in the pipeline was waiting to finish in one of the execution units (BRU, LSU, VSU). Only cycles between issue and finish are counted in this category. ##30008 Cycles in which the oldest instruction in the pipeline was waiting to finish in one of the execution units (BRU, LSU, VSU). Only cycles between issue and finish are counted in this category. #9,u,g,n,n,n,y,PM_DISP_STALL_ITLB_MISS,Cycles when dispatch was stalled while waiting to resolve an instruction TLB miss. ##3000A Cycles when dispatch was stalled while waiting to resolve an instruction TLB miss. #10,u,g,n,n,n,n,PM_FREQ_DOWN,Power Management: Below Threshold B ##3000C Power Management: Below Threshold B #11,u,g,n,n,n,y,PM_ST_REJECT_TIQ,TIQ reject for stores ##3000E TIQ reject for stores #12,u,g,n,n,n,n,PM_PMC2_OVERFLOW,The event selected for PMC2 caused the event counter to overflow. ##30010 The event selected for PMC2 caused the event counter to overflow. #13,u,g,n,n,n,y,PM_FLUSH_COMPLETION,The instruction that was next to complete (oldest in the pipeline) did not complete because it suffered a flush ##30012 The instruction that was next to complete (oldest in the pipeline) did not complete because it suffered a flush #14,u,g,n,n,n,y,PM_EXEC_STALL_STORE,Cycles in which the oldest instruction in the pipeline was a store instruction executing in the Load Store Unit. ##30014 Cycles in which the oldest instruction in the pipeline was a store instruction executing in the Load Store Unit. #15,u,g,n,n,n,y,PM_EXEC_STALL_DERAT_DTLB_MISS,Cycles in which the oldest instruction in the pipeline suffered a TLB miss and waited for it resolve. ##30016 Cycles in which the oldest instruction in the pipeline suffered a TLB miss and waited for it resolve. #16,u,g,n,n,n,y,PM_DISP_STALL_HELD_SCOREBOARD_CYC,Cycles in which the next-to-complete (NTC) instruction is held at dispatch while waiting on the Scoreboard. This event combines VSCR and FPSCR together ##30018 Cycles in which the next-to-complete (NTC) instruction is held at dispatch while waiting on the Scoreboard. This event combines VSCR and FPSCR together #17,u,g,n,n,n,y,PM_LSU_ST2_FIN,LSU Finished an internal operation in ST2 port ##3001A LSU Finished an internal operation in ST2 port #18,u,g,n,n,n,y,PM_PMC2_REWIND,The speculative event selected for PMC2 rewinds and the counter for PMC2 is not charged. ##30020 The speculative event selected for PMC2 rewinds and the counter for PMC2 is not charged. #19,u,g,n,n,n,y,PM_PMC4_SAVED,The conditions for the speculative event selected for PMC4 are met and PMC4 is charged. ##30022 The conditions for the speculative event selected for PMC4 are met and PMC4 is charged. #20,u,g,n,n,n,n,PM_PMC6_OVERFLOW,The event selected for PMC6 caused the event counter to overflow. ##30024 The event selected for PMC6 caused the event counter to overflow. #21,u,g,n,n,n,y,PM_EXEC_STALL_STORE_MISS,Cycles in which the oldest instruction in the pipeline was a store whose cache line was not resident in the L1 and was waiting for allocation of the missing line into the L1. ##30026 Cycles in which the oldest instruction in the pipeline was a store whose cache line was not resident in the L1 and was waiting for allocation of the missing line into the L1. #22,u,g,n,n,n,n,PM_CMPL_STALL_MEM_ECC,Cycles in which the oldest instruction in the pipeline was waiting for the non-speculative finish of either a STCX waiting for its result or a load waiting for non-critical sectors of data and ECC. ##30028 Cycles in which the oldest instruction in the pipeline was waiting for the non-speculative finish of either a STCX waiting for its result or a load waiting for non-critical sectors of data and ECC. #23,u,g,n,n,m,n,PM_MRK_L2_RC_DONE,L2 RC machine completed the transaction for the marked instruction ##3012A L2 RC machine completed the transaction for the marked instruction #24,u,g,n,n,m,y,PM_MRK_ST_FWD,Marked store forward ##3012C Marked store forward #25,u,g,n,n,m,y,PM_MRK_DTLB_MISS_2M,Marked Data TLB reload (after a miss) page size 2M, which implies Radix Page Table translation was used. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches ##3012E Marked Data TLB reload (after a miss) page size 2M, which implies Radix Page Table translation was used. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches #26,u,g,n,n,m,y,PM_MRK_INST_FIN,Marked instruction finished. Excludes instructions that finish at dispatch. Note that stores always finish twice since the address gets issued to the LSU and the data gets issued to the VSU. ##30130 Marked instruction finished. Excludes instructions that finish at dispatch. Note that stores always finish twice since the address gets issued to the LSU and the data gets issued to the VSU. #27,u,g,n,n,m,y,PM_MRK_VSU_FIN,VSU marked instruction finished. Excludes simple FX instructions issued to the Store Unit. ##30132 VSU marked instruction finished. Excludes simple FX instructions issued to the Store Unit. #28,u,g,n,n,m,n,PM_MRK_ST_CMPL_INT,Marked store finished with intervention ##30134 Marked store finished with intervention #29,u,g,n,n,n,y,PM_EXEC_STALL_SIMPLE_FX,Cycles in which the oldest instruction in the pipeline was a simple fixed point instruction executing in the Load Store Unit. ##30036 Cycles in which the oldest instruction in the pipeline was a simple fixed point instruction executing in the Load Store Unit. #30,u,g,n,n,n,y,PM_EXEC_STALL_DMISS_LMEM,Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from the local memory, local OpenCapp cache, or local OpenCapp memory. ##30038 Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from the local memory, local OpenCapp cache, or local OpenCapp memory. #31,u,g,n,n,n,n,PM_CMPL_STALL_EXCEPTION,Cycles in which the oldest instruction in the pipeline was not allowed to complete because it was interrupted by ANY exception, which has to be serviced before the instruction can complete ##3003A Cycles in which the oldest instruction in the pipeline was not allowed to complete because it was interrupted by ANY exception, which has to be serviced before the instruction can complete #32,u,g,n,n,m,y,PM_MRK_DTLB_MISS_4K,Marked Data TLB reload (after a miss) page size 4K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches ##3013C Marked Data TLB reload (after a miss) page size 4K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches #33,u,g,n,n,n,y,PM_ITLB_MISS_1G,Instruction TLB reload (after a miss) page size 1G, which implies Radix Page Table translation is in use. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches. ##3003E Instruction TLB reload (after a miss) page size 1G, which implies Radix Page Table translation is in use. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches. #34,u,g,n,n,n,y,PM_ITLB_MISS_16G,Instruction TLB reload (after a miss) page size 16G. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches. ##34040 Instruction TLB reload (after a miss) page size 16G. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches. #35,u,g,n,n,n,y,PM_HPT_TLB_PARENT_HIT_CHILD_MISS,Hierarchical TLB found parent entry but child entry was not found in the TLB. 2-level TLB, second level miss ##34042 Hierarchical TLB found parent entry but child entry was not found in the TLB. 2-level TLB, second level miss #36,u,g,n,n,n,y,PM_DERAT_MISS_PREF,DERAT miss (TLB access) while servicing a data prefetch. ##34044 DERAT miss (TLB access) while servicing a data prefetch. #37,u,g,n,n,m,n,PM_MRK_LD_CMPL,Marked load instruction completed ##34146 Marked load instruction completed #38,u,g,n,n,m,y,PM_MRK_STORE_DATA,A marked instruction was waiting for data. This event uses edge detection. ##34149 A marked instruction was waiting for data. This event uses edge detection. #39,u,g,n,n,n,y,PM_DATA_RADIX_L2_PTE_FROM_L3MISS,A data Page Table Entry was reloaded to a level 2 page walk cache from a source beyond the core's caches. If MMCR1[16] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. ##3404A A data Page Table Entry was reloaded to a level 2 page walk cache from a source beyond the core's caches. If MMCR1[16] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. #40,u,g,n,n,n,y,PM_DATA_RADIX_L2_PDE_FROM_L3MISS,A data Page Directory Entry was reloaded to a level 2 page walk cache from a source beyond the core's caches. If MMCR1[16] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. ##3404C A data Page Directory Entry was reloaded to a level 2 page walk cache from a source beyond the core's caches. If MMCR1[16] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. #41,u,g,n,n,n,y,PM_DATA_RADIX_L3_PTE_FROM_L3MISS,A data Page Table Entry was reloaded to a level 3 page walk cache from a source beyond the core's caches. If MMCR1[16] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. ##3404E A data Page Table Entry was reloaded to a level 3 page walk cache from a source beyond the core's caches. If MMCR1[16] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. #42,u,g,n,n,n,y,PM_DATA_RADIX_L3_PDE_FROM_L3MISS,A data Page Directory Entry was reloaded to a level 3 page walk cache from a source beyond the core's caches. If MMCR1[16] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. ##35040 A data Page Directory Entry was reloaded to a level 3 page walk cache from a source beyond the core's caches. If MMCR1[16] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. #43,u,g,n,n,n,y,PM_DATA_RADIX_L4_PTE_FROM_L3MISS,A data Page Table Entry was reloaded to a level 4 page walk cache from a source beyond the core's caches. If MMCR1[16] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. ##35042 A data Page Table Entry was reloaded to a level 4 page walk cache from a source beyond the core's caches. If MMCR1[16] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. #44,u,g,n,n,n,y,PM_INST_RADIX_L2_PTE_FROM_L3MISS,An instruction Page Table Entry was reloaded to a level 2 page walk cache from a source beyond the core's caches. If MMCR1[17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[17] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. ##35046 An instruction Page Table Entry was reloaded to a level 2 page walk cache from a source beyond the core's caches. If MMCR1[17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[17] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. #45,u,g,n,n,n,y,PM_INST_RADIX_L3_PTE_FROM_L3MISS,An instruction Page Table Entry was reloaded to a level 3 page walk cache from a source beyond the core's caches. If MMCR1[17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[17] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. ##3504A An instruction Page Table Entry was reloaded to a level 3 page walk cache from a source beyond the core's caches. If MMCR1[17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[17] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. #46,u,g,n,n,n,y,PM_INST_RADIX_L3_PDE_FROM_L3MISS,An instruction Page Directory Entry was reloaded to a level 3 page walk cache from a source beyond the core's caches. If MMCR1[17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[17] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. ##3504C An instruction Page Directory Entry was reloaded to a level 3 page walk cache from a source beyond the core's caches. If MMCR1[17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[17] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. #47,u,g,n,n,n,y,PM_INST_RADIX_L4_PTE_FROM_L3MISS,An instruction Page Table Entry was reloaded to a level 4 page walk cache from a source beyond the core's caches. If MMCR1[17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[17] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. ##3504E An instruction Page Table Entry was reloaded to a level 4 page walk cache from a source beyond the core's caches. If MMCR1[17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[17] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. #48,u,g,n,n,n,y,PM_XFER_FROM_SRC_PMC3,The processor's L1 data cache was reloaded from the source specified in MMCR3[30:42]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads. ##3C040 The processor's L1 data cache was reloaded from the source specified in MMCR3[30:42]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads. #49,u,g,n,n,m,y,PM_MRK_XFER_FROM_SRC_PMC3,For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[30:42]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads. ##3C142 For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[30:42]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads. #50,u,g,n,n,m,y,PM_MRK_XFER_FROM_SRC_CYC_PMC3,Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[30:42]. ##3C144 Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[30:42]. #51,u,g,n,n,m,y,PM_MRK_DATA_FLUSHED_FROM_SRC_PMC3,Marked demand loads that attempted a reload, but were flushed ##3C146 Marked demand loads that attempted a reload, but were flushed #52,u,g,n,n,m,y,PM_MRK_DATA_FLUSHED_FROM_SRC_CYC_PMC3,Cycles spent attempting to reload a line from any source for a marked demand miss that was later flushed ##3C148 Cycles spent attempting to reload a line from any source for a marked demand miss that was later flushed #53,u,g,n,n,m,y,PM_MRK_DATA_SYS_PUMP_MPRED_RTY,Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for a marked demand load ##3C14C Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for a marked demand load #54,u,g,n,n,n,y,PM_PMC1_HELD_CYC,Cycles when the speculative counter for PMC1 is frozen. ##3C04E Cycles when the speculative counter for PMC1 is frozen. #55,u,g,n,n,n,y,PM_HOT_LOCK_COLLISION,A thread [x] larx is sent to the L1 miss pipe to generate a request to the L2. However, the thread [x] larx is blocked because a thread [y] larx stcx sequence to the same cacheline is already in progress. The thread [x] larx will be sent once the thread [y] stcx has drained to the L2. This collision pulses once for the detection described above and is meant as a count event. ##3F042 A thread [x] larx is sent to the L1 miss pipe to generate a request to the L2. However, the thread [x] larx is blocked because a thread [y] larx stcx sequence to the same cacheline is already in progress. The thread [x] larx will be sent once the thread [y] stcx has drained to the L2. This collision pulses once for the detection described above and is meant as a count event. #56,u,g,n,n,n,y,PM_VSU2_ISSUE,VSU instruction issued to VSU pipe 2 ##3F044 VSU instruction issued to VSU pipe 2 #57,u,g,n,n,n,y,PM_ITLB_HIT_1G,Instruction TLB hit (IERAT reload) page size 1G, which implies Radix Page Table translation is in use. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches. ##3F046 Instruction TLB hit (IERAT reload) page size 1G, which implies Radix Page Table translation is in use. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches. #58,u,g,n,n,n,y,PM_ITLB_HIT_16G,Instruction TLB hit (IERAT reload) page size 16G. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches. ##3F048 Instruction TLB hit (IERAT reload) page size 16G. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches. #59,u,g,n,n,n,y,PM_LSU_ST5_FIN,LSU Finished an internal operation in ST2 port ##3F04A LSU Finished an internal operation in ST2 port #60,u,g,n,n,n,y,PM_RADIX_RELOAD,A page was reloaded for a radix translation in the ERAT or TLB. ##3F04C A page was reloaded for a radix translation in the ERAT or TLB. #61,u,g,n,n,n,n,PM_PROBLEM_CYC,Cycles in which the MSR register shows the thread in problem state. ##3F04E Cycles in which the MSR register shows the thread in problem state. #62,u,g,n,n,n,y,PM_GRP_PUMP_MPRED_RTY,Final Pump Scope (group) ended up larger than Initial Pump Scope (chip). Includes instruction and data lines ##30050 Final Pump Scope (group) ended up larger than Initial Pump Scope (chip). Includes instruction and data lines #63,u,g,n,n,n,y,PM_SYS_PUMP_MPRED_TOO_BIG,Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) ##30052 Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) #64,u,g,n,n,m,y,PM_MRK_FAB_RSP_DCLAIM,Marked store had to do a dclaim ##30154 Marked store had to do a dclaim #65,u,g,n,n,n,y,PM_TLBIE_FIN,TLBIE instruction finished in the LSU. Two TLBIEs can finish each cycle. All will be counted ##30058 TLBIE instruction finished in the LSU. Two TLBIEs can finish each cycle. All will be counted #66,u,g,n,n,m,n,PM_MRK_PTESYNC_CYC,Ptesync latency from the cycle the marked instruction becomes next-to-complete (NTC) until it completes in the nest ##3015C Ptesync latency from the cycle the marked instruction becomes next-to-complete (NTC) until it completes in the nest #67,u,g,n,n,m,y,PM_MRK_FAB_RSP_CLAIM_RTY,Sampled store did a rwitm and got a rty ##3015E Sampled store did a rwitm and got a rty #68,u,g,n,n,n,y,PM_INST_SYS_PUMP_CPRED,Initial and Final Pump Scope was system pump (prediction=correct) for an instruction fetch ##34050 Initial and Final Pump Scope was system pump (prediction=correct) for an instruction fetch #69,u,g,n,n,n,y,PM_INST_SYS_PUMP_MPRED_TOO_BIG,Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for an instruction fetch ##34052 Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for an instruction fetch #70,u,g,n,n,n,y,PM_EXEC_STALL_DMISS_L2L3_NOCONFLICT,Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from the local L2 or local L3, without a dispatch conflict. ##34054 Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from the local L2 or local L3, without a dispatch conflict. #71,u,g,n,n,n,y,PM_EXEC_STALL_LOAD_FINISH,Cycles in which the oldest instruction in the pipeline was finishing a load after its data was reloaded from a data source beyond the local L1 ##34056 Cycles in which the oldest instruction in the pipeline was finishing a load after its data was reloaded from a data source beyond the local L1 #72,u,g,n,n,n,y,PM_DISP_STALL_BR_MPRED_ICMISS,Cycles when dispatch was stalled after a mispredicted branch resulted in an instruction cache miss. ##34058 Cycles when dispatch was stalled after a mispredicted branch resulted in an instruction cache miss. #73,u,g,n,n,n,n,PM_PRIVILEGED_INST_CMPL,PowerPC instruction completed while the thread was in Privileged state. ##3405A PowerPC instruction completed while the thread was in Privileged state. #74,u,g,n,n,n,y,PM_DATA_SYS_PUMP_CPRED,Initial and Final Pump Scope was system pump (prediction=correct) for a demand load ##3C050 Initial and Final Pump Scope was system pump (prediction=correct) for a demand load #75,u,g,n,n,n,y,PM_DATA_SYS_PUMP_MPRED_TOO_BIG,Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for a demand load ##3C052 Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for a demand load #76,u,g,n,n,n,y,PM_DERAT_MISS_16M,Data ERAT Miss (Data TLB Access) page size 16M. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches ##3C054 Data ERAT Miss (Data TLB Access) page size 16M. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches #77,u,g,n,n,n,y,PM_DTLB_MISS_64K,Data TLB reload (after a miss) page size 64K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches ##3C056 Data TLB reload (after a miss) page size 64K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches #78,u,g,n,n,n,y,PM_LARX_FIN,Load and reserve instruction (LARX) finished. LARX and STCX are instructions used to acquire a lock ##3C058 Load and reserve instruction (LARX) finished. LARX and STCX are instructions used to acquire a lock #79,u,g,n,n,n,y,PM_DTLB_HIT_64K,Data TLB hit (DERAT reload) page size 64K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches ##3C05A Data TLB hit (DERAT reload) page size 64K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches #80,u,g,n,n,n,y,PM_MEM_RWITM,Memory Read With Intent to Modify for this thread. This event count should be divided by two since the event is sourced from 2:1 clock domain. ##3C05E Memory Read With Intent to Modify for this thread. This event count should be divided by two since the event is sourced from 2:1 clock domain. #81,u,g,n,n,m,y,PM_MRK_DERAT_MISS_16G,Data ERAT Miss (Data TLB Access) page size 16G for a marked instruction. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches ##3D154 Data ERAT Miss (Data TLB Access) page size 16G for a marked instruction. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches #82,u,g,n,n,n,y,PM_SCALAR_FSQRT_FDIV_ISSUE,Scalar versions of four floating point operations: fdiv,fsqrt (xvdivdp, xvdivsp, xvsqrtdp, xvsqrtsp). ##3D058 Scalar versions of four floating point operations: fdiv,fsqrt (xvdivdp, xvdivsp, xvsqrtdp, xvsqrtsp). #83,u,g,n,n,n,y,PM_DISP_STALL_HELD_RENAME_CYC,Cycles in which the next-to-complete (NTC) instruction is held at dispatch because the mapper/SRB was full. Includes GPR (count, link, tar), VSR, VMR, FPR and XVFC ##3D05C Cycles in which the next-to-complete (NTC) instruction is held at dispatch because the mapper/SRB was full. Includes GPR (count, link, tar), VSR, VMR, FPR and XVFC #84,u,g,n,n,m,y,PM_MULT_MRK,mult marked instr ##3D15E mult marked instr #85,u,g,n,n,n,y,PM_EXT_INT_OS,Cycles an external interrupt was active that was initiated by the OS ##3E050 Cycles an external interrupt was active that was initiated by the OS #86,u,g,n,n,n,y,PM_DISP_STALL_IC_L3,Cycles when dispatch was stalled while the instruction was fetched from the local L3. ##3E052 Cycles when dispatch was stalled while the instruction was fetched from the local L3. #87,u,g,n,n,n,y,PM_LD_MISS_L1,Load missed L1, counted at finish time. LMQ merges are not included in this count. i.e. if a load instruction misses on an address that is already allocated on the LMQ, this event will not increment for that load). Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load. ##3E054 Load missed L1, counted at finish time. LMQ merges are not included in this count. i.e. if a load instruction misses on an address that is already allocated on the LMQ, this event will not increment for that load). Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load. #88,u,g,n,n,m,y,PM_MRK_STCX_FAIL,Marked conditional store instruction (STCX) failed. LARX and STCX are instructions used to acquire a lock  ##3E158 Marked conditional store instruction (STCX) failed. LARX and STCX are instructions used to acquire a lock  #89,u,g,n,n,m,y,PM_MRK_ST_FIN,Marked store instruction finished ##3E15A Marked store instruction finished #90,u,g,n,n,n,n,PM_L3_CO_MEPF,L3 castouts in Mepf state for this core. ##3E05E L3 castouts in Mepf state for this core. #91,u,g,n,n,m,n,PM_MRK_ST_DRAIN_CYC,Cycles in which the marked store drained from the core to the L2 ##3F150 Cycles in which the marked store drained from the core to the L2 #92,u,g,n,n,n,y,PM_DISP_SS0_4_INSTR_CYC,Cycles in which Superslice 0 dispatches either 3 or 4 instructions ##3F054 Cycles in which Superslice 0 dispatches either 3 or 4 instructions #93,u,g,n,n,n,y,PM_DISP_SS0_8_INSTR_CYC,Cycles in which Superslice 0 dispatches either 5, 6, 7 or 8 instructions ##3F056 Cycles in which Superslice 0 dispatches either 5, 6, 7 or 8 instructions #94,u,g,n,n,n,y,PM_DISP_HELD_ISSQ_FULL_CYC,Cycles dispatch is held due to Issue queue full. Includes issue queue and branch queue ##3F05E Cycles dispatch is held due to Issue queue full. Includes issue queue and branch queue #95,u,g,n,n,n,y,PM_DISP_HELD_XVFC_MAPPER_CYC,Cycles dispatch is held because the XVFC mapper/SRB was full ##30060 Cycles dispatch is held because the XVFC mapper/SRB was full #96,u,g,n,n,m,y,PM_MRK_ISSUE_DEPENDENT_LOAD,The marked instruction was dependent on a load. It is eligible for issue kill ##30162 The marked instruction was dependent on a load. It is eligible for issue kill #97,u,g,n,n,n,n,PM_NTF_ISSUE_HOLD_CYC,Cycles in which the oldest instruction in the pipeline is being held at issue. ##30064 Cycles in which the oldest instruction in the pipeline is being held at issue. #98,u,g,n,n,n,y,PM_LSU_FIN,LSU Finished an internal operation (up to 4 per cycle) ##30066 LSU Finished an internal operation (up to 4 per cycle) #99,u,g,n,n,n,y,PM_L1_ICACHE_RELOADED_PREF,Counts all instruction cache prefetch reloads (includes demand turned into prefetch) ##30068 Counts all instruction cache prefetch reloads (includes demand turned into prefetch) #100,u,g,n,n,n,n,PM_RUN_CYC_SMT2_MODE,Cycles when this thread's run latch is set and the core is in SMT2 mode ##3006C Cycles when this thread's run latch is set and the core is in SMT2 mode #101,u,g,n,n,n,n,PM_CONSTANT_CLK,This event increments at the 32 MHz rate of Tod_step. ##3006E This event increments at the 32 MHz rate of Tod_step. #102,u,g,n,n,m,n,PM_MRK_ST_CMPL,Marked store completed and sent to nest. Note that this count excludes cache-inhibited stores ##301E2 Marked store completed and sent to nest. Note that this count excludes cache-inhibited stores #103,u,g,n,n,m,n,PM_MRK_BR_MPRED_CMPL,Marked Branch Mispredicted. Includes direction and target ##301E4 Marked Branch Mispredicted. Includes direction and target #104,u,g,n,n,m,y,PM_MRK_DERAT_MISS,Marked Erat Miss (Data TLB Access) All page sizes. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches ##301E6 Marked Erat Miss (Data TLB Access) All page sizes. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches #105,u,g,t,n,m,y,PM_THRESH_EXC_64,Threshold counter exceeded a value of 64 ##301E8 Threshold counter exceeded a value of 64 #106,u,g,t,n,m,y,PM_THRESH_EXC_1024,Threshold counter exceeded a value of 1024 ##301EA Threshold counter exceeded a value of 1024 #107,u,g,n,n,n,y,PM_ST_MISS_L1,Store Missed L1 ##300F0 Store Missed L1 #108,u,g,n,n,n,n,PM_RUN_INST_CMPL_CONC,PowerPC instruction completed by this thread when all threads in the core had the run-latch set ##300F4 PowerPC instruction completed by this thread when all threads in the core had the run-latch set #109,u,g,n,n,n,y,PM_LD_DEMAND_MISS_L1,The L1 cache was reloaded with a line that fulfills a demand miss request. Counted at reload time, before finish. ##300F6 The L1 cache was reloaded with a line that fulfills a demand miss request. Counted at reload time, before finish. #110,u,g,n,n,n,n,PM_TB_BIT_TRANS,timebase event ##300F8 timebase event #111,u,g,n,n,n,u,PM_INST_FROM_L3MISS,The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss. ##300FA The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss. #112,u,g,n,n,n,y,PM_DTLB_MISS,The DPTEG required for the load/store instruction in execution was missing from the TLB. It includes pages of all sizes for demand and prefetch activity ##300FC The DPTEG required for the load/store instruction in execution was missing from the TLB. It includes pages of all sizes for demand and prefetch activity #113,u,g,n,n,n,u,PM_DATA_FROM_L3MISS,The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss. ##300FE The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss. #114,u,g,n,n,m,u,PM_MRK_INST_FROM_L3MISS,The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction. ##000780000003C142 The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction. #115,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2MISS,The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction. ##0003C0000003C142 The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction. #116,u,g,n,n,n,u,PM_EE_OFF_EXT_INT_CYC,Cycles in which MSR[EE] is off and external interrupts are active ##0000002080 Cycles in which MSR[EE] is off and external interrupts are active #117,u,g,n,n,n,u,PM_ISU_FLUSH,All flushes initiated by the Instruction Sequencing Unit (ISU). Excludes LSU NTC+1 flushes ##0000002880 All flushes initiated by the Instruction Sequencing Unit (ISU). Excludes LSU NTC+1 flushes #118,u,g,n,n,n,u,PM_ISU_FLUSH_DISP,Dispatch flushes occur when one thread is causing other threads to stall ##0000002084 Dispatch flushes occur when one thread is causing other threads to stall #119,u,g,n,n,n,u,PM_ISU_FLUSH_BALANCE,A balance flush occurred. Balance flushes are triggered when excessive L3 or TLB misses occur ##0000002884 A balance flush occurred. Balance flushes are triggered when excessive L3 or TLB misses occur #120,u,g,n,n,n,u,PM_ISU_FLUSH_PARTIAL,A flush occurred only to the odd ITAG of a pair. This type of flush requires an additional 10 cycles to process. More pairs of instructions can be included in this count. ##0000002088 A flush occurred only to the odd ITAG of a pair. This type of flush requires an additional 10 cycles to process. More pairs of instructions can be included in this count. #121,u,g,n,n,n,u,PM_ISU_FLUSH_DISP_SRQ_EMPTY,Dispatch flush while waiting for the SRQ to become empty: TLBIE, SLBIEG, SLBIET, EIEIO, TLBSYNC. ##0000002888 Dispatch flush while waiting for the SRQ to become empty: TLBIE, SLBIEG, SLBIET, EIEIO, TLBSYNC. #122,u,g,n,n,n,u,PM_ISU_FLUSH_LD_ECC_ERROR,A load instruction that accessed early data from memory and finished speculatively before the ECC was returned, gets flushed because of a later ECC error ##000000208C A load instruction that accessed early data from memory and finished speculatively before the ECC was returned, gets flushed because of a later ECC error #123,u,g,n,n,n,u,PM_ISU_FLUSH_LWSYNC,A flush to a lightweight synchronizing or barrier instruction (LWSYNC) instruction that had trouble. This event includes NTC flushes and NTC+1 flushes. ##000000288C A flush to a lightweight synchronizing or barrier instruction (LWSYNC) instruction that had trouble. This event includes NTC flushes and NTC+1 flushes. #124,u,g,n,n,n,u,PM_ISU_FLUSH_ISYNC,A flush to an isync instruction that had trouble. This event includes NTC flushes and NTC+1 flushes. ##0000002090 A flush to an isync instruction that had trouble. This event includes NTC flushes and NTC+1 flushes. #125,u,g,n,n,n,u,PM_ISU_FLUSH_HWSYNC,A flush to a heavyweight synchronizing or barrier instruction (HWSYNC) instruction that had trouble. This event includes NTC flushes and NTC+1 flushes. ##0000002094 A flush to a heavyweight synchronizing or barrier instruction (HWSYNC) instruction that had trouble. This event includes NTC flushes and NTC+1 flushes. #126,u,g,n,n,n,u,PM_ISU_FLUSH_MMA_OFF_CYC,If the MMA engine is off when an MMA instruction is issued, the instruction will issue and finish as a nop. It will then get flushed when it becomes NTC and it will not be refetched until the MMA engine is on. This event counts the number of cycles between the flush and the MMA engine turning on. ##0000002894 If the MMA engine is off when an MMA instruction is issued, the instruction will issue and finish as a nop. It will then get flushed when it becomes NTC and it will not be refetched until the MMA engine is on. This event counts the number of cycles between the flush and the MMA engine turning on. #127,u,g,n,n,n,u,PM_ISU_FLUSH_DISP_STF_REBAL,The Sliced Target File (STF) is the register file for GPRs, VSRs, LR, CTR, and TAR. This event indicates that an execution unit attempted to write to a slice that was full. In this case, the instruction gets flushed and the slices get rebalanced. ##00000028AC The Sliced Target File (STF) is the register file for GPRs, VSRs, LR, CTR, and TAR. This event indicates that an execution unit attempted to write to a slice that was full. In this case, the instruction gets flushed and the slices get rebalanced. #128,u,g,n,n,n,u,PM_START_PROBE_NOP_DISP,A start probe nop was dispatched. Instruction AND 0,0,0 ##00000020B0 A start probe nop was dispatched. Instruction AND 0,0,0 #129,u,g,n,n,n,u,PM_STOP_PROBE_NOP_DISP,A stop probe nop was dispatched. Instruction AND 1,1,1 ##00000028B0 A stop probe nop was dispatched. Instruction AND 1,1,1 #130,u,g,n,n,m,u,PM_MRK_STOP_PROBE_NOP_DISP,A stop probe nop was marked at dispatch. Instruction AND 1,1,1 ##00000021B4 A stop probe nop was marked at dispatch. Instruction AND 1,1,1 #131,u,g,n,n,n,u,PM_FUNCTION_CALL_DISP,bl instruction dispatched. Only one reported per cycle. It is possible to dispatch 8 instructions per cycle in single thread mode. ##00000020B8 bl instruction dispatched. Only one reported per cycle. It is possible to dispatch 8 instructions per cycle in single thread mode. #132,u,g,n,n,n,u,PM_FUNCTION_RETURN_DISP,blr instruction dispatched. Only one reported per cycle. It is possible to dispatch 8 instructions per cycle in single thread mode. ##00000028B8 blr instruction dispatched. Only one reported per cycle. It is possible to dispatch 8 instructions per cycle in single thread mode. #133,u,g,n,n,n,u,PM_0CYC_CONST_DISP,Xxor instruction dispatched. ##00000020BC Xxor instruction dispatched. #134,u,g,n,n,n,u,PM_ISSUE_HOLD_STAGS_CYC,Cycles in which one or more instructions are being held at issue while waiting for Store Tags to become available. These instructions could also be held simultaneously for other conditions. Other non-store instructions are allowed to issue while the store is being held. ##0000003080 Cycles in which one or more instructions are being held at issue while waiting for Store Tags to become available. These instructions could also be held simultaneously for other conditions. Other non-store instructions are allowed to issue while the store is being held. #135,u,g,n,n,n,u,PM_ISSUE_HOLD_LTAGS_CYC,Cycles in which one or more instructions are being held at issue while waiting for Load Tags to become available. These instructions could also be held simultaneously for other conditions. Other non-load instructions are allowed to issue while the load is being held. ##0000003880 Cycles in which one or more instructions are being held at issue while waiting for Load Tags to become available. These instructions could also be held simultaneously for other conditions. Other non-load instructions are allowed to issue while the load is being held. #136,u,g,n,n,n,u,PM_ISSUE_KILL_DL_MISS,An instruction was primed to issue but was killed before being written because one of the sources takes a data load miss. I.e. dependent data from a load does not get valid data ##0000003084 An instruction was primed to issue but was killed before being written because one of the sources takes a data load miss. I.e. dependent data from a load does not get valid data #137,u,g,n,n,n,u,PM_ISSUE_KILL_RESOURCE,An instruction was primed to issue but was killed before being written because a resource is unavailable. Includes BFU, FX-DIV, DFU, BRU and SFX instructions that would collide at finish with a store AGEN. ##0000003884 An instruction was primed to issue but was killed before being written because a resource is unavailable. Includes BFU, FX-DIV, DFU, BRU and SFX instructions that would collide at finish with a store AGEN. #138,u,g,n,n,n,u,PM_ISSUE_KILL_THROTTLE,An instruction was primed to issue but was killed before being written because power throttling was enabled ##0000003088 An instruction was primed to issue but was killed before being written because power throttling was enabled #139,u,g,n,n,n,u,PM_SHL_HIT,A dependency was created when a dispatched store matched the address for a load in the Store-Hit-Load Table. ##000000388C A dependency was created when a dispatched store matched the address for a load in the Store-Hit-Load Table. #140,u,g,n,n,n,u,PM_LHS_HIT,A dependency was created when a dispatched load matched the address for a store instruction in the Load-Hit-Store table. ##0000003890 A dependency was created when a dispatched load matched the address for a store instruction in the Load-Hit-Store table. #141,u,g,n,n,n,u,PM_LHS_CREATED,New entry added to the Load-Hit-Store table. ##0000003094 New entry added to the Load-Hit-Store table. #142,u,g,n,n,n,u,PM_LARX_HIT_LARX_HIT,A dependency was created for a LARX instruction that was dispatched and matched an older LARX in the Larx-hit-larx table. ##0000003894 A dependency was created for a LARX instruction that was dispatched and matched an older LARX in the Larx-hit-larx table. #143,u,g,n,n,n,u,PM_LARX_HIT_LARX_CREATED,New entry added to the Larx-hit-larx table. LARX and STCX are instructions used to acquire a lock.  ##0000003098 New entry added to the Larx-hit-larx table. LARX and STCX are instructions used to acquire a lock.  #144,u,g,n,n,n,u,PM_MMA_VSR_CONFLICT_FLUSH,A VSR operation references an ACC that has been primed. This is indicative of a context switch ##0000003898 A VSR operation references an ACC that has been primed. This is indicative of a context switch #145,u,g,n,n,n,u,PM_MMA_ACC_CONFLICT_FLUSH,An MMA instruction references an ACC that has not been primed. This is indicative of faulty software ##000000309C An MMA instruction references an ACC that has not been primed. This is indicative of faulty software #146,u,g,n,n,m,u,PM_MRK_MMA_ACC_VSR_CONFLICT,Either a marked MMA instruction references an ACC that has not been primed or a marked VSR operation references an ACC that has been primed ##000000399C Either a marked MMA instruction references an ACC that has not been primed or a marked VSR operation references an ACC that has been primed #147,u,g,n,n,n,u,PM_MMA_IN_USE_CYC,Cycles in which the MMA engine is actively being used by this thread. This is measured by counting the cycles in which at least one ACC register is primed for MMA use. ##00000030A0 Cycles in which the MMA engine is actively being used by this thread. This is measured by counting the cycles in which at least one ACC register is primed for MMA use. #148,u,g,n,n,n,u,PM_MMA_ON_CYC,Cycles in which this core's MMA engine is enabled. ##00000038A0 Cycles in which this core's MMA engine is enabled. #149,u,g,n,n,n,u,PM_DISP_HELD_OUT_OF_LTAGS_CYC,Cycles in which dispatch is held because the LRQ is full. No LTAGS are available. There are twice as many LTAGS as there are LRQ entries. The signal should be on if less than 8 tags, and should be off if greater than 24 tags, and could be on if in-between. In ST/SMT2, if less than 24 tags, signal can come on, and if less than 8 it will be on. In SMT4, if less than 12 tags, it can come on, if less than 4 tags it will be on. ##00000030B4 Cycles in which dispatch is held because the LRQ is full. No LTAGS are available. There are twice as many LTAGS as there are LRQ entries. The signal should be on if less than 8 tags, and should be off if greater than 24 tags, and could be on if in-between. In ST/SMT2, if less than 24 tags, signal can come on, and if less than 8 it will be on. In SMT4, if less than 12 tags, it can come on, if less than 4 tags it will be on. #150,u,g,n,n,n,u,PM_DISP_HELD_OUT_OF_STAGS_CYC,Cycles in which dispatch is held because the SRQ is full. No STAGS are available. There are twice as many STAGS as there are SRQ entries. The signal should be on if less than 8 tags, should be off is greater than 24 tags, and could be on if in-between. In ST/SMT2, if less than 24 tags, signal can come on, if less than 8 tags it will be on. In SMT4, if less than 12 tags, it can come on, if less than 4 tags it will be on. ##00000038B4 Cycles in which dispatch is held because the SRQ is full. No STAGS are available. There are twice as many STAGS as there are SRQ entries. The signal should be on if less than 8 tags, should be off is greater than 24 tags, and could be on if in-between. In ST/SMT2, if less than 24 tags, signal can come on, if less than 8 tags it will be on. In SMT4, if less than 12 tags, it can come on, if less than 4 tags it will be on. #151,u,g,n,n,n,u,PM_DISP_CLB_HELD_BALANCE_CYC,Dispatch/CLB Hold as cause of Balance Flush. ##00000030B8 Dispatch/CLB Hold as cause of Balance Flush. #152,u,g,n,n,n,u,PM_DISP_CLB_HELD_SRQ_EMPTY_CYC,Dispatch Hold: waiting for the SRQ to become empty: TLBIE, SLBIEG, SLBIET, EIEIO, TLBSYNC. This should exclude cycles when it is only waiting for the ICT to become empty. ##00000038B8 Dispatch Hold: waiting for the SRQ to become empty: TLBIE, SLBIEG, SLBIET, EIEIO, TLBSYNC. This should exclude cycles when it is only waiting for the ICT to become empty. #153,u,g,n,n,n,u,PM_DISP_PARTIAL,Dispatches in which the Instruction Sequencing Unit (ISU) dispatches instructions at either half rate or quarter rate. This can happen when some of the queues (or mapper subblocks) are either full, or close to full. ##00000030BC Dispatches in which the Instruction Sequencing Unit (ISU) dispatches instructions at either half rate or quarter rate. This can happen when some of the queues (or mapper subblocks) are either full, or close to full. #154,u,g,n,n,n,u,PM_ISYNC_CMPL,Isync completion count per thread ##00000038BC Isync completion count per thread #155,u,g,n,n,n,u,PM_LD0_8B_FIN,64-bit or smaller load finished in the LD0 load execution unit. ##000000C080 64-bit or smaller load finished in the LD0 load execution unit. #156,u,g,n,n,n,u,PM_LD1_8B_FIN,64-bit or smaller load finished in the LD1 load execution unit. ##000000C880 64-bit or smaller load finished in the LD1 load execution unit. #157,u,g,n,n,n,u,PM_LD0_16B_FIN,128-bit load finished in the LD0 load execution unit. ##000000C084 128-bit load finished in the LD0 load execution unit. #158,u,g,n,n,n,u,PM_LD1_16B_FIN,128-bit load finished in the LD1 load execution unit. ##000000C884 128-bit load finished in the LD1 load execution unit. #159,u,g,n,n,n,u,PM_LD0_32B_FIN,256-bit load finished in the LD0 load execution unit. ##000000C088 256-bit load finished in the LD0 load execution unit. #160,u,g,n,n,n,u,PM_LD1_32B_FIN,256-bit load finished in the LD1 load execution unit. ##000000C888 256-bit load finished in the LD1 load execution unit. #161,u,g,n,n,n,u,PM_LD0_VECTOR_FIN,Any vector load operation finished in the LD0 execution unit. Excludes load quad, larx quad, fused load double, load float double-pair. ##000000C08C Any vector load operation finished in the LD0 execution unit. Excludes load quad, larx quad, fused load double, load float double-pair. #162,u,g,n,n,n,u,PM_LD1_VECTOR_FIN,Any vector load operation finished in the LD1 execution unit. Excludes load quad, larx quad, fused load double, load float double-pair. ##000000C88C Any vector load operation finished in the LD1 execution unit. Excludes load quad, larx quad, fused load double, load float double-pair. #163,u,g,n,n,n,u,PM_LD0_UNALIGNED_FIN,Load instructions in LD0 port that are either unaligned, or treated as unaligned and require an additional recycle through the pipeline using the load gather buffer. This typically adds about 10 cycles to the latency of the instruction. This includes loads that cross the 128 byte boundary, octword loads that are not aligned, and a special forward progress case of a load that does not hit in the L1 and crosses the 32 byte boundary and is launched NTC. Counted at finish time. ##000000C090 Load instructions in LD0 port that are either unaligned, or treated as unaligned and require an additional recycle through the pipeline using the load gather buffer. This typically adds about 10 cycles to the latency of the instruction. This includes loads that cross the 128 byte boundary, octword loads that are not aligned, and a special forward progress case of a load that does not hit in the L1 and crosses the 32 byte boundary and is launched NTC. Counted at finish time. #164,u,g,n,n,n,u,PM_LD1_UNALIGNED_FIN,Load instructions in LD1 port that are either unaligned, or treated as unaligned and require an additional recycle through the pipeline using the load gather buffer. This typically adds about 10 cycles to the latency of the instruction. This includes loads that cross the 128 byte boundary, octword loads that are not aligned, and a special forward progress case of a load that does not hit in the L1 and crosses the 32 byte boundary and is launched NTC. Counted at finish time. ##000000C890 Load instructions in LD1 port that are either unaligned, or treated as unaligned and require an additional recycle through the pipeline using the load gather buffer. This typically adds about 10 cycles to the latency of the instruction. This includes loads that cross the 128 byte boundary, octword loads that are not aligned, and a special forward progress case of a load that does not hit in the L1 and crosses the 32 byte boundary and is launched NTC. Counted at finish time. #165,u,g,n,n,n,u,PM_ST0_8B_FIN,8-byte or smaller store finished in the ST0 store execution unit. ##000000C094 8-byte or smaller store finished in the ST0 store execution unit. #166,u,g,n,n,n,u,PM_ST1_8B_FIN,8-byte or smaller store finished in the ST1 store execution unit. ##000000C894 8-byte or smaller store finished in the ST1 store execution unit. #167,u,g,n,n,n,u,PM_ST0_16B_FIN,16-byte store finished in the ST0 store execution unit. ##000000C098 16-byte store finished in the ST0 store execution unit. #168,u,g,n,n,n,u,PM_ST1_16B_FIN,16-byte store finished in the ST1 store execution unit. ##000000C898 16-byte store finished in the ST1 store execution unit. #169,u,g,n,n,n,u,PM_ST0_32B_FIN,32-byte store finished in the ST0 store execution unit. ##000000C09C 32-byte store finished in the ST0 store execution unit. #170,u,g,n,n,n,u,PM_ST1_32B_FIN,32-byte store finished in the ST1 store execution unit. ##000000C89C 32-byte store finished in the ST1 store execution unit. #171,u,g,n,n,n,u,PM_ST0_VECTOR_FIN,Any vector store operation finished in the ST0 store execution unit. Excludes store quad, stcx quad, store float double-pair, fused store double. ##000000C0A0 Any vector store operation finished in the ST0 store execution unit. Excludes store quad, stcx quad, store float double-pair, fused store double. #172,u,g,n,n,n,u,PM_ST1_VECTOR_FIN,Any vector store operation finished in the ST1 store execution unit. Excludes store quad, stcx quad, store float double-pair, fused store double. ##000000C8A0 Any vector store operation finished in the ST1 store execution unit. Excludes store quad, stcx quad, store float double-pair, fused store double. #173,u,g,n,n,n,u,PM_ST0_UNALIGNED_FIN,Store instructions in ST0 port that are either unaligned, or treated as unaligned and require an additional recycle through the pipeline. This typically adds about 10 cycles to the latency of the instruction. This only includes stores that cross the 128 byte boundary. Counted at finish time. ##000000C0A4 Store instructions in ST0 port that are either unaligned, or treated as unaligned and require an additional recycle through the pipeline. This typically adds about 10 cycles to the latency of the instruction. This only includes stores that cross the 128 byte boundary. Counted at finish time. #174,u,g,n,n,n,u,PM_ST1_UNALIGNED_FIN,Store instructions in ST1 port that are either unaligned, or treated as unaligned and require an additional recycle through the pipeline. This typically adds about 10 cycles to the latency of the instruction. This only includes stores that cross the 128 byte boundary. Counted at finish time. ##000000C8A4 Store instructions in ST1 port that are either unaligned, or treated as unaligned and require an additional recycle through the pipeline. This typically adds about 10 cycles to the latency of the instruction. This only includes stores that cross the 128 byte boundary. Counted at finish time. #175,u,g,n,n,n,u,PM_FALSE_LHS,False Load-Hit-Store (LHS) match detected. Load and store have a partial Effective Address (EA) match but they are actually independent of each other. The other cases of false LHS cause flushes and they are instrumented with separate PMU events. ##000000C0A8 False Load-Hit-Store (LHS) match detected. Load and store have a partial Effective Address (EA) match but they are actually independent of each other. The other cases of false LHS cause flushes and they are instrumented with separate PMU events. #176,u,g,n,n,n,u,PM_LD0_LHS_REJECT,On the LD0 load execution unit, the real address of a load matched the real address of an earlier store and it is not possible to store forward because not all bytes required by the load are available on the store entry that was hit. In this case, the load must wait for the store to drain or for the store data to issue. ##000000C8A8 On the LD0 load execution unit, the real address of a load matched the real address of an earlier store and it is not possible to store forward because not all bytes required by the load are available on the store entry that was hit. In this case, the load must wait for the store to drain or for the store data to issue. #177,u,g,n,n,n,u,PM_LD1_LHS_REJECT,On the LD1 load execution unit, the real address of a load matched the real address of an earlier store and it is not possible to store forward because not all bytes required by the load are available on the store entry that was hit. In this case, the load must wait for the store to drain or for the store data to issue. ##000000C0AC On the LD1 load execution unit, the real address of a load matched the real address of an earlier store and it is not possible to store forward because not all bytes required by the load are available on the store entry that was hit. In this case, the load must wait for the store to drain or for the store data to issue. #178,u,g,n,n,n,u,PM_ST0_STORE_REJECT,Store reject on the ST0 store execution unit. All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up, to try again after the condition has been met. ##000000C8AC Store reject on the ST0 store execution unit. All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up, to try again after the condition has been met. #179,u,g,n,n,n,u,PM_ST1_STORE_REJECT,Store reject on the ST1 store execution unit. All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up, to try again after the condition has been met. ##000000C0B0 Store reject on the ST1 store execution unit. All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up, to try again after the condition has been met. #180,u,g,n,n,n,u,PM_ST_DRAIN_MERGE,Two stores drain together. Use PM_ST_CMPL as a divider. If one of the stores crosses a cache-line boundary, a store drain can be counted for each half. In this case, if there are three stores they will count as two merges. ##000000C8B0 Two stores drain together. Use PM_ST_CMPL as a divider. If one of the stores crosses a cache-line boundary, a store drain can be counted for each half. In this case, if there are three stores they will count as two merges. #181,u,g,n,n,n,u,PM_LMQ_MERGE,A load-hit-reload occurred. A load launched in the LSU and hit an existing LMQ entry which is fetching data for the same cacheline. ##000000C0B4 A load-hit-reload occurred. A load launched in the LSU and hit an existing LMQ entry which is fetching data for the same cacheline. #182,u,g,n,n,n,u,PM_STCX_CMPL,STCX data was sent to nest, i.e. total count of stcx. stcx instructions are not allowed to gather before the final drain-out to the L1 and L2, so this count is always accurate. ##000000C8B4 STCX data was sent to nest, i.e. total count of stcx. stcx instructions are not allowed to gather before the final drain-out to the L1 and L2, so this count is always accurate. #183,u,g,n,n,n,u,PM_NCST_CMPL,Counts when an I=1 store op is sent to the nest. This event counts at drain time and it may include up to 3 stores that have gathered for the same cache line before drain. ##000000C0B8 Counts when an I=1 store op is sent to the nest. This event counts at drain time and it may include up to 3 stores that have gathered for the same cache line before drain. #184,u,g,n,n,n,u,PM_STCX_SUCCESS_CMPL,STCX instructions that completed successfully. Specifically, counts only when a pass status is returned from the nest. ##000000C8B8 STCX instructions that completed successfully. Specifically, counts only when a pass status is returned from the nest. #185,u,g,n,n,n,u,PM_DC_RELOAD_COLLISIONS,A load reading the L1 cache has a bank collision with another load reading the same bank, or due to a cache-line reload writing to that bank of the L1 cache. ##000000C0BC A load reading the L1 cache has a bank collision with another load reading the same bank, or due to a cache-line reload writing to that bank of the L1 cache. #186,u,g,n,n,n,u,PM_DC_STORE_WRITE_COLLISIONS,A store writing the L1 cache at the same time as a reload or dkill writing the L1 cache that results in a bank collision. ##000000C8BC A store writing the L1 cache at the same time as a reload or dkill writing the L1 cache that results in a bank collision. #187,u,g,n,n,n,u,PM_LSU_SET_MPRED,Set prediction(set-p) miss. The entry was not found in the Set prediction table. The set-p table contains a hash of the EA and it helps access the L1 cache. ##000000D080 Set prediction(set-p) miss. The entry was not found in the Set prediction table. The set-p table contains a hash of the EA and it helps access the L1 cache. #188,u,g,n,n,n,u,PM_DERAT_HIT,A load or store instruction missed the data cache and hit in the primary ERAT. There is no secondary ERAT ##000000D880 A load or store instruction missed the data cache and hit in the primary ERAT. There is no secondary ERAT #189,u,g,n,n,n,u,PM_IERAT_HIT,An instruction fetch missed in the instruction cache and hit in the primary ERAT. There is no secondary ERAT ##000000D084 An instruction fetch missed in the instruction cache and hit in the primary ERAT. There is no secondary ERAT #190,u,g,n,n,n,u,PM_TIQ_BYPASS,A translation request bypasses the TIQ either because the TIQ is completely empty at the time of the request. ##000000D884 A translation request bypasses the TIQ either because the TIQ is completely empty at the time of the request. #191,u,g,n,n,n,u,PM_TIQ_ALLOC_CYC,Cycles when one or more operations on that thread allocated one or more TIQ entries ##000000D088 Cycles when one or more operations on that thread allocated one or more TIQ entries #192,u,g,n,n,n,u,PM_TIQ_HALF_FULL_CYC,Cycles in which the TIQ has 4 or less active entries ##000000D888 Cycles in which the TIQ has 4 or less active entries #193,u,g,n,n,n,u,PM_TIQ_ERAT_MISS_EMB_FULL_RESPIN,A load or store missed in the ERAT and found no space in the EMB. ##000000D08C A load or store missed in the ERAT and found no space in the EMB. #194,u,g,n,n,n,u,PM_EMB_FULL_CYC,Cycles in which the ERAT miss buffer is full. When the ERAT miss buffer is full the operation will go to the TIQ ##000000D88C Cycles in which the ERAT miss buffer is full. When the ERAT miss buffer is full the operation will go to the TIQ #195,u,g,n,n,n,u,PM_LSU_FLUSH_CYC,LSU flushes: includes all LSU flushes. This event only counts one flush per cycle but the hardware can flush up to 5 instructions per cycle. In general, multiple flushes for the same thread get consolidated into a single flush operation. ##000000D090 LSU flushes: includes all LSU flushes. This event only counts one flush per cycle but the hardware can flush up to 5 instructions per cycle. In general, multiple flushes for the same thread get consolidated into a single flush operation. #196,u,g,n,n,n,u,PM_LSU_FLUSH_CI,Load was not initially issued to the LSU as a cache inhibited (non-cacheable) load, but it was later determined to be cache inhibited. ##000000D890 Load was not initially issued to the LSU as a cache inhibited (non-cacheable) load, but it was later determined to be cache inhibited. #197,u,g,n,n,n,u,PM_LSU_FLUSH_ALL_WAYS_LOCKED,Non-speculative stores have locked all ways in the data cache and a newly-issued older store is not able to allocate a way for a given congruence class. ##000000D094 Non-speculative stores have locked all ways in the data cache and a newly-issued older store is not able to allocate a way for a given congruence class. #198,u,g,n,n,n,u,PM_LSU_FLUSH_LHL,If a load hits on an older load of the same address that has been snooped, or two loads of the same thread and address execute out of order and a store of another thread occurs to that address, the younger load will be flushed. The LSU only checks the out-of-orderness of the two loads and ignores the address in detecting this condition. ##000000D894 If a load hits on an older load of the same address that has been snooped, or two loads of the same thread and address execute out of order and a store of another thread occurs to that address, the younger load will be flushed. The LSU only checks the out-of-orderness of the two loads and ignores the address in detecting this condition. #199,u,g,n,n,n,u,PM_LSU_FLUSH_SAME_ICT_GRP,This flush happens if an ICT pair contains a store followed by a load to the same address with at least one byte of overlap between the two. ##000000D098 This flush happens if an ICT pair contains a store followed by a load to the same address with at least one byte of overlap between the two. #200,u,g,n,n,n,u,PM_LSU_REJECT_LHS,Effective Address (EA) alias reject: no EA match but Real Addresses do match. ##000000D898 Effective Address (EA) alias reject: no EA match but Real Addresses do match. #201,u,g,n,n,n,u,PM_LSU_FLUSH_SPECIAL,LSU workaround flush. These flushes are setup with programmable scan-only latches to perform various actions when the flush macro receives a trigger from the debug macros. These actions include things like flushing the next op encountered for a particular thread, or flushing the next op that is the Next To Complete (NTC) op that is encountered on a particular slice. The kind of flush that the workaround is setup to perform is highly variable. ##000000D09C LSU workaround flush. These flushes are setup with programmable scan-only latches to perform various actions when the flush macro receives a trigger from the debug macros. These actions include things like flushing the next op encountered for a particular thread, or flushing the next op that is the Next To Complete (NTC) op that is encountered on a particular slice. The kind of flush that the workaround is setup to perform is highly variable. #202,u,g,n,n,n,u,PM_LSU_FLUSH_SHL,The instruction was flushed because of a sequential load/store consistency issue. If a load or store hits on an older load that has either been snooped (for loads) or has stale data (for stores), a flush will occur. ##000000D89C The instruction was flushed because of a sequential load/store consistency issue. If a load or store hits on an older load that has either been snooped (for loads) or has stale data (for stores), a flush will occur. #203,u,g,n,n,n,u,PM_LSU_FLUSH_SAO,A Load-Hit-Load condition with Strong Address Ordering (SAO) will have address compare disabled and will flush. ##000000D0A0 A Load-Hit-Load condition with Strong Address Ordering (SAO) will have address compare disabled and will flush. #204,u,g,n,n,n,u,PM_LSU_FLUSH_LARX_STCX,A LARX is flushed because an older LARX has an LMQ reservation for the same thread. A STCX is flushed because an older STCX is in the STQ. The flush happens when the older LARX/STCX relaunches ##000000D8A0 A LARX is flushed because an older LARX has an LMQ reservation for the same thread. A STCX is flushed because an older STCX is in the STQ. The flush happens when the older LARX/STCX relaunches #205,u,g,n,n,n,u,PM_LSU_FLUSH_OTHER,Other LSU flushes, including: * Sync - a sync acknowledge from the L2 caused a search of the LRQ for the oldest snooped load. This will either signal a Precise Flush of the oldest snooped load, or a Flush Next PPC. * Data Valid Flush Next - several cases of this, one example is store and reload are lined up such that a store-hit-reload scenario exists and the CDF has already launched and has gotten bad/stale data. * Bad Data Valid (DVAL) Flush Next - might be a few cases of this, one example is a larxa (D-cache hit) return data and DVAL signal, but can't allocate to the LMQ (either the LMQ is full, or some other reason). Already signaled DVAL but can't watch it for snoop_hit_larx. Need to take the “bad dval” back and flush all younger ops). ##000000D0A4 Other LSU flushes, including: * Sync - a sync acknowledge from the L2 caused a search of the LRQ for the oldest snooped load. This will either signal a Precise Flush of the oldest snooped load, or a Flush Next PPC. * Data Valid Flush Next - several cases of this, one example is store and reload are lined up such that a store-hit-reload scenario exists and the CDF has already launched and has gotten bad/stale data. * Bad Data Valid (DVAL) Flush Next - might be a few cases of this, one example is a larxa (D-cache hit) return data and DVAL signal, but can't allocate to the LMQ (either the LMQ is full, or some other reason). Already signaled DVAL but can't watch it for snoop_hit_larx. Need to take the “bad dval” back and flush all younger ops). #206,u,g,n,n,n,u,PM_DC_PREF_HW_ALLOC,Prefetch stream allocated by the hardware prefetch mechanism ##000000D8A4 Prefetch stream allocated by the hardware prefetch mechanism #207,u,g,n,n,n,u,PM_DC_PREF_SW_ALLOC,Prefetch stream allocated by software prefetching ##000000D0A8 Prefetch stream allocated by software prefetching #208,u,g,n,n,n,u,PM_DC_PREF_STRIDED_ALLOC,Strided prefetch stream allocated by either the software or hardware mechanisms ##000000D8A8 Strided prefetch stream allocated by either the software or hardware mechanisms #209,u,g,n,n,n,u,PM_DC_PREF_CONS_ALLOC,Prefetch stream allocated in the conservative phase by either the hardware prefetch mechanism or software prefetch. The sum of this pair subtracted from the total number of allocs will give the total allocs in normal phase ##000000D0AC Prefetch stream allocated in the conservative phase by either the hardware prefetch mechanism or software prefetch. The sum of this pair subtracted from the total number of allocs will give the total allocs in normal phase #210,u,g,n,n,n,u,PM_DC_PREF_XCONS_ALLOC,Prefetch stream allocated in the Ultra conservative phase by either the hardware prefetch mechanism or software prefetch ##000000D8AC Prefetch stream allocated in the Ultra conservative phase by either the hardware prefetch mechanism or software prefetch #211,u,g,n,n,n,u,PM_DC_PREF_CONF,A demand load referenced a line in an active prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. Includes forwards and backwards streams ##000000D0B0 A demand load referenced a line in an active prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. Includes forwards and backwards streams #212,u,g,n,n,n,u,PM_DC_PREF_FUZZY_CONF,A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up) ##000000D8B0 A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up) #213,u,g,n,n,n,u,PM_DC_PREF_STRIDED_CONF,A demand load referenced a line in an active strided prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. ##000000D0B4 A demand load referenced a line in an active strided prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. #214,u,g,n,n,n,u,PM_DC_PREF_DEALLOC_NO_CONF,A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up) ##000000D8B4 A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up) #215,u,g,n,n,n,u,PM_L1_SW_PREF,Software L1 Prefetches, including SW Transient Prefetches ##000000D0B8 Software L1 Prefetches, including SW Transient Prefetches #216,u,g,n,n,n,u,PM_L3_SW_PREF,L3 load prefetch, sourced from a software prefetch stream, was sent to the nest ##000000D0BC L3 load prefetch, sourced from a software prefetch stream, was sent to the nest #217,u,g,n,n,n,u,PM_SNOOP_TLBIE_MY_LPAR_CYC,TLBIE snoops executed in the LSU ##000000F080 TLBIE snoops executed in the LSU #218,u,g,n,n,n,u,PM_SNOOP_TLBIE_CYC,Cycles in which TLBIE snoops are executed in the LSU ##000000F880 Cycles in which TLBIE snoops are executed in the LSU #219,u,g,n,n,n,u,PM_SNOOP_TLBIE_CACHE_WALK_CYC,TLBIE snoop cycles in which the data cache is being walked ##000000F084 TLBIE snoop cycles in which the data cache is being walked #220,u,g,n,n,n,u,PM_SNOOP_TLBIE_WAIT_ST_CYC,TLBIE snoop cycles in which older stores are still draining ##000000F884 TLBIE snoop cycles in which older stores are still draining #221,u,g,n,n,n,u,PM_SNOOP_TLBIE_WAIT_LD_CYC,TLBIE snoop cycles in which older loads are still draining ##000000F088 TLBIE snoop cycles in which older loads are still draining #222,u,g,n,n,n,u,PM_SNOOP_TLBIE_WAIT_IFU_CYC,TLBIE snoop cycles in which the Load-Store unit is waiting for the instruction cache to be walked ##000000F888 TLBIE snoop cycles in which the Load-Store unit is waiting for the instruction cache to be walked #223,u,g,n,n,n,u,PM_SNOOP_TLBIE_WAIT_MMU_CYC,TLBIE snoop cycles in which the Load-Store unit is waiting for the MMU to finish invalidation ##000000F08C TLBIE snoop cycles in which the Load-Store unit is waiting for the MMU to finish invalidation #224,u,g,n,n,n,u,PM_LD0_SETP_HIT_EADIR_MISS,A load in the LD0 execution unit matched the setp Effective Address (EA) hash function for one of the ways in the L1. But the full EA does not match the L1 directory, so the request is sent to the L1 miss pipe. ##000000F094 A load in the LD0 execution unit matched the setp Effective Address (EA) hash function for one of the ways in the L1. But the full EA does not match the L1 directory, so the request is sent to the L1 miss pipe. #225,u,g,n,n,n,u,PM_SAME_EA_DIFF_CTXTAG_RADIR_HIT,A load or store did not get a full Effective Address (EA) plus Context match in the EA directory, so it is sent to the L1 miss pipe. In particular, a full EA match, but a context miss occurred. In the L1 miss pipe, the Real Address (RA) directory lookup finds that the real address is in the L1, but allocated in the EA directory with a different context. ##000000F898 A load or store did not get a full Effective Address (EA) plus Context match in the EA directory, so it is sent to the L1 miss pipe. In particular, a full EA match, but a context miss occurred. In the L1 miss pipe, the Real Address (RA) directory lookup finds that the real address is in the L1, but allocated in the EA directory with a different context. #226,u,g,n,n,n,u,PM_CTXT_MP4_ALLOC,A new entry is created in the 4 entry Context Alias Table due to a load or store that L1 missed due to same EA/different context, but whose Real Address (RA) was found in the L1 during (RA) directory lookup in the miss pipe. ##000000F09C A new entry is created in the 4 entry Context Alias Table due to a load or store that L1 missed due to same EA/different context, but whose Real Address (RA) was found in the L1 during (RA) directory lookup in the miss pipe. #227,u,g,n,n,n,u,PM_CTXT_ALIAS_HIT_CONTRIB,A load or a store in the miss pipe hits in the Real Address (RA) directory and also on one of the 4 entries of the Context Alias Table. The index and way getting an RA directory hit is written with a context alias tag to allow future L1 hits. ##000000F89C A load or a store in the miss pipe hits in the Real Address (RA) directory and also on one of the 4 entries of the Context Alias Table. The index and way getting an RA directory hit is written with a context alias tag to allow future L1 hits. #228,u,g,n,n,n,u,PM_START_NEW_RENAME,Upon creation of a new Context Alias Table entry, a 4k walk is initiated to set the Alias Tag valid for the 31 other congruence classes. The walk is only initiated after it is confirmed that at least 2 other congruence classes detected a context alias situation.  ##000000F0A0 Upon creation of a new Context Alias Table entry, a 4k walk is initiated to set the Alias Tag valid for the 31 other congruence classes. The walk is only initiated after it is confirmed that at least 2 other congruence classes detected a context alias situation.  #229,u,g,n,n,n,u,PM_STORE_ALLOCATE,A store misses the L1 Effective Address (EA) Directory and allocates an L1 index and way with its address for use in tracking the store address in the Load-Store Unit (LSU) during the SRQ lifetime of the store. ##000000F8A0 A store misses the L1 Effective Address (EA) Directory and allocates an L1 index and way with its address for use in tracking the store address in the Load-Store Unit (LSU) during the SRQ lifetime of the store. #230,u,g,n,n,n,u,PM_LOAD_ALLOC_DEPRA_FOR_ALL_WAYS_LOCKED,A load miss allocates an Load Miss Queue (LMQ) entry however it is not able to allocate an L1 index and way for load hazard detection in the LRQ because all 8 ways are locked, either by stores in the SRQ or other loads in the LMQ. The current load is instead marked deprecated. CDF will occur but it will be marked deprecated in the LRQ and ordering hazard checking will be pessimistic. ##000000F0A4 A load miss allocates an Load Miss Queue (LMQ) entry however it is not able to allocate an L1 index and way for load hazard detection in the LRQ because all 8 ways are locked, either by stores in the SRQ or other loads in the LMQ. The current load is instead marked deprecated. CDF will occur but it will be marked deprecated in the LRQ and ordering hazard checking will be pessimistic. #231,u,g,n,n,n,u,PM_STORE_REJECT_FOR_ALL_WAYS_LOCKED,A store misses the L1 Effective Address (EA) Directory, but cannot allocates an L1 index and way with its address due to all 8 ways being locked, either by stores already in the SRQ or by loads in the LMQ. The store is rejected and relaunched immediately. ##000000F8A4 A store misses the L1 Effective Address (EA) Directory, but cannot allocates an L1 index and way with its address due to all 8 ways being locked, either by stores already in the SRQ or by loads in the LMQ. The store is rejected and relaunched immediately. #232,u,g,n,n,n,u,PM_DERAT_HIT_4K,A load or store instruction missed the data cache and hit in the primary ERAT. Page size = 4K ##000000F0B0 A load or store instruction missed the data cache and hit in the primary ERAT. Page size = 4K #233,u,g,n,n,n,u,PM_IERAT_HIT_4K,An instruction fetch missed in the instruction cache and hit in the primary ERAT. Page size = 4k ##000000F8B0 An instruction fetch missed in the instruction cache and hit in the primary ERAT. Page size = 4k #234,u,g,n,n,n,u,PM_DERAT_HIT_64K,A load or store instruction missed the data cache and hit in the primary ERAT. Page size =64k ##000000F0B4 A load or store instruction missed the data cache and hit in the primary ERAT. Page size =64k #235,u,g,n,n,n,u,PM_IERAT_HIT_64K,An instruction fetch missed in the instruction cache and hit in the primary ERAT. Page size = 64k ##000000F8B4 An instruction fetch missed in the instruction cache and hit in the primary ERAT. Page size = 64k #236,u,g,n,n,n,u,PM_DERAT_HIT_2M,A load or store instruction missed the data cache and hit in the primary ERAT. Page size = 2M ##000000F0B8 A load or store instruction missed the data cache and hit in the primary ERAT. Page size = 2M #237,u,g,n,n,n,u,PM_IERAT_HIT_2M,An instruction fetch missed in the instruction cache and hit in the primary ERAT. Page size = 2M ##000000F8B8 An instruction fetch missed in the instruction cache and hit in the primary ERAT. Page size = 2M #238,u,g,n,n,n,u,PM_DERAT_HIT_1G,A load or store instruction missed the data cache and hit in the primary ERAT. Page size = 1G ##000000F0BC A load or store instruction missed the data cache and hit in the primary ERAT. Page size = 1G #239,u,g,n,n,n,u,PM_IERAT_HIT_1G,An instruction fetch missed in the instruction cache and hit in the primary ERAT. Page size = 1G ##000000F8BC An instruction fetch missed in the instruction cache and hit in the primary ERAT. Page size = 1G #240,u,g,n,n,n,u,PM_INST_FROM_L1,An instruction fetch hit in the L1. Each fetch group contains 8 instructions. The same line can hit 4 times if 32 sequential instructions are fetched. ##0000004080 An instruction fetch hit in the L1. Each fetch group contains 8 instructions. The same line can hit 4 times if 32 sequential instructions are fetched. #241,u,g,n,n,n,u,PM_NO_FETCH_BANK_CONFLICT_CYC,Cycles in which no instructions are fetched because of an interleave conflict. The ifar logic will detect an interleave conflict and kill the data that was read that cycle. ##0000004880 Cycles in which no instructions are fetched because of an interleave conflict. The ifar logic will detect an interleave conflict and kill the data that was read that cycle. #242,u,g,n,n,n,u,PM_NO_FETCH_EAT_FULL_CYC,Cycles in which no instructions are fetched because there is no room in EAT ##0000004084 Cycles in which no instructions are fetched because there is no room in EAT #243,u,g,n,n,n,u,PM_NO_FETCH_IBUF_FULL_CYC,Cycles in which no instructions are fetched because there is no room in the instruction buffers ##0000004884 Cycles in which no instructions are fetched because there is no room in the instruction buffers #244,u,g,n,n,n,u,PM_NO_FETCH_THROTTLE_CYC,Cycles in which no instructions are fetched for this thread because it is being throttled ##0000004088 Cycles in which no instructions are fetched for this thread because it is being throttled #245,u,g,n,n,n,u,PM_FETCH_CYC,Cycles in which instructions are successfully fetched from the instruction cache ##0000004888 Cycles in which instructions are successfully fetched from the instruction cache #246,u,g,n,n,n,u,PM_NO_FETCH_THROTTLE_POWMAN_CYC,Cycles in which the thread is throttled because of power management ##000000408C Cycles in which the thread is throttled because of power management #247,u,g,n,n,n,u,PM_NO_FETCH_THROTTLE_OTHER_CYC,Cycles in which the thread is throttled for a reason other than power management, relative priority and dynamic priority. This includes throttles for speculation for power or performance, independently decided by the IFAR ##000000488C Cycles in which the thread is throttled for a reason other than power management, relative priority and dynamic priority. This includes throttles for speculation for power or performance, independently decided by the IFAR #248,u,g,n,n,n,u,PM_NO_FETCH_THROTTLE_REL_PRIO_CYC,Cycles in which the thread is throttled because of relative priority. This is thread arbitration based on the Relative Priority Register (RPR). ##0000004090 Cycles in which the thread is throttled because of relative priority. This is thread arbitration based on the Relative Priority Register (RPR). #249,u,g,n,n,n,u,PM_NO_FETCH_THROTTLE_DYN_PRIO_CYC,Cycles in which the thread is throttled because of dynamic priority. This is the generic thread arbitration without relative thread priority. A thread may also be throttled if an instruction cache reload for a different thread occurs in the same cycle. ##0000004890 Cycles in which the thread is throttled because of dynamic priority. This is the generic thread arbitration without relative thread priority. A thread may also be throttled if an instruction cache reload for a different thread occurs in the same cycle. #250,u,g,n,n,n,u,PM_DECODE_THROTTLE_IIF_CYC,Cycles in which decode was held for a thread due to an Instruction-In-Flight throttle (WOF). This event will increment regardless of other decode holds being present ##0000004894 Cycles in which decode was held for a thread due to an Instruction-In-Flight throttle (WOF). This event will increment regardless of other decode holds being present #251,u,g,n,n,n,u,PM_DECODE_HOLD_NO_ITAGS,Cycles in which the IFU was not able to decode and transmit one or more instructions because all itags were in use. This means the ICT is full for this thread. This event will only increment when no other hold is present. ##0000004098 Cycles in which the IFU was not able to decode and transmit one or more instructions because all itags were in use. This means the ICT is full for this thread. This event will only increment when no other hold is present. #252,u,g,n,n,n,u,PM_DECODE_THROTTLE_IPC_CYC,Cycles in which decode is throttled because M over N throttle is active (WOF). This event will increment regardless of other decode holds being present ##0000004898 Cycles in which decode is throttled because M over N throttle is active (WOF). This event will increment regardless of other decode holds being present #253,u,g,n,n,n,u,PM_IC_INVALIDATE,A line in the instruction cache has been invalidated by an ICBI ##000000409C A line in the instruction cache has been invalidated by an ICBI #254,u,g,n,n,n,u,PM_IC_RELOAD_PRIVATE,An instruction cache line was brought in private for a specific thread. Most lines are brought in shared for all four threads. ##000000489C An instruction cache line was brought in private for a specific thread. Most lines are brought in shared for all four threads. #255,u,g,n,n,n,u,PM_IC_PREF_REQ,Instruction prefetch requests ##00000040A0 Instruction prefetch requests #256,u,g,n,n,n,u,PM_FUSED_BACK_TO_BACK,Back to back two-cycle execution. Counted at decode time ##00000048A0 Back to back two-cycle execution. Counted at decode time #257,u,g,n,n,n,u,PM_FUSED_DESTRUCTIVE,The first and second instruction have the same target register. Counted at decode time ##00000040A4 The first and second instruction have the same target register. Counted at decode time #258,u,g,n,n,n,u,PM_FUSED_RESULT,Two fused PowerPC (PPC set) instructions: the first PPC instruction, in age order, is the result of the second PPC instruction. Counted at decode time. ##00000048A4 Two fused PowerPC (PPC set) instructions: the first PPC instruction, in age order, is the result of the second PPC instruction. Counted at decode time. #259,u,g,n,n,n,u,PM_FUSED_TOGETHER,Produce 2 results together. Ex instruction having a fusable compare: fabs f3,f1 ##00000040A8 Produce 2 results together. Ex instruction having a fusable compare: fabs f3,f1 #260,u,g,n,n,n,u,PM_FUSED_LOADCOMPARE,Fusion of a load and a compare immediate referencing the load's data. Ex: ldx r3,r1,r2 ##00000048A8 Fusion of a load and a compare immediate referencing the load's data. Ex: ldx r3,r1,r2 #261,u,g,n,n,n,u,PM_FUSED_LOAD_LOAD,Fusion of two displacement loads (meeting the requirements for load-load fusion). ##00000040AC Fusion of two displacement loads (meeting the requirements for load-load fusion). #262,u,g,n,n,n,u,PM_BCQ_FULL_CYC,Cycles in which all 12 entries of the BCQ are full ##00000040B0 Cycles in which all 12 entries of the BCQ are full #263,u,g,n,n,n,u,PM_BR_FIN_FROM_BCQ,Branches that were issued with sources not ready (CR=0), counted at finish time. Branches go to the BCQ when their sources are not ready. ##00000048B0 Branches that were issued with sources not ready (CR=0), counted at finish time. Branches go to the BCQ when their sources are not ready. #264,u,g,n,n,n,u,PM_BR_TKN_FIN,A taken branch (conditional or unconditional) finished ##00000040B4 A taken branch (conditional or unconditional) finished #265,u,g,n,n,n,u,PM_BR_TKN_UNCOND_FIN,An unconditional branch finished. All unconditional branches are taken. ##00000048B4 An unconditional branch finished. All unconditional branches are taken. #266,u,g,n,n,n,u,PM_PRED_BR_TKN_COND_DIR,A conditional branch finished with correctly predicted direction. Resolved taken ##00000040B8 A conditional branch finished with correctly predicted direction. Resolved taken #267,u,g,n,n,n,u,PM_PRED_BR_NTKN_COND_DIR,A conditional branch finished with correctly predicted direction. Resolved not taken ##00000048B8 A conditional branch finished with correctly predicted direction. Resolved not taken #268,u,g,n,n,n,u,PM_MPRED_BR_TKN_COND_DIR,A conditional branch finished with mispredicted direction. Resolved taken ##00000040BC A conditional branch finished with mispredicted direction. Resolved taken #269,u,g,n,n,n,u,PM_MPRED_BR_NTKN_COND_DIR,A conditional branch finished with mispredicted direction. Resolved not taken ##00000048BC A conditional branch finished with mispredicted direction. Resolved not taken #270,u,g,n,n,n,u,PM_PRED_BR_TKN_COND_TGT_DIR,A conditional branch finished with correctly predicted target and direction. Resolved taken ##0000005080 A conditional branch finished with correctly predicted target and direction. Resolved taken #271,u,g,n,n,n,u,PM_PRED_BR_NTKN_COND_TGT_DIR,A conditional branch finished with correctly predicted target and direction. Resolved not taken ##0000005880 A conditional branch finished with correctly predicted target and direction. Resolved not taken #272,u,g,n,n,n,u,PM_MPRED_BR_NTKN_COND_TGT_DIR,A conditional branch finished with mispredicted target and direction. Resolved not taken ##0000005884 A conditional branch finished with mispredicted target and direction. Resolved not taken #273,u,g,n,n,n,u,PM_BR_PRED_TKN_COND_DIR_LBHT_LSEL,A conditional branch finished with correctly predicted direction using the Local Branch History Table selected by the local selector. Resolved taken ##0000005088 A conditional branch finished with correctly predicted direction using the Local Branch History Table selected by the local selector. Resolved taken #274,u,g,n,n,n,u,PM_BR_PRED_TKN_COND_DIR_LBHT_GSEL,A conditional branch finished with correctly predicted direction using the Local Branch History Table selected with the global selector. Resolved taken ##0000005888 A conditional branch finished with correctly predicted direction using the Local Branch History Table selected with the global selector. Resolved taken #275,u,g,n,n,n,u,PM_BR_PRED_TKN_COND_DIR_GBHT,A conditional branch finished with correctly predicted direction using the Global Branch History Table. Resolved taken ##000000508C A conditional branch finished with correctly predicted direction using the Global Branch History Table. Resolved taken #276,u,g,n,n,n,u,PM_BR_PRED_TKN_COND_DIR_TAGE,A conditional branch finished with correctly predicted direction using a TAGE override. Resolved taken ##000000588C A conditional branch finished with correctly predicted direction using a TAGE override. Resolved taken #277,u,g,n,n,n,u,PM_BR_PRED_TKN_COND_DIR_TOP,A conditional branch finished with correctly predicted direction using a TOP override to the BHT. Resolved taken ##0000005090 A conditional branch finished with correctly predicted direction using a TOP override to the BHT. Resolved taken #278,u,g,n,n,n,u,PM_BR_PRED_TKN_COND_TGT_COUNT_LCC,A conditional branch finished with correctly predicted target using the local count cache. Resolved taken ##0000005890 A conditional branch finished with correctly predicted target using the local count cache. Resolved taken #279,u,g,n,n,n,u,PM_BR_PRED_TKN_COND_TGT_COUNT_GCC,A conditional branch finished with correctly predicted target using the global count cache. Resolved taken ##0000005094 A conditional branch finished with correctly predicted target using the global count cache. Resolved taken #280,u,g,n,n,n,u,PM_BR_PRED_TKN_COND_TGT_COUNT_TIP,A conditional branch finished with correctly predicted target using the count TIP override to the count cache. Resolved taken ##0000005894 A conditional branch finished with correctly predicted target using the count TIP override to the count cache. Resolved taken #281,u,g,n,n,n,u,PM_BR_PRED_TKN_TGT_LINK,A conditional or unconditional branch finished with correctly predicted target using the Link register (bclr[l]) and predicted by Link Stack (BH(1)=0). Resolved taken ##0000005098 A conditional or unconditional branch finished with correctly predicted target using the Link register (bclr[l]) and predicted by Link Stack (BH(1)=0). Resolved taken #282,u,g,n,n,n,u,PM_BR_PRED_NTKN_COND_DIR_LBHT_LSEL,A conditional branch finished with correctly predicted direction using the Local Branch History Table selected by the local selector. Resolved not taken ##0000005898 A conditional branch finished with correctly predicted direction using the Local Branch History Table selected by the local selector. Resolved not taken #283,u,g,n,n,n,u,PM_BR_PRED_NTKN_COND_DIR_LBHT_GSEL,A conditional branch finished with correctly predicted direction using the Local Branch History Table selected with the global selector. Resolved not taken ##000000509C A conditional branch finished with correctly predicted direction using the Local Branch History Table selected with the global selector. Resolved not taken #284,u,g,n,n,n,u,PM_BR_PRED_NTKN_COND_DIR_GBHT,A conditional branch finished with correctly predicted direction using the Global Branch History Table. Resolved not taken ##000000589C A conditional branch finished with correctly predicted direction using the Global Branch History Table. Resolved not taken #285,u,g,n,n,n,u,PM_BR_PRED_NTKN_COND_DIR_TAGE,A conditional branch finished with correctly predicted direction using a TAGE override. Resolved not taken ##00000050A0 A conditional branch finished with correctly predicted direction using a TAGE override. Resolved not taken #286,u,g,n,n,n,u,PM_BR_PRED_NTKN_COND_DIR_TOP,A conditional branch finished with correctly predicted direction using a TOP override to the BHT. Resolved not taken ##00000058A0 A conditional branch finished with correctly predicted direction using a TOP override to the BHT. Resolved not taken #287,u,g,n,n,n,u,PM_SHL_CREATED,An Store-Hit-Load Table entry was created as a result of an SHL Flush. ##00000050A4 An Store-Hit-Load Table entry was created as a result of an SHL Flush. #288,u,g,n,n,n,u,PM_SHL_ST_DEPENDENCY,A fetched instruction hit in the Store-Hit-Load Table. ##00000058A4 A fetched instruction hit in the Store-Hit-Load Table. #289,u,g,n,n,n,u,PM_IEADIR_HIT_IDIR_MISS,A fetch hit in the IEADIR but missed in the IDIR. This is usually due to IEADIR aliasing, but could be due to an IDIR invalidate that did not invalidate the corresponding IEADIR entry. ##00000050A8 A fetch hit in the IEADIR but missed in the IDIR. This is usually due to IEADIR aliasing, but could be due to an IDIR invalidate that did not invalidate the corresponding IEADIR entry. #290,u,g,n,n,n,u,PM_ICACHE_MISS_DUE_TO_CTXTTAG,A fetch missed the instruction cache due to a context tag miscompare. All other fields matched. This is similar to PM_IEA_TRACKING_TABLE_WRITE but is not restricted to context tags restricted to IEA Sharing and does not require IEA Sharing to be enabled. ##00000058A8 A fetch missed the instruction cache due to a context tag miscompare. All other fields matched. This is similar to PM_IEA_TRACKING_TABLE_WRITE but is not restricted to context tags restricted to IEA Sharing and does not require IEA Sharing to be enabled. #291,u,g,n,n,n,u,PM_BR_MPRED_TKN_COND_DIR_LBHT_LSEL,A conditional branch finished with mispredicted direction using the Local Branch History Table selected by the local selector. Resolved taken ##00000050AC A conditional branch finished with mispredicted direction using the Local Branch History Table selected by the local selector. Resolved taken #292,u,g,n,n,n,u,PM_BR_MPRED_TKN_COND_DIR_LBHT_GSEL,A conditional branch finished with mispredicted direction using the Local Branch History Table selected with the global selector. Resolved taken ##00000058AC A conditional branch finished with mispredicted direction using the Local Branch History Table selected with the global selector. Resolved taken #293,u,g,n,n,n,u,PM_BR_MPRED_TKN_COND_DIR_GBHT,A conditional branch finished with mispredicted direction using the Global Branch History Table. Resolved taken ##00000050B0 A conditional branch finished with mispredicted direction using the Global Branch History Table. Resolved taken #294,u,g,n,n,n,u,PM_BR_MPRED_TKN_COND_DIR_TAGE,A conditional branch finished with mispredicted direction using a TAGE override. Resolved taken ##00000058B0 A conditional branch finished with mispredicted direction using a TAGE override. Resolved taken #295,u,g,n,n,n,u,PM_BR_MPRED_TKN_COND_DIR_TOP,A conditional branch finished with mispredicted direction using a TOP override to the BHT. Resolved taken ##00000050B4 A conditional branch finished with mispredicted direction using a TOP override to the BHT. Resolved taken #296,u,g,n,n,n,u,PM_BR_MPRED_TKN_COND_TGT_COUNT_LCC,A conditional branch finished with mispredicted target using the local count cache. Resolved taken ##00000058B4 A conditional branch finished with mispredicted target using the local count cache. Resolved taken #297,u,g,n,n,n,u,PM_BR_MPRED_TKN_COND_TGT_COUNT_GCC,A conditional branch finished with mispredicted target using the global count cache. Resolved taken ##00000050B8 A conditional branch finished with mispredicted target using the global count cache. Resolved taken #298,u,g,n,n,n,u,PM_BR_MPRED_TKN_COND_TGT_COUNT_TIP,A conditional branch finished with mispredicted target using the count TIP override to the count cache. Resolved taken ##00000058B8 A conditional branch finished with mispredicted target using the count TIP override to the count cache. Resolved taken #299,u,g,n,n,n,u,PM_BR_MPRED_TKN_TGT_LINK,A conditional or unconditional branch finished with mispredicted target using the Link register. Resolved taken ##00000050BC A conditional or unconditional branch finished with mispredicted target using the Link register. Resolved taken #300,u,g,n,n,n,u,PM_BR_MPRED_NTKN_COND_DIR_LBHT_LSEL,A conditional branch finished with mispredicted direction using the Local Branch History Table selected by the local selector. Resolved not taken ##00000058BC A conditional branch finished with mispredicted direction using the Local Branch History Table selected by the local selector. Resolved not taken #301,u,g,n,n,n,u,PM_BR_MPRED_NTKN_COND_DIR_LBHT_GSEL,A conditional branch finished with mispredicted direction using the Local Branch History Table selected with the global selector. Resolved not taken ##000000E080 A conditional branch finished with mispredicted direction using the Local Branch History Table selected with the global selector. Resolved not taken #302,u,g,n,n,n,u,PM_BR_MPRED_NTKN_COND_DIR_GBHT,A conditional branch finished with mispredicted direction using the Global Branch History Table. Resolved not taken ##000000E880 A conditional branch finished with mispredicted direction using the Global Branch History Table. Resolved not taken #303,u,g,n,n,n,u,PM_BR_MPRED_NTKN_COND_DIR_TAGE,A conditional branch finished with mispredicted direction using a TAGE override. Resolved not taken ##000000E084 A conditional branch finished with mispredicted direction using a TAGE override. Resolved not taken #304,u,g,n,n,n,u,PM_BR_MPRED_NTKN_COND_DIR_TOP,A conditional branch finished with mispredicted direction using a TOP override to the BHT. Resolved not taken ##000000E884 A conditional branch finished with mispredicted direction using a TOP override to the BHT. Resolved not taken #305,u,g,n,n,n,u,PM_IEA_ALIAS_TABLE_WRITE,IFU EA Sharing was detected and the sharing info was written to the IFU Alias Table. ##000000E088 IFU EA Sharing was detected and the sharing info was written to the IFU Alias Table. #306,u,g,n,n,n,u,PM_IEA_ALIAS_TABLE_HIT,Instruction cache reload hit on the Alias Table and was written to the ICache as an IEA Shared entry. ##000000E888 Instruction cache reload hit on the Alias Table and was written to the ICache as an IEA Shared entry. #307,u,g,n,n,n,u,PM_IEA_TRACKING_TABLE_WRITE,Instruction cache miss occurred where ICache EA Sharing may be possible. i.e. All IDIR fields matched except the context tag and the incumbent context tag is compatible with IEA Sharing. ##000000E08C Instruction cache miss occurred where ICache EA Sharing may be possible. i.e. All IDIR fields matched except the context tag and the incumbent context tag is compatible with IEA Sharing. #308,u,g,n,n,n,u,PM_IEA_ICACHE_SHARED_HIT,Instruction cache hit occurred on an entry that is marked as IEA Sharing. This does not include ICache reload bypasses. ##000000E88C Instruction cache hit occurred on an entry that is marked as IEA Sharing. This does not include ICache reload bypasses. #309,u,g,n,n,n,u,PM_BR_BTAC_INV_TGT,BTAC predicts a target that is different from what the BHT and count cache predict. The BTAC entry is invalidated. Reported at fetch time ##000000E890 BTAC predicts a target that is different from what the BHT and count cache predict. The BTAC entry is invalidated. Reported at fetch time #310,u,g,n,n,n,u,PM_BR_BTAC_INV_DIR,BTAC predicts taken for a branch that the BHT predicts not taken, so that BTAC entry is invalidated. Reported at fetch time ##000000E094 BTAC predicts taken for a branch that the BHT predicts not taken, so that BTAC entry is invalidated. Reported at fetch time #311,u,g,n,n,n,u,PM_BR_PRED_COND_BTAC,A conditional branch finished with correctly predicted target or direction using the BTAC. Reported at fetch time ##000000E894 A conditional branch finished with correctly predicted target or direction using the BTAC. Reported at fetch time #312,u,g,n,n,n,u,PM_MPRED_BR_FIN,A conditional branch mispredicted its direction or target address. Counted at finish time ##000000E098 A conditional branch mispredicted its direction or target address. Counted at finish time #313,u,g,n,n,n,u,PM_BR_PRED_TKN_SWHINT,A software hinted branch finished and the branch resolved taken and the hint was correct. ##000000E898 A software hinted branch finished and the branch resolved taken and the hint was correct. #314,u,g,n,n,n,u,PM_BR_PRED_NTKN_SWHINT,A software hinted branch finished and the branch resolved not taken and the hint was correct. ##000000E09C A software hinted branch finished and the branch resolved not taken and the hint was correct. #315,u,g,n,n,n,u,PM_BR_MPRED_TKN_SWHINT,A software hinted branch finished and the branch resolved taken and the hint was incorrect. ##000000E89C A software hinted branch finished and the branch resolved taken and the hint was incorrect. #316,u,g,n,n,n,u,PM_BR_MPRED_NTKN_SWHINT,A software hinted branch finished and the branch resolved not taken and the hint was incorrect. ##000000E0A0 A software hinted branch finished and the branch resolved not taken and the hint was incorrect. #317,u,g,n,n,n,u,PM_BACK_BRANCH,Branch whose target address is lower than the program counter ##000000E0A4 Branch whose target address is lower than the program counter #318,u,g,n,n,n,u,PM_TLB_ACCESS_L3PREF,Incoming L3 prefetches that access the TLB (there is no L3 instruction prefetching in POWER10). L3 prefetches access the TLB directly, without accessing the ERAT ##0000008080 Incoming L3 prefetches that access the TLB (there is no L3 instruction prefetching in POWER10). L3 prefetches access the TLB directly, without accessing the ERAT #319,u,g,n,n,n,u,PM_TLB_CHILD_PURGE_CYC,Cycles spent in a TLB scrub. Counted for radix or HPT translations. Implies a parent eviction ##0000008880 Cycles spent in a TLB scrub. Counted for radix or HPT translations. Implies a parent eviction #320,u,g,n,n,n,u,PM_REJ_MMU,The MMU rejects a translation for any reason. This includes loads/stores/ifetches. ##0000008884 The MMU rejects a translation for any reason. This includes loads/stores/ifetches. #321,u,g,n,n,n,u,PM_REJ_EXEC_NTC_SLEEP_SELECT,The operation is rejected because it must be NTC to translate. This includes loads/stores/ifetches. ##0000008088 The operation is rejected because it must be NTC to translate. This includes loads/stores/ifetches. #322,u,g,n,n,n,u,PM_RDXWALK_INSTR_CYC,Cycles when an instruction(MMU type fetch) tablewalk is active. ##000000808C Cycles when an instruction(MMU type fetch) tablewalk is active. #323,u,g,n,n,n,u,PM_RDXWALK_DATA_CYC,Data Tablewalk Cycles. Cycles in which at least one tablewalk is in progress. This event includes data, demand and prefetch(MMU type LD, ST, L1 Prefetch). There can be up to 4 tablewalks in one cycle. ##000000888C Data Tablewalk Cycles. Cycles in which at least one tablewalk is in progress. This event includes data, demand and prefetch(MMU type LD, ST, L1 Prefetch). There can be up to 4 tablewalks in one cycle. #324,u,g,n,n,n,u,PM_REJ_TABLEWALK_L2_PDE_MERGE,A translation is rejected on a level 2 PDE boundary. This is only valid for radix. This is when the incoming translation matches on the 1G address boundary, but not a 2M address boundary. ##0000008090 A translation is rejected on a level 2 PDE boundary. This is only valid for radix. This is when the incoming translation matches on the 1G address boundary, but not a 2M address boundary. #325,u,g,n,n,n,u,PM_REJ_TABLEWALK_L3_PDE_MERGE,A translation is rejected on a level 3 PDE boundary. This is when the incoming translation matches on the 2M address boundary, but not the 64k address boundary. This is only valid in radix translations. ##0000008890 A translation is rejected on a level 3 PDE boundary. This is when the incoming translation matches on the 2M address boundary, but not the 64k address boundary. This is only valid in radix translations. #326,u,g,n,n,n,u,PM_REJ_TABLEWALK_PTE_MERGE,A translation is rejected on a PTE boundary. This indicates that the table walk merged due to a full 4k or 64k address match. This is valid for both Radix and HPT. In HPT this is both the parent hit, child miss case, and the parent miss case. ##0000008094 A translation is rejected on a PTE boundary. This indicates that the table walk merged due to a full 4k or 64k address match. This is valid for both Radix and HPT. In HPT this is both the parent hit, child miss case, and the parent miss case. #327,u,g,n,n,m,u,PM_MRK_DTABLEWALK_CYC,Cycles a data(MMU type LD, ST, L1 PF) tablewalk is in progress for a marked instruction. ##0000008894 Cycles a data(MMU type LD, ST, L1 PF) tablewalk is in progress for a marked instruction. #328,u,g,n,n,n,u,PM_XLATE_HPT_MODE_CYC,MMU reports every cycle the thread is in HPT translation mode (as opposed to radix mode) ##0000008098 MMU reports every cycle the thread is in HPT translation mode (as opposed to radix mode) #329,u,g,n,n,n,u,PM_XLATE_RADIX_MODE_CYC,MMU reports every cycle the thread is in radix translation mode (as opposed to HPT mode) ##0000008898 MMU reports every cycle the thread is in radix translation mode (as opposed to HPT mode) #330,u,g,n,n,n,u,PM_XLATE_L2_REQ,The MMU requested a line from L2 for translation. It may be satisfied from L2 and beyond. Includes speculative instructions. Includes instruction, prefetch and demand. ##000000809C The MMU requested a line from L2 for translation. It may be satisfied from L2 and beyond. Includes speculative instructions. Includes instruction, prefetch and demand. #331,u,g,n,n,n,u,PM_RDXTLB_ANY_NSTD_ANY_HST_HIT,Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup. If this event increments, one and only one of the following must also increment: PM_RDXTLB_ANY_NSTD_64K_HST_HIT, PM_RDXTLB_ANY_NSTD_2M_HST_HIT, or PM_RDXTLB_ANY_NSTD_1G_HST_HIT ##00000080A0 Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup. If this event increments, one and only one of the following must also increment: PM_RDXTLB_ANY_NSTD_64K_HST_HIT, PM_RDXTLB_ANY_NSTD_2M_HST_HIT, or PM_RDXTLB_ANY_NSTD_1G_HST_HIT #332,u,g,n,n,n,u,PM_RDXTLB_ANY_NSTD_4K_HST_HIT,Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup w/ the 4K page size. Due to P10 microarchitecture, this event will never increment. ##00000088A0 Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup w/ the 4K page size. Due to P10 microarchitecture, this event will never increment. #333,u,g,n,n,n,u,PM_RDXTLB_ANY_NSTD_64K_HST_HIT,Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup w/ the 64K page size. ##00000080A4 Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup w/ the 64K page size. #334,u,g,n,n,n,u,PM_RDXTLB_ANY_NSTD_2M_HST_HIT,Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup w/ the 2M page size. ##00000088A4 Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup w/ the 2M page size. #335,u,g,n,n,n,u,PM_RDXTLB_ANY_NSTD_1G_HST_HIT,Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup w/ the 1G page size. ##00000080A8 Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup w/ the 1G page size. #336,u,g,n,n,n,u,PM_RDXTLB_ANY_NSTD_ACC,Qualified as nested radix translations. There was a TLB lookup for any nested radix partition scoped translation. ##00000088A8 Qualified as nested radix translations. There was a TLB lookup for any nested radix partition scoped translation. #337,u,g,n,n,n,u,PM_RDXTLB_ANY_NSTD_MISS,Qualified as nested radix translations. There was a complete TLB miss on any intermediate TLB lookup. ##00000080AC Qualified as nested radix translations. There was a complete TLB miss on any intermediate TLB lookup. #338,u,g,n,n,n,u,PM_SNOOP_TLBIE_ARB_CYC,Cycles the MMU is in the process of arbitrating an incoming TLBIE snoop, but the snoop has not yet acquired the MML lock. ##0000009080 Cycles the MMU is in the process of arbitrating an incoming TLBIE snoop, but the snoop has not yet acquired the MML lock. #339,u,g,n,n,n,u,PM_SNOOP_TLBIE_TLB_INV_CYC,Cycles the MMU is in the process of walking the TLB for a TLBIE. From the time the probe is installed to the time the probe is uninstalled. ##0000009880 Cycles the MMU is in the process of walking the TLB for a TLBIE. From the time the probe is installed to the time the probe is uninstalled. #340,u,g,n,n,n,u,PM_SNOOP_TLBIE_NOT_MY_LPAR_CONTEXT_TABLE_HIT_CYC,Total duration of the snoop TLBIE when there is a context table hit, but a not-my-lpar (LSU is counting my-lpar case). ##0000009084 Total duration of the snoop TLBIE when there is a context table hit, but a not-my-lpar (LSU is counting my-lpar case). #341,u,g,n,n,n,u,PM_SNOOP_TLBIE_NOT_MY_LPAR_CONTEXT_TABLE_MISS_CYC,Total duration of the snoop TLBIE when there is a context table miss. ##0000009884 Total duration of the snoop TLBIE when there is a context table miss. #342,u,g,n,n,n,u,PM_SNOOP_TLBIE,Total number of TLBIE snoops ##0000009088 Total number of TLBIE snoops #343,u,g,n,n,n,u,PM_DTLB_ACCESS_ERAT_MISS,The TLB was read to satisfy a load or store ERAT miss. This includes demands and L1 prefetching data(MMU type LD, ST, L1PF) ##000000908C The TLB was read to satisfy a load or store ERAT miss. This includes demands and L1 prefetching data(MMU type LD, ST, L1PF) #344,u,g,n,n,n,u,PM_ITLB_ACCESS_ERAT_MISS,The TLB was read to satisfy an instruction ERAT miss. This includes demands and L1 prefetching for instruction (MMU Type Fetch) ##000000988C The TLB was read to satisfy an instruction ERAT miss. This includes demands and L1 prefetching for instruction (MMU Type Fetch) #345,u,g,n,n,n,u,PM_HPTWALK_INSTR_CYC,Cycles when an instruction tablewalk is active. This is qualified for HPT translations. ##0000009090 Cycles when an instruction tablewalk is active. This is qualified for HPT translations. #346,u,g,n,n,n,u,PM_HPTWALK_DATA_CYC,Data Tablewalk Cycles. Cycles in which at least one tablewalk is in progress. This event includes data and instruction, demand and prefetch. There can be up to 4 tablewalks in one cycle. (MMU Type LD, ST, L1PF) ##0000009890 Data Tablewalk Cycles. Cycles in which at least one tablewalk is in progress. This event includes data and instruction, demand and prefetch. There can be up to 4 tablewalks in one cycle. (MMU Type LD, ST, L1PF) #347,u,g,n,n,n,u,PM_REJ_PROBE_MATCH_PRS0,A load/store, fetch, or prefetch was rejected because it matched on a partition scoped probe. This is set for both Radix and HPT ##0000009094 A load/store, fetch, or prefetch was rejected because it matched on a partition scoped probe. This is set for both Radix and HPT #348,u,g,n,n,n,u,PM_REJ_PROBE_MATCH_PRS1,A load/store, fetch, or prefetch was rejected because it matched on a process scoped probe. This is Radix only ##0000009894 A load/store, fetch, or prefetch was rejected because it matched on a process scoped probe. This is Radix only #349,u,g,n,n,n,u,PM_REJ_PROBE_MATCH_MML,A load/store, fetch, or prefetch was rejected because it matched on the MML lock. This is set for both Radix and HPT ##0000009098 A load/store, fetch, or prefetch was rejected because it matched on the MML lock. This is set for both Radix and HPT #350,u,g,n,n,n,u,PM_REJ_PIPE_COLLISION_2ND_RELOAD,A load/store or fetch was rejected because there was a collision in the MMU pipeline with a 2nd pass & a reload. ##0000009898 A load/store or fetch was rejected because there was a collision in the MMU pipeline with a 2nd pass & a reload. #351,u,g,n,n,n,u,PM_REJ_XMQ_FULL,A translation was rejected because the MMU was full. ##000000909C A translation was rejected because the MMU was full. #352,u,g,n,n,n,u,PM_BLOCK_ERAT_WRITE,A valid translation reloaded the ERAT with block write enabled. ##000000989C A valid translation reloaded the ERAT with block write enabled. #353,u,g,n,n,n,u,PM_2ND_PASS_RADIX,The 2nd pass for Radix was initiated. ##00000090A0 The 2nd pass for Radix was initiated. #354,u,g,n,n,n,u,PM_2ND_PASS_HPT,The 2nd pass for HPT was initiated. This doesn't include VA hash mispredicts. ##00000098A0 The 2nd pass for HPT was initiated. This doesn't include VA hash mispredicts. #355,u,g,n,n,n,u,PM_VA_HASH_MPRED,The 1st pass for HPT was rejected due to VA hash mispredicts. ##00000090A4 The 1st pass for HPT was rejected due to VA hash mispredicts. #356,u,g,n,n,n,u,PM_CHILD_PURGE_HIT,Total amount of congruence classes that found at least 1 invalidation match for a child purge. ##000000A080 Total amount of congruence classes that found at least 1 invalidation match for a child purge. #357,u,g,n,n,n,u,PM_TLBIE_INV_CC_PRS0_COMPOSITE_CHILD_HASH,Congruence classes that found at least 1 invalidation match for a partition scoped hash match. ##000000A084 Congruence classes that found at least 1 invalidation match for a partition scoped hash match. #358,u,g,n,n,n,u,PM_TLBIE_INV_CC_PRS0_COMPOSITE_PARENT_HASH,Congruence classes that found at least 1 invalidation match for a partition scoped parent hash match. ##000000A884 Congruence classes that found at least 1 invalidation match for a partition scoped parent hash match. #359,u,g,n,n,n,u,PM_TLBIE_INV_ATTEMPT_CC_PRS0_COMPOSITE_CHILD,A partition scoped child hash invalidation was sent to the TLB. ##000000A088 A partition scoped child hash invalidation was sent to the TLB. #360,u,g,n,n,n,u,PM_TLBIE_INV_ATTEMPT_CC_PRS0_COMPOSITE_PARENT,A partition scoped parent hash invalidation was sent to the TLB. ##000000A888 A partition scoped parent hash invalidation was sent to the TLB. #361,u,g,n,n,n,u,PM_TLBIE_INV_ATTEMPT_HPT_PRECISE,Precise TLBIES sent to TLB in HPT. ##000000A08C Precise TLBIES sent to TLB in HPT. #362,u,g,n,n,n,u,PM_TLBIE_INV_CC_HPT_PRECISE,Precise TLBIEs sent to TLB for HPT invalidations and had at least 1 matching entry in the congruence class. ##000000A88C Precise TLBIEs sent to TLB for HPT invalidations and had at least 1 matching entry in the congruence class. #363,u,g,n,n,n,u,PM_CASE_A_HIT_MTPID,mtpid instruction found a Case A Context Table Hit. ##000000A090 mtpid instruction found a Case A Context Table Hit. #364,u,g,n,n,n,u,PM_CASE_A_HIT_MTLPID,mtlpid instruction found a Case A Context Table Hit. ##000000A890 mtlpid instruction found a Case A Context Table Hit. #365,u,g,n,n,n,u,PM_CASE_B_HIT_MTLPID,A mtlpid instruction found a Case B Context table hit. ##000000A094 A mtlpid instruction found a Case B Context table hit. #366,u,g,n,n,n,u,PM_CASE_C_HIT_MTPID,A mtpid instruction found a Case C Context table hit. ##000000A894 A mtpid instruction found a Case C Context table hit. #367,u,g,n,n,n,u,PM_CASE_A_MISS_MTPID,A mtpid instruction found a Case A context table miss ##000000A098 A mtpid instruction found a Case A context table miss #368,u,g,n,n,n,u,PM_CASE_A_MISS_MTLPID,A mtlpid instruction found a Case A Context table miss ##000000A898 A mtlpid instruction found a Case A Context table miss #369,u,g,n,n,n,u,PM_CASE_B_MISS_MTLPID,A mtlpid instruction found a Case B Context table miss ##000000A09C A mtlpid instruction found a Case B Context table miss #370,u,g,n,n,n,u,PM_CASE_C_MISS_MTPID,A mtpid instruction found a Case C Context table miss. ##000000A89C A mtpid instruction found a Case C Context table miss. #371,u,g,n,n,n,u,PM_MTPID,The thread executed a mtpid instruction. ##000000A0A0 The thread executed a mtpid instruction. #372,u,g,n,n,n,u,PM_MTLPID,The thread executed a mtlpid instruction. ##000000A8A0 The thread executed a mtlpid instruction. #373,u,g,n,n,n,u,PM_CASE_A_SNOOP_TLBIE_HIT,A snoop hit on a Case A context tag. ##000000A0A4 A snoop hit on a Case A context tag. #374,u,g,n,n,n,u,PM_CASE_B_SNOOP_TLBIE_HIT,A snoop hit on a Case B Context tag. ##000000A8A4 A snoop hit on a Case B Context tag. #375,u,g,n,n,n,u,PM_CASE_C_SNOOP_TLBIE_HIT,A snoop hit on a Case C context tag. ##000000A0A8 A snoop hit on a Case C context tag. #376,u,g,n,n,n,u,PM_CASE_D_SNOOP_TLBIE_HIT,A snoop hit on a Case D context tag. ##000000A8A8 A snoop hit on a Case D context tag. #377,u,g,n,n,n,u,PM_SNOOP_TLBIE_NOT_MY_LPAR_CONTEXT_TABLE_HIT,A snoop found a not-my-lpar but found a context table hit. ##000000A0AC A snoop found a not-my-lpar but found a context table hit. #378,u,g,n,n,n,u,PM_SNOOP_TLBIE_NOT_MY_LPAR_CONTEXT_TABLE_MISS,A snoop found a not-my-lpar but found a context table miss. ##000000A8AC A snoop found a not-my-lpar but found a context table miss. #379,u,g,n,n,n,u,PM_LPAR_SNOOP_HIT,A snoop found a "my-lpar" match. ##000000A0B0 A snoop found a "my-lpar" match. #380,u,g,n,n,n,u,PM_L3_PF_ON_CHIP_CACHE,L3 PF from on-chip cache. L3PF successfully read data and that data came from an on-chip cache. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##100000036080 L3 PF from on-chip cache. L3PF successfully read data and that data came from an on-chip cache. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #381,u,g,n,n,n,u,PM_L3_PF_OFF_CHIP_CACHE,L3 PF from off-chip cache. L3PF successfully read data and that data came from an off-chip cache. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##100000036880 L3 PF from off-chip cache. L3PF successfully read data and that data came from an off-chip cache. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #382,u,g,n,n,n,u,PM_L3_L2_CO_HIT,L2 CO hits L3. L3 inserted a line due to an L2 castout and the line was already in the L3 (a "hit"). PM_L3_CI_HIT also increments when this does. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##110000036080 L2 CO hits L3. L3 inserted a line due to an L2 castout and the line was already in the L3 (a "hit"). PM_L3_CI_HIT also increments when this does. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #383,u,g,n,n,n,u,PM_L3_L2_CO_MISS,L2 CO misses L3. L3 inserted a line due to an L2 castout and the line was new to the L3 (a "miss"). PM_L3_CI_MISS also increments when this does. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##110000036880 L2 CO misses L3. L3 inserted a line due to an L2 castout and the line was new to the L3 (a "miss"). PM_L3_CI_MISS also increments when this does. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #384,u,g,n,n,n,u,PM_L3_CO_LCO,Incoming LCOs that cause L3 castouts. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##120000036080 Incoming LCOs that cause L3 castouts. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #385,u,g,n,n,n,u,PM_L3_CINJ,L3 castin of cache inject. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##120000036880 L3 castin of cache inject. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #386,u,g,n,n,n,u,PM_SNP_TM_HIT_M,TM snoop that is a store hits line in L3 in M or Mu state (exclusive modified). Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##130000036080 TM snoop that is a store hits line in L3 in M or Mu state (exclusive modified). Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #387,u,g,n,n,n,u,PM_SNP_TM_HIT_T,TM snoop that is a store hits line in L3 in T, Tn or Te state (shared modified). Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##130000036880 TM snoop that is a store hits line in L3 in T, Tn or Te state (shared modified). Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #388,u,g,n,n,n,u,PM_L3_CO,L3 castout occurred (does not include casthrough). Counts L3 castout dispatches, thus includes castout requests that are subsequently dropped, such as CP_Me. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##140000036080 L3 castout occurred (does not include casthrough). Counts L3 castout dispatches, thus includes castout requests that are subsequently dropped, such as CP_Me. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #389,u,g,n,n,n,u,PM_SN_INVL,Snoop of L3 on detects a store to a line in the Sx state and invalidates the line. Lossy - increments only once for all such snoops that occur on the same cycle. Up to 4 can happen in a cycle but only one increment occurs. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##140000036880 Snoop of L3 on detects a store to a line in the Sx state and invalidates the line. Lossy - increments only once for all such snoops that occur on the same cycle. Up to 4 can happen in a cycle but only one increment occurs. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #390,u,g,n,n,n,u,PM_L3_P0_CO_MEM,L3 CO to memory from L3 CO machine 0-7. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##150000036080 L3 CO to memory from L3 CO machine 0-7. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #391,u,g,n,n,n,u,PM_L3_P1_CO_MEM,L3 CO to memory from L3 CO machine 8-15.Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##150000036880 L3 CO to memory from L3 CO machine 8-15.Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #392,u,g,n,n,n,u,PM_L3_SN0_BUSY,Lifetime, sample of snooper machine 0 valid. Increments when L3 snoop machine 0 is valid. Can increment on the same clock as PM_L3_SN_USAGE. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##160000036080 Lifetime, sample of snooper machine 0 valid. Increments when L3 snoop machine 0 is valid. Can increment on the same clock as PM_L3_SN_USAGE. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #393,u,g,n,n,n,u,PM_L3_CO0_BUSY,Lifetime, sample of CO machine 0 valid. Increments when L3 CO machine 0 is valid. Can increment on the same clock as PM_L3_CI_USAGE. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##160000036880 Lifetime, sample of CO machine 0 valid. Increments when L3 CO machine 0 is valid. Can increment on the same clock as PM_L3_CI_USAGE. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #394,u,g,n,n,n,u,PM_L3_P0_CO_RTY,L3 CO received retry on fabric CRESP port 0 (memory only), every retry counted. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##170000036080 L3 CO received retry on fabric CRESP port 0 (memory only), every retry counted. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #395,u,g,n,n,n,u,PM_L3_P1_CO_RTY,L3 CO received retry on fabric CRESP port 1 (memory only), every retry counted. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##170000036880 L3 CO received retry on fabric CRESP port 1 (memory only), every retry counted. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #396,u,g,n,n,n,u,PM_L3_P0_SYS_PUMP,L3 PF sent with sys vg or rn scope from PF machine 0-23, counts even retried requests. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##180000036080 L3 PF sent with sys vg or rn scope from PF machine 0-23, counts even retried requests. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #397,u,g,n,n,n,u,PM_L3_P1_SYS_PUMP,L3 PF sent with sys vg or rn scope from PF machine 24-47, counts even retried requests. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##180000036880 L3 PF sent with sys vg or rn scope from PF machine 24-47, counts even retried requests. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #398,u,g,n,n,n,u,PM_L3_GRP_GUESS_WRONG_LOW,L3 Prefetch scope predictor selected GS or NNS, but was wrong because scope was LNS. Increments when data received for L3 PF machine 0 or 24. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##190000036080 L3 Prefetch scope predictor selected GS or NNS, but was wrong because scope was LNS. Increments when data received for L3 PF machine 0 or 24. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #399,u,g,n,n,n,u,PM_L3_GRP_GUESS_WRONG_HIGH,L3 Prefetch scope predictor selected GS or NNS, but was wrong because scope was VGS or RNS. Increments when data received for L3 PF machine 0 or 24. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##190000036880 L3 Prefetch scope predictor selected GS or NNS, but was wrong because scope was VGS or RNS. Increments when data received for L3 PF machine 0 or 24. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #400,u,g,n,n,n,u,PM_L3_PF0_BUSY,Lifetime, sample of L3 PF machine 0 busy. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##1A0000036080 Lifetime, sample of L3 PF machine 0 busy. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #401,u,g,n,n,n,u,PM_L3_RD0_BUSY,Lifetime, sample of L3 RD machine 0 busy. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##1A0000036880 Lifetime, sample of L3 RD machine 0 busy. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #402,u,g,n,n,n,u,PM_L3_PF_MPRED_DUALMCDATA,L3 prefetch request predicted dual MC data but a cache responded (bad prediction). Lossy - increments only once when multiple L3PF's receive CRESP=good simultaneously, thus may undercount. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##1B0000036080 L3 prefetch request predicted dual MC data but a cache responded (bad prediction). Lossy - increments only once when multiple L3PF's receive CRESP=good simultaneously, thus may undercount. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #403,u,g,n,n,n,u,PM_L3_CO_L31_INST_XLAT,L3 cast out an instruction or translation line to a neighbor L3 (LCO). Lossy - increments only once when multiple L3CO's receive CRESP=good simultaneously, thus may undercount. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##1B0000036880 L3 cast out an instruction or translation line to a neighbor L3 (LCO). Lossy - increments only once when multiple L3CO's receive CRESP=good simultaneously, thus may undercount. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #404,u,g,n,n,n,u,PM_L2_INST,All successful I-side-instruction-fetch (e.g. i-demand, i-prefetch) dispatches for this thread. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##000000036080 All successful I-side-instruction-fetch (e.g. i-demand, i-prefetch) dispatches for this thread. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #405,u,g,n,n,n,u,PM_L2_INST_MISS,All successful instruction (demand and prefetch) dispatches for this thread that missed in the L2. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##000000036880 All successful instruction (demand and prefetch) dispatches for this thread that missed in the L2. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #406,u,g,n,n,n,u,PM_L2_ISIDE_DSIDE,All successful D-side-Ld or I-side-instruction-fetch dispatches for this thread. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##010000036080 All successful D-side-Ld or I-side-instruction-fetch dispatches for this thread. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #407,u,g,n,n,n,u,PM_L2_ISIDE_DSIDE_HIT,All successful D-side-Ld or I-side-instruction-fetch dispatches for this thread that were L2 hits. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##010000036880 All successful D-side-Ld or I-side-instruction-fetch dispatches for this thread that were L2 hits. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #408,u,g,n,n,n,u,PM_L2_ST_ATTEMPT,All D-side store dispatch attempts for this thread. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##020000036080 All D-side store dispatch attempts for this thread. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #409,u,g,n,n,n,u,PM_L2_ST_DISP_FAIL_ADDR,All D-side store dispatch attempts for this thread that failed due to address collision with L2 machine already working on this line (e.g. ld-hit-stq or Read-claim/Castout/Snoop machines). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##020000036880 All D-side store dispatch attempts for this thread that failed due to address collision with L2 machine already working on this line (e.g. ld-hit-stq or Read-claim/Castout/Snoop machines). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #410,u,g,n,n,n,u,PM_L2_RC_ST_DONE,Read-claim machine did store to line that was in Tx or Sx (Tagged or Shared state). Since the event is time-sliced across all 4 threads, the event count should be multiplied by 4. ##030000036080 Read-claim machine did store to line that was in Tx or Sx (Tagged or Shared state). Since the event is time-sliced across all 4 threads, the event count should be multiplied by 4. #411,u,g,n,n,n,u,PM_L2_SN_SX_I_DONE,Snoop dispatched and went from Sx to Ix. Since the event is time-sliced across all 4 threads, the event count should be multiplied by 4. ##030000036880 Snoop dispatched and went from Sx to Ix. Since the event is time-sliced across all 4 threads, the event count should be multiplied by 4. #412,u,g,n,n,n,u,PM_L2_SYS_GUESS_CORRECT,L2 guess system (VGS or RNS) and guess was correct (ie data beyond-group). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##040000036080 L2 guess system (VGS or RNS) and guess was correct (ie data beyond-group). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #413,u,g,n,n,n,u,PM_L2_SYS_GUESS_WRONG,L2 guess system (VGS or RNS) and guess was not correct (ie data ^beyond-group). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##040000036880 L2 guess system (VGS or RNS) and guess was not correct (ie data ^beyond-group). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #414,u,g,n,n,n,u,PM_L2_RTY_ST,RC retries on Power Bus for any store from core (excludes DCBFs). Since the event is time-sliced across all 4 threads, the event count should be multiplied by 4. ##050000036080 RC retries on Power Bus for any store from core (excludes DCBFs). Since the event is time-sliced across all 4 threads, the event count should be multiplied by 4. #415,u,g,n,n,n,u,PM_L2_RTY_LD,RC retries on Power Bus for any load from core (excludes DCBFs). Since the event is time-sliced across all 4 threads, the event count should be multiplied by 4. ##050000036880 RC retries on Power Bus for any load from core (excludes DCBFs). Since the event is time-sliced across all 4 threads, the event count should be multiplied by 4. #416,u,g,n,n,n,u,PM_L2_CO0_BUSY,CO mach 0 Busy. Used by PMU to sample ave CO lifetime (mach0 used as sample point). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##060000036080 CO mach 0 Busy. Used by PMU to sample ave CO lifetime (mach0 used as sample point). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #417,u,g,n,n,n,u,PM_L2_SN_USAGE,Continuous 16 cycle (2to1) window where this signals rotates thru sampling each SN machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##060000036880 Continuous 16 cycle (2to1) window where this signals rotates thru sampling each SN machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #418,u,g,n,n,n,u,PM_TM_ST_FAIL,TM Store (fav or non-fav) ran into conflict (failed). Event count should be multiplied by 2 since the data is coming from a 2:1 clock domain and the data is time sliced across all 4 threads. ##070000036080 TM Store (fav or non-fav) ran into conflict (failed). Event count should be multiplied by 2 since the data is coming from a 2:1 clock domain and the data is time sliced across all 4 threads. #419,u,g,n,n,n,u,PM_TM_ST_CAUSED_FAIL,TM Store (fav or non-fav) caused another thread to fail. Event count should be multiplied by 2 since the data is coming from a 2:1 clock domain and the data is time sliced across all 4 threads. ##070000036880 TM Store (fav or non-fav) caused another thread to fail. Event count should be multiplied by 2 since the data is coming from a 2:1 clock domain and the data is time sliced across all 4 threads. #420,u,g,n,n,n,u,PM_L2_DSIDE_READ,Valid when first beat of data comes in for an d-side fetch where data came exclusively from mem(or L4)(ie total memory accesses by RCs). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##080000036080 Valid when first beat of data comes in for an d-side fetch where data came exclusively from mem(or L4)(ie total memory accesses by RCs). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #421,u,g,n,n,n,u,PM_DUALMCDATA_REQ_USE_LPC_DATA,The L2 RC machine made a dualmcdata request to the PowerBus and the RC was sent LPC data that was usable. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##080000036880 The L2 RC machine made a dualmcdata request to the PowerBus and the RC was sent LPC data that was usable. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #422,u,g,n,n,n,u,PM_L2_RC_CACHE_READ,RC cache read request. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##090000036080 RC cache read request. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #423,u,g,n,n,n,u,PM_L2_TM_FOOTPR_OVERFLOW_LD_MULTI,Multiple TM threads were running and Load footprint was lost due to capacity Cast Out or full TMDIR/LVDIR. Event count should be multiplied by 2 since the data is coming from a 2:1 clock domain and the data is time sliced across all 4 threads. ##0A0000036080 Multiple TM threads were running and Load footprint was lost due to capacity Cast Out or full TMDIR/LVDIR. Event count should be multiplied by 2 since the data is coming from a 2:1 clock domain and the data is time sliced across all 4 threads. #424,u,g,n,n,n,u,PM_L2_TM_FOOTPR_ST_LINES,TM count of total Store Footprint Cachelines formed. Divide this by PM_L2_TM_END to get average Store footprint size. Counts stop when thread gets DeadThreadWalking for two reasons: 1) once a thread TM Overflows, each Ld/St attempt would otherwise inflate this cnt 2) useful to get size cap size of footprint at point transaction first failed(ie Overflow fails)to get a sense of if other threads were present Event count should be multiplied by 2 since the data is coming from a 2:1 clock domain and the data is time sliced across all 4 threads. ##0A0000036880 TM count of total Store Footprint Cachelines formed. Divide this by PM_L2_TM_END to get average Store footprint size. Counts stop when thread gets DeadThreadWalking for two reasons: 1) once a thread TM Overflows, each Ld/St attempt would otherwise inflate this cnt 2) useful to get size cap size of footprint at point transaction first failed(ie Overflow fails)to get a sense of if other threads were present Event count should be multiplied by 2 since the data is coming from a 2:1 clock domain and the data is time sliced across all 4 threads. #425,u,g,n,n,n,u,PM_NCU_SNP_TLBIE_CYC,Cycles in which the NCU had a TLBIE snoop in flight to core. Event count should be multiplied by 2 since the data is coming from a 2:1 clock domain and the data is time sliced across all 4 threads. ##0B0000036080 Cycles in which the NCU had a TLBIE snoop in flight to core. Event count should be multiplied by 2 since the data is coming from a 2:1 clock domain and the data is time sliced across all 4 threads. #426,u,g,n,n,n,u,PM_ST_DATA_FROM_RL2L3,Store data line missed in the local chiplet and was found in a different chip's L2 or L3 (off chip, within the group). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##0C0000036080 Store data line missed in the local chiplet and was found in a different chip's L2 or L3 (off chip, within the group). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #427,u,g,n,n,n,u,PM_ST_DATA_FROM_RMEM,Store data line missed in the local chiplet and was found in remote memory (off chip, within the group). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##0C0000036880 Store data line missed in the local chiplet and was found in remote memory (off chip, within the group). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #428,u,g,n,n,m,u,PM_DATA_RADIX_PROCESS_L2_PTE_FROM_L3MISS,A data Page Table Entry was reloaded to a level 2 page walk cache from a source beyond the core's caches due to a process scoped demand miss. ##00000000003434A A data Page Table Entry was reloaded to a level 2 page walk cache from a source beyond the core's caches due to a process scoped demand miss. #429,u,g,n,n,n,u,PM_DATA_RADIX_PROCESS_L2_PDE_FROM_L3MISS,A data Page Directory Entry was reloaded to a level 2 page walk cache from a source beyond the core's caches due to a process scoped demand miss. ##00000000003424C A data Page Directory Entry was reloaded to a level 2 page walk cache from a source beyond the core's caches due to a process scoped demand miss. #430,u,g,n,n,n,u,PM_DATA_RADIX_PROCESS_L3_PTE_FROM_L3MISS,A data Page Table Entry was reloaded to a level 3 page walk cache from a source beyond the core's caches due to a process scoped demand miss. ##00000000003424E A data Page Table Entry was reloaded to a level 3 page walk cache from a source beyond the core's caches due to a process scoped demand miss. #431,u,g,n,n,n,u,PM_DATA_RADIX_PROCESS_L3_PDE_FROM_L3MISS,A data Page Directory Entry was reloaded to a level 3 page walk cache from a source beyond the core's caches due to a process scoped demand miss. ##000000000035240 A data Page Directory Entry was reloaded to a level 3 page walk cache from a source beyond the core's caches due to a process scoped demand miss. #432,u,g,n,n,n,u,PM_DATA_RADIX_PROCESS_L4_PTE_FROM_L3MISS,A data Page Table Entry was reloaded to a level 4 page walk cache from a source beyond the core's caches due to a process scoped demand miss. ##000000000035242 A data Page Table Entry was reloaded to a level 4 page walk cache from a source beyond the core's caches due to a process scoped demand miss. #433,u,g,n,n,n,u,PM_INST_RADIX_PROCESS_L2_PTE_FROM_L3MISS,An instruction Page Table Entry was reloaded to a level 2 page walk cache from a source beyond the core's caches due to a process scoped demand miss. ##000000000035246 An instruction Page Table Entry was reloaded to a level 2 page walk cache from a source beyond the core's caches due to a process scoped demand miss. #434,u,g,n,n,n,u,PM_INST_RADIX_PROCESS_L3_PTE_FROM_L3MISS,An instruction Page Table Entry was reloaded to a level 3 page walk cache from a source beyond the core's caches due to a process scoped demand miss. ##00000000003524A An instruction Page Table Entry was reloaded to a level 3 page walk cache from a source beyond the core's caches due to a process scoped demand miss. #435,u,g,n,n,n,u,PM_INST_RADIX_PROCESS_L3_PDE_FROM_L3MISS,An instruction Page Directory Entry was reloaded to a level 3 page walk cache from a source beyond the core's caches due to a process scoped demand miss. ##00000000003524C An instruction Page Directory Entry was reloaded to a level 3 page walk cache from a source beyond the core's caches due to a process scoped demand miss. #436,u,g,n,n,n,u,PM_INST_RADIX_PROCESS_L4_PTE_FROM_L3MISS,An instruction Page Table Entry was reloaded to a level 4 page walk cache from a source beyond the core's caches due to a process scoped demand miss. ##00000000003524E An instruction Page Table Entry was reloaded to a level 4 page walk cache from a source beyond the core's caches due to a process scoped demand miss. #437,u,g,n,n,m,u,PM_DATA_RADIX_PROCESS_L2_PTE_FROM_L3MISS_ALL,A data Page Table Entry was reloaded to a level 2 page walk cache from a source beyond the core's caches due to a process scoped demand or prefetch miss. ##00000000023434A A data Page Table Entry was reloaded to a level 2 page walk cache from a source beyond the core's caches due to a process scoped demand or prefetch miss. #438,u,g,n,n,n,u,PM_DATA_RADIX_PROCESS_L2_PDE_FROM_L3MISS_ALL,A data Page Directory Entry was reloaded to a level 2 page walk cache from a source beyond the core's caches due to a process scoped demand or prefetch miss. ##00000000023424C A data Page Directory Entry was reloaded to a level 2 page walk cache from a source beyond the core's caches due to a process scoped demand or prefetch miss. #439,u,g,n,n,n,u,PM_DATA_RADIX_PROCESS_L3_PTE_FROM_L3MISS_ALL,A data Page Table Entry was reloaded to a level 3 page walk cache from a source beyond the core's caches due to a process scoped demand or prefetch miss. ##00000000023424E A data Page Table Entry was reloaded to a level 3 page walk cache from a source beyond the core's caches due to a process scoped demand or prefetch miss. #440,u,g,n,n,n,u,PM_DATA_RADIX_PROCESS_L3_PDE_FROM_L3MISS_ALL,A data Page Directory Entry was reloaded to a level 3 page walk cache from a source beyond the core's caches due to a process scoped demand or prefetch miss. ##000000000235240 A data Page Directory Entry was reloaded to a level 3 page walk cache from a source beyond the core's caches due to a process scoped demand or prefetch miss. #441,u,g,n,n,n,u,PM_DATA_RADIX_PROCESS_L4_PTE_FROM_L3MISS_ALL,A data Page Table Entry was reloaded to a level 4 page walk cache from a source beyond the core's caches due to a process scoped demand or prefetch miss. ##000000000235242 A data Page Table Entry was reloaded to a level 4 page walk cache from a source beyond the core's caches due to a process scoped demand or prefetch miss. #442,u,g,n,n,n,u,PM_INST_RADIX_PROCESS_L2_PTE_FROM_L3MISS_ALL,An instruction Page Table Entry was reloaded to a level 2 page walk cache from a source beyond the core's caches due to a process scoped demand or prefetch miss. ##000000000135246 An instruction Page Table Entry was reloaded to a level 2 page walk cache from a source beyond the core's caches due to a process scoped demand or prefetch miss. #443,u,g,n,n,n,u,PM_INST_RADIX_PROCESS_L3_PTE_FROM_L3MISS_ALL,An instruction Page Table Entry was reloaded to a level 3 page walk cache from a source beyond the core's caches due to a process scoped demand or prefetch miss. ##00000000013524A An instruction Page Table Entry was reloaded to a level 3 page walk cache from a source beyond the core's caches due to a process scoped demand or prefetch miss. #444,u,g,n,n,n,u,PM_INST_RADIX_PROCESS_L3_PDE_FROM_L3MISS_ALL,An instruction Page Directory Entry was reloaded to a level 3 page walk cache from a source beyond the core's caches due to a process scoped demand or prefetch miss. ##00000000013524C An instruction Page Directory Entry was reloaded to a level 3 page walk cache from a source beyond the core's caches due to a process scoped demand or prefetch miss. #445,u,g,n,n,n,u,PM_INST_RADIX_PROCESS_L4_PTE_FROM_L3MISS_ALL,An instruction Page Table Entry was reloaded to a level 4 page walk cache from a source beyond the core's caches due to a process scoped demand or prefetch miss. ##00000000013524E An instruction Page Table Entry was reloaded to a level 4 page walk cache from a source beyond the core's caches due to a process scoped demand or prefetch miss. #446,u,g,n,n,n,u,PM_INST_FROM_L2,The processor's instruction cache was reloaded from the local core's L2 due to a demand miss. ##000300000003C040 The processor's instruction cache was reloaded from the local core's L2 due to a demand miss. #447,u,g,n,n,n,u,PM_IPTEG_FROM_L2,The processor's instruction page table entry was reloaded from the local core's L2 due to a demand miss. ##000320000003C040 The processor's instruction page table entry was reloaded from the local core's L2 due to a demand miss. #448,u,g,n,n,n,u,PM_DATA_FROM_L2,The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss. ##000340000003C040 The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss. #449,u,g,n,n,n,u,PM_DPTEG_FROM_L2,The processor's data page table entry was reloaded from the local core's L2 due to a demand miss. ##000360000003C040 The processor's data page table entry was reloaded from the local core's L2 due to a demand miss. #450,u,g,n,n,n,u,PM_INST_FROM_L2_ALL,The processor's instruction cache was reloaded from the local core's L2 due to a demand miss or prefetch reload. ##000300000013C040 The processor's instruction cache was reloaded from the local core's L2 due to a demand miss or prefetch reload. #451,u,g,n,n,n,u,PM_IPTEG_FROM_L2_ALL,The processor's instruction page table entry was reloaded from the local core's L2 due to a demand miss or prefetch reload. ##000320000013C040 The processor's instruction page table entry was reloaded from the local core's L2 due to a demand miss or prefetch reload. #452,u,g,n,n,n,u,PM_DATA_FROM_L2_ALL,The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss or prefetch reload. ##000340000023C040 The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss or prefetch reload. #453,u,g,n,n,n,u,PM_DPTEG_FROM_L2_ALL,The processor's data page table entry was reloaded from the local core's L2 due to a demand miss or prefetch reload. ##000360000023C040 The processor's data page table entry was reloaded from the local core's L2 due to a demand miss or prefetch reload. #454,u,g,n,n,n,u,PM_INST_FROM_L1MISS,The processor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss. ##003F00000003C040 The processor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss. #455,u,g,n,n,n,u,PM_IPTEG_FROM_L1MISS,The processor's instruction page table entry was reloaded from a source beyond the local core's L1 due to a demand miss. ##003F20000003C040 The processor's instruction page table entry was reloaded from a source beyond the local core's L1 due to a demand miss. #456,u,g,n,n,n,u,PM_DATA_FROM_L1MISS,The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss. ##003F40000003C040 The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss. #457,u,g,n,n,n,u,PM_DPTEG_FROM_L1MISS,The processor's data page table entry was reloaded from a source beyond the local core's L1 due to a demand miss. ##003F60000003C040 The processor's data page table entry was reloaded from a source beyond the local core's L1 due to a demand miss. #458,u,g,n,n,n,u,PM_INST_FROM_L1MISS_ALL,The processor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. ##003F00000013C040 The processor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. #459,u,g,n,n,n,u,PM_IPTEG_FROM_L1MISS_ALL,The processor's instruction page table entry was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. ##003F20000013C040 The processor's instruction page table entry was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. #460,u,g,n,n,n,u,PM_DATA_FROM_L1MISS_ALL,The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. ##003F40000023C040 The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. #461,u,g,n,n,n,u,PM_DPTEG_FROM_L1MISS_ALL,The processor's data page table entry was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. ##003F60000023C040 The processor's data page table entry was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. #462,u,g,n,n,n,u,PM_IPTEG_FROM_L2_NO_CONFLICT,The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. ##000020000003C040 The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. #463,u,g,n,n,n,u,PM_DATA_FROM_L2_NO_CONFLICT,The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. ##000040000003C040 The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. #464,u,g,n,n,n,u,PM_DPTEG_FROM_L2_NO_CONFLICT,The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. ##000060000003C040 The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. #465,u,g,n,n,n,u,PM_IPTEG_FROM_L2_NO_CONFLICT_ALL,The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. ##000020000013C040 The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. #466,u,g,n,n,n,u,PM_DATA_FROM_L2_NO_CONFLICT_ALL,The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. ##000040000023C040 The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. #467,u,g,n,n,n,u,PM_DPTEG_FROM_L2_NO_CONFLICT_ALL,The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. ##000060000023C040 The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. #468,u,g,n,n,n,u,PM_IPTEG_FROM_L2_MEPF,The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. ##004020000003C040 The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. #469,u,g,n,n,n,u,PM_DATA_FROM_L2_MEPF,The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. ##004040000003C040 The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. #470,u,g,n,n,n,u,PM_DPTEG_FROM_L2_MEPF,The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. ##004060000003C040 The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. #471,u,g,n,n,n,u,PM_IPTEG_FROM_L2_MEPF_ALL,The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. ##004020000013C040 The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. #472,u,g,n,n,n,u,PM_DATA_FROM_L2_MEPF_ALL,The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. ##004040000023C040 The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. #473,u,g,n,n,n,u,PM_DPTEG_FROM_L2_MEPF_ALL,The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. ##004060000023C040 The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. #474,u,g,n,n,n,u,PM_IPTEG_FROM_L2_LDHITST_CONFLICT,The processor's instruction page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. ##008020000003C040 The processor's instruction page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. #475,u,g,n,n,n,u,PM_DATA_FROM_L2_LDHITST_CONFLICT,The processor's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. ##008040000003C040 The processor's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. #476,u,g,n,n,n,u,PM_DPTEG_FROM_L2_LDHITST_CONFLICT,The processor's data page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. ##008060000003C040 The processor's data page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. #477,u,g,n,n,n,u,PM_IPTEG_FROM_L2_LDHITST_CONFLICT_ALL,The processor's instruction page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. ##008020000013C040 The processor's instruction page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. #478,u,g,n,n,n,u,PM_DATA_FROM_L2_LDHITST_CONFLICT_ALL,The processor's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. ##008040000023C040 The processor's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. #479,u,g,n,n,n,u,PM_DPTEG_FROM_L2_LDHITST_CONFLICT_ALL,The processor's data page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. ##008060000023C040 The processor's data page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. #480,u,g,n,n,n,u,PM_IPTEG_FROM_L2_OTHER_CONFLICT,The processor's instruction page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. ##00C020000003C040 The processor's instruction page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. #481,u,g,n,n,n,u,PM_DATA_FROM_L2_OTHER_CONFLICT,The processor's L1 data cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. ##00C040000003C040 The processor's L1 data cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. #482,u,g,n,n,n,u,PM_DPTEG_FROM_L2_OTHER_CONFLICT,The processor's data page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. ##00C060000003C040 The processor's data page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. #483,u,g,n,n,n,u,PM_IPTEG_FROM_L2_OTHER_CONFLICT_ALL,The processor's instruction page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. ##00C020000013C040 The processor's instruction page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. #484,u,g,n,n,n,u,PM_DATA_FROM_L2_OTHER_CONFLICT_ALL,The processor's L1 data cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. ##00C040000023C040 The processor's L1 data cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. #485,u,g,n,n,n,u,PM_DPTEG_FROM_L2_OTHER_CONFLICT_ALL,The processor's data page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. ##00C060000023C040 The processor's data page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. #486,u,g,n,n,n,u,PM_INST_FROM_L2MISS,The processor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss. ##000380000003C040 The processor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss. #487,u,g,n,n,n,u,PM_IPTEG_FROM_L2MISS,The processor's instruction page table entry was reloaded from a source beyond the local core's L2 due to a demand miss. ##0003A0000003C040 The processor's instruction page table entry was reloaded from a source beyond the local core's L2 due to a demand miss. #488,u,g,n,n,n,u,PM_DPTEG_FROM_L2MISS,The processor's data page table entry was reloaded from a source beyond the local core's L2 due to a demand miss. ##0003E0000003C040 The processor's data page table entry was reloaded from a source beyond the local core's L2 due to a demand miss. #489,u,g,n,n,n,u,PM_INST_FROM_L2MISS_ALL,The processor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. ##000380000013C040 The processor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. #490,u,g,n,n,n,u,PM_IPTEG_FROM_L2MISS_ALL,The processor's instruction page table entry was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. ##0003A0000013C040 The processor's instruction page table entry was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. #491,u,g,n,n,n,u,PM_DATA_FROM_L2MISS_ALL,The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. ##0003C0000023C040 The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. #492,u,g,n,n,n,u,PM_DPTEG_FROM_L2MISS_ALL,The processor's data page table entry was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. ##0003E0000023C040 The processor's data page table entry was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. #493,u,g,n,n,n,u,PM_INST_FROM_L3,The processor's instruction cache was reloaded from the local core's L3 due to a demand miss. ##010300000003C040 The processor's instruction cache was reloaded from the local core's L3 due to a demand miss. #494,u,g,n,n,n,u,PM_IPTEG_FROM_L3,The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss. ##010320000003C040 The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss. #495,u,g,n,n,n,u,PM_DATA_FROM_L3,The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss. ##010340000003C040 The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss. #496,u,g,n,n,n,u,PM_DPTEG_FROM_L3,The processor's data page table entry was reloaded from the local core's L3 due to a demand miss. ##010360000003C040 The processor's data page table entry was reloaded from the local core's L3 due to a demand miss. #497,u,g,n,n,n,u,PM_INST_FROM_L3_ALL,The processor's instruction cache was reloaded from the local core's L3 due to a demand miss or prefetch reload. ##010300000013C040 The processor's instruction cache was reloaded from the local core's L3 due to a demand miss or prefetch reload. #498,u,g,n,n,n,u,PM_IPTEG_FROM_L3_ALL,The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload. ##010320000013C040 The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload. #499,u,g,n,n,n,u,PM_DATA_FROM_L3_ALL,The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload. ##010340000023C040 The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload. #500,u,g,n,n,n,u,PM_DPTEG_FROM_L3_ALL,The processor's data page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload. ##010360000023C040 The processor's data page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload. #501,u,g,n,n,n,u,PM_IPTEG_FROM_L3_NO_CONFLICT,The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. ##010020000003C040 The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. #502,u,g,n,n,n,u,PM_DATA_FROM_L3_NO_CONFLICT,The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. ##010040000003C040 The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. #503,u,g,n,n,n,u,PM_DPTEG_FROM_L3_NO_CONFLICT,The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. ##010060000003C040 The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. #504,u,g,n,n,n,u,PM_IPTEG_FROM_L3_NO_CONFLICT_ALL,The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. ##010020000013C040 The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. #505,u,g,n,n,n,u,PM_DATA_FROM_L3_NO_CONFLICT_ALL,The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. ##010040000023C040 The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. #506,u,g,n,n,n,u,PM_DPTEG_FROM_L3_NO_CONFLICT_ALL,The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. ##010060000023C040 The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. #507,u,g,n,n,n,u,PM_IPTEG_FROM_L3_MEPF,The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. ##014020000003C040 The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. #508,u,g,n,n,n,u,PM_DATA_FROM_L3_MEPF,The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. ##014040000003C040 The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. #509,u,g,n,n,n,u,PM_DPTEG_FROM_L3_MEPF,The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. ##014060000003C040 The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. #510,u,g,n,n,n,u,PM_IPTEG_FROM_L3_MEPF_ALL,The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. ##014020000013C040 The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. #511,u,g,n,n,n,u,PM_DATA_FROM_L3_MEPF_ALL,The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. ##014040000023C040 The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. #512,u,g,n,n,n,u,PM_DPTEG_FROM_L3_MEPF_ALL,The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. ##014060000023C040 The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. #513,u,g,n,n,n,u,PM_IPTEG_FROM_L3_CONFLICT,The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss. ##01C020000003C040 The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss. #514,u,g,n,n,n,u,PM_DATA_FROM_L3_CONFLICT,The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss. ##01C040000003C040 The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss. #515,u,g,n,n,n,u,PM_DPTEG_FROM_L3_CONFLICT,The processor's data page table entry was reloaded from the local core's L3 due to a demand miss. ##01C060000003C040 The processor's data page table entry was reloaded from the local core's L3 due to a demand miss. #516,u,g,n,n,n,u,PM_IPTEG_FROM_L3_CONFLICT_ALL,The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload. ##01C020000013C040 The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload. #517,u,g,n,n,n,u,PM_DATA_FROM_L3_CONFLICT_ALL,The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload. ##01C040000023C040 The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload. #518,u,g,n,n,n,u,PM_DPTEG_FROM_L3_CONFLICT_ALL,The processor's data page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload. ##01C060000023C040 The processor's data page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload. #519,u,g,n,n,n,u,PM_IPTEG_FROM_L3MISS,The processor's instruction page table entry was reloaded from beyond the local core's L3 due to a demand miss. ##0007A0000003C040 The processor's instruction page table entry was reloaded from beyond the local core's L3 due to a demand miss. #520,u,g,n,n,n,u,PM_DPTEG_FROM_L3MISS,The processor's data page table entry was reloaded from beyond the local core's L3 due to a demand miss. ##0007E0000003C040 The processor's data page table entry was reloaded from beyond the local core's L3 due to a demand miss. #521,u,g,n,n,n,u,PM_INST_FROM_L3MISS_ALL,The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. ##000780000013C040 The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. #522,u,g,n,n,n,u,PM_IPTEG_FROM_L3MISS_ALL,The processor's instruction page table entry was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. ##0007A0000013C040 The processor's instruction page table entry was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. #523,u,g,n,n,n,u,PM_DATA_FROM_L3MISS_ALL,The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. ##0007C0000023C040 The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. #524,u,g,n,n,n,u,PM_DPTEG_FROM_L3MISS_ALL,The processor's data page table entry was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. ##0007E0000023C040 The processor's data page table entry was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. #525,u,g,n,n,n,u,PM_IPTEG_FROM_L21_REGENT_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. ##080020000003C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. #526,u,g,n,n,n,u,PM_DATA_FROM_L21_REGENT_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. ##080040000003C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. #527,u,g,n,n,n,u,PM_DPTEG_FROM_L21_REGENT_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. ##080060000003C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. #528,u,g,n,n,n,u,PM_IPTEG_FROM_L21_REGENT_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. ##080020000013C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. #529,u,g,n,n,n,u,PM_DATA_FROM_L21_REGENT_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. ##080040000023C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. #530,u,g,n,n,n,u,PM_DPTEG_FROM_L21_REGENT_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. ##080060000023C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. #531,u,g,n,n,n,u,PM_IPTEG_FROM_L21_REGENT_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. ##084020000003C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. #532,u,g,n,n,n,u,PM_DATA_FROM_L21_REGENT_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. ##084040000003C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. #533,u,g,n,n,n,u,PM_DPTEG_FROM_L21_REGENT_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. ##084060000003C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. #534,u,g,n,n,n,u,PM_IPTEG_FROM_L21_REGENT_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. ##084020000013C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. #535,u,g,n,n,n,u,PM_DATA_FROM_L21_REGENT_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. ##084040000023C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. #536,u,g,n,n,n,u,PM_DPTEG_FROM_L21_REGENT_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. ##084060000023C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. #537,u,g,n,n,n,u,PM_INST_FROM_L21_REGENT,The processor's instruction cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. ##080100000003C040 The processor's instruction cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. #538,u,g,n,n,n,u,PM_IPTEG_FROM_L21_REGENT,The processor's instruction page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. ##080120000003C040 The processor's instruction page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. #539,u,g,n,n,n,u,PM_DATA_FROM_L21_REGENT,The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. ##080140000003C040 The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. #540,u,g,n,n,n,u,PM_DPTEG_FROM_L21_REGENT,The processor's data page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. ##080160000003C040 The processor's data page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. #541,u,g,n,n,n,u,PM_INST_FROM_L21_REGENT_ALL,The processor's instruction cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. ##080100000013C040 The processor's instruction cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. #542,u,g,n,n,n,u,PM_IPTEG_FROM_L21_REGENT_ALL,The processor's instruction page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. ##080120000013C040 The processor's instruction page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. #543,u,g,n,n,n,u,PM_DATA_FROM_L21_REGENT_ALL,The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. ##080140000023C040 The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. #544,u,g,n,n,n,u,PM_DPTEG_FROM_L21_REGENT_ALL,The processor's data page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. ##080160000023C040 The processor's data page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. #545,u,g,n,n,n,u,PM_IPTEG_FROM_L31_REGENT_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. ##088020000003C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. #546,u,g,n,n,n,u,PM_DATA_FROM_L31_REGENT_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. ##088040000003C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. #547,u,g,n,n,n,u,PM_DPTEG_FROM_L31_REGENT_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. ##088060000003C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. #548,u,g,n,n,n,u,PM_IPTEG_FROM_L31_REGENT_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##088020000013C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. #549,u,g,n,n,n,u,PM_DATA_FROM_L31_REGENT_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##088040000023C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. #550,u,g,n,n,n,u,PM_DPTEG_FROM_L31_REGENT_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##088060000023C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. #551,u,g,n,n,n,u,PM_IPTEG_FROM_L31_REGENT_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. ##08C020000003C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. #552,u,g,n,n,n,u,PM_DATA_FROM_L31_REGENT_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. ##08C040000003C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. #553,u,g,n,n,n,u,PM_DPTEG_FROM_L31_REGENT_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. ##08C060000003C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. #554,u,g,n,n,n,u,PM_IPTEG_FROM_L31_REGENT_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##08C020000013C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. #555,u,g,n,n,n,u,PM_DATA_FROM_L31_REGENT_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##08C040000023C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. #556,u,g,n,n,n,u,PM_DPTEG_FROM_L31_REGENT_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##08C060000023C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. #557,u,g,n,n,n,u,PM_INST_FROM_L31_REGENT,The processor's instruction cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. ##088100000003C040 The processor's instruction cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. #558,u,g,n,n,n,u,PM_IPTEG_FROM_L31_REGENT,The processor's instruction page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. ##088120000003C040 The processor's instruction page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. #559,u,g,n,n,n,u,PM_DATA_FROM_L31_REGENT,The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. ##088140000003C040 The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. #560,u,g,n,n,n,u,PM_DPTEG_FROM_L31_REGENT,The processor's data page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. ##088160000003C040 The processor's data page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. #561,u,g,n,n,n,u,PM_INST_FROM_L31_REGENT_ALL,The processor's instruction cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##088100000013C040 The processor's instruction cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. #562,u,g,n,n,n,u,PM_IPTEG_FROM_L31_REGENT_ALL,The processor's instruction page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##088120000013C040 The processor's instruction page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. #563,u,g,n,n,n,u,PM_DATA_FROM_L31_REGENT_ALL,The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##088140000023C040 The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. #564,u,g,n,n,n,u,PM_DPTEG_FROM_L31_REGENT_ALL,The processor's data page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##088160000023C040 The processor's data page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. #565,u,g,n,n,n,u,PM_IPTEG_FROM_REGENT_L2L3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. ##080220000003C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. #566,u,g,n,n,n,u,PM_DATA_FROM_REGENT_L2L3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. ##080240000003C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. #567,u,g,n,n,n,u,PM_DPTEG_FROM_REGENT_L2L3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. ##080260000003C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. #568,u,g,n,n,n,u,PM_IPTEG_FROM_REGENT_L2L3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##080220000013C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. #569,u,g,n,n,n,u,PM_DATA_FROM_REGENT_L2L3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##080240000023C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. #570,u,g,n,n,n,u,PM_DPTEG_FROM_REGENT_L2L3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##080260000023C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. #571,u,g,n,n,n,u,PM_IPTEG_FROM_REGENT_L2L3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. ##084220000003C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. #572,u,g,n,n,n,u,PM_DATA_FROM_REGENT_L2L3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. ##084240000003C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. #573,u,g,n,n,n,u,PM_DPTEG_FROM_REGENT_L2L3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. ##084260000003C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. #574,u,g,n,n,n,u,PM_IPTEG_FROM_REGENT_L2L3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##084220000013C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. #575,u,g,n,n,n,u,PM_DATA_FROM_REGENT_L2L3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##084240000023C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. #576,u,g,n,n,n,u,PM_DPTEG_FROM_REGENT_L2L3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##084260000023C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. #577,u,g,n,n,n,u,PM_INST_FROM_REGENT_L2L3,The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. ##080300000003C040 The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. #578,u,g,n,n,n,u,PM_IPTEG_FROM_REGENT_L2L3,The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. ##080320000003C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. #579,u,g,n,n,n,u,PM_DATA_FROM_REGENT_L2L3,The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. ##080340000003C040 The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. #580,u,g,n,n,n,u,PM_DPTEG_FROM_REGENT_L2L3,The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. ##080360000003C040 The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. #581,u,g,n,n,n,u,PM_INST_FROM_REGENT_L2L3_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##080300000013C040 The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. #582,u,g,n,n,n,u,PM_IPTEG_FROM_REGENT_L2L3_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##080320000013C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. #583,u,g,n,n,n,u,PM_DATA_FROM_REGENT_L2L3_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##080340000023C040 The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. #584,u,g,n,n,n,u,PM_DPTEG_FROM_REGENT_L2L3_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##080360000023C040 The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. #585,u,g,n,n,n,u,PM_IPTEG_FROM_L21_NON_REGENT_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. ##0A0020000003C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. #586,u,g,n,n,n,u,PM_DATA_FROM_L21_NON_REGENT_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. ##0A0040000003C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. #587,u,g,n,n,n,u,PM_DPTEG_FROM_L21_NON_REGENT_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. ##0A0060000003C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. #588,u,g,n,n,n,u,PM_IPTEG_FROM_L21_NON_REGENT_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0020000013C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. #589,u,g,n,n,n,u,PM_DATA_FROM_L21_NON_REGENT_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0040000023C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. #590,u,g,n,n,n,u,PM_DPTEG_FROM_L21_NON_REGENT_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0060000023C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. #591,u,g,n,n,n,u,PM_IPTEG_FROM_L21_NON_REGENT_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. ##0A4020000003C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. #592,u,g,n,n,n,u,PM_DATA_FROM_L21_NON_REGENT_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. ##0A4040000003C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. #593,u,g,n,n,n,u,PM_DPTEG_FROM_L21_NON_REGENT_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. ##0A4060000003C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. #594,u,g,n,n,n,u,PM_IPTEG_FROM_L21_NON_REGENT_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A4020000013C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. #595,u,g,n,n,n,u,PM_DATA_FROM_L21_NON_REGENT_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A4040000023C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. #596,u,g,n,n,n,u,PM_DPTEG_FROM_L21_NON_REGENT_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A4060000023C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. #597,u,g,n,n,n,u,PM_INST_FROM_L21_NON_REGENT,The processor's instruction cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. ##0A0100000003C040 The processor's instruction cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. #598,u,g,n,n,n,u,PM_IPTEG_FROM_L21_NON_REGENT,The processor's instruction page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. ##0A0120000003C040 The processor's instruction page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. #599,u,g,n,n,n,u,PM_DATA_FROM_L21_NON_REGENT,The processor's L1 data cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. ##0A0140000003C040 The processor's L1 data cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. #600,u,g,n,n,n,u,PM_DPTEG_FROM_L21_NON_REGENT,The processor's data page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. ##0A0160000003C040 The processor's data page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. #601,u,g,n,n,n,u,PM_INST_FROM_L21_NON_REGENT_ALL,The processor's instruction cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0100000013C040 The processor's instruction cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. #602,u,g,n,n,n,u,PM_IPTEG_FROM_L21_NON_REGENT_ALL,The processor's instruction page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0120000013C040 The processor's instruction page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. #603,u,g,n,n,n,u,PM_DATA_FROM_L21_NON_REGENT_ALL,The processor's L1 data cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0140000023C040 The processor's L1 data cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. #604,u,g,n,n,n,u,PM_DPTEG_FROM_L21_NON_REGENT_ALL,The processor's data page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0160000023C040 The processor's data page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. #605,u,g,n,n,n,u,PM_IPTEG_FROM_L31_NON_REGENT_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. ##0A8020000003C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. #606,u,g,n,n,n,u,PM_DATA_FROM_L31_NON_REGENT_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. ##0A8040000003C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. #607,u,g,n,n,n,u,PM_DPTEG_FROM_L31_NON_REGENT_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. ##0A8060000003C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. #608,u,g,n,n,n,u,PM_IPTEG_FROM_L31_NON_REGENT_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A8020000013C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. #609,u,g,n,n,n,u,PM_DATA_FROM_L31_NON_REGENT_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A8040000023C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. #610,u,g,n,n,n,u,PM_DPTEG_FROM_L31_NON_REGENT_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A8060000023C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. #611,u,g,n,n,n,u,PM_IPTEG_FROM_L31_NON_REGENT_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. ##0AC020000003C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. #612,u,g,n,n,n,u,PM_DATA_FROM_L31_NON_REGENT_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. ##0AC040000003C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. #613,u,g,n,n,n,u,PM_DPTEG_FROM_L31_NON_REGENT_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. ##0AC060000003C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. #614,u,g,n,n,n,u,PM_IPTEG_FROM_L31_NON_REGENT_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0AC020000013C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. #615,u,g,n,n,n,u,PM_DATA_FROM_L31_NON_REGENT_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0AC040000023C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. #616,u,g,n,n,n,u,PM_DPTEG_FROM_L31_NON_REGENT_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0AC060000023C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. #617,u,g,n,n,n,u,PM_INST_FROM_L31_NON_REGENT,The processor's instruction cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. ##0A8100000003C040 The processor's instruction cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. #618,u,g,n,n,n,u,PM_IPTEG_FROM_L31_NON_REGENT,The processor's instruction page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. ##0A8120000003C040 The processor's instruction page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. #619,u,g,n,n,n,u,PM_DATA_FROM_L31_NON_REGENT,The processor's L1 data cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. ##0A8140000003C040 The processor's L1 data cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. #620,u,g,n,n,n,u,PM_DPTEG_FROM_L31_NON_REGENT,The processor's data page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. ##0A8160000003C040 The processor's data page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. #621,u,g,n,n,n,u,PM_INST_FROM_L31_NON_REGENT_ALL,The processor's instruction cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A8100000013C040 The processor's instruction cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. #622,u,g,n,n,n,u,PM_IPTEG_FROM_L31_NON_REGENT_ALL,The processor's instruction page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A8120000013C040 The processor's instruction page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. #623,u,g,n,n,n,u,PM_DATA_FROM_L31_NON_REGENT_ALL,The processor's L1 data cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A8140000023C040 The processor's L1 data cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. #624,u,g,n,n,n,u,PM_DPTEG_FROM_L31_NON_REGENT_ALL,The processor's data page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A8160000023C040 The processor's data page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. #625,u,g,n,n,n,u,PM_IPTEG_FROM_NON_REGENT_L2L3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. ##0A0220000003C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. #626,u,g,n,n,n,u,PM_DATA_FROM_NON_REGENT_L2L3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. ##0A0240000003C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. #627,u,g,n,n,n,u,PM_DPTEG_FROM_NON_REGENT_L2L3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. ##0A0260000003C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. #628,u,g,n,n,n,u,PM_IPTEG_FROM_NON_REGENT_L2L3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0220000013C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. #629,u,g,n,n,n,u,PM_DATA_FROM_NON_REGENT_L2L3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0240000023C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. #630,u,g,n,n,n,u,PM_DPTEG_FROM_NON_REGENT_L2L3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0260000023C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. #631,u,g,n,n,n,u,PM_IPTEG_FROM_NON_REGENT_L2L3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. ##0A4220000003C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. #632,u,g,n,n,n,u,PM_DATA_FROM_NON_REGENT_L2L3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. ##0A4240000003C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. #633,u,g,n,n,n,u,PM_DPTEG_FROM_NON_REGENT_L2L3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. ##0A4260000003C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. #634,u,g,n,n,n,u,PM_IPTEG_FROM_NON_REGENT_L2L3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A4220000013C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. #635,u,g,n,n,n,u,PM_DATA_FROM_NON_REGENT_L2L3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A4240000023C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. #636,u,g,n,n,n,u,PM_DPTEG_FROM_NON_REGENT_L2L3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A4260000023C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. #637,u,g,n,n,n,u,PM_INST_FROM_NON_REGENT_L2L3,The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. ##0A0300000003C040 The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. #638,u,g,n,n,n,u,PM_IPTEG_FROM_NON_REGENT_L2L3,The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. ##0A0320000003C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. #639,u,g,n,n,n,u,PM_DATA_FROM_NON_REGENT_L2L3,The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. ##0A0340000003C040 The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. #640,u,g,n,n,n,u,PM_DPTEG_FROM_NON_REGENT_L2L3,The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. ##0A0360000003C040 The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. #641,u,g,n,n,n,u,PM_INST_FROM_NON_REGENT_L2L3_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0300000013C040 The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. #642,u,g,n,n,n,u,PM_IPTEG_FROM_NON_REGENT_L2L3_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0320000013C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. #643,u,g,n,n,n,u,PM_DATA_FROM_NON_REGENT_L2L3_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0340000023C040 The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. #644,u,g,n,n,n,u,PM_DPTEG_FROM_NON_REGENT_L2L3_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0360000023C040 The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. #645,u,g,n,n,n,u,PM_INST_FROM_LMEM,The processor's instruction cache was reloaded from the local chip's memory due to a demand miss. ##094100000003C040 The processor's instruction cache was reloaded from the local chip's memory due to a demand miss. #646,u,g,n,n,n,u,PM_IPTEG_FROM_LMEM,The processor's instruction page table entry was reloaded from the local chip's memory due to a demand miss. ##094020000003C040 The processor's instruction page table entry was reloaded from the local chip's memory due to a demand miss. #647,u,g,n,n,n,u,PM_DATA_FROM_LMEM,The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss. ##094040000003C040 The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss. #648,u,g,n,n,n,u,PM_DPTEG_FROM_LMEM,The processor's data page table entry was reloaded from the local chip's memory due to a demand miss. ##094060000003C040 The processor's data page table entry was reloaded from the local chip's memory due to a demand miss. #649,u,g,n,n,n,u,PM_INST_FROM_LMEM_ALL,The processor's instruction cache was reloaded from the local chip's memory due to a demand miss or prefetch reload. ##094100000013C040 The processor's instruction cache was reloaded from the local chip's memory due to a demand miss or prefetch reload. #650,u,g,n,n,n,u,PM_IPTEG_FROM_LMEM_ALL,The processor's instruction page table entry was reloaded from the local chip's memory due to a demand miss or prefetch reload. ##094020000013C040 The processor's instruction page table entry was reloaded from the local chip's memory due to a demand miss or prefetch reload. #651,u,g,n,n,n,u,PM_DATA_FROM_LMEM_ALL,The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss or prefetch reload. ##094040000023C040 The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss or prefetch reload. #652,u,g,n,n,n,u,PM_DPTEG_FROM_LMEM_ALL,The processor's data page table entry was reloaded from the local chip's memory due to a demand miss or prefetch reload. ##094060000023C040 The processor's data page table entry was reloaded from the local chip's memory due to a demand miss or prefetch reload. #653,u,g,n,n,n,u,PM_IPTEG_FROM_L_OC_CACHE,The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss. ##098020000003C040 The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss. #654,u,g,n,n,n,u,PM_DATA_FROM_L_OC_CACHE,The processor's L1 data cache was reloaded from the local chip's OpenCapp cache due to a demand miss. ##098040000003C040 The processor's L1 data cache was reloaded from the local chip's OpenCapp cache due to a demand miss. #655,u,g,n,n,n,u,PM_DPTEG_FROM_L_OC_CACHE,The processor's data page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss. ##098060000003C040 The processor's data page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss. #656,u,g,n,n,n,u,PM_IPTEG_FROM_L_OC_CACHE_ALL,The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. ##098020000013C040 The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. #657,u,g,n,n,n,u,PM_DATA_FROM_L_OC_CACHE_ALL,The processor's L1 data cache was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. ##098040000023C040 The processor's L1 data cache was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. #658,u,g,n,n,n,u,PM_DPTEG_FROM_L_OC_CACHE_ALL,The processor's data page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. ##098060000023C040 The processor's data page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. #659,u,g,n,n,n,u,PM_IPTEG_FROM_L_OC_MEM,The processor's instruction page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss. ##09C020000003C040 The processor's instruction page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss. #660,u,g,n,n,n,u,PM_DATA_FROM_L_OC_MEM,The processor's L1 data cache was reloaded from the local chip's OpenCapp memory due to a demand miss. ##09C040000003C040 The processor's L1 data cache was reloaded from the local chip's OpenCapp memory due to a demand miss. #661,u,g,n,n,n,u,PM_DPTEG_FROM_L_OC_MEM,The processor's data page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss. ##09C060000003C040 The processor's data page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss. #662,u,g,n,n,n,u,PM_IPTEG_FROM_L_OC_MEM_ALL,The processor's instruction page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. ##09C020000013C040 The processor's instruction page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. #663,u,g,n,n,n,u,PM_DATA_FROM_L_OC_MEM_ALL,The processor's L1 data cache was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. ##09C040000023C040 The processor's L1 data cache was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. #664,u,g,n,n,n,u,PM_DPTEG_FROM_L_OC_MEM_ALL,The processor's data page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. ##09C060000023C040 The processor's data page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. #665,u,g,n,n,n,u,PM_INST_FROM_L_OC_ANY,The processor's instruction cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. ##098100000003C040 The processor's instruction cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. #666,u,g,n,n,n,u,PM_IPTEG_FROM_L_OC_ANY,The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. ##098120000003C040 The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. #667,u,g,n,n,n,u,PM_DATA_FROM_L_OC_ANY,The processor's L1 data cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. ##098140000003C040 The processor's L1 data cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. #668,u,g,n,n,n,u,PM_DPTEG_FROM_L_OC_ANY,The processor's data page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. ##098160000003C040 The processor's data page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. #669,u,g,n,n,n,u,PM_INST_FROM_L_OC_ANY_ALL,The processor's instruction cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##098100000013C040 The processor's instruction cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #670,u,g,n,n,n,u,PM_IPTEG_FROM_L_OC_ANY_ALL,The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##098120000013C040 The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #671,u,g,n,n,n,u,PM_DATA_FROM_L_OC_ANY_ALL,The processor's L1 data cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##098140000023C040 The processor's L1 data cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #672,u,g,n,n,n,u,PM_DPTEG_FROM_L_OC_ANY_ALL,The processor's data page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##098160000023C040 The processor's data page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #673,u,g,n,n,n,u,PM_IPTEG_FROM_RL2_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. ##0C0020000003C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. #674,u,g,n,n,n,u,PM_DATA_FROM_RL2_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. ##0C0040000003C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. #675,u,g,n,n,n,u,PM_DPTEG_FROM_RL2_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. ##0C0060000003C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. #676,u,g,n,n,n,u,PM_IPTEG_FROM_RL2_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. ##0C0020000013C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. #677,u,g,n,n,n,u,PM_DATA_FROM_RL2_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. ##0C0040000023C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. #678,u,g,n,n,n,u,PM_DPTEG_FROM_RL2_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. ##0C0060000023C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. #679,u,g,n,n,n,u,PM_IPTEG_FROM_RL2_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. ##0C4020000003C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. #680,u,g,n,n,n,u,PM_DATA_FROM_RL2_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. ##0C4040000003C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. #681,u,g,n,n,n,u,PM_DPTEG_FROM_RL2_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. ##0C4060000003C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. #682,u,g,n,n,n,u,PM_IPTEG_FROM_RL2_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. ##0C4020000013C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. #683,u,g,n,n,n,u,PM_DATA_FROM_RL2_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. ##0C4040000023C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. #684,u,g,n,n,n,u,PM_DPTEG_FROM_RL2_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. ##0C4060000023C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. #685,u,g,n,n,n,u,PM_INST_FROM_RL2,The processor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss. ##0C0100000003C040 The processor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss. #686,u,g,n,n,n,u,PM_IPTEG_FROM_RL2,The processor's instruction page table entry was reloaded from another core's L2 from a remote chip due to a demand miss. ##0C0120000003C040 The processor's instruction page table entry was reloaded from another core's L2 from a remote chip due to a demand miss. #687,u,g,n,n,n,u,PM_DATA_FROM_RL2,The processor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss. ##0C0140000003C040 The processor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss. #688,u,g,n,n,n,u,PM_DPTEG_FROM_RL2,The processor's data page table entry was reloaded from another core's L2 from a remote chip due to a demand miss. ##0C0160000003C040 The processor's data page table entry was reloaded from another core's L2 from a remote chip due to a demand miss. #689,u,g,n,n,n,u,PM_INST_FROM_RL2_ALL,The processor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. ##0C0100000013C040 The processor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. #690,u,g,n,n,n,u,PM_IPTEG_FROM_RL2_ALL,The processor's instruction page table entry was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. ##0C0120000013C040 The processor's instruction page table entry was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. #691,u,g,n,n,n,u,PM_DATA_FROM_RL2_ALL,The processor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. ##0C0140000023C040 The processor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. #692,u,g,n,n,n,u,PM_DPTEG_FROM_RL2_ALL,The processor's data page table entry was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. ##0C0160000023C040 The processor's data page table entry was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. #693,u,g,n,n,n,u,PM_IPTEG_FROM_RL3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. ##0C8020000003C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. #694,u,g,n,n,n,u,PM_DATA_FROM_RL3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. ##0C8040000003C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. #695,u,g,n,n,n,u,PM_DPTEG_FROM_RL3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. ##0C8060000003C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. #696,u,g,n,n,n,u,PM_IPTEG_FROM_RL3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. ##0C8020000013C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. #697,u,g,n,n,n,u,PM_DATA_FROM_RL3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. ##0C8040000023C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. #698,u,g,n,n,n,u,PM_DPTEG_FROM_RL3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. ##0C8060000023C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. #699,u,g,n,n,n,u,PM_IPTEG_FROM_RL3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. ##0CC020000003C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. #700,u,g,n,n,n,u,PM_DATA_FROM_RL3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. ##0CC040000003C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. #701,u,g,n,n,n,u,PM_DPTEG_FROM_RL3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. ##0CC060000003C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. #702,u,g,n,n,n,u,PM_IPTEG_FROM_RL3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. ##0CC020000013C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. #703,u,g,n,n,n,u,PM_DATA_FROM_RL3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. ##0CC040000023C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. #704,u,g,n,n,n,u,PM_DPTEG_FROM_RL3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. ##0CC060000023C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. #705,u,g,n,n,n,u,PM_INST_FROM_RL3,The processor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss. ##0C8100000003C040 The processor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss. #706,u,g,n,n,n,u,PM_IPTEG_FROM_RL3,The processor's instruction page table entry was reloaded from another core's L3 from a remote chip due to a demand miss. ##0C8120000003C040 The processor's instruction page table entry was reloaded from another core's L3 from a remote chip due to a demand miss. #707,u,g,n,n,n,u,PM_DATA_FROM_RL3,The processor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss. ##0C8140000003C040 The processor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss. #708,u,g,n,n,n,u,PM_DPTEG_FROM_RL3,The processor's data page table entry was reloaded from another core's L3 from a remote chip due to a demand miss. ##0C8160000003C040 The processor's data page table entry was reloaded from another core's L3 from a remote chip due to a demand miss. #709,u,g,n,n,n,u,PM_INST_FROM_RL3_ALL,The processor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. ##0C8100000013C040 The processor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. #710,u,g,n,n,n,u,PM_IPTEG_FROM_RL3_ALL,The processor's instruction page table entry was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. ##0C8120000013C040 The processor's instruction page table entry was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. #711,u,g,n,n,n,u,PM_DATA_FROM_RL3_ALL,The processor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. ##0C8140000023C040 The processor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. #712,u,g,n,n,n,u,PM_DPTEG_FROM_RL3_ALL,The processor's data page table entry was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. ##0C8160000023C040 The processor's data page table entry was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. #713,u,g,n,n,n,u,PM_IPTEG_FROM_RL2L3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. ##0C0220000003C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. #714,u,g,n,n,n,u,PM_DATA_FROM_RL2L3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. ##0C0240000003C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. #715,u,g,n,n,n,u,PM_DPTEG_FROM_RL2L3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. ##0C0260000003C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. #716,u,g,n,n,n,u,PM_IPTEG_FROM_RL2L3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. ##0C0220000013C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. #717,u,g,n,n,n,u,PM_DATA_FROM_RL2L3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. ##0C0240000023C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. #718,u,g,n,n,n,u,PM_DPTEG_FROM_RL2L3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. ##0C0260000023C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. #719,u,g,n,n,n,u,PM_IPTEG_FROM_RL2L3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. ##0C4220000003C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. #720,u,g,n,n,n,u,PM_DATA_FROM_RL2L3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. ##0C4240000003C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. #721,u,g,n,n,n,u,PM_DPTEG_FROM_RL2L3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. ##0C4260000003C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. #722,u,g,n,n,n,u,PM_IPTEG_FROM_RL2L3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. ##0C4220000013C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. #723,u,g,n,n,n,u,PM_DATA_FROM_RL2L3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. ##0C4240000023C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. #724,u,g,n,n,n,u,PM_DPTEG_FROM_RL2L3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. ##0C4260000023C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. #725,u,g,n,n,n,u,PM_INST_FROM_RL2L3,The processor's instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. ##0C0300000003C040 The processor's instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. #726,u,g,n,n,n,u,PM_IPTEG_FROM_RL2L3,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. ##0C0320000003C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. #727,u,g,n,n,n,u,PM_DATA_FROM_RL2L3,The processor's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. ##0C0340000003C040 The processor's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. #728,u,g,n,n,n,u,PM_DPTEG_FROM_RL2L3,The processor's data page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. ##0C0360000003C040 The processor's data page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. #729,u,g,n,n,n,u,PM_INST_FROM_RL2L3_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. ##0C0300000013C040 The processor's instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. #730,u,g,n,n,n,u,PM_IPTEG_FROM_RL2L3_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. ##0C0320000013C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. #731,u,g,n,n,n,u,PM_DATA_FROM_RL2L3_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. ##0C0340000023C040 The processor's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. #732,u,g,n,n,n,u,PM_DPTEG_FROM_RL2L3_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. ##0C0360000023C040 The processor's data page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. #733,u,g,n,n,n,u,PM_INST_FROM_RMEM,The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss. ##0D4100000003C040 The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss. #734,u,g,n,n,n,u,PM_IPTEG_FROM_RMEM,The processor's instruction page table entry was reloaded from remote memory (MC slow) due to a demand miss. ##0D4020000003C040 The processor's instruction page table entry was reloaded from remote memory (MC slow) due to a demand miss. #735,u,g,n,n,n,u,PM_DATA_FROM_RMEM,The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss. ##0D4040000003C040 The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss. #736,u,g,n,n,n,u,PM_DPTEG_FROM_RMEM,The processor's data page table entry was reloaded from remote memory (MC slow) due to a demand miss. ##0D4060000003C040 The processor's data page table entry was reloaded from remote memory (MC slow) due to a demand miss. #737,u,g,n,n,n,u,PM_INST_FROM_RMEM_ALL,The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. ##0D4100000013C040 The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. #738,u,g,n,n,n,u,PM_IPTEG_FROM_RMEM_ALL,The processor's instruction page table entry was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. ##0D4020000013C040 The processor's instruction page table entry was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. #739,u,g,n,n,n,u,PM_DATA_FROM_RMEM_ALL,The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. ##0D4040000023C040 The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. #740,u,g,n,n,n,u,PM_DPTEG_FROM_RMEM_ALL,The processor's data page table entry was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. ##0D4060000023C040 The processor's data page table entry was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. #741,u,g,n,n,n,u,PM_IPTEG_FROM_R_OC_CACHE,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss. ##0D8020000003C040 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss. #742,u,g,n,n,n,u,PM_DATA_FROM_R_OC_CACHE,The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache due to a demand miss. ##0D8040000003C040 The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache due to a demand miss. #743,u,g,n,n,n,u,PM_DPTEG_FROM_R_OC_CACHE,The processor's data page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss. ##0D8060000003C040 The processor's data page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss. #744,u,g,n,n,n,u,PM_IPTEG_FROM_R_OC_CACHE_ALL,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. ##0D8020000013C040 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. #745,u,g,n,n,n,u,PM_DATA_FROM_R_OC_CACHE_ALL,The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. ##0D8040000023C040 The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. #746,u,g,n,n,n,u,PM_DPTEG_FROM_R_OC_CACHE_ALL,The processor's data page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. ##0D8060000023C040 The processor's data page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. #747,u,g,n,n,n,u,PM_IPTEG_FROM_R_OC_MEM,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss. ##0DC020000003C040 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss. #748,u,g,n,n,n,u,PM_DATA_FROM_R_OC_MEM,The processor's L1 data cache was reloaded from a remote chip's OpenCapp memory due to a demand miss. ##0DC040000003C040 The processor's L1 data cache was reloaded from a remote chip's OpenCapp memory due to a demand miss. #749,u,g,n,n,n,u,PM_DPTEG_FROM_R_OC_MEM,The processor's data page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss. ##0DC060000003C040 The processor's data page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss. #750,u,g,n,n,n,u,PM_IPTEG_FROM_R_OC_MEM_ALL,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. ##0DC020000013C040 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. #751,u,g,n,n,n,u,PM_DATA_FROM_R_OC_MEM_ALL,The processor's L1 data cache was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. ##0DC040000023C040 The processor's L1 data cache was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. #752,u,g,n,n,n,u,PM_DPTEG_FROM_R_OC_MEM_ALL,The processor's data page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. ##0DC060000023C040 The processor's data page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. #753,u,g,n,n,n,u,PM_INST_FROM_R_OC_ANY,The processor's instruction cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. ##0D8100000003C040 The processor's instruction cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. #754,u,g,n,n,n,u,PM_IPTEG_FROM_R_OC_ANY,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. ##0D8120000003C040 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. #755,u,g,n,n,n,u,PM_DATA_FROM_R_OC_ANY,The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. ##0D8140000003C040 The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. #756,u,g,n,n,n,u,PM_DPTEG_FROM_R_OC_ANY,The processor's data page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. ##0D8160000003C040 The processor's data page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. #757,u,g,n,n,n,u,PM_INST_FROM_R_OC_ANY_ALL,The processor's instruction cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##0D8100000013C040 The processor's instruction cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #758,u,g,n,n,n,u,PM_IPTEG_FROM_R_OC_ANY_ALL,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##0D8120000013C040 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #759,u,g,n,n,n,u,PM_DATA_FROM_R_OC_ANY_ALL,The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##0D8140000023C040 The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #760,u,g,n,n,n,u,PM_DPTEG_FROM_R_OC_ANY_ALL,The processor's data page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##0D8160000023C040 The processor's data page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #761,u,g,n,n,n,u,PM_IPTEG_FROM_DL2_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. ##0E0020000003C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. #762,u,g,n,n,n,u,PM_DATA_FROM_DL2_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. ##0E0040000003C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. #763,u,g,n,n,n,u,PM_DPTEG_FROM_DL2_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. ##0E0060000003C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. #764,u,g,n,n,n,u,PM_IPTEG_FROM_DL2_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. ##0E0020000013C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. #765,u,g,n,n,n,u,PM_DATA_FROM_DL2_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. ##0E0040000023C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. #766,u,g,n,n,n,u,PM_DPTEG_FROM_DL2_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. ##0E0060000023C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. #767,u,g,n,n,n,u,PM_IPTEG_FROM_DL2_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. ##0E4020000003C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. #768,u,g,n,n,n,u,PM_DATA_FROM_DL2_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. ##0E4040000003C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. #769,u,g,n,n,n,u,PM_DPTEG_FROM_DL2_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. ##0E4060000003C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. #770,u,g,n,n,n,u,PM_IPTEG_FROM_DL2_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. ##0E4020000013C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. #771,u,g,n,n,n,u,PM_DATA_FROM_DL2_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. ##0E4040000023C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. #772,u,g,n,n,n,u,PM_DPTEG_FROM_DL2_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. ##0E4060000023C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. #773,u,g,n,n,n,u,PM_INST_FROM_DL2,The processor's instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss. ##0E0100000003C040 The processor's instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss. #774,u,g,n,n,n,u,PM_IPTEG_FROM_DL2,The processor's instruction page table entry was reloaded from another core's L2 from a distant chip due to a demand miss. ##0E0120000003C040 The processor's instruction page table entry was reloaded from another core's L2 from a distant chip due to a demand miss. #775,u,g,n,n,n,u,PM_DATA_FROM_DL2,The processor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss. ##0E0140000003C040 The processor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss. #776,u,g,n,n,n,u,PM_DPTEG_FROM_DL2,The processor's data page table entry was reloaded from another core's L2 from a distant chip due to a demand miss. ##0E0160000003C040 The processor's data page table entry was reloaded from another core's L2 from a distant chip due to a demand miss. #777,u,g,n,n,n,u,PM_INST_FROM_DL2_ALL,The processor's instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. ##0E0100000013C040 The processor's instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. #778,u,g,n,n,n,u,PM_IPTEG_FROM_DL2_ALL,The processor's instruction page table entry was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. ##0E0120000013C040 The processor's instruction page table entry was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. #779,u,g,n,n,n,u,PM_DATA_FROM_DL2_ALL,The processor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. ##0E0140000023C040 The processor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. #780,u,g,n,n,n,u,PM_DPTEG_FROM_DL2_ALL,The processor's data page table entry was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. ##0E0160000023C040 The processor's data page table entry was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. #781,u,g,n,n,n,u,PM_IPTEG_FROM_DL3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. ##0E8020000003C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. #782,u,g,n,n,n,u,PM_DATA_FROM_DL3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. ##0E8040000003C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. #783,u,g,n,n,n,u,PM_DPTEG_FROM_DL3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. ##0E8060000003C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. #784,u,g,n,n,n,u,PM_IPTEG_FROM_DL3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. ##0E8020000013C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. #785,u,g,n,n,n,u,PM_DATA_FROM_DL3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. ##0E8040000023C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. #786,u,g,n,n,n,u,PM_DPTEG_FROM_DL3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. ##0E8060000023C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. #787,u,g,n,n,n,u,PM_IPTEG_FROM_DL3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. ##0EC020000003C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. #788,u,g,n,n,n,u,PM_DATA_FROM_DL3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. ##0EC040000003C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. #789,u,g,n,n,n,u,PM_DPTEG_FROM_DL3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. ##0EC060000003C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. #790,u,g,n,n,n,u,PM_IPTEG_FROM_DL3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. ##0EC020000013C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. #791,u,g,n,n,n,u,PM_DATA_FROM_DL3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. ##0EC040000023C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. #792,u,g,n,n,n,u,PM_DPTEG_FROM_DL3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. ##0EC060000023C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. #793,u,g,n,n,n,u,PM_INST_FROM_DL3,The processor's instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss. ##0E8100000003C040 The processor's instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss. #794,u,g,n,n,n,u,PM_IPTEG_FROM_DL3,The processor's instruction page table entry was reloaded from another core's L3 from a distant chip due to a demand miss. ##0E8120000003C040 The processor's instruction page table entry was reloaded from another core's L3 from a distant chip due to a demand miss. #795,u,g,n,n,n,u,PM_DATA_FROM_DL3,The processor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss. ##0E8140000003C040 The processor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss. #796,u,g,n,n,n,u,PM_DPTEG_FROM_DL3,The processor's data page table entry was reloaded from another core's L3 from a distant chip due to a demand miss. ##0E8160000003C040 The processor's data page table entry was reloaded from another core's L3 from a distant chip due to a demand miss. #797,u,g,n,n,n,u,PM_INST_FROM_DL3_ALL,The processor's instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. ##0E8100000013C040 The processor's instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. #798,u,g,n,n,n,u,PM_IPTEG_FROM_DL3_ALL,The processor's instruction page table entry was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. ##0E8120000013C040 The processor's instruction page table entry was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. #799,u,g,n,n,n,u,PM_DATA_FROM_DL3_ALL,The processor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. ##0E8140000023C040 The processor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. #800,u,g,n,n,n,u,PM_DPTEG_FROM_DL3_ALL,The processor's data page table entry was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. ##0E8160000023C040 The processor's data page table entry was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. #801,u,g,n,n,n,u,PM_IPTEG_FROM_DL2L3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. ##0E0220000003C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. #802,u,g,n,n,n,u,PM_DATA_FROM_DL2L3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. ##0E0240000003C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. #803,u,g,n,n,n,u,PM_DPTEG_FROM_DL2L3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. ##0E0260000003C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. #804,u,g,n,n,n,u,PM_IPTEG_FROM_DL2L3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. ##0E0220000013C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. #805,u,g,n,n,n,u,PM_DATA_FROM_DL2L3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. ##0E0240000023C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. #806,u,g,n,n,n,u,PM_DPTEG_FROM_DL2L3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. ##0E0260000023C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. #807,u,g,n,n,n,u,PM_IPTEG_FROM_DL2L3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. ##0E4220000003C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. #808,u,g,n,n,n,u,PM_DATA_FROM_DL2L3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. ##0E4240000003C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. #809,u,g,n,n,n,u,PM_DPTEG_FROM_DL2L3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. ##0E4260000003C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. #810,u,g,n,n,n,u,PM_IPTEG_FROM_DL2L3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. ##0E4220000013C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. #811,u,g,n,n,n,u,PM_DATA_FROM_DL2L3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. ##0E4240000023C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. #812,u,g,n,n,n,u,PM_DPTEG_FROM_DL2L3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. ##0E4260000023C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. #813,u,g,n,n,n,u,PM_INST_FROM_DL2L3,The processor's instruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. ##0E0300000003C040 The processor's instruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. #814,u,g,n,n,n,u,PM_IPTEG_FROM_DL2L3,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. ##0E0320000003C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. #815,u,g,n,n,n,u,PM_DATA_FROM_DL2L3,The processor's L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. ##0E0340000003C040 The processor's L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. #816,u,g,n,n,n,u,PM_DPTEG_FROM_DL2L3,The processor's data page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. ##0E0360000003C040 The processor's data page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. #817,u,g,n,n,n,u,PM_INST_FROM_DL2L3_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. ##0E0300000013C040 The processor's instruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. #818,u,g,n,n,n,u,PM_IPTEG_FROM_DL2L3_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. ##0E0320000013C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. #819,u,g,n,n,n,u,PM_DATA_FROM_DL2L3_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. ##0E0340000023C040 The processor's L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. #820,u,g,n,n,n,u,PM_DPTEG_FROM_DL2L3_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. ##0E0360000023C040 The processor's data page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. #821,u,g,n,n,n,u,PM_INST_FROM_DMEM,The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss. ##0F4100000003C040 The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss. #822,u,g,n,n,n,u,PM_IPTEG_FROM_DMEM,The processor's instruction page table entry was reloaded from distant memory (MC slow) due to a demand miss. ##0F4020000003C040 The processor's instruction page table entry was reloaded from distant memory (MC slow) due to a demand miss. #823,u,g,n,n,n,u,PM_DATA_FROM_DMEM,The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss. ##0F4040000003C040 The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss. #824,u,g,n,n,n,u,PM_DPTEG_FROM_DMEM,The processor's data page table entry was reloaded from distant memory (MC slow) due to a demand miss. ##0F4060000003C040 The processor's data page table entry was reloaded from distant memory (MC slow) due to a demand miss. #825,u,g,n,n,n,u,PM_INST_FROM_DMEM_ALL,The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. ##0F4100000013C040 The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. #826,u,g,n,n,n,u,PM_IPTEG_FROM_DMEM_ALL,The processor's instruction page table entry was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. ##0F4020000013C040 The processor's instruction page table entry was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. #827,u,g,n,n,n,u,PM_DATA_FROM_DMEM_ALL,The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. ##0F4040000023C040 The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. #828,u,g,n,n,n,u,PM_DPTEG_FROM_DMEM_ALL,The processor's data page table entry was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. ##0F4060000023C040 The processor's data page table entry was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. #829,u,g,n,n,n,u,PM_IPTEG_FROM_D_OC_CACHE,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss. ##0F8020000003C040 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss. #830,u,g,n,n,n,u,PM_DATA_FROM_D_OC_CACHE,The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache due to a demand miss. ##0F8040000003C040 The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache due to a demand miss. #831,u,g,n,n,n,u,PM_DPTEG_FROM_D_OC_CACHE,The processor's data page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss. ##0F8060000003C040 The processor's data page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss. #832,u,g,n,n,n,u,PM_IPTEG_FROM_D_OC_CACHE_ALL,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. ##0F8020000013C040 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. #833,u,g,n,n,n,u,PM_DATA_FROM_D_OC_CACHE_ALL,The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. ##0F8040000023C040 The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. #834,u,g,n,n,n,u,PM_DPTEG_FROM_D_OC_CACHE_ALL,The processor's data page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. ##0F8060000023C040 The processor's data page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. #835,u,g,n,n,n,u,PM_IPTEG_FROM_D_OC_MEM,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss. ##0FC020000003C040 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss. #836,u,g,n,n,n,u,PM_DATA_FROM_D_OC_MEM,The processor's L1 data cache was reloaded from a distant chip's OpenCapp memory due to a demand miss. ##0FC040000003C040 The processor's L1 data cache was reloaded from a distant chip's OpenCapp memory due to a demand miss. #837,u,g,n,n,n,u,PM_DPTEG_FROM_D_OC_MEM,The processor's data page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss. ##0FC060000003C040 The processor's data page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss. #838,u,g,n,n,n,u,PM_IPTEG_FROM_D_OC_MEM_ALL,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. ##0FC020000013C040 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. #839,u,g,n,n,n,u,PM_DATA_FROM_D_OC_MEM_ALL,The processor's L1 data cache was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. ##0FC040000023C040 The processor's L1 data cache was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. #840,u,g,n,n,n,u,PM_DPTEG_FROM_D_OC_MEM_ALL,The processor's data page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. ##0FC060000023C040 The processor's data page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. #841,u,g,n,n,n,u,PM_INST_FROM_D_OC_ANY,The processor's instruction cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. ##0F8100000003C040 The processor's instruction cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. #842,u,g,n,n,n,u,PM_IPTEG_FROM_D_OC_ANY,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. ##0F8120000003C040 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. #843,u,g,n,n,n,u,PM_DATA_FROM_D_OC_ANY,The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. ##0F8140000003C040 The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. #844,u,g,n,n,n,u,PM_DPTEG_FROM_D_OC_ANY,The processor's data page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. ##0F8160000003C040 The processor's data page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. #845,u,g,n,n,n,u,PM_INST_FROM_D_OC_ANY_ALL,The processor's instruction cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##0F8100000013C040 The processor's instruction cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #846,u,g,n,n,n,u,PM_IPTEG_FROM_D_OC_ANY_ALL,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##0F8120000013C040 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #847,u,g,n,n,n,u,PM_DATA_FROM_D_OC_ANY_ALL,The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##0F8140000023C040 The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #848,u,g,n,n,n,u,PM_DPTEG_FROM_D_OC_ANY_ALL,The processor's data page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##0F8160000023C040 The processor's data page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #849,u,g,n,n,n,u,PM_INST_FROM_ONCHIP_CACHE,The processor's instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss. ##080B00000003C040 The processor's instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss. #850,u,g,n,n,n,u,PM_IPTEG_FROM_ONCHIP_CACHE,The processor's instruction page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss. ##080B20000003C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss. #851,u,g,n,n,n,u,PM_DATA_FROM_ONCHIP_CACHE,The processor's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss. ##080B40000003C040 The processor's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss. #852,u,g,n,n,n,u,PM_DPTEG_FROM_ONCHIP_CACHE,The processor's data page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss. ##080B60000003C040 The processor's data page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss. #853,u,g,n,n,n,u,PM_INST_FROM_ONCHIP_CACHE_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. ##080B00000013C040 The processor's instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. #854,u,g,n,n,n,u,PM_IPTEG_FROM_ONCHIP_CACHE_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. ##080B20000013C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. #855,u,g,n,n,n,u,PM_DATA_FROM_ONCHIP_CACHE_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. ##080B40000023C040 The processor's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. #856,u,g,n,n,n,u,PM_DPTEG_FROM_ONCHIP_CACHE_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. ##080B60000023C040 The processor's data page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. #857,u,g,n,n,n,u,PM_INST_FROM_OFFCHIP_CACHE,The processor's instruction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss. ##0C0B00000003C040 The processor's instruction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss. #858,u,g,n,n,n,u,PM_IPTEG_FROM_OFFCHIP_CACHE,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss. ##0C0B20000003C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss. #859,u,g,n,n,n,u,PM_DATA_FROM_OFFCHIP_CACHE,The processor's L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss. ##0C0B40000003C040 The processor's L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss. #860,u,g,n,n,n,u,PM_DPTEG_FROM_OFFCHIP_CACHE,The processor's data page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss. ##0C0B60000003C040 The processor's data page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss. #861,u,g,n,n,n,u,PM_INST_FROM_OFFCHIP_CACHE_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. ##0C0B00000013C040 The processor's instruction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. #862,u,g,n,n,n,u,PM_IPTEG_FROM_OFFCHIP_CACHE_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. ##0C0B20000013C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. #863,u,g,n,n,n,u,PM_DATA_FROM_OFFCHIP_CACHE_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. ##0C0B40000023C040 The processor's L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. #864,u,g,n,n,n,u,PM_DPTEG_FROM_OFFCHIP_CACHE_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. ##0C0B60000023C040 The processor's data page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. #865,u,g,n,n,n,u,PM_INST_FROM_ANY_MEMORY,The processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss. ##095900000003C040 The processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss. #866,u,g,n,n,n,u,PM_IPTEG_FROM_ANY_MEMORY,The processor's instruction page table entry was reloaded from any chip's memory (MC slow) due to a demand miss. ##095820000003C040 The processor's instruction page table entry was reloaded from any chip's memory (MC slow) due to a demand miss. #867,u,g,n,n,n,u,PM_DATA_FROM_ANY_MEMORY,The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss. ##095840000003C040 The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss. #868,u,g,n,n,n,u,PM_DPTEG_FROM_ANY_MEMORY,The processor's data page table entry was reloaded from any chip's memory (MC slow) due to a demand miss. ##095860000003C040 The processor's data page table entry was reloaded from any chip's memory (MC slow) due to a demand miss. #869,u,g,n,n,n,u,PM_INST_FROM_ANY_MEMORY_ALL,The processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. ##095900000013C040 The processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. #870,u,g,n,n,n,u,PM_IPTEG_FROM_ANY_MEMORY_ALL,The processor's instruction page table entry was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. ##095820000013C040 The processor's instruction page table entry was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. #871,u,g,n,n,n,u,PM_DATA_FROM_ANY_MEMORY_ALL,The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. ##095840000023C040 The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. #872,u,g,n,n,n,u,PM_DPTEG_FROM_ANY_MEMORY_ALL,The processor's data page table entry was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. ##095860000023C040 The processor's data page table entry was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. #873,u,g,n,n,m,u,PM_MRK_INST_FROM_L2,The processor's instruction cache was reloaded from the local core's L2 due to a demand miss for a marked instruction. ##000300000003C142 The processor's instruction cache was reloaded from the local core's L2 due to a demand miss for a marked instruction. #874,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2,The processor's instruction page table entry was reloaded from the local core's L2 due to a demand miss for a marked instruction. ##000320000003C142 The processor's instruction page table entry was reloaded from the local core's L2 due to a demand miss for a marked instruction. #875,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2,The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss for a marked instruction. ##000340000003C142 The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss for a marked instruction. #876,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2,The processor's data page table entry was reloaded from the local core's L2 due to a demand miss for a marked instruction. ##000360000003C142 The processor's data page table entry was reloaded from the local core's L2 due to a demand miss for a marked instruction. #877,u,g,n,n,m,u,PM_MRK_INST_FROM_L2_ALL,The processor's instruction cache was reloaded from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##000300000013C142 The processor's instruction cache was reloaded from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #878,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_ALL,The processor's instruction page table entry was reloaded from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##000320000013C142 The processor's instruction page table entry was reloaded from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #879,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_ALL,The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##000340000023C142 The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #880,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_ALL,The processor's data page table entry was reloaded from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##000360000023C142 The processor's data page table entry was reloaded from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #881,u,g,n,n,m,u,PM_MRK_INST_FROM_L1MISS,The processor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss for a marked instruction. ##003F00000003C142 The processor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss for a marked instruction. #882,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L1MISS,The processor's instruction page table entry was reloaded from a source beyond the local core's L1 due to a demand miss for a marked instruction. ##003F20000003C142 The processor's instruction page table entry was reloaded from a source beyond the local core's L1 due to a demand miss for a marked instruction. #883,u,g,n,n,m,u,PM_MRK_DATA_FROM_L1MISS,The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss for a marked instruction. ##003F40000003C142 The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss for a marked instruction. #884,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L1MISS,The processor's data page table entry was reloaded from a source beyond the local core's L1 due to a demand miss for a marked instruction. ##003F60000003C142 The processor's data page table entry was reloaded from a source beyond the local core's L1 due to a demand miss for a marked instruction. #885,u,g,n,n,m,u,PM_MRK_INST_FROM_L1MISS_ALL,The processor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload for a marked instruction. ##003F00000013C142 The processor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload for a marked instruction. #886,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L1MISS_ALL,The processor's instruction page table entry was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload for a marked instruction. ##003F20000013C142 The processor's instruction page table entry was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload for a marked instruction. #887,u,g,n,n,m,u,PM_MRK_DATA_FROM_L1MISS_ALL,The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload for a marked instruction. ##003F40000023C142 The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload for a marked instruction. #888,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L1MISS_ALL,The processor's data page table entry was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload for a marked instruction. ##003F60000023C142 The processor's data page table entry was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload for a marked instruction. #889,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_NO_CONFLICT,The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss for a marked instruction. ##000020000003C142 The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss for a marked instruction. #890,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_NO_CONFLICT,The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss for a marked instruction. ##000040000003C142 The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss for a marked instruction. #891,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_NO_CONFLICT,The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss for a marked instruction. ##000060000003C142 The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss for a marked instruction. #892,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_NO_CONFLICT_ALL,The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##000020000013C142 The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #893,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_NO_CONFLICT_ALL,The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##000040000023C142 The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #894,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_NO_CONFLICT_ALL,The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##000060000023C142 The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #895,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_MEPF,The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss for a marked instruction. ##004020000003C142 The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss for a marked instruction. #896,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_MEPF,The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss for a marked instruction. ##004040000003C142 The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss for a marked instruction. #897,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_MEPF,The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss for a marked instruction. ##004060000003C142 The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss for a marked instruction. #898,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_MEPF_ALL,The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##004020000013C142 The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #899,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_MEPF_ALL,The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##004040000023C142 The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #900,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_MEPF_ALL,The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##004060000023C142 The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #901,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_LDHITST_CONFLICT,The processor's instruction page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. ##008020000003C142 The processor's instruction page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. #902,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_LDHITST_CONFLICT,The processor's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. ##008040000003C142 The processor's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. #903,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_LDHITST_CONFLICT,The processor's data page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. ##008060000003C142 The processor's data page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. #904,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_LDHITST_CONFLICT_ALL,The processor's instruction page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##008020000013C142 The processor's instruction page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #905,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_LDHITST_CONFLICT_ALL,The processor's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##008040000023C142 The processor's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #906,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_LDHITST_CONFLICT_ALL,The processor's data page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##008060000023C142 The processor's data page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #907,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_OTHER_CONFLICT,The processor's instruction page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. ##00C020000003C142 The processor's instruction page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. #908,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_OTHER_CONFLICT,The processor's L1 data cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. ##00C040000003C142 The processor's L1 data cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. #909,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_OTHER_CONFLICT,The processor's data page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. ##00C060000003C142 The processor's data page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. #910,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_OTHER_CONFLICT_ALL,The processor's instruction page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##00C020000013C142 The processor's instruction page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #911,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_OTHER_CONFLICT_ALL,The processor's L1 data cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##00C040000023C142 The processor's L1 data cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #912,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_OTHER_CONFLICT_ALL,The processor's data page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##00C060000023C142 The processor's data page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #913,u,g,n,n,m,u,PM_MRK_INST_FROM_L2MISS,The processor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction. ##000380000003C142 The processor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction. #914,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2MISS,The processor's instruction page table entry was reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction. ##0003A0000003C142 The processor's instruction page table entry was reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction. #915,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2MISS,The processor's data page table entry was reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction. ##0003E0000003C142 The processor's data page table entry was reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction. #916,u,g,n,n,m,u,PM_MRK_INST_FROM_L2MISS_ALL,The processor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##000380000013C142 The processor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #917,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2MISS_ALL,The processor's instruction page table entry was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##0003A0000013C142 The processor's instruction page table entry was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #918,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2MISS_ALL,The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##0003C0000023C142 The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #919,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2MISS_ALL,The processor's data page table entry was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##0003E0000023C142 The processor's data page table entry was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #920,u,g,n,n,m,u,PM_MRK_INST_FROM_L3,The processor's instruction cache was reloaded from the local core's L3 due to a demand miss for a marked instruction. ##010300000003C142 The processor's instruction cache was reloaded from the local core's L3 due to a demand miss for a marked instruction. #921,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3,The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss for a marked instruction. ##010320000003C142 The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss for a marked instruction. #922,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3,The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss for a marked instruction. ##010340000003C142 The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss for a marked instruction. #923,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3,The processor's data page table entry was reloaded from the local core's L3 due to a demand miss for a marked instruction. ##010360000003C142 The processor's data page table entry was reloaded from the local core's L3 due to a demand miss for a marked instruction. #924,u,g,n,n,m,u,PM_MRK_INST_FROM_L3_ALL,The processor's instruction cache was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##010300000013C142 The processor's instruction cache was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #925,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_ALL,The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##010320000013C142 The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #926,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_ALL,The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##010340000023C142 The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #927,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_ALL,The processor's data page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##010360000023C142 The processor's data page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #928,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_NO_CONFLICT,The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss for a marked instruction. ##010020000003C142 The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss for a marked instruction. #929,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_NO_CONFLICT,The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss for a marked instruction. ##010040000003C142 The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss for a marked instruction. #930,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_NO_CONFLICT,The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss for a marked instruction. ##010060000003C142 The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss for a marked instruction. #931,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_NO_CONFLICT_ALL,The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##010020000013C142 The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #932,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_NO_CONFLICT_ALL,The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##010040000023C142 The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #933,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_NO_CONFLICT_ALL,The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##010060000023C142 The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #934,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_MEPF,The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss for a marked instruction. ##014020000003C142 The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss for a marked instruction. #935,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_MEPF,The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss for a marked instruction. ##014040000003C142 The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss for a marked instruction. #936,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_MEPF,The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss for a marked instruction. ##014060000003C142 The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss for a marked instruction. #937,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_MEPF_ALL,The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##014020000013C142 The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #938,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_MEPF_ALL,The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##014040000023C142 The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #939,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_MEPF_ALL,The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##014060000023C142 The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #940,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_CONFLICT,The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss for a marked instruction. ##01C020000003C142 The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss for a marked instruction. #941,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_CONFLICT,The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss for a marked instruction. ##01C040000003C142 The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss for a marked instruction. #942,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_CONFLICT,The processor's data page table entry was reloaded from the local core's L3 due to a demand miss for a marked instruction. ##01C060000003C142 The processor's data page table entry was reloaded from the local core's L3 due to a demand miss for a marked instruction. #943,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_CONFLICT_ALL,The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##01C020000013C142 The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #944,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_CONFLICT_ALL,The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##01C040000023C142 The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #945,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_CONFLICT_ALL,The processor's data page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##01C060000023C142 The processor's data page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #946,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3MISS,The processor's instruction page table entry was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction. ##0007A0000003C142 The processor's instruction page table entry was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction. #947,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3MISS,The processor's data page table entry was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction. ##0007E0000003C142 The processor's data page table entry was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction. #948,u,g,n,n,m,u,PM_MRK_INST_FROM_L3MISS_ALL,The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##000780000013C142 The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #949,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3MISS_ALL,The processor's instruction page table entry was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##0007A0000013C142 The processor's instruction page table entry was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #950,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3MISS_ALL,The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##0007C0000023C142 The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #951,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3MISS_ALL,The processor's data page table entry was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##0007E0000023C142 The processor's data page table entry was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #952,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. ##080020000003C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. #953,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. ##080040000003C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. #954,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. ##080060000003C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. #955,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080020000013C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #956,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080040000023C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #957,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080060000023C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #958,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. ##084020000003C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. #959,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. ##084040000003C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. #960,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. ##084060000003C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. #961,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##084020000013C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #962,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##084040000023C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #963,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##084060000023C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #964,u,g,n,n,m,u,PM_MRK_INST_FROM_L21_REGENT,The processor's instruction cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. ##080100000003C142 The processor's instruction cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. #965,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT,The processor's instruction page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. ##080120000003C142 The processor's instruction page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. #966,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT,The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. ##080140000003C142 The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. #967,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT,The processor's data page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. ##080160000003C142 The processor's data page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. #968,u,g,n,n,m,u,PM_MRK_INST_FROM_L21_REGENT_ALL,The processor's instruction cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080100000013C142 The processor's instruction cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #969,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_ALL,The processor's instruction page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080120000013C142 The processor's instruction page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #970,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_ALL,The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080140000023C142 The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #971,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_ALL,The processor's data page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080160000023C142 The processor's data page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #972,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##088020000003C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. #973,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##088040000003C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. #974,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##088060000003C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. #975,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##088020000013C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #976,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##088040000023C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #977,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##088060000023C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #978,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##08C020000003C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. #979,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##08C040000003C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. #980,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##08C060000003C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. #981,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##08C020000013C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #982,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##08C040000023C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #983,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##08C060000023C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #984,u,g,n,n,m,u,PM_MRK_INST_FROM_L31_REGENT,The processor's instruction cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##088100000003C142 The processor's instruction cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. #985,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT,The processor's instruction page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##088120000003C142 The processor's instruction page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. #986,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT,The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##088140000003C142 The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. #987,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT,The processor's data page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##088160000003C142 The processor's data page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. #988,u,g,n,n,m,u,PM_MRK_INST_FROM_L31_REGENT_ALL,The processor's instruction cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##088100000013C142 The processor's instruction cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #989,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_ALL,The processor's instruction page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##088120000013C142 The processor's instruction page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #990,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_ALL,The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##088140000023C142 The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #991,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_ALL,The processor's data page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##088160000023C142 The processor's data page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #992,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##080220000003C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. #993,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##080240000003C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. #994,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##080260000003C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. #995,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080220000013C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #996,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080240000023C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #997,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080260000023C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #998,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##084220000003C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. #999,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##084240000003C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. #1000,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##084260000003C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. #1001,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##084220000013C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #1002,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##084240000023C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #1003,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##084260000023C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #1004,u,g,n,n,m,u,PM_MRK_INST_FROM_REGENT_L2L3,The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##080300000003C142 The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. #1005,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3,The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##080320000003C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. #1006,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3,The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##080340000003C142 The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. #1007,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3,The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##080360000003C142 The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. #1008,u,g,n,n,m,u,PM_MRK_INST_FROM_REGENT_L2L3_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080300000013C142 The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #1009,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080320000013C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #1010,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080340000023C142 The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #1011,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080360000023C142 The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #1012,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0020000003C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. #1013,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0040000003C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. #1014,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0060000003C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. #1015,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0020000013C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1016,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0040000023C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1017,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0060000023C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1018,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A4020000003C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. #1019,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A4040000003C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. #1020,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A4060000003C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. #1021,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A4020000013C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1022,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A4040000023C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1023,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A4060000023C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1024,u,g,n,n,m,u,PM_MRK_INST_FROM_L21_NON_REGENT,The processor's instruction cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0100000003C142 The processor's instruction cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. #1025,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT,The processor's instruction page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0120000003C142 The processor's instruction page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. #1026,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT,The processor's L1 data cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0140000003C142 The processor's L1 data cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. #1027,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT,The processor's data page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0160000003C142 The processor's data page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. #1028,u,g,n,n,m,u,PM_MRK_INST_FROM_L21_NON_REGENT_ALL,The processor's instruction cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0100000013C142 The processor's instruction cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1029,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_ALL,The processor's instruction page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0120000013C142 The processor's instruction page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1030,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_ALL,The processor's L1 data cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0140000023C142 The processor's L1 data cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1031,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_ALL,The processor's data page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0160000023C142 The processor's data page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1032,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A8020000003C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1033,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A8040000003C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1034,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A8060000003C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1035,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A8020000013C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1036,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A8040000023C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1037,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A8060000023C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1038,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0AC020000003C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1039,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0AC040000003C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1040,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0AC060000003C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1041,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0AC020000013C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1042,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0AC040000023C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1043,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0AC060000023C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1044,u,g,n,n,m,u,PM_MRK_INST_FROM_L31_NON_REGENT,The processor's instruction cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A8100000003C142 The processor's instruction cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1045,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT,The processor's instruction page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A8120000003C142 The processor's instruction page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1046,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT,The processor's L1 data cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A8140000003C142 The processor's L1 data cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1047,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT,The processor's data page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A8160000003C142 The processor's data page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1048,u,g,n,n,m,u,PM_MRK_INST_FROM_L31_NON_REGENT_ALL,The processor's instruction cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A8100000013C142 The processor's instruction cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1049,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_ALL,The processor's instruction page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A8120000013C142 The processor's instruction page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1050,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_ALL,The processor's L1 data cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A8140000023C142 The processor's L1 data cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1051,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_ALL,The processor's data page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A8160000023C142 The processor's data page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1052,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0220000003C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1053,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0240000003C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1054,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0260000003C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1055,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0220000013C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1056,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0240000023C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1057,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0260000023C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1058,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A4220000003C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1059,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A4240000003C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1060,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A4260000003C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1061,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A4220000013C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1062,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A4240000023C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1063,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A4260000023C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1064,u,g,n,n,m,u,PM_MRK_INST_FROM_NON_REGENT_L2L3,The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0300000003C142 The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1065,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3,The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0320000003C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1066,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3,The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0340000003C142 The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1067,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3,The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0360000003C142 The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1068,u,g,n,n,m,u,PM_MRK_INST_FROM_NON_REGENT_L2L3_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0300000013C142 The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1069,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0320000013C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1070,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0340000023C142 The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1071,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0360000023C142 The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1072,u,g,n,n,m,u,PM_MRK_INST_FROM_LMEM,The processor's instruction cache was reloaded from the local chip's memory due to a demand miss for a marked instruction. ##094100000003C142 The processor's instruction cache was reloaded from the local chip's memory due to a demand miss for a marked instruction. #1073,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_LMEM,The processor's instruction page table entry was reloaded from the local chip's memory due to a demand miss for a marked instruction. ##094020000003C142 The processor's instruction page table entry was reloaded from the local chip's memory due to a demand miss for a marked instruction. #1074,u,g,n,n,m,u,PM_MRK_DATA_FROM_LMEM,The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss for a marked instruction. ##094040000003C142 The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss for a marked instruction. #1075,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_LMEM,The processor's data page table entry was reloaded from the local chip's memory due to a demand miss for a marked instruction. ##094060000003C142 The processor's data page table entry was reloaded from the local chip's memory due to a demand miss for a marked instruction. #1076,u,g,n,n,m,u,PM_MRK_INST_FROM_LMEM_ALL,The processor's instruction cache was reloaded from the local chip's memory due to a demand miss or prefetch reload for a marked instruction. ##094100000013C142 The processor's instruction cache was reloaded from the local chip's memory due to a demand miss or prefetch reload for a marked instruction. #1077,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_LMEM_ALL,The processor's instruction page table entry was reloaded from the local chip's memory due to a demand miss or prefetch reload for a marked instruction. ##094020000013C142 The processor's instruction page table entry was reloaded from the local chip's memory due to a demand miss or prefetch reload for a marked instruction. #1078,u,g,n,n,m,u,PM_MRK_DATA_FROM_LMEM_ALL,The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss or prefetch reload for a marked instruction. ##094040000023C142 The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss or prefetch reload for a marked instruction. #1079,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_LMEM_ALL,The processor's data page table entry was reloaded from the local chip's memory due to a demand miss or prefetch reload for a marked instruction. ##094060000023C142 The processor's data page table entry was reloaded from the local chip's memory due to a demand miss or prefetch reload for a marked instruction. #1080,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_CACHE,The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss for a marked instruction. ##098020000003C142 The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss for a marked instruction. #1081,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_CACHE,The processor's L1 data cache was reloaded from the local chip's OpenCapp cache due to a demand miss for a marked instruction. ##098040000003C142 The processor's L1 data cache was reloaded from the local chip's OpenCapp cache due to a demand miss for a marked instruction. #1082,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_CACHE,The processor's data page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss for a marked instruction. ##098060000003C142 The processor's data page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss for a marked instruction. #1083,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_CACHE_ALL,The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. ##098020000013C142 The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. #1084,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_CACHE_ALL,The processor's L1 data cache was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. ##098040000023C142 The processor's L1 data cache was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. #1085,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_CACHE_ALL,The processor's data page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. ##098060000023C142 The processor's data page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. #1086,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_MEM,The processor's instruction page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss for a marked instruction. ##09C020000003C142 The processor's instruction page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss for a marked instruction. #1087,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_MEM,The processor's L1 data cache was reloaded from the local chip's OpenCapp memory due to a demand miss for a marked instruction. ##09C040000003C142 The processor's L1 data cache was reloaded from the local chip's OpenCapp memory due to a demand miss for a marked instruction. #1088,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_MEM,The processor's data page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss for a marked instruction. ##09C060000003C142 The processor's data page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss for a marked instruction. #1089,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_MEM_ALL,The processor's instruction page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. ##09C020000013C142 The processor's instruction page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. #1090,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_MEM_ALL,The processor's L1 data cache was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. ##09C040000023C142 The processor's L1 data cache was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. #1091,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_MEM_ALL,The processor's data page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. ##09C060000023C142 The processor's data page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. #1092,u,g,n,n,m,u,PM_MRK_INST_FROM_L_OC_ANY,The processor's instruction cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##098100000003C142 The processor's instruction cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1093,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_ANY,The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##098120000003C142 The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1094,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_ANY,The processor's L1 data cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##098140000003C142 The processor's L1 data cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1095,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_ANY,The processor's data page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##098160000003C142 The processor's data page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1096,u,g,n,n,m,u,PM_MRK_INST_FROM_L_OC_ANY_ALL,The processor's instruction cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##098100000013C142 The processor's instruction cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1097,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_ANY_ALL,The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##098120000013C142 The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1098,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_ANY_ALL,The processor's L1 data cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##098140000023C142 The processor's L1 data cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1099,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_ANY_ALL,The processor's data page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##098160000023C142 The processor's data page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1100,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. ##0C0020000003C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. #1101,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. ##0C0040000003C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. #1102,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. ##0C0060000003C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. #1103,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0020000013C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1104,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0040000023C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1105,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0060000023C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1106,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. ##0C4020000003C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. #1107,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. ##0C4040000003C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. #1108,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. ##0C4060000003C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. #1109,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C4020000013C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1110,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C4040000023C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1111,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C4060000023C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1112,u,g,n,n,m,u,PM_MRK_INST_FROM_RL2,The processor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss for a marked instruction. ##0C0100000003C142 The processor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss for a marked instruction. #1113,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2,The processor's instruction page table entry was reloaded from another core's L2 from a remote chip due to a demand miss for a marked instruction. ##0C0120000003C142 The processor's instruction page table entry was reloaded from another core's L2 from a remote chip due to a demand miss for a marked instruction. #1114,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2,The processor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss for a marked instruction. ##0C0140000003C142 The processor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss for a marked instruction. #1115,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2,The processor's data page table entry was reloaded from another core's L2 from a remote chip due to a demand miss for a marked instruction. ##0C0160000003C142 The processor's data page table entry was reloaded from another core's L2 from a remote chip due to a demand miss for a marked instruction. #1116,u,g,n,n,m,u,PM_MRK_INST_FROM_RL2_ALL,The processor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0100000013C142 The processor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1117,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_ALL,The processor's instruction page table entry was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0120000013C142 The processor's instruction page table entry was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1118,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_ALL,The processor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0140000023C142 The processor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1119,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_ALL,The processor's data page table entry was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0160000023C142 The processor's data page table entry was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1120,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. ##0C8020000003C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. #1121,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. ##0C8040000003C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. #1122,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. ##0C8060000003C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. #1123,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C8020000013C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1124,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C8040000023C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1125,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C8060000023C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1126,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. ##0CC020000003C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. #1127,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. ##0CC040000003C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. #1128,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. ##0CC060000003C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. #1129,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0CC020000013C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1130,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0CC040000023C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1131,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0CC060000023C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1132,u,g,n,n,m,u,PM_MRK_INST_FROM_RL3,The processor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss for a marked instruction. ##0C8100000003C142 The processor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss for a marked instruction. #1133,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3,The processor's instruction page table entry was reloaded from another core's L3 from a remote chip due to a demand miss for a marked instruction. ##0C8120000003C142 The processor's instruction page table entry was reloaded from another core's L3 from a remote chip due to a demand miss for a marked instruction. #1134,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3,The processor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss for a marked instruction. ##0C8140000003C142 The processor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss for a marked instruction. #1135,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3,The processor's data page table entry was reloaded from another core's L3 from a remote chip due to a demand miss for a marked instruction. ##0C8160000003C142 The processor's data page table entry was reloaded from another core's L3 from a remote chip due to a demand miss for a marked instruction. #1136,u,g,n,n,m,u,PM_MRK_INST_FROM_RL3_ALL,The processor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C8100000013C142 The processor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1137,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_ALL,The processor's instruction page table entry was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C8120000013C142 The processor's instruction page table entry was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1138,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_ALL,The processor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C8140000023C142 The processor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1139,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_ALL,The processor's data page table entry was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C8160000023C142 The processor's data page table entry was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1140,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. ##0C0220000003C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. #1141,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. ##0C0240000003C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. #1142,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. ##0C0260000003C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. #1143,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0220000013C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1144,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0240000023C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1145,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0260000023C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1146,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. ##0C4220000003C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. #1147,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. ##0C4240000003C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. #1148,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. ##0C4260000003C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. #1149,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C4220000013C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1150,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C4240000023C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1151,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C4260000023C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1152,u,g,n,n,m,u,PM_MRK_INST_FROM_RL2L3,The processor's instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. ##0C0300000003C142 The processor's instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. #1153,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. ##0C0320000003C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. #1154,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3,The processor's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. ##0C0340000003C142 The processor's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. #1155,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3,The processor's data page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. ##0C0360000003C142 The processor's data page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. #1156,u,g,n,n,m,u,PM_MRK_INST_FROM_RL2L3_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0300000013C142 The processor's instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1157,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0320000013C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1158,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0340000023C142 The processor's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1159,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0360000023C142 The processor's data page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1160,u,g,n,n,m,u,PM_MRK_INST_FROM_RMEM,The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss for a marked instruction. ##0D4100000003C142 The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss for a marked instruction. #1161,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RMEM,The processor's instruction page table entry was reloaded from remote memory (MC slow) due to a demand miss for a marked instruction. ##0D4020000003C142 The processor's instruction page table entry was reloaded from remote memory (MC slow) due to a demand miss for a marked instruction. #1162,u,g,n,n,m,u,PM_MRK_DATA_FROM_RMEM,The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss for a marked instruction. ##0D4040000003C142 The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss for a marked instruction. #1163,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RMEM,The processor's data page table entry was reloaded from remote memory (MC slow) due to a demand miss for a marked instruction. ##0D4060000003C142 The processor's data page table entry was reloaded from remote memory (MC slow) due to a demand miss for a marked instruction. #1164,u,g,n,n,m,u,PM_MRK_INST_FROM_RMEM_ALL,The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##0D4100000013C142 The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1165,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RMEM_ALL,The processor's instruction page table entry was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##0D4020000013C142 The processor's instruction page table entry was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1166,u,g,n,n,m,u,PM_MRK_DATA_FROM_RMEM_ALL,The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##0D4040000023C142 The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1167,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RMEM_ALL,The processor's data page table entry was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##0D4060000023C142 The processor's data page table entry was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1168,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_CACHE,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss for a marked instruction. ##0D8020000003C142 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss for a marked instruction. #1169,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_CACHE,The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache due to a demand miss for a marked instruction. ##0D8040000003C142 The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache due to a demand miss for a marked instruction. #1170,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_CACHE,The processor's data page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss for a marked instruction. ##0D8060000003C142 The processor's data page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss for a marked instruction. #1171,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_CACHE_ALL,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. ##0D8020000013C142 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. #1172,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_CACHE_ALL,The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. ##0D8040000023C142 The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. #1173,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_CACHE_ALL,The processor's data page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. ##0D8060000023C142 The processor's data page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. #1174,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_MEM,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss for a marked instruction. ##0DC020000003C142 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss for a marked instruction. #1175,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_MEM,The processor's L1 data cache was reloaded from a remote chip's OpenCapp memory due to a demand miss for a marked instruction. ##0DC040000003C142 The processor's L1 data cache was reloaded from a remote chip's OpenCapp memory due to a demand miss for a marked instruction. #1176,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_MEM,The processor's data page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss for a marked instruction. ##0DC060000003C142 The processor's data page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss for a marked instruction. #1177,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_MEM_ALL,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. ##0DC020000013C142 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. #1178,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_MEM_ALL,The processor's L1 data cache was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. ##0DC040000023C142 The processor's L1 data cache was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. #1179,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_MEM_ALL,The processor's data page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. ##0DC060000023C142 The processor's data page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. #1180,u,g,n,n,m,u,PM_MRK_INST_FROM_R_OC_ANY,The processor's instruction cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##0D8100000003C142 The processor's instruction cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1181,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_ANY,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##0D8120000003C142 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1182,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_ANY,The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##0D8140000003C142 The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1183,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_ANY,The processor's data page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##0D8160000003C142 The processor's data page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1184,u,g,n,n,m,u,PM_MRK_INST_FROM_R_OC_ANY_ALL,The processor's instruction cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##0D8100000013C142 The processor's instruction cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1185,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_ANY_ALL,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##0D8120000013C142 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1186,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_ANY_ALL,The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##0D8140000023C142 The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1187,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_ANY_ALL,The processor's data page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##0D8160000023C142 The processor's data page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1188,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. ##0E0020000003C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. #1189,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. ##0E0040000003C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. #1190,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. ##0E0060000003C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. #1191,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0020000013C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1192,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0040000023C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1193,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0060000023C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1194,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. ##0E4020000003C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. #1195,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. ##0E4040000003C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. #1196,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. ##0E4060000003C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. #1197,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E4020000013C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1198,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E4040000023C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1199,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E4060000023C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1200,u,g,n,n,m,u,PM_MRK_INST_FROM_DL2,The processor's instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss for a marked instruction. ##0E0100000003C142 The processor's instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss for a marked instruction. #1201,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2,The processor's instruction page table entry was reloaded from another core's L2 from a distant chip due to a demand miss for a marked instruction. ##0E0120000003C142 The processor's instruction page table entry was reloaded from another core's L2 from a distant chip due to a demand miss for a marked instruction. #1202,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2,The processor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss for a marked instruction. ##0E0140000003C142 The processor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss for a marked instruction. #1203,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2,The processor's data page table entry was reloaded from another core's L2 from a distant chip due to a demand miss for a marked instruction. ##0E0160000003C142 The processor's data page table entry was reloaded from another core's L2 from a distant chip due to a demand miss for a marked instruction. #1204,u,g,n,n,m,u,PM_MRK_INST_FROM_DL2_ALL,The processor's instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0100000013C142 The processor's instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1205,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_ALL,The processor's instruction page table entry was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0120000013C142 The processor's instruction page table entry was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1206,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_ALL,The processor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0140000023C142 The processor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1207,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_ALL,The processor's data page table entry was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0160000023C142 The processor's data page table entry was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1208,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. ##0E8020000003C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. #1209,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. ##0E8040000003C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. #1210,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. ##0E8060000003C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. #1211,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E8020000013C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1212,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E8040000023C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1213,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E8060000023C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1214,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. ##0EC020000003C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. #1215,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. ##0EC040000003C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. #1216,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. ##0EC060000003C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. #1217,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0EC020000013C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1218,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0EC040000023C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1219,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0EC060000023C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1220,u,g,n,n,m,u,PM_MRK_INST_FROM_DL3,The processor's instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss for a marked instruction. ##0E8100000003C142 The processor's instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss for a marked instruction. #1221,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3,The processor's instruction page table entry was reloaded from another core's L3 from a distant chip due to a demand miss for a marked instruction. ##0E8120000003C142 The processor's instruction page table entry was reloaded from another core's L3 from a distant chip due to a demand miss for a marked instruction. #1222,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3,The processor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss for a marked instruction. ##0E8140000003C142 The processor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss for a marked instruction. #1223,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3,The processor's data page table entry was reloaded from another core's L3 from a distant chip due to a demand miss for a marked instruction. ##0E8160000003C142 The processor's data page table entry was reloaded from another core's L3 from a distant chip due to a demand miss for a marked instruction. #1224,u,g,n,n,m,u,PM_MRK_INST_FROM_DL3_ALL,The processor's instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E8100000013C142 The processor's instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1225,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_ALL,The processor's instruction page table entry was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E8120000013C142 The processor's instruction page table entry was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1226,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_ALL,The processor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E8140000023C142 The processor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1227,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_ALL,The processor's data page table entry was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E8160000023C142 The processor's data page table entry was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1228,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. ##0E0220000003C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. #1229,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. ##0E0240000003C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. #1230,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. ##0E0260000003C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. #1231,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0220000013C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1232,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0240000023C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1233,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0260000023C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1234,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. ##0E4220000003C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. #1235,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. ##0E4240000003C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. #1236,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. ##0E4260000003C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. #1237,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E4220000013C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1238,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E4240000023C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1239,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E4260000023C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1240,u,g,n,n,m,u,PM_MRK_INST_FROM_DL2L3,The processor's instruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. ##0E0300000003C142 The processor's instruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. #1241,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. ##0E0320000003C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. #1242,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3,The processor's L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. ##0E0340000003C142 The processor's L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. #1243,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3,The processor's data page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. ##0E0360000003C142 The processor's data page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. #1244,u,g,n,n,m,u,PM_MRK_INST_FROM_DL2L3_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0300000013C142 The processor's instruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1245,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0320000013C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1246,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0340000023C142 The processor's L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1247,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0360000023C142 The processor's data page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1248,u,g,n,n,m,u,PM_MRK_INST_FROM_DMEM,The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss for a marked instruction. ##0F4100000003C142 The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss for a marked instruction. #1249,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DMEM,The processor's instruction page table entry was reloaded from distant memory (MC slow) due to a demand miss for a marked instruction. ##0F4020000003C142 The processor's instruction page table entry was reloaded from distant memory (MC slow) due to a demand miss for a marked instruction. #1250,u,g,n,n,m,u,PM_MRK_DATA_FROM_DMEM,The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss for a marked instruction. ##0F4040000003C142 The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss for a marked instruction. #1251,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DMEM,The processor's data page table entry was reloaded from distant memory (MC slow) due to a demand miss for a marked instruction. ##0F4060000003C142 The processor's data page table entry was reloaded from distant memory (MC slow) due to a demand miss for a marked instruction. #1252,u,g,n,n,m,u,PM_MRK_INST_FROM_DMEM_ALL,The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##0F4100000013C142 The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1253,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DMEM_ALL,The processor's instruction page table entry was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##0F4020000013C142 The processor's instruction page table entry was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1254,u,g,n,n,m,u,PM_MRK_DATA_FROM_DMEM_ALL,The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##0F4040000023C142 The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1255,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DMEM_ALL,The processor's data page table entry was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##0F4060000023C142 The processor's data page table entry was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1256,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_CACHE,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss for a marked instruction. ##0F8020000003C142 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss for a marked instruction. #1257,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_CACHE,The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache due to a demand miss for a marked instruction. ##0F8040000003C142 The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache due to a demand miss for a marked instruction. #1258,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_CACHE,The processor's data page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss for a marked instruction. ##0F8060000003C142 The processor's data page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss for a marked instruction. #1259,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_CACHE_ALL,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. ##0F8020000013C142 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. #1260,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_CACHE_ALL,The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. ##0F8040000023C142 The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. #1261,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_CACHE_ALL,The processor's data page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. ##0F8060000023C142 The processor's data page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. #1262,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_MEM,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss for a marked instruction. ##0FC020000003C142 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss for a marked instruction. #1263,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_MEM,The processor's L1 data cache was reloaded from a distant chip's OpenCapp memory due to a demand miss for a marked instruction. ##0FC040000003C142 The processor's L1 data cache was reloaded from a distant chip's OpenCapp memory due to a demand miss for a marked instruction. #1264,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_MEM,The processor's data page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss for a marked instruction. ##0FC060000003C142 The processor's data page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss for a marked instruction. #1265,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_MEM_ALL,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. ##0FC020000013C142 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. #1266,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_MEM_ALL,The processor's L1 data cache was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. ##0FC040000023C142 The processor's L1 data cache was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. #1267,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_MEM_ALL,The processor's data page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. ##0FC060000023C142 The processor's data page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. #1268,u,g,n,n,m,u,PM_MRK_INST_FROM_D_OC_ANY,The processor's instruction cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##0F8100000003C142 The processor's instruction cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1269,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_ANY,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##0F8120000003C142 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1270,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_ANY,The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##0F8140000003C142 The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1271,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_ANY,The processor's data page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##0F8160000003C142 The processor's data page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1272,u,g,n,n,m,u,PM_MRK_INST_FROM_D_OC_ANY_ALL,The processor's instruction cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##0F8100000013C142 The processor's instruction cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1273,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_ANY_ALL,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##0F8120000013C142 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1274,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_ANY_ALL,The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##0F8140000023C142 The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1275,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_ANY_ALL,The processor's data page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##0F8160000023C142 The processor's data page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1276,u,g,n,n,m,u,PM_MRK_INST_FROM_ONCHIP_CACHE,The processor's instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss for a marked instruction. ##080B00000003C142 The processor's instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss for a marked instruction. #1277,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_ONCHIP_CACHE,The processor's instruction page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss for a marked instruction. ##080B20000003C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss for a marked instruction. #1278,u,g,n,n,m,u,PM_MRK_DATA_FROM_ONCHIP_CACHE,The processor's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss for a marked instruction. ##080B40000003C142 The processor's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss for a marked instruction. #1279,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_ONCHIP_CACHE,The processor's data page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss for a marked instruction. ##080B60000003C142 The processor's data page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss for a marked instruction. #1280,u,g,n,n,m,u,PM_MRK_INST_FROM_ONCHIP_CACHE_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload for a marked instruction. ##080B00000013C142 The processor's instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload for a marked instruction. #1281,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_ONCHIP_CACHE_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload for a marked instruction. ##080B20000013C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload for a marked instruction. #1282,u,g,n,n,m,u,PM_MRK_DATA_FROM_ONCHIP_CACHE_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload for a marked instruction. ##080B40000023C142 The processor's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload for a marked instruction. #1283,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_ONCHIP_CACHE_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload for a marked instruction. ##080B60000023C142 The processor's data page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload for a marked instruction. #1284,u,g,n,n,m,u,PM_MRK_INST_FROM_OFFCHIP_CACHE,The processor's instruction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss for a marked instruction. ##0C0B00000003C142 The processor's instruction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss for a marked instruction. #1285,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_OFFCHIP_CACHE,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss for a marked instruction. ##0C0B20000003C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss for a marked instruction. #1286,u,g,n,n,m,u,PM_MRK_DATA_FROM_OFFCHIP_CACHE,The processor's L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss for a marked instruction. ##0C0B40000003C142 The processor's L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss for a marked instruction. #1287,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_OFFCHIP_CACHE,The processor's data page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss for a marked instruction. ##0C0B60000003C142 The processor's data page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss for a marked instruction. #1288,u,g,n,n,m,u,PM_MRK_INST_FROM_OFFCHIP_CACHE_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload for a marked instruction. ##0C0B00000013C142 The processor's instruction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload for a marked instruction. #1289,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_OFFCHIP_CACHE_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload for a marked instruction. ##0C0B20000013C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload for a marked instruction. #1290,u,g,n,n,m,u,PM_MRK_DATA_FROM_OFFCHIP_CACHE_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload for a marked instruction. ##0C0B40000023C142 The processor's L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload for a marked instruction. #1291,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_OFFCHIP_CACHE_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload for a marked instruction. ##0C0B60000023C142 The processor's data page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload for a marked instruction. #1292,u,g,n,n,m,u,PM_MRK_INST_FROM_ANY_MEMORY,The processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss for a marked instruction. ##095900000003C142 The processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss for a marked instruction. #1293,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_ANY_MEMORY,The processor's instruction page table entry was reloaded from any chip's memory (MC slow) due to a demand miss for a marked instruction. ##095820000003C142 The processor's instruction page table entry was reloaded from any chip's memory (MC slow) due to a demand miss for a marked instruction. #1294,u,g,n,n,m,u,PM_MRK_DATA_FROM_ANY_MEMORY,The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss for a marked instruction. ##095840000003C142 The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss for a marked instruction. #1295,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_ANY_MEMORY,The processor's data page table entry was reloaded from any chip's memory (MC slow) due to a demand miss for a marked instruction. ##095860000003C142 The processor's data page table entry was reloaded from any chip's memory (MC slow) due to a demand miss for a marked instruction. #1296,u,g,n,n,m,u,PM_MRK_INST_FROM_ANY_MEMORY_ALL,The processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##095900000013C142 The processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1297,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_ANY_MEMORY_ALL,The processor's instruction page table entry was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##095820000013C142 The processor's instruction page table entry was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1298,u,g,n,n,m,u,PM_MRK_DATA_FROM_ANY_MEMORY_ALL,The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##095840000023C142 The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1299,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_ANY_MEMORY_ALL,The processor's data page table entry was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##095860000023C142 The processor's data page table entry was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1300,u,g,n,n,m,u,PM_MRK_INST_FROM_L2_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local core's L2 due to a demand miss. Divide this count by PM_MRK_INST_FROM_L2 to obtain the average L2 latency for instruction reloads. ##000300000003C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local core's L2 due to a demand miss. Divide this count by PM_MRK_INST_FROM_L2 to obtain the average L2 latency for instruction reloads. #1301,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2 to obtain the average L2 latency for instruction page table reloads. ##000320000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2 to obtain the average L2 latency for instruction page table reloads. #1302,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2 to obtain the average L2 latency for data reloads. ##000340000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2 to obtain the average L2 latency for data reloads. #1303,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2 to obtain the average L2 latency for data page table reloads. ##000360000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2 to obtain the average L2 latency for data page table reloads. #1304,u,g,n,n,m,u,PM_MRK_INST_FROM_L2_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L2_ALL to obtain the average L2_ALL latency for instruction reloads. ##000300000013C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L2_ALL to obtain the average L2_ALL latency for instruction reloads. #1305,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2_ALL to obtain the average L2_ALL latency for instruction page table reloads. ##000320000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2_ALL to obtain the average L2_ALL latency for instruction page table reloads. #1306,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2_ALL to obtain the average L2_ALL latency for data reloads. ##000340000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2_ALL to obtain the average L2_ALL latency for data reloads. #1307,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2_ALL to obtain the average L2_ALL latency for data page table reloads. ##000360000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2_ALL to obtain the average L2_ALL latency for data page table reloads. #1308,u,g,n,n,m,u,PM_MRK_INST_FROM_L1MISS_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a source beyond the local core's L1 due to a demand miss. Divide this count by PM_MRK_INST_FROM_L1MISS to obtain the average L1MISS latency for instruction reloads. ##003F00000003C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a source beyond the local core's L1 due to a demand miss. Divide this count by PM_MRK_INST_FROM_L1MISS to obtain the average L1MISS latency for instruction reloads. #1309,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L1MISS_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a source beyond the local core's L1 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L1MISS to obtain the average L1MISS latency for instruction page table reloads. ##003F20000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a source beyond the local core's L1 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L1MISS to obtain the average L1MISS latency for instruction page table reloads. #1310,u,g,n,n,m,u,PM_MRK_DATA_FROM_L1MISS_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a source beyond the local core's L1 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L1MISS to obtain the average L1MISS latency for data reloads. ##003F40000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a source beyond the local core's L1 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L1MISS to obtain the average L1MISS latency for data reloads. #1311,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L1MISS_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a source beyond the local core's L1 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L1MISS to obtain the average L1MISS latency for data page table reloads. ##003F60000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a source beyond the local core's L1 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L1MISS to obtain the average L1MISS latency for data page table reloads. #1312,u,g,n,n,m,u,PM_MRK_INST_FROM_L1MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L1MISS_ALL to obtain the average L1MISS_ALL latency for instruction reloads. ##003F00000013C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L1MISS_ALL to obtain the average L1MISS_ALL latency for instruction reloads. #1313,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L1MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L1MISS_ALL to obtain the average L1MISS_ALL latency for instruction page table reloads. ##003F20000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L1MISS_ALL to obtain the average L1MISS_ALL latency for instruction page table reloads. #1314,u,g,n,n,m,u,PM_MRK_DATA_FROM_L1MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L1MISS_ALL to obtain the average L1MISS_ALL latency for data reloads. ##003F40000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L1MISS_ALL to obtain the average L1MISS_ALL latency for data reloads. #1315,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L1MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L1MISS_ALL to obtain the average L1MISS_ALL latency for data page table reloads. ##003F60000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L1MISS_ALL to obtain the average L1MISS_ALL latency for data page table reloads. #1316,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_NO_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2_NO_CONFLICT to obtain the average L2_NO_CONFLICT latency for instruction page table reloads. ##000020000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2_NO_CONFLICT to obtain the average L2_NO_CONFLICT latency for instruction page table reloads. #1317,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2_NO_CONFLICT to obtain the average L2_NO_CONFLICT latency for data reloads. ##000040000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2_NO_CONFLICT to obtain the average L2_NO_CONFLICT latency for data reloads. #1318,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_NO_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2_NO_CONFLICT to obtain the average L2_NO_CONFLICT latency for data page table reloads. ##000060000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2_NO_CONFLICT to obtain the average L2_NO_CONFLICT latency for data page table reloads. #1319,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_NO_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2_NO_CONFLICT_ALL to obtain the average L2_NO_CONFLICT_ALL latency for instruction page table reloads. ##000020000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2_NO_CONFLICT_ALL to obtain the average L2_NO_CONFLICT_ALL latency for instruction page table reloads. #1320,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_NO_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2_NO_CONFLICT_ALL to obtain the average L2_NO_CONFLICT_ALL latency for data reloads. ##000040000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2_NO_CONFLICT_ALL to obtain the average L2_NO_CONFLICT_ALL latency for data reloads. #1321,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_NO_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2_NO_CONFLICT_ALL to obtain the average L2_NO_CONFLICT_ALL latency for data page table reloads. ##000060000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2_NO_CONFLICT_ALL to obtain the average L2_NO_CONFLICT_ALL latency for data page table reloads. #1322,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_MEPF_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2_MEPF to obtain the average L2_MEPF latency for instruction page table reloads. ##004020000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2_MEPF to obtain the average L2_MEPF latency for instruction page table reloads. #1323,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_MEPF_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2_MEPF to obtain the average L2_MEPF latency for data reloads. ##004040000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2_MEPF to obtain the average L2_MEPF latency for data reloads. #1324,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_MEPF_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2_MEPF to obtain the average L2_MEPF latency for data page table reloads. ##004060000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2_MEPF to obtain the average L2_MEPF latency for data page table reloads. #1325,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_MEPF_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2_MEPF_ALL to obtain the average L2_MEPF_ALL latency for instruction page table reloads. ##004020000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2_MEPF_ALL to obtain the average L2_MEPF_ALL latency for instruction page table reloads. #1326,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_MEPF_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2_MEPF_ALL to obtain the average L2_MEPF_ALL latency for data reloads. ##004040000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2_MEPF_ALL to obtain the average L2_MEPF_ALL latency for data reloads. #1327,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_MEPF_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2_MEPF_ALL to obtain the average L2_MEPF_ALL latency for data page table reloads. ##004060000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2_MEPF_ALL to obtain the average L2_MEPF_ALL latency for data page table reloads. #1328,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_LDHITST_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2_LDHITST_CONFLICT to obtain the average L2_LDHITST_CONFLICT latency for instruction page table reloads. ##008020000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2_LDHITST_CONFLICT to obtain the average L2_LDHITST_CONFLICT latency for instruction page table reloads. #1329,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_LDHITST_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2_LDHITST_CONFLICT to obtain the average L2_LDHITST_CONFLICT latency for data reloads. ##008040000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2_LDHITST_CONFLICT to obtain the average L2_LDHITST_CONFLICT latency for data reloads. #1330,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_LDHITST_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2_LDHITST_CONFLICT to obtain the average L2_LDHITST_CONFLICT latency for data page table reloads. ##008060000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2_LDHITST_CONFLICT to obtain the average L2_LDHITST_CONFLICT latency for data page table reloads. #1331,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_LDHITST_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2_LDHITST_CONFLICT_ALL to obtain the average L2_LDHITST_CONFLICT_ALL latency for instruction page table reloads. ##008020000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2_LDHITST_CONFLICT_ALL to obtain the average L2_LDHITST_CONFLICT_ALL latency for instruction page table reloads. #1332,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_LDHITST_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2_LDHITST_CONFLICT_ALL to obtain the average L2_LDHITST_CONFLICT_ALL latency for data reloads. ##008040000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2_LDHITST_CONFLICT_ALL to obtain the average L2_LDHITST_CONFLICT_ALL latency for data reloads. #1333,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_LDHITST_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2_LDHITST_CONFLICT_ALL to obtain the average L2_LDHITST_CONFLICT_ALL latency for data page table reloads. ##008060000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2_LDHITST_CONFLICT_ALL to obtain the average L2_LDHITST_CONFLICT_ALL latency for data page table reloads. #1334,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_OTHER_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2_OTHER_CONFLICT to obtain the average L2_OTHER_CONFLICT latency for instruction page table reloads. ##00C020000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2_OTHER_CONFLICT to obtain the average L2_OTHER_CONFLICT latency for instruction page table reloads. #1335,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_OTHER_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2_OTHER_CONFLICT to obtain the average L2_OTHER_CONFLICT latency for data reloads. ##00C040000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2_OTHER_CONFLICT to obtain the average L2_OTHER_CONFLICT latency for data reloads. #1336,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_OTHER_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2_OTHER_CONFLICT to obtain the average L2_OTHER_CONFLICT latency for data page table reloads. ##00C060000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2_OTHER_CONFLICT to obtain the average L2_OTHER_CONFLICT latency for data page table reloads. #1337,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_OTHER_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2_OTHER_CONFLICT_ALL to obtain the average L2_OTHER_CONFLICT_ALL latency for instruction page table reloads. ##00C020000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2_OTHER_CONFLICT_ALL to obtain the average L2_OTHER_CONFLICT_ALL latency for instruction page table reloads. #1338,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_OTHER_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2_OTHER_CONFLICT_ALL to obtain the average L2_OTHER_CONFLICT_ALL latency for data reloads. ##00C040000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2_OTHER_CONFLICT_ALL to obtain the average L2_OTHER_CONFLICT_ALL latency for data reloads. #1339,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_OTHER_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2_OTHER_CONFLICT_ALL to obtain the average L2_OTHER_CONFLICT_ALL latency for data page table reloads. ##00C060000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2_OTHER_CONFLICT_ALL to obtain the average L2_OTHER_CONFLICT_ALL latency for data page table reloads. #1340,u,g,n,n,m,u,PM_MRK_INST_FROM_L2MISS_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a source beyond the local core's L2 due to a demand miss. Divide this count by PM_MRK_INST_FROM_L2MISS to obtain the average L2MISS latency for instruction reloads. ##000380000003C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a source beyond the local core's L2 due to a demand miss. Divide this count by PM_MRK_INST_FROM_L2MISS to obtain the average L2MISS latency for instruction reloads. #1341,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2MISS_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a source beyond the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2MISS to obtain the average L2MISS latency for instruction page table reloads. ##0003A0000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a source beyond the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2MISS to obtain the average L2MISS latency for instruction page table reloads. #1342,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2MISS_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a source beyond the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2MISS to obtain the average L2MISS latency for data reloads. ##0003C0000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a source beyond the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2MISS to obtain the average L2MISS latency for data reloads. #1343,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2MISS_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a source beyond the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2MISS to obtain the average L2MISS latency for data page table reloads. ##0003E0000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a source beyond the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2MISS to obtain the average L2MISS latency for data page table reloads. #1344,u,g,n,n,m,u,PM_MRK_INST_FROM_L2MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L2MISS_ALL to obtain the average L2MISS_ALL latency for instruction reloads. ##000380000013C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L2MISS_ALL to obtain the average L2MISS_ALL latency for instruction reloads. #1345,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2MISS_ALL to obtain the average L2MISS_ALL latency for instruction page table reloads. ##0003A0000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2MISS_ALL to obtain the average L2MISS_ALL latency for instruction page table reloads. #1346,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2MISS_ALL to obtain the average L2MISS_ALL latency for data reloads. ##0003C0000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2MISS_ALL to obtain the average L2MISS_ALL latency for data reloads. #1347,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2MISS_ALL to obtain the average L2MISS_ALL latency for data page table reloads. ##0003E0000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2MISS_ALL to obtain the average L2MISS_ALL latency for data page table reloads. #1348,u,g,n,n,m,u,PM_MRK_INST_FROM_L3_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_INST_FROM_L3 to obtain the average L3 latency for instruction reloads. ##010300000003C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_INST_FROM_L3 to obtain the average L3 latency for instruction reloads. #1349,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L3 to obtain the average L3 latency for instruction page table reloads. ##010320000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L3 to obtain the average L3 latency for instruction page table reloads. #1350,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L3 to obtain the average L3 latency for data reloads. ##010340000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L3 to obtain the average L3 latency for data reloads. #1351,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L3 to obtain the average L3 latency for data page table reloads. ##010360000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L3 to obtain the average L3 latency for data page table reloads. #1352,u,g,n,n,m,u,PM_MRK_INST_FROM_L3_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L3_ALL to obtain the average L3_ALL latency for instruction reloads. ##010300000013C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L3_ALL to obtain the average L3_ALL latency for instruction reloads. #1353,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L3_ALL to obtain the average L3_ALL latency for instruction page table reloads. ##010320000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L3_ALL to obtain the average L3_ALL latency for instruction page table reloads. #1354,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L3_ALL to obtain the average L3_ALL latency for data reloads. ##010340000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L3_ALL to obtain the average L3_ALL latency for data reloads. #1355,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L3_ALL to obtain the average L3_ALL latency for data page table reloads. ##010360000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L3_ALL to obtain the average L3_ALL latency for data page table reloads. #1356,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_NO_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L3_NO_CONFLICT to obtain the average L3_NO_CONFLICT latency for instruction page table reloads. ##010020000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L3_NO_CONFLICT to obtain the average L3_NO_CONFLICT latency for instruction page table reloads. #1357,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L3_NO_CONFLICT to obtain the average L3_NO_CONFLICT latency for data reloads. ##010040000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L3_NO_CONFLICT to obtain the average L3_NO_CONFLICT latency for data reloads. #1358,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_NO_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L3_NO_CONFLICT to obtain the average L3_NO_CONFLICT latency for data page table reloads. ##010060000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L3_NO_CONFLICT to obtain the average L3_NO_CONFLICT latency for data page table reloads. #1359,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_NO_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L3_NO_CONFLICT_ALL to obtain the average L3_NO_CONFLICT_ALL latency for instruction page table reloads. ##010020000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L3_NO_CONFLICT_ALL to obtain the average L3_NO_CONFLICT_ALL latency for instruction page table reloads. #1360,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_NO_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L3_NO_CONFLICT_ALL to obtain the average L3_NO_CONFLICT_ALL latency for data reloads. ##010040000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L3_NO_CONFLICT_ALL to obtain the average L3_NO_CONFLICT_ALL latency for data reloads. #1361,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_NO_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L3_NO_CONFLICT_ALL to obtain the average L3_NO_CONFLICT_ALL latency for data page table reloads. ##010060000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L3_NO_CONFLICT_ALL to obtain the average L3_NO_CONFLICT_ALL latency for data page table reloads. #1362,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_MEPF_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L3_MEPF to obtain the average L3_MEPF latency for instruction page table reloads. ##014020000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L3_MEPF to obtain the average L3_MEPF latency for instruction page table reloads. #1363,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_MEPF_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L3_MEPF to obtain the average L3_MEPF latency for data reloads. ##014040000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L3_MEPF to obtain the average L3_MEPF latency for data reloads. #1364,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_MEPF_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L3_MEPF to obtain the average L3_MEPF latency for data page table reloads. ##014060000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L3_MEPF to obtain the average L3_MEPF latency for data page table reloads. #1365,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_MEPF_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L3_MEPF_ALL to obtain the average L3_MEPF_ALL latency for instruction page table reloads. ##014020000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L3_MEPF_ALL to obtain the average L3_MEPF_ALL latency for instruction page table reloads. #1366,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_MEPF_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L3_MEPF_ALL to obtain the average L3_MEPF_ALL latency for data reloads. ##014040000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L3_MEPF_ALL to obtain the average L3_MEPF_ALL latency for data reloads. #1367,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_MEPF_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L3_MEPF_ALL to obtain the average L3_MEPF_ALL latency for data page table reloads. ##014060000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L3_MEPF_ALL to obtain the average L3_MEPF_ALL latency for data page table reloads. #1368,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L3_CONFLICT to obtain the average L3_CONFLICT latency for instruction page table reloads. ##01C020000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L3_CONFLICT to obtain the average L3_CONFLICT latency for instruction page table reloads. #1369,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L3_CONFLICT to obtain the average L3_CONFLICT latency for data reloads. ##01C040000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L3_CONFLICT to obtain the average L3_CONFLICT latency for data reloads. #1370,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L3_CONFLICT to obtain the average L3_CONFLICT latency for data page table reloads. ##01C060000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L3_CONFLICT to obtain the average L3_CONFLICT latency for data page table reloads. #1371,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L3_CONFLICT_ALL to obtain the average L3_CONFLICT_ALL latency for instruction page table reloads. ##01C020000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L3_CONFLICT_ALL to obtain the average L3_CONFLICT_ALL latency for instruction page table reloads. #1372,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L3_CONFLICT_ALL to obtain the average L3_CONFLICT_ALL latency for data reloads. ##01C040000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L3_CONFLICT_ALL to obtain the average L3_CONFLICT_ALL latency for data reloads. #1373,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L3_CONFLICT_ALL to obtain the average L3_CONFLICT_ALL latency for data page table reloads. ##01C060000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L3_CONFLICT_ALL to obtain the average L3_CONFLICT_ALL latency for data page table reloads. #1374,u,g,n,n,m,u,PM_MRK_INST_FROM_L3MISS_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from beyond the local core's L3 due to a demand miss. Divide this count by PM_MRK_INST_FROM_L3MISS to obtain the average L3MISS latency for instruction reloads. ##000780000003C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from beyond the local core's L3 due to a demand miss. Divide this count by PM_MRK_INST_FROM_L3MISS to obtain the average L3MISS latency for instruction reloads. #1375,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3MISS_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from beyond the local core's L3 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L3MISS to obtain the average L3MISS latency for instruction page table reloads. ##0007A0000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from beyond the local core's L3 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L3MISS to obtain the average L3MISS latency for instruction page table reloads. #1376,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3MISS_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from beyond the local core's L3 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L3MISS to obtain the average L3MISS latency for data reloads. ##0007C0000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from beyond the local core's L3 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L3MISS to obtain the average L3MISS latency for data reloads. #1377,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3MISS_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from beyond the local core's L3 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L3MISS to obtain the average L3MISS latency for data page table reloads. ##0007E0000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from beyond the local core's L3 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L3MISS to obtain the average L3MISS latency for data page table reloads. #1378,u,g,n,n,m,u,PM_MRK_INST_FROM_L3MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L3MISS_ALL to obtain the average L3MISS_ALL latency for instruction reloads. ##000780000013C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L3MISS_ALL to obtain the average L3MISS_ALL latency for instruction reloads. #1379,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L3MISS_ALL to obtain the average L3MISS_ALL latency for instruction page table reloads. ##0007A0000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L3MISS_ALL to obtain the average L3MISS_ALL latency for instruction page table reloads. #1380,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L3MISS_ALL to obtain the average L3MISS_ALL latency for data reloads. ##0007C0000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L3MISS_ALL to obtain the average L3MISS_ALL latency for data reloads. #1381,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L3MISS_ALL to obtain the average L3MISS_ALL latency for data page table reloads. ##0007E0000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L3MISS_ALL to obtain the average L3MISS_ALL latency for data page table reloads. #1382,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT_SHR to obtain the average L21_REGENT_SHR latency for instruction page table reloads. ##080020000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT_SHR to obtain the average L21_REGENT_SHR latency for instruction page table reloads. #1383,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_REGENT_SHR to obtain the average L21_REGENT_SHR latency for data reloads. ##080040000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_REGENT_SHR to obtain the average L21_REGENT_SHR latency for data reloads. #1384,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT_SHR to obtain the average L21_REGENT_SHR latency for data page table reloads. ##080060000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT_SHR to obtain the average L21_REGENT_SHR latency for data page table reloads. #1385,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT_SHR_ALL to obtain the average L21_REGENT_SHR_ALL latency for instruction page table reloads. ##080020000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT_SHR_ALL to obtain the average L21_REGENT_SHR_ALL latency for instruction page table reloads. #1386,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_REGENT_SHR_ALL to obtain the average L21_REGENT_SHR_ALL latency for data reloads. ##080040000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_REGENT_SHR_ALL to obtain the average L21_REGENT_SHR_ALL latency for data reloads. #1387,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT_SHR_ALL to obtain the average L21_REGENT_SHR_ALL latency for data page table reloads. ##080060000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT_SHR_ALL to obtain the average L21_REGENT_SHR_ALL latency for data page table reloads. #1388,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT_MOD to obtain the average L21_REGENT_MOD latency for instruction page table reloads. ##084020000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT_MOD to obtain the average L21_REGENT_MOD latency for instruction page table reloads. #1389,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_REGENT_MOD to obtain the average L21_REGENT_MOD latency for data reloads. ##084040000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_REGENT_MOD to obtain the average L21_REGENT_MOD latency for data reloads. #1390,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT_MOD to obtain the average L21_REGENT_MOD latency for data page table reloads. ##084060000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT_MOD to obtain the average L21_REGENT_MOD latency for data page table reloads. #1391,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT_MOD_ALL to obtain the average L21_REGENT_MOD_ALL latency for instruction page table reloads. ##084020000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT_MOD_ALL to obtain the average L21_REGENT_MOD_ALL latency for instruction page table reloads. #1392,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_REGENT_MOD_ALL to obtain the average L21_REGENT_MOD_ALL latency for data reloads. ##084040000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_REGENT_MOD_ALL to obtain the average L21_REGENT_MOD_ALL latency for data reloads. #1393,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT_MOD_ALL to obtain the average L21_REGENT_MOD_ALL latency for data page table reloads. ##084060000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT_MOD_ALL to obtain the average L21_REGENT_MOD_ALL latency for data page table reloads. #1394,u,g,n,n,m,u,PM_MRK_INST_FROM_L21_REGENT_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_L21_REGENT to obtain the average L21_REGENT latency for instruction reloads. ##080100000003C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_L21_REGENT to obtain the average L21_REGENT latency for instruction reloads. #1395,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT to obtain the average L21_REGENT latency for instruction page table reloads. ##080120000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT to obtain the average L21_REGENT latency for instruction page table reloads. #1396,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_REGENT to obtain the average L21_REGENT latency for data reloads. ##080140000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_REGENT to obtain the average L21_REGENT latency for data reloads. #1397,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT to obtain the average L21_REGENT latency for data page table reloads. ##080160000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT to obtain the average L21_REGENT latency for data page table reloads. #1398,u,g,n,n,m,u,PM_MRK_INST_FROM_L21_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L21_REGENT_ALL to obtain the average L21_REGENT_ALL latency for instruction reloads. ##080100000013C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L21_REGENT_ALL to obtain the average L21_REGENT_ALL latency for instruction reloads. #1399,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT_ALL to obtain the average L21_REGENT_ALL latency for instruction page table reloads. ##080120000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT_ALL to obtain the average L21_REGENT_ALL latency for instruction page table reloads. #1400,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_REGENT_ALL to obtain the average L21_REGENT_ALL latency for data reloads. ##080140000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_REGENT_ALL to obtain the average L21_REGENT_ALL latency for data reloads. #1401,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT_ALL to obtain the average L21_REGENT_ALL latency for data page table reloads. ##080160000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT_ALL to obtain the average L21_REGENT_ALL latency for data page table reloads. #1402,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT_SHR to obtain the average L31_REGENT_SHR latency for instruction page table reloads. ##088020000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT_SHR to obtain the average L31_REGENT_SHR latency for instruction page table reloads. #1403,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_REGENT_SHR to obtain the average L31_REGENT_SHR latency for data reloads. ##088040000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_REGENT_SHR to obtain the average L31_REGENT_SHR latency for data reloads. #1404,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT_SHR to obtain the average L31_REGENT_SHR latency for data page table reloads. ##088060000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT_SHR to obtain the average L31_REGENT_SHR latency for data page table reloads. #1405,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT_SHR_ALL to obtain the average L31_REGENT_SHR_ALL latency for instruction page table reloads. ##088020000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT_SHR_ALL to obtain the average L31_REGENT_SHR_ALL latency for instruction page table reloads. #1406,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_REGENT_SHR_ALL to obtain the average L31_REGENT_SHR_ALL latency for data reloads. ##088040000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_REGENT_SHR_ALL to obtain the average L31_REGENT_SHR_ALL latency for data reloads. #1407,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT_SHR_ALL to obtain the average L31_REGENT_SHR_ALL latency for data page table reloads. ##088060000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT_SHR_ALL to obtain the average L31_REGENT_SHR_ALL latency for data page table reloads. #1408,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT_MOD to obtain the average L31_REGENT_MOD latency for instruction page table reloads. ##08C020000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT_MOD to obtain the average L31_REGENT_MOD latency for instruction page table reloads. #1409,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_REGENT_MOD to obtain the average L31_REGENT_MOD latency for data reloads. ##08C040000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_REGENT_MOD to obtain the average L31_REGENT_MOD latency for data reloads. #1410,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT_MOD to obtain the average L31_REGENT_MOD latency for data page table reloads. ##08C060000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT_MOD to obtain the average L31_REGENT_MOD latency for data page table reloads. #1411,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT_MOD_ALL to obtain the average L31_REGENT_MOD_ALL latency for instruction page table reloads. ##08C020000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT_MOD_ALL to obtain the average L31_REGENT_MOD_ALL latency for instruction page table reloads. #1412,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_REGENT_MOD_ALL to obtain the average L31_REGENT_MOD_ALL latency for data reloads. ##08C040000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_REGENT_MOD_ALL to obtain the average L31_REGENT_MOD_ALL latency for data reloads. #1413,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT_MOD_ALL to obtain the average L31_REGENT_MOD_ALL latency for data page table reloads. ##08C060000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT_MOD_ALL to obtain the average L31_REGENT_MOD_ALL latency for data page table reloads. #1414,u,g,n,n,m,u,PM_MRK_INST_FROM_L31_REGENT_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_L31_REGENT to obtain the average L31_REGENT latency for instruction reloads. ##088100000003C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_L31_REGENT to obtain the average L31_REGENT latency for instruction reloads. #1415,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT to obtain the average L31_REGENT latency for instruction page table reloads. ##088120000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT to obtain the average L31_REGENT latency for instruction page table reloads. #1416,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_REGENT to obtain the average L31_REGENT latency for data reloads. ##088140000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_REGENT to obtain the average L31_REGENT latency for data reloads. #1417,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT to obtain the average L31_REGENT latency for data page table reloads. ##088160000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT to obtain the average L31_REGENT latency for data page table reloads. #1418,u,g,n,n,m,u,PM_MRK_INST_FROM_L31_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L31_REGENT_ALL to obtain the average L31_REGENT_ALL latency for instruction reloads. ##088100000013C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L31_REGENT_ALL to obtain the average L31_REGENT_ALL latency for instruction reloads. #1419,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT_ALL to obtain the average L31_REGENT_ALL latency for instruction page table reloads. ##088120000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT_ALL to obtain the average L31_REGENT_ALL latency for instruction page table reloads. #1420,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_REGENT_ALL to obtain the average L31_REGENT_ALL latency for data reloads. ##088140000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_REGENT_ALL to obtain the average L31_REGENT_ALL latency for data reloads. #1421,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT_ALL to obtain the average L31_REGENT_ALL latency for data page table reloads. ##088160000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT_ALL to obtain the average L31_REGENT_ALL latency for data page table reloads. #1422,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3_SHR to obtain the average REGENT_L2L3_SHR latency for instruction page table reloads. ##080220000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3_SHR to obtain the average REGENT_L2L3_SHR latency for instruction page table reloads. #1423,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3_SHR to obtain the average REGENT_L2L3_SHR latency for data reloads. ##080240000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3_SHR to obtain the average REGENT_L2L3_SHR latency for data reloads. #1424,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3_SHR to obtain the average REGENT_L2L3_SHR latency for data page table reloads. ##080260000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3_SHR to obtain the average REGENT_L2L3_SHR latency for data page table reloads. #1425,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3_SHR_ALL to obtain the average REGENT_L2L3_SHR_ALL latency for instruction page table reloads. ##080220000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3_SHR_ALL to obtain the average REGENT_L2L3_SHR_ALL latency for instruction page table reloads. #1426,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3_SHR_ALL to obtain the average REGENT_L2L3_SHR_ALL latency for data reloads. ##080240000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3_SHR_ALL to obtain the average REGENT_L2L3_SHR_ALL latency for data reloads. #1427,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3_SHR_ALL to obtain the average REGENT_L2L3_SHR_ALL latency for data page table reloads. ##080260000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3_SHR_ALL to obtain the average REGENT_L2L3_SHR_ALL latency for data page table reloads. #1428,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3_MOD to obtain the average REGENT_L2L3_MOD latency for instruction page table reloads. ##084220000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3_MOD to obtain the average REGENT_L2L3_MOD latency for instruction page table reloads. #1429,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3_MOD to obtain the average REGENT_L2L3_MOD latency for data reloads. ##084240000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3_MOD to obtain the average REGENT_L2L3_MOD latency for data reloads. #1430,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3_MOD to obtain the average REGENT_L2L3_MOD latency for data page table reloads. ##084260000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3_MOD to obtain the average REGENT_L2L3_MOD latency for data page table reloads. #1431,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3_MOD_ALL to obtain the average REGENT_L2L3_MOD_ALL latency for instruction page table reloads. ##084220000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3_MOD_ALL to obtain the average REGENT_L2L3_MOD_ALL latency for instruction page table reloads. #1432,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3_MOD_ALL to obtain the average REGENT_L2L3_MOD_ALL latency for data reloads. ##084240000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3_MOD_ALL to obtain the average REGENT_L2L3_MOD_ALL latency for data reloads. #1433,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3_MOD_ALL to obtain the average REGENT_L2L3_MOD_ALL latency for data page table reloads. ##084260000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3_MOD_ALL to obtain the average REGENT_L2L3_MOD_ALL latency for data page table reloads. #1434,u,g,n,n,m,u,PM_MRK_INST_FROM_REGENT_L2L3_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_REGENT_L2L3 to obtain the average REGENT_L2L3 latency for instruction reloads. ##080300000003C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_REGENT_L2L3 to obtain the average REGENT_L2L3 latency for instruction reloads. #1435,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3 to obtain the average REGENT_L2L3 latency for instruction page table reloads. ##080320000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3 to obtain the average REGENT_L2L3 latency for instruction page table reloads. #1436,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3 to obtain the average REGENT_L2L3 latency for data reloads. ##080340000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3 to obtain the average REGENT_L2L3 latency for data reloads. #1437,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3 to obtain the average REGENT_L2L3 latency for data page table reloads. ##080360000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3 to obtain the average REGENT_L2L3 latency for data page table reloads. #1438,u,g,n,n,m,u,PM_MRK_INST_FROM_REGENT_L2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_REGENT_L2L3_ALL to obtain the average REGENT_L2L3_ALL latency for instruction reloads. ##080300000013C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_REGENT_L2L3_ALL to obtain the average REGENT_L2L3_ALL latency for instruction reloads. #1439,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3_ALL to obtain the average REGENT_L2L3_ALL latency for instruction page table reloads. ##080320000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3_ALL to obtain the average REGENT_L2L3_ALL latency for instruction page table reloads. #1440,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3_ALL to obtain the average REGENT_L2L3_ALL latency for data reloads. ##080340000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3_ALL to obtain the average REGENT_L2L3_ALL latency for data reloads. #1441,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3_ALL to obtain the average REGENT_L2L3_ALL latency for data page table reloads. ##080360000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3_ALL to obtain the average REGENT_L2L3_ALL latency for data page table reloads. #1442,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT_SHR to obtain the average L21_NON_REGENT_SHR latency for instruction page table reloads. ##0A0020000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT_SHR to obtain the average L21_NON_REGENT_SHR latency for instruction page table reloads. #1443,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT_SHR to obtain the average L21_NON_REGENT_SHR latency for data reloads. ##0A0040000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT_SHR to obtain the average L21_NON_REGENT_SHR latency for data reloads. #1444,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT_SHR to obtain the average L21_NON_REGENT_SHR latency for data page table reloads. ##0A0060000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT_SHR to obtain the average L21_NON_REGENT_SHR latency for data page table reloads. #1445,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT_SHR_ALL to obtain the average L21_NON_REGENT_SHR_ALL latency for instruction page table reloads. ##0A0020000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT_SHR_ALL to obtain the average L21_NON_REGENT_SHR_ALL latency for instruction page table reloads. #1446,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT_SHR_ALL to obtain the average L21_NON_REGENT_SHR_ALL latency for data reloads. ##0A0040000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT_SHR_ALL to obtain the average L21_NON_REGENT_SHR_ALL latency for data reloads. #1447,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT_SHR_ALL to obtain the average L21_NON_REGENT_SHR_ALL latency for data page table reloads. ##0A0060000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT_SHR_ALL to obtain the average L21_NON_REGENT_SHR_ALL latency for data page table reloads. #1448,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT_MOD to obtain the average L21_NON_REGENT_MOD latency for instruction page table reloads. ##0A4020000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT_MOD to obtain the average L21_NON_REGENT_MOD latency for instruction page table reloads. #1449,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT_MOD to obtain the average L21_NON_REGENT_MOD latency for data reloads. ##0A4040000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT_MOD to obtain the average L21_NON_REGENT_MOD latency for data reloads. #1450,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT_MOD to obtain the average L21_NON_REGENT_MOD latency for data page table reloads. ##0A4060000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT_MOD to obtain the average L21_NON_REGENT_MOD latency for data page table reloads. #1451,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT_MOD_ALL to obtain the average L21_NON_REGENT_MOD_ALL latency for instruction page table reloads. ##0A4020000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT_MOD_ALL to obtain the average L21_NON_REGENT_MOD_ALL latency for instruction page table reloads. #1452,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT_MOD_ALL to obtain the average L21_NON_REGENT_MOD_ALL latency for data reloads. ##0A4040000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT_MOD_ALL to obtain the average L21_NON_REGENT_MOD_ALL latency for data reloads. #1453,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT_MOD_ALL to obtain the average L21_NON_REGENT_MOD_ALL latency for data page table reloads. ##0A4060000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT_MOD_ALL to obtain the average L21_NON_REGENT_MOD_ALL latency for data page table reloads. #1454,u,g,n,n,m,u,PM_MRK_INST_FROM_L21_NON_REGENT_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_L21_NON_REGENT to obtain the average L21_NON_REGENT latency for instruction reloads. ##0A0100000003C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_L21_NON_REGENT to obtain the average L21_NON_REGENT latency for instruction reloads. #1455,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT to obtain the average L21_NON_REGENT latency for instruction page table reloads. ##0A0120000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT to obtain the average L21_NON_REGENT latency for instruction page table reloads. #1456,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT to obtain the average L21_NON_REGENT latency for data reloads. ##0A0140000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT to obtain the average L21_NON_REGENT latency for data reloads. #1457,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT to obtain the average L21_NON_REGENT latency for data page table reloads. ##0A0160000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT to obtain the average L21_NON_REGENT latency for data page table reloads. #1458,u,g,n,n,m,u,PM_MRK_INST_FROM_L21_NON_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L21_NON_REGENT_ALL to obtain the average L21_NON_REGENT_ALL latency for instruction reloads. ##0A0100000013C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L21_NON_REGENT_ALL to obtain the average L21_NON_REGENT_ALL latency for instruction reloads. #1459,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT_ALL to obtain the average L21_NON_REGENT_ALL latency for instruction page table reloads. ##0A0120000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT_ALL to obtain the average L21_NON_REGENT_ALL latency for instruction page table reloads. #1460,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT_ALL to obtain the average L21_NON_REGENT_ALL latency for data reloads. ##0A0140000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT_ALL to obtain the average L21_NON_REGENT_ALL latency for data reloads. #1461,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT_ALL to obtain the average L21_NON_REGENT_ALL latency for data page table reloads. ##0A0160000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT_ALL to obtain the average L21_NON_REGENT_ALL latency for data page table reloads. #1462,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT_SHR to obtain the average L31_NON_REGENT_SHR latency for instruction page table reloads. ##0A8020000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT_SHR to obtain the average L31_NON_REGENT_SHR latency for instruction page table reloads. #1463,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT_SHR to obtain the average L31_NON_REGENT_SHR latency for data reloads. ##0A8040000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT_SHR to obtain the average L31_NON_REGENT_SHR latency for data reloads. #1464,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT_SHR to obtain the average L31_NON_REGENT_SHR latency for data page table reloads. ##0A8060000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT_SHR to obtain the average L31_NON_REGENT_SHR latency for data page table reloads. #1465,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT_SHR_ALL to obtain the average L31_NON_REGENT_SHR_ALL latency for instruction page table reloads. ##0A8020000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT_SHR_ALL to obtain the average L31_NON_REGENT_SHR_ALL latency for instruction page table reloads. #1466,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT_SHR_ALL to obtain the average L31_NON_REGENT_SHR_ALL latency for data reloads. ##0A8040000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT_SHR_ALL to obtain the average L31_NON_REGENT_SHR_ALL latency for data reloads. #1467,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT_SHR_ALL to obtain the average L31_NON_REGENT_SHR_ALL latency for data page table reloads. ##0A8060000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT_SHR_ALL to obtain the average L31_NON_REGENT_SHR_ALL latency for data page table reloads. #1468,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT_MOD to obtain the average L31_NON_REGENT_MOD latency for instruction page table reloads. ##0AC020000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT_MOD to obtain the average L31_NON_REGENT_MOD latency for instruction page table reloads. #1469,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT_MOD to obtain the average L31_NON_REGENT_MOD latency for data reloads. ##0AC040000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT_MOD to obtain the average L31_NON_REGENT_MOD latency for data reloads. #1470,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT_MOD to obtain the average L31_NON_REGENT_MOD latency for data page table reloads. ##0AC060000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT_MOD to obtain the average L31_NON_REGENT_MOD latency for data page table reloads. #1471,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT_MOD_ALL to obtain the average L31_NON_REGENT_MOD_ALL latency for instruction page table reloads. ##0AC020000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT_MOD_ALL to obtain the average L31_NON_REGENT_MOD_ALL latency for instruction page table reloads. #1472,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT_MOD_ALL to obtain the average L31_NON_REGENT_MOD_ALL latency for data reloads. ##0AC040000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT_MOD_ALL to obtain the average L31_NON_REGENT_MOD_ALL latency for data reloads. #1473,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT_MOD_ALL to obtain the average L31_NON_REGENT_MOD_ALL latency for data page table reloads. ##0AC060000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT_MOD_ALL to obtain the average L31_NON_REGENT_MOD_ALL latency for data page table reloads. #1474,u,g,n,n,m,u,PM_MRK_INST_FROM_L31_NON_REGENT_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_L31_NON_REGENT to obtain the average L31_NON_REGENT latency for instruction reloads. ##0A8100000003C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_L31_NON_REGENT to obtain the average L31_NON_REGENT latency for instruction reloads. #1475,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT to obtain the average L31_NON_REGENT latency for instruction page table reloads. ##0A8120000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT to obtain the average L31_NON_REGENT latency for instruction page table reloads. #1476,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT to obtain the average L31_NON_REGENT latency for data reloads. ##0A8140000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT to obtain the average L31_NON_REGENT latency for data reloads. #1477,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT to obtain the average L31_NON_REGENT latency for data page table reloads. ##0A8160000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT to obtain the average L31_NON_REGENT latency for data page table reloads. #1478,u,g,n,n,m,u,PM_MRK_INST_FROM_L31_NON_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L31_NON_REGENT_ALL to obtain the average L31_NON_REGENT_ALL latency for instruction reloads. ##0A8100000013C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L31_NON_REGENT_ALL to obtain the average L31_NON_REGENT_ALL latency for instruction reloads. #1479,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT_ALL to obtain the average L31_NON_REGENT_ALL latency for instruction page table reloads. ##0A8120000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT_ALL to obtain the average L31_NON_REGENT_ALL latency for instruction page table reloads. #1480,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT_ALL to obtain the average L31_NON_REGENT_ALL latency for data reloads. ##0A8140000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT_ALL to obtain the average L31_NON_REGENT_ALL latency for data reloads. #1481,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT_ALL to obtain the average L31_NON_REGENT_ALL latency for data page table reloads. ##0A8160000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT_ALL to obtain the average L31_NON_REGENT_ALL latency for data page table reloads. #1482,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_SHR to obtain the average NON_REGENT_L2L3_SHR latency for instruction page table reloads. ##0A0220000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_SHR to obtain the average NON_REGENT_L2L3_SHR latency for instruction page table reloads. #1483,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3_SHR to obtain the average NON_REGENT_L2L3_SHR latency for data reloads. ##0A0240000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3_SHR to obtain the average NON_REGENT_L2L3_SHR latency for data reloads. #1484,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_SHR to obtain the average NON_REGENT_L2L3_SHR latency for data page table reloads. ##0A0260000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_SHR to obtain the average NON_REGENT_L2L3_SHR latency for data page table reloads. #1485,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_SHR_ALL to obtain the average NON_REGENT_L2L3_SHR_ALL latency for instruction page table reloads. ##0A0220000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_SHR_ALL to obtain the average NON_REGENT_L2L3_SHR_ALL latency for instruction page table reloads. #1486,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3_SHR_ALL to obtain the average NON_REGENT_L2L3_SHR_ALL latency for data reloads. ##0A0240000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3_SHR_ALL to obtain the average NON_REGENT_L2L3_SHR_ALL latency for data reloads. #1487,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_SHR_ALL to obtain the average NON_REGENT_L2L3_SHR_ALL latency for data page table reloads. ##0A0260000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_SHR_ALL to obtain the average NON_REGENT_L2L3_SHR_ALL latency for data page table reloads. #1488,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_MOD to obtain the average NON_REGENT_L2L3_MOD latency for instruction page table reloads. ##0A4220000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_MOD to obtain the average NON_REGENT_L2L3_MOD latency for instruction page table reloads. #1489,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3_MOD to obtain the average NON_REGENT_L2L3_MOD latency for data reloads. ##0A4240000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3_MOD to obtain the average NON_REGENT_L2L3_MOD latency for data reloads. #1490,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_MOD to obtain the average NON_REGENT_L2L3_MOD latency for data page table reloads. ##0A4260000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_MOD to obtain the average NON_REGENT_L2L3_MOD latency for data page table reloads. #1491,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_MOD_ALL to obtain the average NON_REGENT_L2L3_MOD_ALL latency for instruction page table reloads. ##0A4220000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_MOD_ALL to obtain the average NON_REGENT_L2L3_MOD_ALL latency for instruction page table reloads. #1492,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3_MOD_ALL to obtain the average NON_REGENT_L2L3_MOD_ALL latency for data reloads. ##0A4240000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3_MOD_ALL to obtain the average NON_REGENT_L2L3_MOD_ALL latency for data reloads. #1493,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_MOD_ALL to obtain the average NON_REGENT_L2L3_MOD_ALL latency for data page table reloads. ##0A4260000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_MOD_ALL to obtain the average NON_REGENT_L2L3_MOD_ALL latency for data page table reloads. #1494,u,g,n,n,m,u,PM_MRK_INST_FROM_NON_REGENT_L2L3_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_NON_REGENT_L2L3 to obtain the average NON_REGENT_L2L3 latency for instruction reloads. ##0A0300000003C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_NON_REGENT_L2L3 to obtain the average NON_REGENT_L2L3 latency for instruction reloads. #1495,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3 to obtain the average NON_REGENT_L2L3 latency for instruction page table reloads. ##0A0320000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3 to obtain the average NON_REGENT_L2L3 latency for instruction page table reloads. #1496,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3 to obtain the average NON_REGENT_L2L3 latency for data reloads. ##0A0340000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3 to obtain the average NON_REGENT_L2L3 latency for data reloads. #1497,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3 to obtain the average NON_REGENT_L2L3 latency for data page table reloads. ##0A0360000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3 to obtain the average NON_REGENT_L2L3 latency for data page table reloads. #1498,u,g,n,n,m,u,PM_MRK_INST_FROM_NON_REGENT_L2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_NON_REGENT_L2L3_ALL to obtain the average NON_REGENT_L2L3_ALL latency for instruction reloads. ##0A0300000013C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_NON_REGENT_L2L3_ALL to obtain the average NON_REGENT_L2L3_ALL latency for instruction reloads. #1499,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_ALL to obtain the average NON_REGENT_L2L3_ALL latency for instruction page table reloads. ##0A0320000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_ALL to obtain the average NON_REGENT_L2L3_ALL latency for instruction page table reloads. #1500,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3_ALL to obtain the average NON_REGENT_L2L3_ALL latency for data reloads. ##0A0340000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3_ALL to obtain the average NON_REGENT_L2L3_ALL latency for data reloads. #1501,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_ALL to obtain the average NON_REGENT_L2L3_ALL latency for data page table reloads. ##0A0360000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_ALL to obtain the average NON_REGENT_L2L3_ALL latency for data page table reloads. #1502,u,g,n,n,m,u,PM_MRK_INST_FROM_LMEM_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local chip's memory due to a demand miss. Divide this count by PM_MRK_INST_FROM_LMEM to obtain the average LMEM latency for instruction reloads. ##094100000003C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local chip's memory due to a demand miss. Divide this count by PM_MRK_INST_FROM_LMEM to obtain the average LMEM latency for instruction reloads. #1503,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_LMEM_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_LMEM to obtain the average LMEM latency for instruction page table reloads. ##094020000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_LMEM to obtain the average LMEM latency for instruction page table reloads. #1504,u,g,n,n,m,u,PM_MRK_DATA_FROM_LMEM_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_LMEM to obtain the average LMEM latency for data reloads. ##094040000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_LMEM to obtain the average LMEM latency for data reloads. #1505,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_LMEM_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_LMEM to obtain the average LMEM latency for data page table reloads. ##094060000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_LMEM to obtain the average LMEM latency for data page table reloads. #1506,u,g,n,n,m,u,PM_MRK_INST_FROM_LMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local chip's memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_LMEM_ALL to obtain the average LMEM_ALL latency for instruction reloads. ##094100000013C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local chip's memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_LMEM_ALL to obtain the average LMEM_ALL latency for instruction reloads. #1507,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_LMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_LMEM_ALL to obtain the average LMEM_ALL latency for instruction page table reloads. ##094020000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_LMEM_ALL to obtain the average LMEM_ALL latency for instruction page table reloads. #1508,u,g,n,n,m,u,PM_MRK_DATA_FROM_LMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_LMEM_ALL to obtain the average LMEM_ALL latency for data reloads. ##094040000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_LMEM_ALL to obtain the average LMEM_ALL latency for data reloads. #1509,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_LMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_LMEM_ALL to obtain the average LMEM_ALL latency for data page table reloads. ##094060000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_LMEM_ALL to obtain the average LMEM_ALL latency for data page table reloads. #1510,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_CACHE_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L_OC_CACHE to obtain the average L_OC_CACHE latency for instruction page table reloads. ##098020000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L_OC_CACHE to obtain the average L_OC_CACHE latency for instruction page table reloads. #1511,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_CACHE_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L_OC_CACHE to obtain the average L_OC_CACHE latency for data reloads. ##098040000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L_OC_CACHE to obtain the average L_OC_CACHE latency for data reloads. #1512,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_CACHE_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L_OC_CACHE to obtain the average L_OC_CACHE latency for data page table reloads. ##098060000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L_OC_CACHE to obtain the average L_OC_CACHE latency for data page table reloads. #1513,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L_OC_CACHE_ALL to obtain the average L_OC_CACHE_ALL latency for instruction page table reloads. ##098020000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L_OC_CACHE_ALL to obtain the average L_OC_CACHE_ALL latency for instruction page table reloads. #1514,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L_OC_CACHE_ALL to obtain the average L_OC_CACHE_ALL latency for data reloads. ##098040000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L_OC_CACHE_ALL to obtain the average L_OC_CACHE_ALL latency for data reloads. #1515,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L_OC_CACHE_ALL to obtain the average L_OC_CACHE_ALL latency for data page table reloads. ##098060000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L_OC_CACHE_ALL to obtain the average L_OC_CACHE_ALL latency for data page table reloads. #1516,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_MEM_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L_OC_MEM to obtain the average L_OC_MEM latency for instruction page table reloads. ##09C020000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L_OC_MEM to obtain the average L_OC_MEM latency for instruction page table reloads. #1517,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_MEM_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L_OC_MEM to obtain the average L_OC_MEM latency for data reloads. ##09C040000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L_OC_MEM to obtain the average L_OC_MEM latency for data reloads. #1518,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_MEM_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L_OC_MEM to obtain the average L_OC_MEM latency for data page table reloads. ##09C060000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L_OC_MEM to obtain the average L_OC_MEM latency for data page table reloads. #1519,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_MEM_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L_OC_MEM_ALL to obtain the average L_OC_MEM_ALL latency for instruction page table reloads. ##09C020000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L_OC_MEM_ALL to obtain the average L_OC_MEM_ALL latency for instruction page table reloads. #1520,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_MEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L_OC_MEM_ALL to obtain the average L_OC_MEM_ALL latency for data reloads. ##09C040000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L_OC_MEM_ALL to obtain the average L_OC_MEM_ALL latency for data reloads. #1521,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_MEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L_OC_MEM_ALL to obtain the average L_OC_MEM_ALL latency for data page table reloads. ##09C060000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L_OC_MEM_ALL to obtain the average L_OC_MEM_ALL latency for data page table reloads. #1522,u,g,n,n,m,u,PM_MRK_INST_FROM_L_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_INST_FROM_L_OC_ANY to obtain the average L_OC_ANY latency for instruction reloads. ##098100000003C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_INST_FROM_L_OC_ANY to obtain the average L_OC_ANY latency for instruction reloads. #1523,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L_OC_ANY to obtain the average L_OC_ANY latency for instruction page table reloads. ##098120000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L_OC_ANY to obtain the average L_OC_ANY latency for instruction page table reloads. #1524,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L_OC_ANY to obtain the average L_OC_ANY latency for data reloads. ##098140000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L_OC_ANY to obtain the average L_OC_ANY latency for data reloads. #1525,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L_OC_ANY to obtain the average L_OC_ANY latency for data page table reloads. ##098160000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L_OC_ANY to obtain the average L_OC_ANY latency for data page table reloads. #1526,u,g,n,n,m,u,PM_MRK_INST_FROM_L_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L_OC_ANY_ALL to obtain the average L_OC_ANY_ALL latency for instruction reloads. ##098100000013C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L_OC_ANY_ALL to obtain the average L_OC_ANY_ALL latency for instruction reloads. #1527,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L_OC_ANY_ALL to obtain the average L_OC_ANY_ALL latency for instruction page table reloads. ##098120000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L_OC_ANY_ALL to obtain the average L_OC_ANY_ALL latency for instruction page table reloads. #1528,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L_OC_ANY_ALL to obtain the average L_OC_ANY_ALL latency for data reloads. ##098140000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L_OC_ANY_ALL to obtain the average L_OC_ANY_ALL latency for data reloads. #1529,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L_OC_ANY_ALL to obtain the average L_OC_ANY_ALL latency for data page table reloads. ##098160000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L_OC_ANY_ALL to obtain the average L_OC_ANY_ALL latency for data page table reloads. #1530,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2_SHR to obtain the average RL2_SHR latency for instruction page table reloads. ##0C0020000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2_SHR to obtain the average RL2_SHR latency for instruction page table reloads. #1531,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2_SHR to obtain the average RL2_SHR latency for data reloads. ##0C0040000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2_SHR to obtain the average RL2_SHR latency for data reloads. #1532,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2_SHR to obtain the average RL2_SHR latency for data page table reloads. ##0C0060000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2_SHR to obtain the average RL2_SHR latency for data page table reloads. #1533,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2_SHR_ALL to obtain the average RL2_SHR_ALL latency for instruction page table reloads. ##0C0020000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2_SHR_ALL to obtain the average RL2_SHR_ALL latency for instruction page table reloads. #1534,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2_SHR_ALL to obtain the average RL2_SHR_ALL latency for data reloads. ##0C0040000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2_SHR_ALL to obtain the average RL2_SHR_ALL latency for data reloads. #1535,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2_SHR_ALL to obtain the average RL2_SHR_ALL latency for data page table reloads. ##0C0060000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2_SHR_ALL to obtain the average RL2_SHR_ALL latency for data page table reloads. #1536,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2_MOD to obtain the average RL2_MOD latency for instruction page table reloads. ##0C4020000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2_MOD to obtain the average RL2_MOD latency for instruction page table reloads. #1537,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2_MOD to obtain the average RL2_MOD latency for data reloads. ##0C4040000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2_MOD to obtain the average RL2_MOD latency for data reloads. #1538,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2_MOD to obtain the average RL2_MOD latency for data page table reloads. ##0C4060000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2_MOD to obtain the average RL2_MOD latency for data page table reloads. #1539,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2_MOD_ALL to obtain the average RL2_MOD_ALL latency for instruction page table reloads. ##0C4020000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2_MOD_ALL to obtain the average RL2_MOD_ALL latency for instruction page table reloads. #1540,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2_MOD_ALL to obtain the average RL2_MOD_ALL latency for data reloads. ##0C4040000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2_MOD_ALL to obtain the average RL2_MOD_ALL latency for data reloads. #1541,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2_MOD_ALL to obtain the average RL2_MOD_ALL latency for data page table reloads. ##0C4060000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2_MOD_ALL to obtain the average RL2_MOD_ALL latency for data page table reloads. #1542,u,g,n,n,m,u,PM_MRK_INST_FROM_RL2_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_RL2 to obtain the average RL2 latency for instruction reloads. ##0C0100000003C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_RL2 to obtain the average RL2 latency for instruction reloads. #1543,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2 to obtain the average RL2 latency for instruction page table reloads. ##0C0120000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2 to obtain the average RL2 latency for instruction page table reloads. #1544,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2 to obtain the average RL2 latency for data reloads. ##0C0140000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2 to obtain the average RL2 latency for data reloads. #1545,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2 to obtain the average RL2 latency for data page table reloads. ##0C0160000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2 to obtain the average RL2 latency for data page table reloads. #1546,u,g,n,n,m,u,PM_MRK_INST_FROM_RL2_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_RL2_ALL to obtain the average RL2_ALL latency for instruction reloads. ##0C0100000013C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_RL2_ALL to obtain the average RL2_ALL latency for instruction reloads. #1547,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2_ALL to obtain the average RL2_ALL latency for instruction page table reloads. ##0C0120000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2_ALL to obtain the average RL2_ALL latency for instruction page table reloads. #1548,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2_ALL to obtain the average RL2_ALL latency for data reloads. ##0C0140000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2_ALL to obtain the average RL2_ALL latency for data reloads. #1549,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2_ALL to obtain the average RL2_ALL latency for data page table reloads. ##0C0160000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2_ALL to obtain the average RL2_ALL latency for data page table reloads. #1550,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL3_SHR to obtain the average RL3_SHR latency for instruction page table reloads. ##0C8020000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL3_SHR to obtain the average RL3_SHR latency for instruction page table reloads. #1551,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL3_SHR to obtain the average RL3_SHR latency for data reloads. ##0C8040000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL3_SHR to obtain the average RL3_SHR latency for data reloads. #1552,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL3_SHR to obtain the average RL3_SHR latency for data page table reloads. ##0C8060000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL3_SHR to obtain the average RL3_SHR latency for data page table reloads. #1553,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL3_SHR_ALL to obtain the average RL3_SHR_ALL latency for instruction page table reloads. ##0C8020000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL3_SHR_ALL to obtain the average RL3_SHR_ALL latency for instruction page table reloads. #1554,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL3_SHR_ALL to obtain the average RL3_SHR_ALL latency for data reloads. ##0C8040000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL3_SHR_ALL to obtain the average RL3_SHR_ALL latency for data reloads. #1555,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL3_SHR_ALL to obtain the average RL3_SHR_ALL latency for data page table reloads. ##0C8060000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL3_SHR_ALL to obtain the average RL3_SHR_ALL latency for data page table reloads. #1556,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL3_MOD to obtain the average RL3_MOD latency for instruction page table reloads. ##0CC020000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL3_MOD to obtain the average RL3_MOD latency for instruction page table reloads. #1557,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL3_MOD to obtain the average RL3_MOD latency for data reloads. ##0CC040000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL3_MOD to obtain the average RL3_MOD latency for data reloads. #1558,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL3_MOD to obtain the average RL3_MOD latency for data page table reloads. ##0CC060000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL3_MOD to obtain the average RL3_MOD latency for data page table reloads. #1559,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL3_MOD_ALL to obtain the average RL3_MOD_ALL latency for instruction page table reloads. ##0CC020000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL3_MOD_ALL to obtain the average RL3_MOD_ALL latency for instruction page table reloads. #1560,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL3_MOD_ALL to obtain the average RL3_MOD_ALL latency for data reloads. ##0CC040000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL3_MOD_ALL to obtain the average RL3_MOD_ALL latency for data reloads. #1561,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL3_MOD_ALL to obtain the average RL3_MOD_ALL latency for data page table reloads. ##0CC060000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL3_MOD_ALL to obtain the average RL3_MOD_ALL latency for data page table reloads. #1562,u,g,n,n,m,u,PM_MRK_INST_FROM_RL3_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_RL3 to obtain the average RL3 latency for instruction reloads. ##0C8100000003C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_RL3 to obtain the average RL3 latency for instruction reloads. #1563,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL3 to obtain the average RL3 latency for instruction page table reloads. ##0C8120000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL3 to obtain the average RL3 latency for instruction page table reloads. #1564,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL3 to obtain the average RL3 latency for data reloads. ##0C8140000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL3 to obtain the average RL3 latency for data reloads. #1565,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL3 to obtain the average RL3 latency for data page table reloads. ##0C8160000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL3 to obtain the average RL3 latency for data page table reloads. #1566,u,g,n,n,m,u,PM_MRK_INST_FROM_RL3_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_RL3_ALL to obtain the average RL3_ALL latency for instruction reloads. ##0C8100000013C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_RL3_ALL to obtain the average RL3_ALL latency for instruction reloads. #1567,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL3_ALL to obtain the average RL3_ALL latency for instruction page table reloads. ##0C8120000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL3_ALL to obtain the average RL3_ALL latency for instruction page table reloads. #1568,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL3_ALL to obtain the average RL3_ALL latency for data reloads. ##0C8140000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL3_ALL to obtain the average RL3_ALL latency for data reloads. #1569,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL3_ALL to obtain the average RL3_ALL latency for data page table reloads. ##0C8160000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL3_ALL to obtain the average RL3_ALL latency for data page table reloads. #1570,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2L3_SHR to obtain the average RL2L3_SHR latency for instruction page table reloads. ##0C0220000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2L3_SHR to obtain the average RL2L3_SHR latency for instruction page table reloads. #1571,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2L3_SHR to obtain the average RL2L3_SHR latency for data reloads. ##0C0240000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2L3_SHR to obtain the average RL2L3_SHR latency for data reloads. #1572,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2L3_SHR to obtain the average RL2L3_SHR latency for data page table reloads. ##0C0260000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2L3_SHR to obtain the average RL2L3_SHR latency for data page table reloads. #1573,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2L3_SHR_ALL to obtain the average RL2L3_SHR_ALL latency for instruction page table reloads. ##0C0220000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2L3_SHR_ALL to obtain the average RL2L3_SHR_ALL latency for instruction page table reloads. #1574,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2L3_SHR_ALL to obtain the average RL2L3_SHR_ALL latency for data reloads. ##0C0240000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2L3_SHR_ALL to obtain the average RL2L3_SHR_ALL latency for data reloads. #1575,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2L3_SHR_ALL to obtain the average RL2L3_SHR_ALL latency for data page table reloads. ##0C0260000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2L3_SHR_ALL to obtain the average RL2L3_SHR_ALL latency for data page table reloads. #1576,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2L3_MOD to obtain the average RL2L3_MOD latency for instruction page table reloads. ##0C4220000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2L3_MOD to obtain the average RL2L3_MOD latency for instruction page table reloads. #1577,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2L3_MOD to obtain the average RL2L3_MOD latency for data reloads. ##0C4240000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2L3_MOD to obtain the average RL2L3_MOD latency for data reloads. #1578,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2L3_MOD to obtain the average RL2L3_MOD latency for data page table reloads. ##0C4260000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2L3_MOD to obtain the average RL2L3_MOD latency for data page table reloads. #1579,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2L3_MOD_ALL to obtain the average RL2L3_MOD_ALL latency for instruction page table reloads. ##0C4220000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2L3_MOD_ALL to obtain the average RL2L3_MOD_ALL latency for instruction page table reloads. #1580,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2L3_MOD_ALL to obtain the average RL2L3_MOD_ALL latency for data reloads. ##0C4240000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2L3_MOD_ALL to obtain the average RL2L3_MOD_ALL latency for data reloads. #1581,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2L3_MOD_ALL to obtain the average RL2L3_MOD_ALL latency for data page table reloads. ##0C4260000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2L3_MOD_ALL to obtain the average RL2L3_MOD_ALL latency for data page table reloads. #1582,u,g,n,n,m,u,PM_MRK_INST_FROM_RL2L3_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_RL2L3 to obtain the average RL2L3 latency for instruction reloads. ##0C0300000003C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_RL2L3 to obtain the average RL2L3 latency for instruction reloads. #1583,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2L3 to obtain the average RL2L3 latency for instruction page table reloads. ##0C0320000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2L3 to obtain the average RL2L3 latency for instruction page table reloads. #1584,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2L3 to obtain the average RL2L3 latency for data reloads. ##0C0340000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2L3 to obtain the average RL2L3 latency for data reloads. #1585,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2L3 to obtain the average RL2L3 latency for data page table reloads. ##0C0360000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2L3 to obtain the average RL2L3 latency for data page table reloads. #1586,u,g,n,n,m,u,PM_MRK_INST_FROM_RL2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_RL2L3_ALL to obtain the average RL2L3_ALL latency for instruction reloads. ##0C0300000013C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_RL2L3_ALL to obtain the average RL2L3_ALL latency for instruction reloads. #1587,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2L3_ALL to obtain the average RL2L3_ALL latency for instruction page table reloads. ##0C0320000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2L3_ALL to obtain the average RL2L3_ALL latency for instruction page table reloads. #1588,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2L3_ALL to obtain the average RL2L3_ALL latency for data reloads. ##0C0340000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2L3_ALL to obtain the average RL2L3_ALL latency for data reloads. #1589,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2L3_ALL to obtain the average RL2L3_ALL latency for data page table reloads. ##0C0360000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2L3_ALL to obtain the average RL2L3_ALL latency for data page table reloads. #1590,u,g,n,n,m,u,PM_MRK_INST_FROM_RMEM_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from remote memory (MC slow) due to a demand miss. Divide this count by PM_MRK_INST_FROM_RMEM to obtain the average RMEM latency for instruction reloads. ##0D4100000003C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from remote memory (MC slow) due to a demand miss. Divide this count by PM_MRK_INST_FROM_RMEM to obtain the average RMEM latency for instruction reloads. #1591,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RMEM_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from remote memory (MC slow) due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RMEM to obtain the average RMEM latency for instruction page table reloads. ##0D4020000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from remote memory (MC slow) due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RMEM to obtain the average RMEM latency for instruction page table reloads. #1592,u,g,n,n,m,u,PM_MRK_DATA_FROM_RMEM_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from remote memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RMEM to obtain the average RMEM latency for data reloads. ##0D4040000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from remote memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RMEM to obtain the average RMEM latency for data reloads. #1593,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RMEM_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from remote memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RMEM to obtain the average RMEM latency for data page table reloads. ##0D4060000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from remote memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RMEM to obtain the average RMEM latency for data page table reloads. #1594,u,g,n,n,m,u,PM_MRK_INST_FROM_RMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_RMEM_ALL to obtain the average RMEM_ALL latency for instruction reloads. ##0D4100000013C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_RMEM_ALL to obtain the average RMEM_ALL latency for instruction reloads. #1595,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RMEM_ALL to obtain the average RMEM_ALL latency for instruction page table reloads. ##0D4020000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RMEM_ALL to obtain the average RMEM_ALL latency for instruction page table reloads. #1596,u,g,n,n,m,u,PM_MRK_DATA_FROM_RMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RMEM_ALL to obtain the average RMEM_ALL latency for data reloads. ##0D4040000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RMEM_ALL to obtain the average RMEM_ALL latency for data reloads. #1597,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RMEM_ALL to obtain the average RMEM_ALL latency for data page table reloads. ##0D4060000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RMEM_ALL to obtain the average RMEM_ALL latency for data page table reloads. #1598,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_CACHE_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_R_OC_CACHE to obtain the average R_OC_CACHE latency for instruction page table reloads. ##0D8020000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_R_OC_CACHE to obtain the average R_OC_CACHE latency for instruction page table reloads. #1599,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_CACHE_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DATA_FROM_R_OC_CACHE to obtain the average R_OC_CACHE latency for data reloads. ##0D8040000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DATA_FROM_R_OC_CACHE to obtain the average R_OC_CACHE latency for data reloads. #1600,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_CACHE_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_R_OC_CACHE to obtain the average R_OC_CACHE latency for data page table reloads. ##0D8060000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_R_OC_CACHE to obtain the average R_OC_CACHE latency for data page table reloads. #1601,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_R_OC_CACHE_ALL to obtain the average R_OC_CACHE_ALL latency for instruction page table reloads. ##0D8020000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_R_OC_CACHE_ALL to obtain the average R_OC_CACHE_ALL latency for instruction page table reloads. #1602,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_R_OC_CACHE_ALL to obtain the average R_OC_CACHE_ALL latency for data reloads. ##0D8040000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_R_OC_CACHE_ALL to obtain the average R_OC_CACHE_ALL latency for data reloads. #1603,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_R_OC_CACHE_ALL to obtain the average R_OC_CACHE_ALL latency for data page table reloads. ##0D8060000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_R_OC_CACHE_ALL to obtain the average R_OC_CACHE_ALL latency for data page table reloads. #1604,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_MEM_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_R_OC_MEM to obtain the average R_OC_MEM latency for instruction page table reloads. ##0DC020000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_R_OC_MEM to obtain the average R_OC_MEM latency for instruction page table reloads. #1605,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_MEM_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_R_OC_MEM to obtain the average R_OC_MEM latency for data reloads. ##0DC040000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_R_OC_MEM to obtain the average R_OC_MEM latency for data reloads. #1606,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_MEM_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_R_OC_MEM to obtain the average R_OC_MEM latency for data page table reloads. ##0DC060000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_R_OC_MEM to obtain the average R_OC_MEM latency for data page table reloads. #1607,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_MEM_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_R_OC_MEM_ALL to obtain the average R_OC_MEM_ALL latency for instruction page table reloads. ##0DC020000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_R_OC_MEM_ALL to obtain the average R_OC_MEM_ALL latency for instruction page table reloads. #1608,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_MEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_R_OC_MEM_ALL to obtain the average R_OC_MEM_ALL latency for data reloads. ##0DC040000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_R_OC_MEM_ALL to obtain the average R_OC_MEM_ALL latency for data reloads. #1609,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_MEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_R_OC_MEM_ALL to obtain the average R_OC_MEM_ALL latency for data page table reloads. ##0DC060000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_R_OC_MEM_ALL to obtain the average R_OC_MEM_ALL latency for data page table reloads. #1610,u,g,n,n,m,u,PM_MRK_INST_FROM_R_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_INST_FROM_R_OC_ANY to obtain the average R_OC_ANY latency for instruction reloads. ##0D8100000003C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_INST_FROM_R_OC_ANY to obtain the average R_OC_ANY latency for instruction reloads. #1611,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_R_OC_ANY to obtain the average R_OC_ANY latency for instruction page table reloads. ##0D8120000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_R_OC_ANY to obtain the average R_OC_ANY latency for instruction page table reloads. #1612,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_R_OC_ANY to obtain the average R_OC_ANY latency for data reloads. ##0D8140000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_R_OC_ANY to obtain the average R_OC_ANY latency for data reloads. #1613,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_R_OC_ANY to obtain the average R_OC_ANY latency for data page table reloads. ##0D8160000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_R_OC_ANY to obtain the average R_OC_ANY latency for data page table reloads. #1614,u,g,n,n,m,u,PM_MRK_INST_FROM_R_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_R_OC_ANY_ALL to obtain the average R_OC_ANY_ALL latency for instruction reloads. ##0D8100000013C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_R_OC_ANY_ALL to obtain the average R_OC_ANY_ALL latency for instruction reloads. #1615,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_R_OC_ANY_ALL to obtain the average R_OC_ANY_ALL latency for instruction page table reloads. ##0D8120000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_R_OC_ANY_ALL to obtain the average R_OC_ANY_ALL latency for instruction page table reloads. #1616,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_R_OC_ANY_ALL to obtain the average R_OC_ANY_ALL latency for data reloads. ##0D8140000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_R_OC_ANY_ALL to obtain the average R_OC_ANY_ALL latency for data reloads. #1617,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_R_OC_ANY_ALL to obtain the average R_OC_ANY_ALL latency for data page table reloads. ##0D8160000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_R_OC_ANY_ALL to obtain the average R_OC_ANY_ALL latency for data page table reloads. #1618,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2_SHR to obtain the average DL2_SHR latency for instruction page table reloads. ##0E0020000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2_SHR to obtain the average DL2_SHR latency for instruction page table reloads. #1619,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2_SHR to obtain the average DL2_SHR latency for data reloads. ##0E0040000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2_SHR to obtain the average DL2_SHR latency for data reloads. #1620,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2_SHR to obtain the average DL2_SHR latency for data page table reloads. ##0E0060000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2_SHR to obtain the average DL2_SHR latency for data page table reloads. #1621,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2_SHR_ALL to obtain the average DL2_SHR_ALL latency for instruction page table reloads. ##0E0020000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2_SHR_ALL to obtain the average DL2_SHR_ALL latency for instruction page table reloads. #1622,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2_SHR_ALL to obtain the average DL2_SHR_ALL latency for data reloads. ##0E0040000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2_SHR_ALL to obtain the average DL2_SHR_ALL latency for data reloads. #1623,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2_SHR_ALL to obtain the average DL2_SHR_ALL latency for data page table reloads. ##0E0060000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2_SHR_ALL to obtain the average DL2_SHR_ALL latency for data page table reloads. #1624,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2_MOD to obtain the average DL2_MOD latency for instruction page table reloads. ##0E4020000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2_MOD to obtain the average DL2_MOD latency for instruction page table reloads. #1625,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2_MOD to obtain the average DL2_MOD latency for data reloads. ##0E4040000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2_MOD to obtain the average DL2_MOD latency for data reloads. #1626,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2_MOD to obtain the average DL2_MOD latency for data page table reloads. ##0E4060000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2_MOD to obtain the average DL2_MOD latency for data page table reloads. #1627,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2_MOD_ALL to obtain the average DL2_MOD_ALL latency for instruction page table reloads. ##0E4020000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2_MOD_ALL to obtain the average DL2_MOD_ALL latency for instruction page table reloads. #1628,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2_MOD_ALL to obtain the average DL2_MOD_ALL latency for data reloads. ##0E4040000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2_MOD_ALL to obtain the average DL2_MOD_ALL latency for data reloads. #1629,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2_MOD_ALL to obtain the average DL2_MOD_ALL latency for data page table reloads. ##0E4060000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2_MOD_ALL to obtain the average DL2_MOD_ALL latency for data page table reloads. #1630,u,g,n,n,m,u,PM_MRK_INST_FROM_DL2_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_DL2 to obtain the average DL2 latency for instruction reloads. ##0E0100000003C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_DL2 to obtain the average DL2 latency for instruction reloads. #1631,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2 to obtain the average DL2 latency for instruction page table reloads. ##0E0120000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2 to obtain the average DL2 latency for instruction page table reloads. #1632,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2 to obtain the average DL2 latency for data reloads. ##0E0140000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2 to obtain the average DL2 latency for data reloads. #1633,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2 to obtain the average DL2 latency for data page table reloads. ##0E0160000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2 to obtain the average DL2 latency for data page table reloads. #1634,u,g,n,n,m,u,PM_MRK_INST_FROM_DL2_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_DL2_ALL to obtain the average DL2_ALL latency for instruction reloads. ##0E0100000013C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_DL2_ALL to obtain the average DL2_ALL latency for instruction reloads. #1635,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2_ALL to obtain the average DL2_ALL latency for instruction page table reloads. ##0E0120000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2_ALL to obtain the average DL2_ALL latency for instruction page table reloads. #1636,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2_ALL to obtain the average DL2_ALL latency for data reloads. ##0E0140000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2_ALL to obtain the average DL2_ALL latency for data reloads. #1637,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2_ALL to obtain the average DL2_ALL latency for data page table reloads. ##0E0160000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2_ALL to obtain the average DL2_ALL latency for data page table reloads. #1638,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL3_SHR to obtain the average DL3_SHR latency for instruction page table reloads. ##0E8020000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL3_SHR to obtain the average DL3_SHR latency for instruction page table reloads. #1639,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL3_SHR to obtain the average DL3_SHR latency for data reloads. ##0E8040000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL3_SHR to obtain the average DL3_SHR latency for data reloads. #1640,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL3_SHR to obtain the average DL3_SHR latency for data page table reloads. ##0E8060000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL3_SHR to obtain the average DL3_SHR latency for data page table reloads. #1641,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL3_SHR_ALL to obtain the average DL3_SHR_ALL latency for instruction page table reloads. ##0E8020000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL3_SHR_ALL to obtain the average DL3_SHR_ALL latency for instruction page table reloads. #1642,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL3_SHR_ALL to obtain the average DL3_SHR_ALL latency for data reloads. ##0E8040000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL3_SHR_ALL to obtain the average DL3_SHR_ALL latency for data reloads. #1643,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL3_SHR_ALL to obtain the average DL3_SHR_ALL latency for data page table reloads. ##0E8060000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL3_SHR_ALL to obtain the average DL3_SHR_ALL latency for data page table reloads. #1644,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL3_MOD to obtain the average DL3_MOD latency for instruction page table reloads. ##0EC020000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL3_MOD to obtain the average DL3_MOD latency for instruction page table reloads. #1645,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL3_MOD to obtain the average DL3_MOD latency for data reloads. ##0EC040000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL3_MOD to obtain the average DL3_MOD latency for data reloads. #1646,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL3_MOD to obtain the average DL3_MOD latency for data page table reloads. ##0EC060000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL3_MOD to obtain the average DL3_MOD latency for data page table reloads. #1647,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL3_MOD_ALL to obtain the average DL3_MOD_ALL latency for instruction page table reloads. ##0EC020000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL3_MOD_ALL to obtain the average DL3_MOD_ALL latency for instruction page table reloads. #1648,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL3_MOD_ALL to obtain the average DL3_MOD_ALL latency for data reloads. ##0EC040000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL3_MOD_ALL to obtain the average DL3_MOD_ALL latency for data reloads. #1649,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL3_MOD_ALL to obtain the average DL3_MOD_ALL latency for data page table reloads. ##0EC060000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL3_MOD_ALL to obtain the average DL3_MOD_ALL latency for data page table reloads. #1650,u,g,n,n,m,u,PM_MRK_INST_FROM_DL3_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_DL3 to obtain the average DL3 latency for instruction reloads. ##0E8100000003C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_DL3 to obtain the average DL3 latency for instruction reloads. #1651,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL3 to obtain the average DL3 latency for instruction page table reloads. ##0E8120000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL3 to obtain the average DL3 latency for instruction page table reloads. #1652,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL3 to obtain the average DL3 latency for data reloads. ##0E8140000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL3 to obtain the average DL3 latency for data reloads. #1653,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL3 to obtain the average DL3 latency for data page table reloads. ##0E8160000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL3 to obtain the average DL3 latency for data page table reloads. #1654,u,g,n,n,m,u,PM_MRK_INST_FROM_DL3_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_DL3_ALL to obtain the average DL3_ALL latency for instruction reloads. ##0E8100000013C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_DL3_ALL to obtain the average DL3_ALL latency for instruction reloads. #1655,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL3_ALL to obtain the average DL3_ALL latency for instruction page table reloads. ##0E8120000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL3_ALL to obtain the average DL3_ALL latency for instruction page table reloads. #1656,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL3_ALL to obtain the average DL3_ALL latency for data reloads. ##0E8140000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL3_ALL to obtain the average DL3_ALL latency for data reloads. #1657,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL3_ALL to obtain the average DL3_ALL latency for data page table reloads. ##0E8160000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL3_ALL to obtain the average DL3_ALL latency for data page table reloads. #1658,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2L3_SHR to obtain the average DL2L3_SHR latency for instruction page table reloads. ##0E0220000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2L3_SHR to obtain the average DL2L3_SHR latency for instruction page table reloads. #1659,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2L3_SHR to obtain the average DL2L3_SHR latency for data reloads. ##0E0240000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2L3_SHR to obtain the average DL2L3_SHR latency for data reloads. #1660,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2L3_SHR to obtain the average DL2L3_SHR latency for data page table reloads. ##0E0260000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2L3_SHR to obtain the average DL2L3_SHR latency for data page table reloads. #1661,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2L3_SHR_ALL to obtain the average DL2L3_SHR_ALL latency for instruction page table reloads. ##0E0220000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2L3_SHR_ALL to obtain the average DL2L3_SHR_ALL latency for instruction page table reloads. #1662,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2L3_SHR_ALL to obtain the average DL2L3_SHR_ALL latency for data reloads. ##0E0240000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2L3_SHR_ALL to obtain the average DL2L3_SHR_ALL latency for data reloads. #1663,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2L3_SHR_ALL to obtain the average DL2L3_SHR_ALL latency for data page table reloads. ##0E0260000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2L3_SHR_ALL to obtain the average DL2L3_SHR_ALL latency for data page table reloads. #1664,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2L3_MOD to obtain the average DL2L3_MOD latency for instruction page table reloads. ##0E4220000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2L3_MOD to obtain the average DL2L3_MOD latency for instruction page table reloads. #1665,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2L3_MOD to obtain the average DL2L3_MOD latency for data reloads. ##0E4240000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2L3_MOD to obtain the average DL2L3_MOD latency for data reloads. #1666,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2L3_MOD to obtain the average DL2L3_MOD latency for data page table reloads. ##0E4260000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2L3_MOD to obtain the average DL2L3_MOD latency for data page table reloads. #1667,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2L3_MOD_ALL to obtain the average DL2L3_MOD_ALL latency for instruction page table reloads. ##0E4220000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2L3_MOD_ALL to obtain the average DL2L3_MOD_ALL latency for instruction page table reloads. #1668,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2L3_MOD_ALL to obtain the average DL2L3_MOD_ALL latency for data reloads. ##0E4240000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2L3_MOD_ALL to obtain the average DL2L3_MOD_ALL latency for data reloads. #1669,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2L3_MOD_ALL to obtain the average DL2L3_MOD_ALL latency for data page table reloads. ##0E4260000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2L3_MOD_ALL to obtain the average DL2L3_MOD_ALL latency for data page table reloads. #1670,u,g,n,n,m,u,PM_MRK_INST_FROM_DL2L3_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_DL2L3 to obtain the average DL2L3 latency for instruction reloads. ##0E0300000003C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_DL2L3 to obtain the average DL2L3 latency for instruction reloads. #1671,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2L3 to obtain the average DL2L3 latency for instruction page table reloads. ##0E0320000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2L3 to obtain the average DL2L3 latency for instruction page table reloads. #1672,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2L3 to obtain the average DL2L3 latency for data reloads. ##0E0340000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2L3 to obtain the average DL2L3 latency for data reloads. #1673,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2L3 to obtain the average DL2L3 latency for data page table reloads. ##0E0360000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2L3 to obtain the average DL2L3 latency for data page table reloads. #1674,u,g,n,n,m,u,PM_MRK_INST_FROM_DL2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_DL2L3_ALL to obtain the average DL2L3_ALL latency for instruction reloads. ##0E0300000013C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_DL2L3_ALL to obtain the average DL2L3_ALL latency for instruction reloads. #1675,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2L3_ALL to obtain the average DL2L3_ALL latency for instruction page table reloads. ##0E0320000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2L3_ALL to obtain the average DL2L3_ALL latency for instruction page table reloads. #1676,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2L3_ALL to obtain the average DL2L3_ALL latency for data reloads. ##0E0340000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2L3_ALL to obtain the average DL2L3_ALL latency for data reloads. #1677,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2L3_ALL to obtain the average DL2L3_ALL latency for data page table reloads. ##0E0360000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2L3_ALL to obtain the average DL2L3_ALL latency for data page table reloads. #1678,u,g,n,n,m,u,PM_MRK_INST_FROM_DMEM_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from distant memory (MC slow) due to a demand miss. Divide this count by PM_MRK_INST_FROM_DMEM to obtain the average DMEM latency for instruction reloads. ##0F4100000003C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from distant memory (MC slow) due to a demand miss. Divide this count by PM_MRK_INST_FROM_DMEM to obtain the average DMEM latency for instruction reloads. #1679,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DMEM_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from distant memory (MC slow) due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DMEM to obtain the average DMEM latency for instruction page table reloads. ##0F4020000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from distant memory (MC slow) due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DMEM to obtain the average DMEM latency for instruction page table reloads. #1680,u,g,n,n,m,u,PM_MRK_DATA_FROM_DMEM_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from distant memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DMEM to obtain the average DMEM latency for data reloads. ##0F4040000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from distant memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DMEM to obtain the average DMEM latency for data reloads. #1681,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DMEM_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from distant memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DMEM to obtain the average DMEM latency for data page table reloads. ##0F4060000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from distant memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DMEM to obtain the average DMEM latency for data page table reloads. #1682,u,g,n,n,m,u,PM_MRK_INST_FROM_DMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_DMEM_ALL to obtain the average DMEM_ALL latency for instruction reloads. ##0F4100000013C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_DMEM_ALL to obtain the average DMEM_ALL latency for instruction reloads. #1683,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DMEM_ALL to obtain the average DMEM_ALL latency for instruction page table reloads. ##0F4020000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DMEM_ALL to obtain the average DMEM_ALL latency for instruction page table reloads. #1684,u,g,n,n,m,u,PM_MRK_DATA_FROM_DMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DMEM_ALL to obtain the average DMEM_ALL latency for data reloads. ##0F4040000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DMEM_ALL to obtain the average DMEM_ALL latency for data reloads. #1685,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DMEM_ALL to obtain the average DMEM_ALL latency for data page table reloads. ##0F4060000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DMEM_ALL to obtain the average DMEM_ALL latency for data page table reloads. #1686,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_CACHE_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_D_OC_CACHE to obtain the average D_OC_CACHE latency for instruction page table reloads. ##0F8020000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_D_OC_CACHE to obtain the average D_OC_CACHE latency for instruction page table reloads. #1687,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_CACHE_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DATA_FROM_D_OC_CACHE to obtain the average D_OC_CACHE latency for data reloads. ##0F8040000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DATA_FROM_D_OC_CACHE to obtain the average D_OC_CACHE latency for data reloads. #1688,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_CACHE_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_D_OC_CACHE to obtain the average D_OC_CACHE latency for data page table reloads. ##0F8060000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_D_OC_CACHE to obtain the average D_OC_CACHE latency for data page table reloads. #1689,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_D_OC_CACHE_ALL to obtain the average D_OC_CACHE_ALL latency for instruction page table reloads. ##0F8020000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_D_OC_CACHE_ALL to obtain the average D_OC_CACHE_ALL latency for instruction page table reloads. #1690,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_D_OC_CACHE_ALL to obtain the average D_OC_CACHE_ALL latency for data reloads. ##0F8040000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_D_OC_CACHE_ALL to obtain the average D_OC_CACHE_ALL latency for data reloads. #1691,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_D_OC_CACHE_ALL to obtain the average D_OC_CACHE_ALL latency for data page table reloads. ##0F8060000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_D_OC_CACHE_ALL to obtain the average D_OC_CACHE_ALL latency for data page table reloads. #1692,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_MEM_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_D_OC_MEM to obtain the average D_OC_MEM latency for instruction page table reloads. ##0FC020000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_D_OC_MEM to obtain the average D_OC_MEM latency for instruction page table reloads. #1693,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_MEM_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_D_OC_MEM to obtain the average D_OC_MEM latency for data reloads. ##0FC040000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_D_OC_MEM to obtain the average D_OC_MEM latency for data reloads. #1694,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_MEM_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_D_OC_MEM to obtain the average D_OC_MEM latency for data page table reloads. ##0FC060000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_D_OC_MEM to obtain the average D_OC_MEM latency for data page table reloads. #1695,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_MEM_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_D_OC_MEM_ALL to obtain the average D_OC_MEM_ALL latency for instruction page table reloads. ##0FC020000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_D_OC_MEM_ALL to obtain the average D_OC_MEM_ALL latency for instruction page table reloads. #1696,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_MEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_D_OC_MEM_ALL to obtain the average D_OC_MEM_ALL latency for data reloads. ##0FC040000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_D_OC_MEM_ALL to obtain the average D_OC_MEM_ALL latency for data reloads. #1697,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_MEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_D_OC_MEM_ALL to obtain the average D_OC_MEM_ALL latency for data page table reloads. ##0FC060000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_D_OC_MEM_ALL to obtain the average D_OC_MEM_ALL latency for data page table reloads. #1698,u,g,n,n,m,u,PM_MRK_INST_FROM_D_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_INST_FROM_D_OC_ANY to obtain the average D_OC_ANY latency for instruction reloads. ##0F8100000003C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_INST_FROM_D_OC_ANY to obtain the average D_OC_ANY latency for instruction reloads. #1699,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_D_OC_ANY to obtain the average D_OC_ANY latency for instruction page table reloads. ##0F8120000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_D_OC_ANY to obtain the average D_OC_ANY latency for instruction page table reloads. #1700,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_D_OC_ANY to obtain the average D_OC_ANY latency for data reloads. ##0F8140000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_D_OC_ANY to obtain the average D_OC_ANY latency for data reloads. #1701,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_D_OC_ANY to obtain the average D_OC_ANY latency for data page table reloads. ##0F8160000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_D_OC_ANY to obtain the average D_OC_ANY latency for data page table reloads. #1702,u,g,n,n,m,u,PM_MRK_INST_FROM_D_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_D_OC_ANY_ALL to obtain the average D_OC_ANY_ALL latency for instruction reloads. ##0F8100000013C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_D_OC_ANY_ALL to obtain the average D_OC_ANY_ALL latency for instruction reloads. #1703,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_D_OC_ANY_ALL to obtain the average D_OC_ANY_ALL latency for instruction page table reloads. ##0F8120000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_D_OC_ANY_ALL to obtain the average D_OC_ANY_ALL latency for instruction page table reloads. #1704,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_D_OC_ANY_ALL to obtain the average D_OC_ANY_ALL latency for data reloads. ##0F8140000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_D_OC_ANY_ALL to obtain the average D_OC_ANY_ALL latency for data reloads. #1705,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_D_OC_ANY_ALL to obtain the average D_OC_ANY_ALL latency for data page table reloads. ##0F8160000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_D_OC_ANY_ALL to obtain the average D_OC_ANY_ALL latency for data page table reloads. #1706,u,g,n,n,m,u,PM_MRK_INST_FROM_ONCHIP_CACHE_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_ONCHIP_CACHE to obtain the average ONCHIP_CACHE latency for instruction reloads. ##080B00000003C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_ONCHIP_CACHE to obtain the average ONCHIP_CACHE latency for instruction reloads. #1707,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_ONCHIP_CACHE_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_ONCHIP_CACHE to obtain the average ONCHIP_CACHE latency for instruction page table reloads. ##080B20000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_ONCHIP_CACHE to obtain the average ONCHIP_CACHE latency for instruction page table reloads. #1708,u,g,n,n,m,u,PM_MRK_DATA_FROM_ONCHIP_CACHE_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_ONCHIP_CACHE to obtain the average ONCHIP_CACHE latency for data reloads. ##080B40000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_ONCHIP_CACHE to obtain the average ONCHIP_CACHE latency for data reloads. #1709,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_ONCHIP_CACHE_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_ONCHIP_CACHE to obtain the average ONCHIP_CACHE latency for data page table reloads. ##080B60000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_ONCHIP_CACHE to obtain the average ONCHIP_CACHE latency for data page table reloads. #1710,u,g,n,n,m,u,PM_MRK_INST_FROM_ONCHIP_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_ONCHIP_CACHE_ALL to obtain the average ONCHIP_CACHE_ALL latency for instruction reloads. ##080B00000013C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_ONCHIP_CACHE_ALL to obtain the average ONCHIP_CACHE_ALL latency for instruction reloads. #1711,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_ONCHIP_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_ONCHIP_CACHE_ALL to obtain the average ONCHIP_CACHE_ALL latency for instruction page table reloads. ##080B20000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_ONCHIP_CACHE_ALL to obtain the average ONCHIP_CACHE_ALL latency for instruction page table reloads. #1712,u,g,n,n,m,u,PM_MRK_DATA_FROM_ONCHIP_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_ONCHIP_CACHE_ALL to obtain the average ONCHIP_CACHE_ALL latency for data reloads. ##080B40000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_ONCHIP_CACHE_ALL to obtain the average ONCHIP_CACHE_ALL latency for data reloads. #1713,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_ONCHIP_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_ONCHIP_CACHE_ALL to obtain the average ONCHIP_CACHE_ALL latency for data page table reloads. ##080B60000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_ONCHIP_CACHE_ALL to obtain the average ONCHIP_CACHE_ALL latency for data page table reloads. #1714,u,g,n,n,m,u,PM_MRK_INST_FROM_OFFCHIP_CACHE_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_OFFCHIP_CACHE to obtain the average OFFCHIP_CACHE latency for instruction reloads. ##0C0B00000003C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_OFFCHIP_CACHE to obtain the average OFFCHIP_CACHE latency for instruction reloads. #1715,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_OFFCHIP_CACHE_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_OFFCHIP_CACHE to obtain the average OFFCHIP_CACHE latency for instruction page table reloads. ##0C0B20000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_OFFCHIP_CACHE to obtain the average OFFCHIP_CACHE latency for instruction page table reloads. #1716,u,g,n,n,m,u,PM_MRK_DATA_FROM_OFFCHIP_CACHE_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_OFFCHIP_CACHE to obtain the average OFFCHIP_CACHE latency for data reloads. ##0C0B40000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_OFFCHIP_CACHE to obtain the average OFFCHIP_CACHE latency for data reloads. #1717,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_OFFCHIP_CACHE_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_OFFCHIP_CACHE to obtain the average OFFCHIP_CACHE latency for data page table reloads. ##0C0B60000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_OFFCHIP_CACHE to obtain the average OFFCHIP_CACHE latency for data page table reloads. #1718,u,g,n,n,m,u,PM_MRK_INST_FROM_OFFCHIP_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_OFFCHIP_CACHE_ALL to obtain the average OFFCHIP_CACHE_ALL latency for instruction reloads. ##0C0B00000013C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_OFFCHIP_CACHE_ALL to obtain the average OFFCHIP_CACHE_ALL latency for instruction reloads. #1719,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_OFFCHIP_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_OFFCHIP_CACHE_ALL to obtain the average OFFCHIP_CACHE_ALL latency for instruction page table reloads. ##0C0B20000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_OFFCHIP_CACHE_ALL to obtain the average OFFCHIP_CACHE_ALL latency for instruction page table reloads. #1720,u,g,n,n,m,u,PM_MRK_DATA_FROM_OFFCHIP_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_OFFCHIP_CACHE_ALL to obtain the average OFFCHIP_CACHE_ALL latency for data reloads. ##0C0B40000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_OFFCHIP_CACHE_ALL to obtain the average OFFCHIP_CACHE_ALL latency for data reloads. #1721,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_OFFCHIP_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_OFFCHIP_CACHE_ALL to obtain the average OFFCHIP_CACHE_ALL latency for data page table reloads. ##0C0B60000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_OFFCHIP_CACHE_ALL to obtain the average OFFCHIP_CACHE_ALL latency for data page table reloads. #1722,u,g,n,n,m,u,PM_MRK_INST_FROM_ANY_MEMORY_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from any chip's memory (MC slow) due to a demand miss. Divide this count by PM_MRK_INST_FROM_ANY_MEMORY to obtain the average ANY_MEMORY latency for instruction reloads. ##095900000003C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from any chip's memory (MC slow) due to a demand miss. Divide this count by PM_MRK_INST_FROM_ANY_MEMORY to obtain the average ANY_MEMORY latency for instruction reloads. #1723,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_ANY_MEMORY_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from any chip's memory (MC slow) due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_ANY_MEMORY to obtain the average ANY_MEMORY latency for instruction page table reloads. ##095820000003C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from any chip's memory (MC slow) due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_ANY_MEMORY to obtain the average ANY_MEMORY latency for instruction page table reloads. #1724,u,g,n,n,m,u,PM_MRK_DATA_FROM_ANY_MEMORY_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from any chip's memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DATA_FROM_ANY_MEMORY to obtain the average ANY_MEMORY latency for data reloads. ##095840000003C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from any chip's memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DATA_FROM_ANY_MEMORY to obtain the average ANY_MEMORY latency for data reloads. #1725,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_ANY_MEMORY_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from any chip's memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_ANY_MEMORY to obtain the average ANY_MEMORY latency for data page table reloads. ##095860000003C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from any chip's memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_ANY_MEMORY to obtain the average ANY_MEMORY latency for data page table reloads. #1726,u,g,n,n,m,u,PM_MRK_INST_FROM_ANY_MEMORY_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_ANY_MEMORY_ALL to obtain the average ANY_MEMORY_ALL latency for instruction reloads. ##095900000013C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_ANY_MEMORY_ALL to obtain the average ANY_MEMORY_ALL latency for instruction reloads. #1727,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_ANY_MEMORY_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_ANY_MEMORY_ALL to obtain the average ANY_MEMORY_ALL latency for instruction page table reloads. ##095820000013C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_ANY_MEMORY_ALL to obtain the average ANY_MEMORY_ALL latency for instruction page table reloads. #1728,u,g,n,n,m,u,PM_MRK_DATA_FROM_ANY_MEMORY_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_ANY_MEMORY_ALL to obtain the average ANY_MEMORY_ALL latency for data reloads. ##095840000023C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_ANY_MEMORY_ALL to obtain the average ANY_MEMORY_ALL latency for data reloads. #1729,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_ANY_MEMORY_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_ANY_MEMORY_ALL to obtain the average ANY_MEMORY_ALL latency for data page table reloads. ##095860000023C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_ANY_MEMORY_ALL to obtain the average ANY_MEMORY_ALL latency for data page table reloads. $$$$$$$$ { counter 4} #0,u,g,n,n,n,n,PM_SUSPENDED,Counter off ##40000 Counter off #1,u,g,n,n,n,n,PM_INST_CMPL,PowerPC instruction completed ##40002 PowerPC instruction completed #2,u,g,n,n,n,n,PM_CYC,Processor cycles ##4001E Processor cycles #3,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3MISS,The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction. ##0007C0000004C142 The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction. #4,u,g,n,n,n,u,PM_DATA_FROM_L2MISS,The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss. ##0003C0000004C040 The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss. #5,u,g,n,n,n,u,PM_INST_FROM_L3MISS,The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss. ##000780000004C040 The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss. #6,u,g,n,n,n,u,PM_DATA_FROM_L3MISS,The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss. ##0007C0000004C040 The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss. #7,u,g,n,n,n,y,PM_FXU_ISSUE,A fixed point instruction was issued to the VSU. ##40004 A fixed point instruction was issued to the VSU. #8,u,g,n,n,n,y,PM_ISSUE_KILL,Cycles in which an instruction or group of instructions were cancelled after being issued. This event increments once per occurance, regardless of how many instructions are included in the issue group ##40006 Cycles in which an instruction or group of instructions were cancelled after being issued. This event increments once per occurance, regardless of how many instructions are included in the issue group #9,u,g,n,n,n,y,PM_NTC_ALL_FIN,Cycles in which both instructions in the ICT entry pair show as finished. These are the cycles between finish and completion for the oldest pair of instructions in the pipeline ##40008 Cycles in which both instructions in the ICT entry pair show as finished. These are the cycles between finish and completion for the oldest pair of instructions in the pipeline #10,u,g,n,n,n,n,PM_DEBUG_TRIGGER,Counts a trigger generated from the debug logic for lab use ##4000A Counts a trigger generated from the debug logic for lab use #11,u,g,n,n,n,n,PM_FREQ_UP,Power Management: Above Threshold A ##4000C Power Management: Above Threshold A #12,u,g,n,n,m,y,PM_MRK_TLBIE_FIN,Marked TLBIE instruction finished. Includes TLBIE and TLBIEL instructions ##4010E Marked TLBIE instruction finished. Includes TLBIE and TLBIEL instructions #13,u,g,n,n,n,n,PM_PMC3_OVERFLOW,The event selected for PMC3 caused the event counter to overflow. ##40010 The event selected for PMC3 caused the event counter to overflow. #14,u,g,n,n,n,y,PM_L1_ICACHE_RELOADED_ALL,Counts all instruction cache reloads includes demand, prefetch, prefetch turned into demand and demand turned into prefetch ##40012 Counts all instruction cache reloads includes demand, prefetch, prefetch turned into demand and demand turned into prefetch #15,u,g,n,n,m,y,PM_MRK_START_PROBE_NOP_DISP,Marked Start probe nop dispatched. Instruction AND R0,R0,R0 ##40114 Marked Start probe nop dispatched. Instruction AND R0,R0,R0 #16,u,g,n,n,m,y,PM_MRK_LARX_FIN,Marked load and reserve instruction (LARX) finished. LARX and STCX are instructions used to acquire a lock ##40116 Marked load and reserve instruction (LARX) finished. LARX and STCX are instructions used to acquire a lock #17,u,g,n,n,m,y,PM_MRK_DCACHE_RELOAD_INTV,The marked instruction reloaded data from any of the caches on the system excluding the local caches. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches ##40118 The marked instruction reloaded data from any of the caches on the system excluding the local caches. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches #18,u,g,n,n,n,n,PM_SMT_MODE_SWITCH,Counts every time the SMT mode changes, SMT up or SMT down ##4001A Counts every time the SMT mode changes, SMT up or SMT down #19,u,g,n,n,n,y,PM_VSU_FIN,VSU instruction finished ##4001C VSU instruction finished #20,u,g,n,n,n,y,PM_DISP_STALL_BR_MPRED_IC_L3MISS,Cycles when dispatch was stalled while the instruction was fetched from sources beyond the local L3 after suffering a mispredicted branch. ##4C010 Cycles when dispatch was stalled while the instruction was fetched from sources beyond the local L3 after suffering a mispredicted branch. #21,u,g,n,n,n,y,PM_EXEC_STALL_DERAT_ONLY_MISS,Cycles in which the oldest instruction in the pipeline suffered an ERAT miss and waited for it resolve. ##4C012 Cycles in which the oldest instruction in the pipeline suffered an ERAT miss and waited for it resolve. #22,u,g,n,n,n,y,PM_EXEC_STALL_DMISS_L2L3_CONFLICT,Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from the local L2 or local L3, with a dispatch conflict. ##4C016 Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from the local L2 or local L3, with a dispatch conflict. #23,u,g,n,n,n,n,PM_CMPL_STALL,Cycles in which the oldest instruction in the pipeline cannot complete because the thread was blocked for any reason. ##4C018 Cycles in which the oldest instruction in the pipeline cannot complete because the thread was blocked for any reason. #24,u,g,n,n,n,y,PM_EXEC_STALL_DMISS_OFF_NODE,Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from a distant chip. ##4C01A Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from a distant chip. #25,u,g,n,n,n,y,PM_INT_DOORBELL,Cycles an internal doorbell interrupt was active ##4C01C Cycles an internal doorbell interrupt was active #26,u,g,n,n,n,y,PM_LSU_ST3_FIN,LSU Finished an internal operation in ST3 port ##4C01E LSU Finished an internal operation in ST3 port #27,u,g,n,n,n,y,PM_PMC1_SAVED,The conditions for the speculative event selected for PMC1 are met and PMC1 is charged. ##4D010 The conditions for the speculative event selected for PMC1 are met and PMC1 is charged. #28,u,g,n,n,n,y,PM_PMC3_SAVED,The conditions for the speculative event selected for PMC3 are met and PMC3 is charged. ##4D012 The conditions for the speculative event selected for PMC3 are met and PMC3 is charged. #29,u,g,n,n,n,y,PM_EXEC_STALL_LOAD,Cycles in which the oldest instruction in the pipeline was a load instruction executing in the Load Store Unit. ##4D014 Cycles in which the oldest instruction in the pipeline was a load instruction executing in the Load Store Unit. #30,u,g,n,n,n,y,PM_EXEC_STALL_PTESYNC,Cycles in which the oldest instruction in the pipeline was a PTESYNC instruction executing in the Load Store Unit. ##4D016 Cycles in which the oldest instruction in the pipeline was a PTESYNC instruction executing in the Load Store Unit. #31,u,g,n,n,n,y,PM_EXEC_STALL_BRU,Cycles in which the oldest instruction in the pipeline was executing in the Branch unit. ##4D018 Cycles in which the oldest instruction in the pipeline was executing in the Branch unit. #32,u,g,n,n,n,n,PM_CMPL_STALL_HWSYNC,Cycles in which the oldest instruction in the pipeline was a hwsync waiting for response from L2 before completing. ##4D01A Cycles in which the oldest instruction in the pipeline was a hwsync waiting for response from L2 before completing. #33,u,g,n,n,n,y,PM_EXEC_STALL_TLBIEL,Cycles in which the oldest instruction in the pipeline was a TLBIEL instruction executing in the Load Store Unit. TLBIEL instructions have lower overhead than TLBIE instructions because they don't get set to the nest. ##4D01C Cycles in which the oldest instruction in the pipeline was a TLBIEL instruction executing in the Load Store Unit. TLBIEL instructions have lower overhead than TLBIE instructions because they don't get set to the nest. #34,u,g,n,n,n,y,PM_DISP_STALL_BR_MPRED,Cycles when dispatch was stalled for this thread due to a mispredicted branch. ##4D01E Cycles when dispatch was stalled for this thread due to a mispredicted branch. #35,u,g,n,n,n,y,PM_DISP_STALL_IC_L3MISS,Cycles when dispatch was stalled while the instruction was fetched from any source beyond the local L3. ##4E010 Cycles when dispatch was stalled while the instruction was fetched from any source beyond the local L3. #36,u,g,n,n,n,y,PM_EXEC_STALL_UNKNOWN,Cycles in which the oldest instruction in the pipeline completed without an ntf_type pulse. The ntf_pulse was missed by the ISU because the next-to-finish (NTF) instruction finishes and completions came too close together. ##4E012 Cycles in which the oldest instruction in the pipeline completed without an ntf_type pulse. The ntf_pulse was missed by the ISU because the next-to-finish (NTF) instruction finishes and completions came too close together. #37,u,g,n,n,n,y,PM_DISP_STALL_HELD_CYC,Cycles in which the next-to-complete (NTC) instruction is held at dispatch for any reason ##4E01A Cycles in which the next-to-complete (NTC) instruction is held at dispatch for any reason #38,u,g,n,n,n,y,PM_VSU3_ISSUE,VSU instruction was issued to VSU pipe 3 ##4D020 VSU instruction was issued to VSU pipe 3 #39,u,g,n,n,n,n,PM_HYPERVISOR_INST_CMPL,PowerPC instruction completed while the thread was in hypervisor state. ##4D022 PowerPC instruction completed while the thread was in hypervisor state. #40,u,g,n,n,n,n,PM_PROBLEM_INST_CMPL,PowerPC instruction completed while the thread was in problem state. ##4D024 PowerPC instruction completed while the thread was in problem state. #41,u,g,n,n,n,n,PM_ULTRAVISOR_CYC,Cycles when the thread is in Ultravisor state. MSR[S HV PR]=110 ##4D026 Cycles when the thread is in Ultravisor state. MSR[S HV PR]=110 #42,u,g,n,n,n,n,PM_PRIVILEGED_CYC,Cycles when the thread is in Privileged state. MSR[S HV PR]=x00 ##4D028 Cycles when the thread is in Privileged state. MSR[S HV PR]=x00 #43,u,g,n,n,n,y,PM_PMC1_REWIND,The speculative event selected for PMC1 rewinds and the counter for PMC1 is not charged. ##4D02C The speculative event selected for PMC1 rewinds and the counter for PMC1 is not charged. #44,u,g,n,n,n,n,PM_NO_FETCH_CYC,Cycles in which no instructions were fetched by the Instruction Fetch Unit (IFU), for any reason ##4D02E Cycles in which no instructions were fetched by the Instruction Fetch Unit (IFU), for any reason #45,u,g,n,n,n,y,PM_INST_FIN,Instruction finished ##40030 Instruction finished #46,u,g,n,n,m,y,PM_MRK_LSU_FIN,LSU marked instruction finish ##40132 LSU marked instruction finish #47,u,g,n,n,m,y,PM_MRK_INST_TIMEO,Marked instruction finish timeout (instruction was lost) ##40134 Marked instruction finish timeout (instruction was lost) #48,u,g,n,n,m,y,PM_MRK_STORE_DATA_CYC,Cycles in which the marked instruction was waiting for data. Divide by PM_MRK_STORE_DATA to obtain the average Store data latency. ##40136 Cycles in which the marked instruction was waiting for data. Divide by PM_MRK_STORE_DATA to obtain the average Store data latency. #49,u,g,n,n,n,y,PM_DISP_STALL_HELD_SYNC_CYC,Cycles in which the next-to-complete (NTC) instruction is held at dispatch because of a synchronizing instruction that requires the ICT to be empty before dispatch ##4003C Cycles in which the next-to-complete (NTC) instruction is held at dispatch because of a synchronizing instruction that requires the ICT to be empty before dispatch #50,u,g,n,n,n,n,PM_LD_CMPL,Load instruction completed ##4003E Load instruction completed #51,u,g,n,n,n,y,PM_L2_PWC_HIT,A translation reload hits in the L2 page walk cache ##44040 A translation reload hits in the L2 page walk cache #52,u,g,n,n,n,y,PM_L3_PWC_HIT,A translation reload hits in the L3 page walk cache ##44042 A translation reload hits in the L3 page walk cache #53,u,g,n,n,m,n,PM_MRK_STCX_CORE_CYC,Cycles spent in the core portion of a marked STCX instruction. It starts counting when the instruction is decoded and stops counting when it drains into the L2 ##44146 Cycles spent in the core portion of a marked STCX instruction. It starts counting when the instruction is decoded and stops counting when it drains into the L2 #54,u,g,n,n,n,y,PM_DATA_RADIX_L2_PTE_FROM_DISTANT,A data Page Table Entry was reloaded to a level 2 page walk cache from distant memory. If MMCR1[16] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. ##4404A A data Page Table Entry was reloaded to a level 2 page walk cache from distant memory. If MMCR1[16] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. #55,u,g,n,n,n,y,PM_DATA_RADIX_L2_PDE_FROM_DISTANT,A data Page Directory Entry was reloaded to a level 2 page walk cache from distant memory. If MMCR1[16] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. ##4404C A data Page Directory Entry was reloaded to a level 2 page walk cache from distant memory. If MMCR1[16] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. #56,u,g,n,n,n,y,PM_DATA_RADIX_L3_PTE_FROM_DISTANT,A data Page Table Entry was reloaded to a level 3 page walk cache from distant memory. If MMCR1[16] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. ##4404E A data Page Table Entry was reloaded to a level 3 page walk cache from distant memory. If MMCR1[16] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. #57,u,g,n,n,n,y,PM_DATA_RADIX_L3_PDE_FROM_DISTANT,A data Page Directory Entry was reloaded to a level 3 page walk cache from distant memory. If MMCR1[16] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. ##45040 A data Page Directory Entry was reloaded to a level 3 page walk cache from distant memory. If MMCR1[16] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. #58,u,g,n,n,n,y,PM_DATA_RADIX_L4_PTE_FROM_DISTANT,A data Page Table Entry was reloaded to a level 4 page walk cache from distant memory. If MMCR1[16] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. ##45042 A data Page Table Entry was reloaded to a level 4 page walk cache from distant memory. If MMCR1[16] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. #59,u,g,n,n,n,y,PM_INST_RADIX_L2_PTE_FROM_DISTANT,An instruction Page Table Entry was reloaded to a level 2 page walk cache from distant memory. If MMCR1[17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[17] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. ##45046 An instruction Page Table Entry was reloaded to a level 2 page walk cache from distant memory. If MMCR1[17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[17] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. #60,u,g,n,n,n,y,PM_INST_RADIX_L3_PTE_FROM_DISTANT,An instruction Page Table Entry was reloaded to a level 3 page walk cache from distant memory. If MMCR1[17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[17] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. ##4504A An instruction Page Table Entry was reloaded to a level 3 page walk cache from distant memory. If MMCR1[17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[17] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. #61,u,g,n,n,n,y,PM_INST_RADIX_L3_PDE_FROM_DISTANT,An instruction Page Directory Entry was reloaded to a level 3 page walk cache from distant memory. If MMCR1[17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[17] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. ##4504C An instruction Page Directory Entry was reloaded to a level 3 page walk cache from distant memory. If MMCR1[17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[17] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. #62,u,g,n,n,n,y,PM_INST_RADIX_L4_PTE_FROM_DISTANT,An instruction Page Table Entry was reloaded to a level 4 page walk cache from distant memory. If MMCR1[17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[17] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. ##4504E An instruction Page Table Entry was reloaded to a level 4 page walk cache from distant memory. If MMCR1[17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[17] is 1, this count includes both demand miss and prefetch reloads. Further, if MMCR1[18] is 0 (default), only partition scoped accesses are included. If MMCR1[18] is 1, only process scoped accesses are included in this count. #63,u,g,n,n,n,y,PM_XFER_FROM_SRC_PMC4,The processor's L1 data cache was reloaded from the source specified in MMCR3[45:57]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads. ##4C040 The processor's L1 data cache was reloaded from the source specified in MMCR3[45:57]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads. #64,u,g,n,n,m,y,PM_MRK_XFER_FROM_SRC_PMC4,For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[45:57]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads. ##4C142 For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[45:57]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads. #65,u,g,n,n,m,y,PM_MRK_XFER_FROM_SRC_CYC_PMC4,Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[45:57]. ##4C144 Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[45:57]. #66,u,g,n,n,m,y,PM_MRK_DATA_FLUSHED_FROM_SRC_PMC4,Marked demand loads that attempted a reload, but were flushed ##4C146 Marked demand loads that attempted a reload, but were flushed #67,u,g,n,n,m,y,PM_MRK_DATA_FLUSHED_FROM_SRC_CYC_PMC4,Cycles spent attempting to reload a line from any source for a marked demand miss that was later flushed ##4C148 Cycles spent attempting to reload a line from any source for a marked demand miss that was later flushed #68,u,g,n,n,n,y,PM_PMC2_HELD_CYC,Cycles when the speculative counter for PMC2 is frozen. ##4C04A Cycles when the speculative counter for PMC2 is frozen. #69,u,g,n,n,n,y,PM_VECTOR_FSQRT_FDIV_ISSUE,Vector versions of fdiv or fsqrt: fdiv, fdivs, fsqrt, fsqrts (or a record variant of any one). ##4D04E Vector versions of fdiv or fsqrt: fdiv, fdivs, fsqrt, fsqrts (or a record variant of any one). #70,u,g,n,n,n,n,PM_SP_MMA_CMPL,Single precision MMA instruction completed ##4E040 Single precision MMA instruction completed #71,u,g,n,n,n,n,PM_DP_MMA_CMPL,Double precision MMA instruction completed ##4E042 Double precision MMA instruction completed #72,u,g,n,n,n,n,PM_HP_MMA_CMPL,FP16 half precision MMA instruction completed ##4E044 FP16 half precision MMA instruction completed #73,u,g,n,n,n,n,PM_4INT_MMA_CMPL,Int4 mixed precision MMA instructionscompleted ##4E046 Int4 mixed precision MMA instructionscompleted #74,u,g,n,n,n,n,PM_8INT_MMA_CMPL,Int8 mixed precision MMA instruction completed ##4E048 Int8 mixed precision MMA instruction completed #75,u,g,n,n,n,n,PM_16INT_MMA_CMPL,Int16 mixed precision MMA instruction completed ##4E04A Int16 mixed precision MMA instruction completed #76,u,g,n,n,n,n,PM_BF16_MMA_CMPL,Bfloat16 half precision MMA instruction completed ##4E04C Bfloat16 half precision MMA instruction completed #77,u,g,n,n,n,n,PM_MOVE_TO_MMA_CMPL,VSR to Accumulator move MMA instruction completed (xxmtacc and xxsetaccz). These implies priming instructions. ##4E04E VSR to Accumulator move MMA instruction completed (xxmtacc and xxsetaccz). These implies priming instructions. #78,u,g,n,n,n,n,PM_MOVE_FROM_MMA_CMPL,Accumulator to VSR move MMA instruction completed (xxmfacc). These implies de-priming instructions. ##4F040 Accumulator to VSR move MMA instruction completed (xxmfacc). These implies de-priming instructions. #79,u,g,n,n,n,n,PM_MUL_MMA_CMPL,All multiply-only MMA instruction completed. These might imply priming instructions. ##4F042 All multiply-only MMA instruction completed. These might imply priming instructions. #80,u,g,n,n,n,y,PM_SYS_PUMP_MPRED_RTY,Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group). Includes instruction and data lines ##40050 Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group). Includes instruction and data lines #81,u,g,n,n,m,u,PM_MRK_PUMP_MPRED,Pump misprediction. Counts across all types of pumps with a marked instruction for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) ##40152 Pump misprediction. Counts across all types of pumps with a marked instruction for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) #82,u,g,n,n,m,y,PM_MRK_FAB_RSP_BKILL,Marked store had to do a bkill ##40154 Marked store had to do a bkill #83,u,g,n,n,m,y,PM_MRK_GRP_PUMP_MPRED_RTY,Final Pump Scope (group) ended up larger than Initial Pump Scope (chip) for a marked instruction. Includes instruction and data lines ##40156 Final Pump Scope (group) ended up larger than Initial Pump Scope (chip) for a marked instruction. Includes instruction and data lines #84,u,g,n,n,m,y,PM_MRK_FAB_RSP_RD_RTY,Sampled L2 reads retry count ##4015E Sampled L2 reads retry count #85,u,g,n,n,n,y,PM_INST_SYS_PUMP_MPRED_RTY,Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for an instruction fetch ##44050 Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for an instruction fetch #86,u,g,n,n,n,n,PM_VECTOR_LD_CMPL,Vector load instruction completed ##44054 Vector load instruction completed #87,u,g,n,n,n,n,PM_VECTOR_ST_CMPL,Vector store instruction completed ##44056 Vector store instruction completed #88,u,g,n,n,n,n,PM_LWSYNC_CMPL,A lightweight synchronizing or barrier instruction (LWSYNC) completed. ##44058 A lightweight synchronizing or barrier instruction (LWSYNC) completed. #89,u,g,n,n,n,n,PM_HWSYNC_CMPL,A heavyweight synchronizing or barrier instruction (HWSYNC) completed. ##4405A A heavyweight synchronizing or barrier instruction (HWSYNC) completed. #90,u,g,n,n,n,n,PM_ANY_FLOP_CMPL,Duplicate of PM_FLOP_CMPL. A floating point (FLOP) instruction of any type completed. It counts once for each 1, 2, 4 or 8 FLOP instruction. Use PM_1|2|4|8_FLOP_CMPL events to count FLOPs. ##4405E Duplicate of PM_FLOP_CMPL. A floating point (FLOP) instruction of any type completed. It counts once for each 1, 2, 4 or 8 FLOP instruction. Use PM_1|2|4|8_FLOP_CMPL events to count FLOPs. #91,u,g,n,n,n,n,PM_1FLOP_CMPL,One floating point instruction completed (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) ##45050 One floating point instruction completed (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) #92,u,g,n,n,n,n,PM_4FLOP_CMPL,Four floating point instruction completed (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) ##45052 Four floating point instruction completed (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) #93,u,g,n,n,n,n,PM_FMA_CMPL,Two floating point instruction completed (FMA class of instructions: fmadd, fnmadd, fmsub, fnmsub). Scalar instructions only.  ##45054 Two floating point instruction completed (FMA class of instructions: fmadd, fnmadd, fmsub, fnmsub). Scalar instructions only.  #94,u,g,n,n,n,n,PM_SCALAR_FLOP_CMPL,Scalar floating point instruction completed. ##45056 Scalar floating point instruction completed. #95,u,g,n,n,n,n,PM_IC_MISS_CMPL,Non-speculative instruction cache miss, counted at completion ##45058 Non-speculative instruction cache miss, counted at completion #96,u,g,n,n,n,n,PM_SP_FLOP_CMPL,Single Precision floating point instruction completed. ##4505A Single Precision floating point instruction completed. #97,u,g,n,n,n,n,PM_MATH_FLOP_CMPL,Math floating point instruction completed ##4505C Math floating point instruction completed #98,u,g,n,n,n,y,PM_DATA_SYS_PUMP_MPRED_RTY,Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for a demand load ##4C050 Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for a demand load #99,u,g,n,n,n,y,PM_DERAT_MISS_16G,Data ERAT Miss (Data TLB Access) page size 16G. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches ##4C054 Data ERAT Miss (Data TLB Access) page size 16G. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches #100,u,g,n,n,n,y,PM_DTLB_MISS_16M,Data TLB reload (after a miss) page size 16M. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches ##4C056 Data TLB reload (after a miss) page size 16M. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches #101,u,g,n,n,n,y,PM_DTLB_MISS_1G,Data TLB reload (after a miss) page size 1G. Implies radix translation was used. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches ##4C05A Data TLB reload (after a miss) page size 1G. Implies radix translation was used. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches #102,u,g,n,n,m,y,PM_MRK_DERAT_MISS_1G,Data ERAT Miss (Data TLB Access) page size 1G for a marked instruction. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches ##4C15C Data ERAT Miss (Data TLB Access) page size 1G for a marked instruction. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches #103,u,g,n,n,m,y,PM_MRK_DTLB_MISS_64K,Marked Data TLB reload (after a miss) page size 64K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches ##4C15E Marked Data TLB reload (after a miss) page size 64K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches #104,u,g,n,n,n,n,PM_VSU_NON_FLOP_CMPL,Non-floating point VSU instruction completed ##4D050 Non-floating point VSU instruction completed #105,u,g,n,n,n,n,PM_2FLOP_CMPL,Double Precision vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg completed. ##4D052 Double Precision vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg completed. #106,u,g,n,n,n,n,PM_8FLOP_CMPL,Four Double Precision vector instruction completed. ##4D054 Four Double Precision vector instruction completed. #107,u,g,n,n,n,n,PM_NON_FMA_FLOP_CMPL,Non FMA instruction completed ##4D056 Non FMA instruction completed #108,u,g,n,n,n,n,PM_VECTOR_FLOP_CMPL,Vector floating point instruction completed ##4D058 Vector floating point instruction completed #109,u,g,n,n,n,n,PM_NON_MATH_FLOP_CMPL,Non Math instruction completed ##4D05A Non Math instruction completed #110,u,g,n,n,n,n,PM_DPP_FLOP_CMPL,Double-Precision or Quad-Precision instruction completed ##4D05C Double-Precision or Quad-Precision instruction completed #111,u,g,n,n,n,n,PM_BR_CMPL,A branch completed. All branches are included. ##4D05E A branch completed. All branches are included. #112,u,g,n,n,n,y,PM_STCX_PASS_FIN,Conditional store instruction (STCX) passed. LARX and STCX are instructions used to acquire a lock  ##4E050 Conditional store instruction (STCX) passed. LARX and STCX are instructions used to acquire a lock  #113,u,g,n,n,n,y,PM_DTLB_HIT_16M,Data TLB hit (DERAT reload) page size 16M. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches ##4E052 Data TLB hit (DERAT reload) page size 16M. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches #114,u,g,n,n,n,y,PM_DTLB_HIT_1G,Data TLB hit (DERAT reload) page size 1G. Implies radix translation. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches ##4E054 Data TLB hit (DERAT reload) page size 1G. Implies radix translation. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches #115,u,g,n,n,n,n,PM_BR_COND_CMPL,A conditional branch completed. ##4E058 A conditional branch completed. #116,u,g,n,n,n,n,PM_PREFIXED_CMPL,Prefixed instruction completed ##4E05A Prefixed instruction completed #117,u,g,n,n,m,y,PM_MRK_INST_FLUSHED,The marked instruction was flushed ##4E15E The marked instruction was flushed #118,u,g,n,n,m,n,PM_MRK_FAB_RSP_RWITM_CYC,Cycles L2 RC took for a rwitm ##4F150 Cycles L2 RC took for a rwitm #119,u,g,n,n,n,y,PM_DISP_SS1_8_INSTR_CYC,Cycles in which Superslice 0 dispatches either 5, 6, 7 or 8 instructions ##4F056 Cycles in which Superslice 0 dispatches either 5, 6, 7 or 8 instructions #120,u,g,n,n,n,y,PM_DISP_HELD_SCOREBOARD_CYC,Cycles dispatch is held while waiting on the Scoreboard. This event combines VSCR and FPSCR together ##40060 Cycles dispatch is held while waiting on the Scoreboard. This event combines VSCR and FPSCR together #121,u,g,n,n,n,y,PM_DISP_HELD_RENAME_CYC,Cycles dispatch is held because the mapper/SRB was full. Includes GPR (count, link, tar), VSR, VMR, FPR and XVFC ##40062 Cycles dispatch is held because the mapper/SRB was full. Includes GPR (count, link, tar), VSR, VMR, FPR and XVFC #122,u,g,n,n,m,y,PM_MRK_DERAT_MISS_2M,Data ERAT Miss (Data TLB Access) page size 2M for a marked instruction. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches ##40164 Data ERAT Miss (Data TLB Access) page size 2M for a marked instruction. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches #123,u,g,n,n,n,y,PM_ITLB_HIT_4K,Instruction TLB hit (IERAT reload) page size 4K. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches. ##40066 Instruction TLB hit (IERAT reload) page size 4K. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches. #124,u,g,n,n,n,y,PM_ITLB_MISS_4K,Instruction TLB reload (after a miss) page size 4K. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches. ##4006C Instruction TLB reload (after a miss) page size 4K. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches. #125,u,g,t,n,m,y,PM_THRESH_NOT_MET,Threshold counter did not meet threshold ##4016E Threshold counter did not meet threshold #126,u,g,n,n,m,n,PM_MRK_INST_CMPL,Marked instruction completed ##401E0 Marked instruction completed #127,u,g,n,n,m,y,PM_MRK_DTLB_MISS,The DPTEG required for the marked load/store instruction in execution was missing from the TLB. It includes pages of all sizes for demand and prefetch activity ##401E4 The DPTEG required for the marked load/store instruction in execution was missing from the TLB. It includes pages of all sizes for demand and prefetch activity #128,u,g,n,n,m,u,PM_MRK_INST_FROM_L3MISS,The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction. ##401E6 The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction. #129,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2MISS,The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction. ##401E8 The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction. #130,u,g,t,n,m,y,PM_THRESH_EXC_128,Threshold counter exceeded a value of 128 ##401EA Threshold counter exceeded a value of 128 #131,u,g,t,n,m,y,PM_THRESH_EXC_2048,Threshold counter exceeded a value of 2048 ##401EC Threshold counter exceeded a value of 2048 #132,u,g,n,n,n,y,PM_LD_DEMAND_MISS_L1_FIN,Load missed L1, counted at finish time ##400F0 Load missed L1, counted at finish time #133,u,g,n,n,n,y,PM_1PLUS_PPC_DISP,Cycles at least one Instr Dispatched ##400F2 Cycles at least one Instr Dispatched #134,u,g,n,n,n,n,PM_RUN_PURR,PURR bit 59 toggled ##400F4 PURR bit 59 toggled #135,u,g,n,n,n,n,PM_BR_MPRED_CMPL,A mispredicted branch completed. Includes direction and target. ##400F6 A mispredicted branch completed. Includes direction and target. #136,u,g,n,n,n,y,PM_FLUSH,Flush (any type) ##400F8 Flush (any type) #137,u,g,n,n,n,n,PM_RUN_INST_CMPL,PowerPC instruction completed while the run latch is set ##400FA PowerPC instruction completed while the run latch is set #138,u,g,n,n,n,y,PM_ITLB_MISS,Instruction TLB reload (after a miss), all page sizes. Includes only demand misses. ##400FC Instruction TLB reload (after a miss), all page sizes. Includes only demand misses. #139,u,g,n,n,n,n,PM_DATA_FROM_MEMORY,The processor's data cache was reloaded from local, remote, or distant memory due to a demand miss ##400FE The processor's data cache was reloaded from local, remote, or distant memory due to a demand miss #140,u,g,n,n,n,u,PM_EE_OFF_EXT_INT_CYC,Cycles in which MSR[EE] is off and external interrupts are active ##0000002080 Cycles in which MSR[EE] is off and external interrupts are active #141,u,g,n,n,n,u,PM_ISU_FLUSH,All flushes initiated by the Instruction Sequencing Unit (ISU). Excludes LSU NTC+1 flushes ##0000002880 All flushes initiated by the Instruction Sequencing Unit (ISU). Excludes LSU NTC+1 flushes #142,u,g,n,n,n,u,PM_ISU_FLUSH_DISP,Dispatch flushes occur when one thread is causing other threads to stall ##0000002084 Dispatch flushes occur when one thread is causing other threads to stall #143,u,g,n,n,n,u,PM_ISU_FLUSH_BALANCE,A balance flush occurred. Balance flushes are triggered when excessive L3 or TLB misses occur ##0000002884 A balance flush occurred. Balance flushes are triggered when excessive L3 or TLB misses occur #144,u,g,n,n,n,u,PM_ISU_FLUSH_PARTIAL,A flush occurred only to the odd ITAG of a pair. This type of flush requires an additional 10 cycles to process. More pairs of instructions can be included in this count. ##0000002088 A flush occurred only to the odd ITAG of a pair. This type of flush requires an additional 10 cycles to process. More pairs of instructions can be included in this count. #145,u,g,n,n,n,u,PM_ISU_FLUSH_DISP_SRQ_EMPTY,Dispatch flush while waiting for the SRQ to become empty: TLBIE, SLBIEG, SLBIET, EIEIO, TLBSYNC. ##0000002888 Dispatch flush while waiting for the SRQ to become empty: TLBIE, SLBIEG, SLBIET, EIEIO, TLBSYNC. #146,u,g,n,n,n,u,PM_ISU_FLUSH_LD_ECC_ERROR,A load instruction that accessed early data from memory and finished speculatively before the ECC was returned, gets flushed because of a later ECC error ##000000208C A load instruction that accessed early data from memory and finished speculatively before the ECC was returned, gets flushed because of a later ECC error #147,u,g,n,n,n,u,PM_ISU_FLUSH_LWSYNC,A flush to a lightweight synchronizing or barrier instruction (LWSYNC) instruction that had trouble. This event includes NTC flushes and NTC+1 flushes. ##000000288C A flush to a lightweight synchronizing or barrier instruction (LWSYNC) instruction that had trouble. This event includes NTC flushes and NTC+1 flushes. #148,u,g,n,n,n,u,PM_ISU_FLUSH_ISYNC,A flush to an isync instruction that had trouble. This event includes NTC flushes and NTC+1 flushes. ##0000002090 A flush to an isync instruction that had trouble. This event includes NTC flushes and NTC+1 flushes. #149,u,g,n,n,n,u,PM_ISU_FLUSH_HWSYNC,A flush to a heavyweight synchronizing or barrier instruction (HWSYNC) instruction that had trouble. This event includes NTC flushes and NTC+1 flushes. ##0000002094 A flush to a heavyweight synchronizing or barrier instruction (HWSYNC) instruction that had trouble. This event includes NTC flushes and NTC+1 flushes. #150,u,g,n,n,n,u,PM_ISU_FLUSH_MMA_OFF_CYC,If the MMA engine is off when an MMA instruction is issued, the instruction will issue and finish as a nop. It will then get flushed when it becomes NTC and it will not be refetched until the MMA engine is on. This event counts the number of cycles between the flush and the MMA engine turning on. ##0000002894 If the MMA engine is off when an MMA instruction is issued, the instruction will issue and finish as a nop. It will then get flushed when it becomes NTC and it will not be refetched until the MMA engine is on. This event counts the number of cycles between the flush and the MMA engine turning on. #151,u,g,n,n,n,u,PM_ISU_FLUSH_DISP_STF_REBAL,The Sliced Target File (STF) is the register file for GPRs, VSRs, LR, CTR, and TAR. This event indicates that an execution unit attempted to write to a slice that was full. In this case, the instruction gets flushed and the slices get rebalanced. ##00000028AC The Sliced Target File (STF) is the register file for GPRs, VSRs, LR, CTR, and TAR. This event indicates that an execution unit attempted to write to a slice that was full. In this case, the instruction gets flushed and the slices get rebalanced. #152,u,g,n,n,n,u,PM_START_PROBE_NOP_DISP,A start probe nop was dispatched. Instruction AND 0,0,0 ##00000020B0 A start probe nop was dispatched. Instruction AND 0,0,0 #153,u,g,n,n,n,u,PM_STOP_PROBE_NOP_DISP,A stop probe nop was dispatched. Instruction AND 1,1,1 ##00000028B0 A stop probe nop was dispatched. Instruction AND 1,1,1 #154,u,g,n,n,m,u,PM_MRK_STOP_PROBE_NOP_DISP,A stop probe nop was marked at dispatch. Instruction AND 1,1,1 ##00000021B4 A stop probe nop was marked at dispatch. Instruction AND 1,1,1 #155,u,g,n,n,n,u,PM_FUNCTION_CALL_DISP,bl instruction dispatched. Only one reported per cycle. It is possible to dispatch 8 instructions per cycle in single thread mode. ##00000020B8 bl instruction dispatched. Only one reported per cycle. It is possible to dispatch 8 instructions per cycle in single thread mode. #156,u,g,n,n,n,u,PM_FUNCTION_RETURN_DISP,blr instruction dispatched. Only one reported per cycle. It is possible to dispatch 8 instructions per cycle in single thread mode. ##00000028B8 blr instruction dispatched. Only one reported per cycle. It is possible to dispatch 8 instructions per cycle in single thread mode. #157,u,g,n,n,n,u,PM_0CYC_CONST_DISP,Xxor instruction dispatched. ##00000020BC Xxor instruction dispatched. #158,u,g,n,n,n,u,PM_ISSUE_HOLD_STAGS_CYC,Cycles in which one or more instructions are being held at issue while waiting for Store Tags to become available. These instructions could also be held simultaneously for other conditions. Other non-store instructions are allowed to issue while the store is being held. ##0000003080 Cycles in which one or more instructions are being held at issue while waiting for Store Tags to become available. These instructions could also be held simultaneously for other conditions. Other non-store instructions are allowed to issue while the store is being held. #159,u,g,n,n,n,u,PM_ISSUE_HOLD_LTAGS_CYC,Cycles in which one or more instructions are being held at issue while waiting for Load Tags to become available. These instructions could also be held simultaneously for other conditions. Other non-load instructions are allowed to issue while the load is being held. ##0000003880 Cycles in which one or more instructions are being held at issue while waiting for Load Tags to become available. These instructions could also be held simultaneously for other conditions. Other non-load instructions are allowed to issue while the load is being held. #160,u,g,n,n,n,u,PM_ISSUE_KILL_DL_MISS,An instruction was primed to issue but was killed before being written because one of the sources takes a data load miss. I.e. dependent data from a load does not get valid data ##0000003084 An instruction was primed to issue but was killed before being written because one of the sources takes a data load miss. I.e. dependent data from a load does not get valid data #161,u,g,n,n,n,u,PM_ISSUE_KILL_RESOURCE,An instruction was primed to issue but was killed before being written because a resource is unavailable. Includes BFU, FX-DIV, DFU, BRU and SFX instructions that would collide at finish with a store AGEN. ##0000003884 An instruction was primed to issue but was killed before being written because a resource is unavailable. Includes BFU, FX-DIV, DFU, BRU and SFX instructions that would collide at finish with a store AGEN. #162,u,g,n,n,n,u,PM_ISSUE_KILL_THROTTLE,An instruction was primed to issue but was killed before being written because power throttling was enabled ##0000003088 An instruction was primed to issue but was killed before being written because power throttling was enabled #163,u,g,n,n,n,u,PM_SHL_HIT,A dependency was created when a dispatched store matched the address for a load in the Store-Hit-Load Table. ##000000388C A dependency was created when a dispatched store matched the address for a load in the Store-Hit-Load Table. #164,u,g,n,n,n,u,PM_LHS_HIT,A dependency was created when a dispatched load matched the address for a store instruction in the Load-Hit-Store table. ##0000003890 A dependency was created when a dispatched load matched the address for a store instruction in the Load-Hit-Store table. #165,u,g,n,n,n,u,PM_LHS_CREATED,New entry added to the Load-Hit-Store table. ##0000003094 New entry added to the Load-Hit-Store table. #166,u,g,n,n,n,u,PM_LARX_HIT_LARX_HIT,A dependency was created for a LARX instruction that was dispatched and matched an older LARX in the Larx-hit-larx table. ##0000003894 A dependency was created for a LARX instruction that was dispatched and matched an older LARX in the Larx-hit-larx table. #167,u,g,n,n,n,u,PM_LARX_HIT_LARX_CREATED,New entry added to the Larx-hit-larx table. LARX and STCX are instructions used to acquire a lock.  ##0000003098 New entry added to the Larx-hit-larx table. LARX and STCX are instructions used to acquire a lock.  #168,u,g,n,n,n,u,PM_MMA_VSR_CONFLICT_FLUSH,A VSR operation references an ACC that has been primed. This is indicative of a context switch ##0000003898 A VSR operation references an ACC that has been primed. This is indicative of a context switch #169,u,g,n,n,n,u,PM_MMA_ACC_CONFLICT_FLUSH,An MMA instruction references an ACC that has not been primed. This is indicative of faulty software ##000000309C An MMA instruction references an ACC that has not been primed. This is indicative of faulty software #170,u,g,n,n,m,u,PM_MRK_MMA_ACC_VSR_CONFLICT,Either a marked MMA instruction references an ACC that has not been primed or a marked VSR operation references an ACC that has been primed ##000000399C Either a marked MMA instruction references an ACC that has not been primed or a marked VSR operation references an ACC that has been primed #171,u,g,n,n,n,u,PM_MMA_IN_USE_CYC,Cycles in which the MMA engine is actively being used by this thread. This is measured by counting the cycles in which at least one ACC register is primed for MMA use. ##00000030A0 Cycles in which the MMA engine is actively being used by this thread. This is measured by counting the cycles in which at least one ACC register is primed for MMA use. #172,u,g,n,n,n,u,PM_MMA_ON_CYC,Cycles in which this core's MMA engine is enabled. ##00000038A0 Cycles in which this core's MMA engine is enabled. #173,u,g,n,n,n,u,PM_DISP_HELD_OUT_OF_LTAGS_CYC,Cycles in which dispatch is held because the LRQ is full. No LTAGS are available. There are twice as many LTAGS as there are LRQ entries. The signal should be on if less than 8 tags, and should be off if greater than 24 tags, and could be on if in-between. In ST/SMT2, if less than 24 tags, signal can come on, and if less than 8 it will be on. In SMT4, if less than 12 tags, it can come on, if less than 4 tags it will be on. ##00000030B4 Cycles in which dispatch is held because the LRQ is full. No LTAGS are available. There are twice as many LTAGS as there are LRQ entries. The signal should be on if less than 8 tags, and should be off if greater than 24 tags, and could be on if in-between. In ST/SMT2, if less than 24 tags, signal can come on, and if less than 8 it will be on. In SMT4, if less than 12 tags, it can come on, if less than 4 tags it will be on. #174,u,g,n,n,n,u,PM_DISP_HELD_OUT_OF_STAGS_CYC,Cycles in which dispatch is held because the SRQ is full. No STAGS are available. There are twice as many STAGS as there are SRQ entries. The signal should be on if less than 8 tags, should be off is greater than 24 tags, and could be on if in-between. In ST/SMT2, if less than 24 tags, signal can come on, if less than 8 tags it will be on. In SMT4, if less than 12 tags, it can come on, if less than 4 tags it will be on. ##00000038B4 Cycles in which dispatch is held because the SRQ is full. No STAGS are available. There are twice as many STAGS as there are SRQ entries. The signal should be on if less than 8 tags, should be off is greater than 24 tags, and could be on if in-between. In ST/SMT2, if less than 24 tags, signal can come on, if less than 8 tags it will be on. In SMT4, if less than 12 tags, it can come on, if less than 4 tags it will be on. #175,u,g,n,n,n,u,PM_DISP_CLB_HELD_BALANCE_CYC,Dispatch/CLB Hold as cause of Balance Flush. ##00000030B8 Dispatch/CLB Hold as cause of Balance Flush. #176,u,g,n,n,n,u,PM_DISP_CLB_HELD_SRQ_EMPTY_CYC,Dispatch Hold: waiting for the SRQ to become empty: TLBIE, SLBIEG, SLBIET, EIEIO, TLBSYNC. This should exclude cycles when it is only waiting for the ICT to become empty. ##00000038B8 Dispatch Hold: waiting for the SRQ to become empty: TLBIE, SLBIEG, SLBIET, EIEIO, TLBSYNC. This should exclude cycles when it is only waiting for the ICT to become empty. #177,u,g,n,n,n,u,PM_DISP_PARTIAL,Dispatches in which the Instruction Sequencing Unit (ISU) dispatches instructions at either half rate or quarter rate. This can happen when some of the queues (or mapper subblocks) are either full, or close to full. ##00000030BC Dispatches in which the Instruction Sequencing Unit (ISU) dispatches instructions at either half rate or quarter rate. This can happen when some of the queues (or mapper subblocks) are either full, or close to full. #178,u,g,n,n,n,u,PM_ISYNC_CMPL,Isync completion count per thread ##00000038BC Isync completion count per thread #179,u,g,n,n,n,u,PM_LD0_8B_FIN,64-bit or smaller load finished in the LD0 load execution unit. ##000000C080 64-bit or smaller load finished in the LD0 load execution unit. #180,u,g,n,n,n,u,PM_LD1_8B_FIN,64-bit or smaller load finished in the LD1 load execution unit. ##000000C880 64-bit or smaller load finished in the LD1 load execution unit. #181,u,g,n,n,n,u,PM_LD0_16B_FIN,128-bit load finished in the LD0 load execution unit. ##000000C084 128-bit load finished in the LD0 load execution unit. #182,u,g,n,n,n,u,PM_LD1_16B_FIN,128-bit load finished in the LD1 load execution unit. ##000000C884 128-bit load finished in the LD1 load execution unit. #183,u,g,n,n,n,u,PM_LD0_32B_FIN,256-bit load finished in the LD0 load execution unit. ##000000C088 256-bit load finished in the LD0 load execution unit. #184,u,g,n,n,n,u,PM_LD1_32B_FIN,256-bit load finished in the LD1 load execution unit. ##000000C888 256-bit load finished in the LD1 load execution unit. #185,u,g,n,n,n,u,PM_LD0_VECTOR_FIN,Any vector load operation finished in the LD0 execution unit. Excludes load quad, larx quad, fused load double, load float double-pair. ##000000C08C Any vector load operation finished in the LD0 execution unit. Excludes load quad, larx quad, fused load double, load float double-pair. #186,u,g,n,n,n,u,PM_LD1_VECTOR_FIN,Any vector load operation finished in the LD1 execution unit. Excludes load quad, larx quad, fused load double, load float double-pair. ##000000C88C Any vector load operation finished in the LD1 execution unit. Excludes load quad, larx quad, fused load double, load float double-pair. #187,u,g,n,n,n,u,PM_LD0_UNALIGNED_FIN,Load instructions in LD0 port that are either unaligned, or treated as unaligned and require an additional recycle through the pipeline using the load gather buffer. This typically adds about 10 cycles to the latency of the instruction. This includes loads that cross the 128 byte boundary, octword loads that are not aligned, and a special forward progress case of a load that does not hit in the L1 and crosses the 32 byte boundary and is launched NTC. Counted at finish time. ##000000C090 Load instructions in LD0 port that are either unaligned, or treated as unaligned and require an additional recycle through the pipeline using the load gather buffer. This typically adds about 10 cycles to the latency of the instruction. This includes loads that cross the 128 byte boundary, octword loads that are not aligned, and a special forward progress case of a load that does not hit in the L1 and crosses the 32 byte boundary and is launched NTC. Counted at finish time. #188,u,g,n,n,n,u,PM_LD1_UNALIGNED_FIN,Load instructions in LD1 port that are either unaligned, or treated as unaligned and require an additional recycle through the pipeline using the load gather buffer. This typically adds about 10 cycles to the latency of the instruction. This includes loads that cross the 128 byte boundary, octword loads that are not aligned, and a special forward progress case of a load that does not hit in the L1 and crosses the 32 byte boundary and is launched NTC. Counted at finish time. ##000000C890 Load instructions in LD1 port that are either unaligned, or treated as unaligned and require an additional recycle through the pipeline using the load gather buffer. This typically adds about 10 cycles to the latency of the instruction. This includes loads that cross the 128 byte boundary, octword loads that are not aligned, and a special forward progress case of a load that does not hit in the L1 and crosses the 32 byte boundary and is launched NTC. Counted at finish time. #189,u,g,n,n,n,u,PM_ST0_8B_FIN,8-byte or smaller store finished in the ST0 store execution unit. ##000000C094 8-byte or smaller store finished in the ST0 store execution unit. #190,u,g,n,n,n,u,PM_ST1_8B_FIN,8-byte or smaller store finished in the ST1 store execution unit. ##000000C894 8-byte or smaller store finished in the ST1 store execution unit. #191,u,g,n,n,n,u,PM_ST0_16B_FIN,16-byte store finished in the ST0 store execution unit. ##000000C098 16-byte store finished in the ST0 store execution unit. #192,u,g,n,n,n,u,PM_ST1_16B_FIN,16-byte store finished in the ST1 store execution unit. ##000000C898 16-byte store finished in the ST1 store execution unit. #193,u,g,n,n,n,u,PM_ST0_32B_FIN,32-byte store finished in the ST0 store execution unit. ##000000C09C 32-byte store finished in the ST0 store execution unit. #194,u,g,n,n,n,u,PM_ST1_32B_FIN,32-byte store finished in the ST1 store execution unit. ##000000C89C 32-byte store finished in the ST1 store execution unit. #195,u,g,n,n,n,u,PM_ST0_VECTOR_FIN,Any vector store operation finished in the ST0 store execution unit. Excludes store quad, stcx quad, store float double-pair, fused store double. ##000000C0A0 Any vector store operation finished in the ST0 store execution unit. Excludes store quad, stcx quad, store float double-pair, fused store double. #196,u,g,n,n,n,u,PM_ST1_VECTOR_FIN,Any vector store operation finished in the ST1 store execution unit. Excludes store quad, stcx quad, store float double-pair, fused store double. ##000000C8A0 Any vector store operation finished in the ST1 store execution unit. Excludes store quad, stcx quad, store float double-pair, fused store double. #197,u,g,n,n,n,u,PM_ST0_UNALIGNED_FIN,Store instructions in ST0 port that are either unaligned, or treated as unaligned and require an additional recycle through the pipeline. This typically adds about 10 cycles to the latency of the instruction. This only includes stores that cross the 128 byte boundary. Counted at finish time. ##000000C0A4 Store instructions in ST0 port that are either unaligned, or treated as unaligned and require an additional recycle through the pipeline. This typically adds about 10 cycles to the latency of the instruction. This only includes stores that cross the 128 byte boundary. Counted at finish time. #198,u,g,n,n,n,u,PM_ST1_UNALIGNED_FIN,Store instructions in ST1 port that are either unaligned, or treated as unaligned and require an additional recycle through the pipeline. This typically adds about 10 cycles to the latency of the instruction. This only includes stores that cross the 128 byte boundary. Counted at finish time. ##000000C8A4 Store instructions in ST1 port that are either unaligned, or treated as unaligned and require an additional recycle through the pipeline. This typically adds about 10 cycles to the latency of the instruction. This only includes stores that cross the 128 byte boundary. Counted at finish time. #199,u,g,n,n,n,u,PM_FALSE_LHS,False Load-Hit-Store (LHS) match detected. Load and store have a partial Effective Address (EA) match but they are actually independent of each other. The other cases of false LHS cause flushes and they are instrumented with separate PMU events. ##000000C0A8 False Load-Hit-Store (LHS) match detected. Load and store have a partial Effective Address (EA) match but they are actually independent of each other. The other cases of false LHS cause flushes and they are instrumented with separate PMU events. #200,u,g,n,n,n,u,PM_LD0_LHS_REJECT,On the LD0 load execution unit, the real address of a load matched the real address of an earlier store and it is not possible to store forward because not all bytes required by the load are available on the store entry that was hit. In this case, the load must wait for the store to drain or for the store data to issue. ##000000C8A8 On the LD0 load execution unit, the real address of a load matched the real address of an earlier store and it is not possible to store forward because not all bytes required by the load are available on the store entry that was hit. In this case, the load must wait for the store to drain or for the store data to issue. #201,u,g,n,n,n,u,PM_LD1_LHS_REJECT,On the LD1 load execution unit, the real address of a load matched the real address of an earlier store and it is not possible to store forward because not all bytes required by the load are available on the store entry that was hit. In this case, the load must wait for the store to drain or for the store data to issue. ##000000C0AC On the LD1 load execution unit, the real address of a load matched the real address of an earlier store and it is not possible to store forward because not all bytes required by the load are available on the store entry that was hit. In this case, the load must wait for the store to drain or for the store data to issue. #202,u,g,n,n,n,u,PM_ST0_STORE_REJECT,Store reject on the ST0 store execution unit. All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up, to try again after the condition has been met. ##000000C8AC Store reject on the ST0 store execution unit. All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up, to try again after the condition has been met. #203,u,g,n,n,n,u,PM_ST1_STORE_REJECT,Store reject on the ST1 store execution unit. All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up, to try again after the condition has been met. ##000000C0B0 Store reject on the ST1 store execution unit. All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up, to try again after the condition has been met. #204,u,g,n,n,n,u,PM_ST_DRAIN_MERGE,Two stores drain together. Use PM_ST_CMPL as a divider. If one of the stores crosses a cache-line boundary, a store drain can be counted for each half. In this case, if there are three stores they will count as two merges. ##000000C8B0 Two stores drain together. Use PM_ST_CMPL as a divider. If one of the stores crosses a cache-line boundary, a store drain can be counted for each half. In this case, if there are three stores they will count as two merges. #205,u,g,n,n,n,u,PM_LMQ_MERGE,A load-hit-reload occurred. A load launched in the LSU and hit an existing LMQ entry which is fetching data for the same cacheline. ##000000C0B4 A load-hit-reload occurred. A load launched in the LSU and hit an existing LMQ entry which is fetching data for the same cacheline. #206,u,g,n,n,n,u,PM_STCX_CMPL,STCX data was sent to nest, i.e. total count of stcx. stcx instructions are not allowed to gather before the final drain-out to the L1 and L2, so this count is always accurate. ##000000C8B4 STCX data was sent to nest, i.e. total count of stcx. stcx instructions are not allowed to gather before the final drain-out to the L1 and L2, so this count is always accurate. #207,u,g,n,n,n,u,PM_NCST_CMPL,Counts when an I=1 store op is sent to the nest. This event counts at drain time and it may include up to 3 stores that have gathered for the same cache line before drain. ##000000C0B8 Counts when an I=1 store op is sent to the nest. This event counts at drain time and it may include up to 3 stores that have gathered for the same cache line before drain. #208,u,g,n,n,n,u,PM_STCX_SUCCESS_CMPL,STCX instructions that completed successfully. Specifically, counts only when a pass status is returned from the nest. ##000000C8B8 STCX instructions that completed successfully. Specifically, counts only when a pass status is returned from the nest. #209,u,g,n,n,n,u,PM_DC_RELOAD_COLLISIONS,A load reading the L1 cache has a bank collision with another load reading the same bank, or due to a cache-line reload writing to that bank of the L1 cache. ##000000C0BC A load reading the L1 cache has a bank collision with another load reading the same bank, or due to a cache-line reload writing to that bank of the L1 cache. #210,u,g,n,n,n,u,PM_DC_STORE_WRITE_COLLISIONS,A store writing the L1 cache at the same time as a reload or dkill writing the L1 cache that results in a bank collision. ##000000C8BC A store writing the L1 cache at the same time as a reload or dkill writing the L1 cache that results in a bank collision. #211,u,g,n,n,n,u,PM_LSU_SET_MPRED,Set prediction(set-p) miss. The entry was not found in the Set prediction table. The set-p table contains a hash of the EA and it helps access the L1 cache. ##000000D080 Set prediction(set-p) miss. The entry was not found in the Set prediction table. The set-p table contains a hash of the EA and it helps access the L1 cache. #212,u,g,n,n,n,u,PM_DERAT_HIT,A load or store instruction missed the data cache and hit in the primary ERAT. There is no secondary ERAT ##000000D880 A load or store instruction missed the data cache and hit in the primary ERAT. There is no secondary ERAT #213,u,g,n,n,n,u,PM_IERAT_HIT,An instruction fetch missed in the instruction cache and hit in the primary ERAT. There is no secondary ERAT ##000000D084 An instruction fetch missed in the instruction cache and hit in the primary ERAT. There is no secondary ERAT #214,u,g,n,n,n,u,PM_TIQ_BYPASS,A translation request bypasses the TIQ either because the TIQ is completely empty at the time of the request. ##000000D884 A translation request bypasses the TIQ either because the TIQ is completely empty at the time of the request. #215,u,g,n,n,n,u,PM_TIQ_ALLOC_CYC,Cycles when one or more operations on that thread allocated one or more TIQ entries ##000000D088 Cycles when one or more operations on that thread allocated one or more TIQ entries #216,u,g,n,n,n,u,PM_TIQ_HALF_FULL_CYC,Cycles in which the TIQ has 4 or less active entries ##000000D888 Cycles in which the TIQ has 4 or less active entries #217,u,g,n,n,n,u,PM_TIQ_ERAT_MISS_EMB_FULL_RESPIN,A load or store missed in the ERAT and found no space in the EMB. ##000000D08C A load or store missed in the ERAT and found no space in the EMB. #218,u,g,n,n,n,u,PM_EMB_FULL_CYC,Cycles in which the ERAT miss buffer is full. When the ERAT miss buffer is full the operation will go to the TIQ ##000000D88C Cycles in which the ERAT miss buffer is full. When the ERAT miss buffer is full the operation will go to the TIQ #219,u,g,n,n,n,u,PM_LSU_FLUSH_CYC,LSU flushes: includes all LSU flushes. This event only counts one flush per cycle but the hardware can flush up to 5 instructions per cycle. In general, multiple flushes for the same thread get consolidated into a single flush operation. ##000000D090 LSU flushes: includes all LSU flushes. This event only counts one flush per cycle but the hardware can flush up to 5 instructions per cycle. In general, multiple flushes for the same thread get consolidated into a single flush operation. #220,u,g,n,n,n,u,PM_LSU_FLUSH_CI,Load was not initially issued to the LSU as a cache inhibited (non-cacheable) load, but it was later determined to be cache inhibited. ##000000D890 Load was not initially issued to the LSU as a cache inhibited (non-cacheable) load, but it was later determined to be cache inhibited. #221,u,g,n,n,n,u,PM_LSU_FLUSH_ALL_WAYS_LOCKED,Non-speculative stores have locked all ways in the data cache and a newly-issued older store is not able to allocate a way for a given congruence class. ##000000D094 Non-speculative stores have locked all ways in the data cache and a newly-issued older store is not able to allocate a way for a given congruence class. #222,u,g,n,n,n,u,PM_LSU_FLUSH_LHL,If a load hits on an older load of the same address that has been snooped, or two loads of the same thread and address execute out of order and a store of another thread occurs to that address, the younger load will be flushed. The LSU only checks the out-of-orderness of the two loads and ignores the address in detecting this condition. ##000000D894 If a load hits on an older load of the same address that has been snooped, or two loads of the same thread and address execute out of order and a store of another thread occurs to that address, the younger load will be flushed. The LSU only checks the out-of-orderness of the two loads and ignores the address in detecting this condition. #223,u,g,n,n,n,u,PM_LSU_FLUSH_SAME_ICT_GRP,This flush happens if an ICT pair contains a store followed by a load to the same address with at least one byte of overlap between the two. ##000000D098 This flush happens if an ICT pair contains a store followed by a load to the same address with at least one byte of overlap between the two. #224,u,g,n,n,n,u,PM_LSU_REJECT_LHS,Effective Address (EA) alias reject: no EA match but Real Addresses do match. ##000000D898 Effective Address (EA) alias reject: no EA match but Real Addresses do match. #225,u,g,n,n,n,u,PM_LSU_FLUSH_SPECIAL,LSU workaround flush. These flushes are setup with programmable scan-only latches to perform various actions when the flush macro receives a trigger from the debug macros. These actions include things like flushing the next op encountered for a particular thread, or flushing the next op that is the Next To Complete (NTC) op that is encountered on a particular slice. The kind of flush that the workaround is setup to perform is highly variable. ##000000D09C LSU workaround flush. These flushes are setup with programmable scan-only latches to perform various actions when the flush macro receives a trigger from the debug macros. These actions include things like flushing the next op encountered for a particular thread, or flushing the next op that is the Next To Complete (NTC) op that is encountered on a particular slice. The kind of flush that the workaround is setup to perform is highly variable. #226,u,g,n,n,n,u,PM_LSU_FLUSH_SHL,The instruction was flushed because of a sequential load/store consistency issue. If a load or store hits on an older load that has either been snooped (for loads) or has stale data (for stores), a flush will occur. ##000000D89C The instruction was flushed because of a sequential load/store consistency issue. If a load or store hits on an older load that has either been snooped (for loads) or has stale data (for stores), a flush will occur. #227,u,g,n,n,n,u,PM_LSU_FLUSH_SAO,A Load-Hit-Load condition with Strong Address Ordering (SAO) will have address compare disabled and will flush. ##000000D0A0 A Load-Hit-Load condition with Strong Address Ordering (SAO) will have address compare disabled and will flush. #228,u,g,n,n,n,u,PM_LSU_FLUSH_LARX_STCX,A LARX is flushed because an older LARX has an LMQ reservation for the same thread. A STCX is flushed because an older STCX is in the STQ. The flush happens when the older LARX/STCX relaunches ##000000D8A0 A LARX is flushed because an older LARX has an LMQ reservation for the same thread. A STCX is flushed because an older STCX is in the STQ. The flush happens when the older LARX/STCX relaunches #229,u,g,n,n,n,u,PM_LSU_FLUSH_OTHER,Other LSU flushes, including: * Sync - a sync acknowledge from the L2 caused a search of the LRQ for the oldest snooped load. This will either signal a Precise Flush of the oldest snooped load, or a Flush Next PPC. * Data Valid Flush Next - several cases of this, one example is store and reload are lined up such that a store-hit-reload scenario exists and the CDF has already launched and has gotten bad/stale data. * Bad Data Valid (DVAL) Flush Next - might be a few cases of this, one example is a larxa (D-cache hit) return data and DVAL signal, but can't allocate to the LMQ (either the LMQ is full, or some other reason). Already signaled DVAL but can't watch it for snoop_hit_larx. Need to take the “bad dval” back and flush all younger ops). ##000000D0A4 Other LSU flushes, including: * Sync - a sync acknowledge from the L2 caused a search of the LRQ for the oldest snooped load. This will either signal a Precise Flush of the oldest snooped load, or a Flush Next PPC. * Data Valid Flush Next - several cases of this, one example is store and reload are lined up such that a store-hit-reload scenario exists and the CDF has already launched and has gotten bad/stale data. * Bad Data Valid (DVAL) Flush Next - might be a few cases of this, one example is a larxa (D-cache hit) return data and DVAL signal, but can't allocate to the LMQ (either the LMQ is full, or some other reason). Already signaled DVAL but can't watch it for snoop_hit_larx. Need to take the “bad dval” back and flush all younger ops). #230,u,g,n,n,n,u,PM_DC_PREF_HW_ALLOC,Prefetch stream allocated by the hardware prefetch mechanism ##000000D8A4 Prefetch stream allocated by the hardware prefetch mechanism #231,u,g,n,n,n,u,PM_DC_PREF_SW_ALLOC,Prefetch stream allocated by software prefetching ##000000D0A8 Prefetch stream allocated by software prefetching #232,u,g,n,n,n,u,PM_DC_PREF_STRIDED_ALLOC,Strided prefetch stream allocated by either the software or hardware mechanisms ##000000D8A8 Strided prefetch stream allocated by either the software or hardware mechanisms #233,u,g,n,n,n,u,PM_DC_PREF_CONS_ALLOC,Prefetch stream allocated in the conservative phase by either the hardware prefetch mechanism or software prefetch. The sum of this pair subtracted from the total number of allocs will give the total allocs in normal phase ##000000D0AC Prefetch stream allocated in the conservative phase by either the hardware prefetch mechanism or software prefetch. The sum of this pair subtracted from the total number of allocs will give the total allocs in normal phase #234,u,g,n,n,n,u,PM_DC_PREF_XCONS_ALLOC,Prefetch stream allocated in the Ultra conservative phase by either the hardware prefetch mechanism or software prefetch ##000000D8AC Prefetch stream allocated in the Ultra conservative phase by either the hardware prefetch mechanism or software prefetch #235,u,g,n,n,n,u,PM_DC_PREF_CONF,A demand load referenced a line in an active prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. Includes forwards and backwards streams ##000000D0B0 A demand load referenced a line in an active prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. Includes forwards and backwards streams #236,u,g,n,n,n,u,PM_DC_PREF_FUZZY_CONF,A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up) ##000000D8B0 A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up) #237,u,g,n,n,n,u,PM_DC_PREF_STRIDED_CONF,A demand load referenced a line in an active strided prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. ##000000D0B4 A demand load referenced a line in an active strided prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. #238,u,g,n,n,n,u,PM_DC_PREF_DEALLOC_NO_CONF,A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up) ##000000D8B4 A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up) #239,u,g,n,n,n,u,PM_L1_SW_PREF,Software L1 Prefetches, including SW Transient Prefetches ##000000D0B8 Software L1 Prefetches, including SW Transient Prefetches #240,u,g,n,n,n,u,PM_L3_SW_PREF,L3 load prefetch, sourced from a software prefetch stream, was sent to the nest ##000000D0BC L3 load prefetch, sourced from a software prefetch stream, was sent to the nest #241,u,g,n,n,n,u,PM_SNOOP_TLBIE_MY_LPAR_CYC,TLBIE snoops executed in the LSU ##000000F080 TLBIE snoops executed in the LSU #242,u,g,n,n,n,u,PM_SNOOP_TLBIE_CYC,Cycles in which TLBIE snoops are executed in the LSU ##000000F880 Cycles in which TLBIE snoops are executed in the LSU #243,u,g,n,n,n,u,PM_SNOOP_TLBIE_CACHE_WALK_CYC,TLBIE snoop cycles in which the data cache is being walked ##000000F084 TLBIE snoop cycles in which the data cache is being walked #244,u,g,n,n,n,u,PM_SNOOP_TLBIE_WAIT_ST_CYC,TLBIE snoop cycles in which older stores are still draining ##000000F884 TLBIE snoop cycles in which older stores are still draining #245,u,g,n,n,n,u,PM_SNOOP_TLBIE_WAIT_LD_CYC,TLBIE snoop cycles in which older loads are still draining ##000000F088 TLBIE snoop cycles in which older loads are still draining #246,u,g,n,n,n,u,PM_SNOOP_TLBIE_WAIT_IFU_CYC,TLBIE snoop cycles in which the Load-Store unit is waiting for the instruction cache to be walked ##000000F888 TLBIE snoop cycles in which the Load-Store unit is waiting for the instruction cache to be walked #247,u,g,n,n,n,u,PM_SNOOP_TLBIE_WAIT_MMU_CYC,TLBIE snoop cycles in which the Load-Store unit is waiting for the MMU to finish invalidation ##000000F08C TLBIE snoop cycles in which the Load-Store unit is waiting for the MMU to finish invalidation #248,u,g,n,n,n,u,PM_LD0_SETP_HIT_EADIR_MISS,A load in the LD0 execution unit matched the setp Effective Address (EA) hash function for one of the ways in the L1. But the full EA does not match the L1 directory, so the request is sent to the L1 miss pipe. ##000000F094 A load in the LD0 execution unit matched the setp Effective Address (EA) hash function for one of the ways in the L1. But the full EA does not match the L1 directory, so the request is sent to the L1 miss pipe. #249,u,g,n,n,n,u,PM_SAME_EA_DIFF_CTXTAG_RADIR_HIT,A load or store did not get a full Effective Address (EA) plus Context match in the EA directory, so it is sent to the L1 miss pipe. In particular, a full EA match, but a context miss occurred. In the L1 miss pipe, the Real Address (RA) directory lookup finds that the real address is in the L1, but allocated in the EA directory with a different context. ##000000F898 A load or store did not get a full Effective Address (EA) plus Context match in the EA directory, so it is sent to the L1 miss pipe. In particular, a full EA match, but a context miss occurred. In the L1 miss pipe, the Real Address (RA) directory lookup finds that the real address is in the L1, but allocated in the EA directory with a different context. #250,u,g,n,n,n,u,PM_CTXT_MP4_ALLOC,A new entry is created in the 4 entry Context Alias Table due to a load or store that L1 missed due to same EA/different context, but whose Real Address (RA) was found in the L1 during (RA) directory lookup in the miss pipe. ##000000F09C A new entry is created in the 4 entry Context Alias Table due to a load or store that L1 missed due to same EA/different context, but whose Real Address (RA) was found in the L1 during (RA) directory lookup in the miss pipe. #251,u,g,n,n,n,u,PM_CTXT_ALIAS_HIT_CONTRIB,A load or a store in the miss pipe hits in the Real Address (RA) directory and also on one of the 4 entries of the Context Alias Table. The index and way getting an RA directory hit is written with a context alias tag to allow future L1 hits. ##000000F89C A load or a store in the miss pipe hits in the Real Address (RA) directory and also on one of the 4 entries of the Context Alias Table. The index and way getting an RA directory hit is written with a context alias tag to allow future L1 hits. #252,u,g,n,n,n,u,PM_START_NEW_RENAME,Upon creation of a new Context Alias Table entry, a 4k walk is initiated to set the Alias Tag valid for the 31 other congruence classes. The walk is only initiated after it is confirmed that at least 2 other congruence classes detected a context alias situation.  ##000000F0A0 Upon creation of a new Context Alias Table entry, a 4k walk is initiated to set the Alias Tag valid for the 31 other congruence classes. The walk is only initiated after it is confirmed that at least 2 other congruence classes detected a context alias situation.  #253,u,g,n,n,n,u,PM_STORE_ALLOCATE,A store misses the L1 Effective Address (EA) Directory and allocates an L1 index and way with its address for use in tracking the store address in the Load-Store Unit (LSU) during the SRQ lifetime of the store. ##000000F8A0 A store misses the L1 Effective Address (EA) Directory and allocates an L1 index and way with its address for use in tracking the store address in the Load-Store Unit (LSU) during the SRQ lifetime of the store. #254,u,g,n,n,n,u,PM_LOAD_ALLOC_DEPRA_FOR_ALL_WAYS_LOCKED,A load miss allocates an Load Miss Queue (LMQ) entry however it is not able to allocate an L1 index and way for load hazard detection in the LRQ because all 8 ways are locked, either by stores in the SRQ or other loads in the LMQ. The current load is instead marked deprecated. CDF will occur but it will be marked deprecated in the LRQ and ordering hazard checking will be pessimistic. ##000000F0A4 A load miss allocates an Load Miss Queue (LMQ) entry however it is not able to allocate an L1 index and way for load hazard detection in the LRQ because all 8 ways are locked, either by stores in the SRQ or other loads in the LMQ. The current load is instead marked deprecated. CDF will occur but it will be marked deprecated in the LRQ and ordering hazard checking will be pessimistic. #255,u,g,n,n,n,u,PM_STORE_REJECT_FOR_ALL_WAYS_LOCKED,A store misses the L1 Effective Address (EA) Directory, but cannot allocates an L1 index and way with its address due to all 8 ways being locked, either by stores already in the SRQ or by loads in the LMQ. The store is rejected and relaunched immediately. ##000000F8A4 A store misses the L1 Effective Address (EA) Directory, but cannot allocates an L1 index and way with its address due to all 8 ways being locked, either by stores already in the SRQ or by loads in the LMQ. The store is rejected and relaunched immediately. #256,u,g,n,n,n,u,PM_DERAT_HIT_4K,A load or store instruction missed the data cache and hit in the primary ERAT. Page size = 4K ##000000F0B0 A load or store instruction missed the data cache and hit in the primary ERAT. Page size = 4K #257,u,g,n,n,n,u,PM_IERAT_HIT_4K,An instruction fetch missed in the instruction cache and hit in the primary ERAT. Page size = 4k ##000000F8B0 An instruction fetch missed in the instruction cache and hit in the primary ERAT. Page size = 4k #258,u,g,n,n,n,u,PM_DERAT_HIT_64K,A load or store instruction missed the data cache and hit in the primary ERAT. Page size =64k ##000000F0B4 A load or store instruction missed the data cache and hit in the primary ERAT. Page size =64k #259,u,g,n,n,n,u,PM_IERAT_HIT_64K,An instruction fetch missed in the instruction cache and hit in the primary ERAT. Page size = 64k ##000000F8B4 An instruction fetch missed in the instruction cache and hit in the primary ERAT. Page size = 64k #260,u,g,n,n,n,u,PM_DERAT_HIT_2M,A load or store instruction missed the data cache and hit in the primary ERAT. Page size = 2M ##000000F0B8 A load or store instruction missed the data cache and hit in the primary ERAT. Page size = 2M #261,u,g,n,n,n,u,PM_IERAT_HIT_2M,An instruction fetch missed in the instruction cache and hit in the primary ERAT. Page size = 2M ##000000F8B8 An instruction fetch missed in the instruction cache and hit in the primary ERAT. Page size = 2M #262,u,g,n,n,n,u,PM_DERAT_HIT_1G,A load or store instruction missed the data cache and hit in the primary ERAT. Page size = 1G ##000000F0BC A load or store instruction missed the data cache and hit in the primary ERAT. Page size = 1G #263,u,g,n,n,n,u,PM_IERAT_HIT_1G,An instruction fetch missed in the instruction cache and hit in the primary ERAT. Page size = 1G ##000000F8BC An instruction fetch missed in the instruction cache and hit in the primary ERAT. Page size = 1G #264,u,g,n,n,n,u,PM_INST_FROM_L1,An instruction fetch hit in the L1. Each fetch group contains 8 instructions. The same line can hit 4 times if 32 sequential instructions are fetched. ##0000004080 An instruction fetch hit in the L1. Each fetch group contains 8 instructions. The same line can hit 4 times if 32 sequential instructions are fetched. #265,u,g,n,n,n,u,PM_NO_FETCH_BANK_CONFLICT_CYC,Cycles in which no instructions are fetched because of an interleave conflict. The ifar logic will detect an interleave conflict and kill the data that was read that cycle. ##0000004880 Cycles in which no instructions are fetched because of an interleave conflict. The ifar logic will detect an interleave conflict and kill the data that was read that cycle. #266,u,g,n,n,n,u,PM_NO_FETCH_EAT_FULL_CYC,Cycles in which no instructions are fetched because there is no room in EAT ##0000004084 Cycles in which no instructions are fetched because there is no room in EAT #267,u,g,n,n,n,u,PM_NO_FETCH_IBUF_FULL_CYC,Cycles in which no instructions are fetched because there is no room in the instruction buffers ##0000004884 Cycles in which no instructions are fetched because there is no room in the instruction buffers #268,u,g,n,n,n,u,PM_NO_FETCH_THROTTLE_CYC,Cycles in which no instructions are fetched for this thread because it is being throttled ##0000004088 Cycles in which no instructions are fetched for this thread because it is being throttled #269,u,g,n,n,n,u,PM_FETCH_CYC,Cycles in which instructions are successfully fetched from the instruction cache ##0000004888 Cycles in which instructions are successfully fetched from the instruction cache #270,u,g,n,n,n,u,PM_NO_FETCH_THROTTLE_POWMAN_CYC,Cycles in which the thread is throttled because of power management ##000000408C Cycles in which the thread is throttled because of power management #271,u,g,n,n,n,u,PM_NO_FETCH_THROTTLE_OTHER_CYC,Cycles in which the thread is throttled for a reason other than power management, relative priority and dynamic priority. This includes throttles for speculation for power or performance, independently decided by the IFAR ##000000488C Cycles in which the thread is throttled for a reason other than power management, relative priority and dynamic priority. This includes throttles for speculation for power or performance, independently decided by the IFAR #272,u,g,n,n,n,u,PM_NO_FETCH_THROTTLE_REL_PRIO_CYC,Cycles in which the thread is throttled because of relative priority. This is thread arbitration based on the Relative Priority Register (RPR). ##0000004090 Cycles in which the thread is throttled because of relative priority. This is thread arbitration based on the Relative Priority Register (RPR). #273,u,g,n,n,n,u,PM_NO_FETCH_THROTTLE_DYN_PRIO_CYC,Cycles in which the thread is throttled because of dynamic priority. This is the generic thread arbitration without relative thread priority. A thread may also be throttled if an instruction cache reload for a different thread occurs in the same cycle. ##0000004890 Cycles in which the thread is throttled because of dynamic priority. This is the generic thread arbitration without relative thread priority. A thread may also be throttled if an instruction cache reload for a different thread occurs in the same cycle. #274,u,g,n,n,n,u,PM_DECODE_THROTTLE_IIF_CYC,Cycles in which decode was held for a thread due to an Instruction-In-Flight throttle (WOF). This event will increment regardless of other decode holds being present ##0000004894 Cycles in which decode was held for a thread due to an Instruction-In-Flight throttle (WOF). This event will increment regardless of other decode holds being present #275,u,g,n,n,n,u,PM_DECODE_HOLD_NO_ITAGS,Cycles in which the IFU was not able to decode and transmit one or more instructions because all itags were in use. This means the ICT is full for this thread. This event will only increment when no other hold is present. ##0000004098 Cycles in which the IFU was not able to decode and transmit one or more instructions because all itags were in use. This means the ICT is full for this thread. This event will only increment when no other hold is present. #276,u,g,n,n,n,u,PM_DECODE_THROTTLE_IPC_CYC,Cycles in which decode is throttled because M over N throttle is active (WOF). This event will increment regardless of other decode holds being present ##0000004898 Cycles in which decode is throttled because M over N throttle is active (WOF). This event will increment regardless of other decode holds being present #277,u,g,n,n,n,u,PM_IC_INVALIDATE,A line in the instruction cache has been invalidated by an ICBI ##000000409C A line in the instruction cache has been invalidated by an ICBI #278,u,g,n,n,n,u,PM_IC_RELOAD_PRIVATE,An instruction cache line was brought in private for a specific thread. Most lines are brought in shared for all four threads. ##000000489C An instruction cache line was brought in private for a specific thread. Most lines are brought in shared for all four threads. #279,u,g,n,n,n,u,PM_IC_PREF_REQ,Instruction prefetch requests ##00000040A0 Instruction prefetch requests #280,u,g,n,n,n,u,PM_FUSED_BACK_TO_BACK,Back to back two-cycle execution. Counted at decode time ##00000048A0 Back to back two-cycle execution. Counted at decode time #281,u,g,n,n,n,u,PM_FUSED_DESTRUCTIVE,The first and second instruction have the same target register. Counted at decode time ##00000040A4 The first and second instruction have the same target register. Counted at decode time #282,u,g,n,n,n,u,PM_FUSED_RESULT,Two fused PowerPC (PPC set) instructions: the first PPC instruction, in age order, is the result of the second PPC instruction. Counted at decode time. ##00000048A4 Two fused PowerPC (PPC set) instructions: the first PPC instruction, in age order, is the result of the second PPC instruction. Counted at decode time. #283,u,g,n,n,n,u,PM_FUSED_TOGETHER,Produce 2 results together. Ex instruction having a fusable compare: fabs f3,f1 ##00000040A8 Produce 2 results together. Ex instruction having a fusable compare: fabs f3,f1 #284,u,g,n,n,n,u,PM_FUSED_LOADCOMPARE,Fusion of a load and a compare immediate referencing the load's data. Ex: ldx r3,r1,r2 ##00000048A8 Fusion of a load and a compare immediate referencing the load's data. Ex: ldx r3,r1,r2 #285,u,g,n,n,n,u,PM_FUSED_LOAD_LOAD,Fusion of two displacement loads (meeting the requirements for load-load fusion). ##00000040AC Fusion of two displacement loads (meeting the requirements for load-load fusion). #286,u,g,n,n,n,u,PM_BCQ_FULL_CYC,Cycles in which all 12 entries of the BCQ are full ##00000040B0 Cycles in which all 12 entries of the BCQ are full #287,u,g,n,n,n,u,PM_BR_FIN_FROM_BCQ,Branches that were issued with sources not ready (CR=0), counted at finish time. Branches go to the BCQ when their sources are not ready. ##00000048B0 Branches that were issued with sources not ready (CR=0), counted at finish time. Branches go to the BCQ when their sources are not ready. #288,u,g,n,n,n,u,PM_BR_TKN_FIN,A taken branch (conditional or unconditional) finished ##00000040B4 A taken branch (conditional or unconditional) finished #289,u,g,n,n,n,u,PM_BR_TKN_UNCOND_FIN,An unconditional branch finished. All unconditional branches are taken. ##00000048B4 An unconditional branch finished. All unconditional branches are taken. #290,u,g,n,n,n,u,PM_PRED_BR_TKN_COND_DIR,A conditional branch finished with correctly predicted direction. Resolved taken ##00000040B8 A conditional branch finished with correctly predicted direction. Resolved taken #291,u,g,n,n,n,u,PM_PRED_BR_NTKN_COND_DIR,A conditional branch finished with correctly predicted direction. Resolved not taken ##00000048B8 A conditional branch finished with correctly predicted direction. Resolved not taken #292,u,g,n,n,n,u,PM_MPRED_BR_TKN_COND_DIR,A conditional branch finished with mispredicted direction. Resolved taken ##00000040BC A conditional branch finished with mispredicted direction. Resolved taken #293,u,g,n,n,n,u,PM_MPRED_BR_NTKN_COND_DIR,A conditional branch finished with mispredicted direction. Resolved not taken ##00000048BC A conditional branch finished with mispredicted direction. Resolved not taken #294,u,g,n,n,n,u,PM_PRED_BR_TKN_COND_TGT_DIR,A conditional branch finished with correctly predicted target and direction. Resolved taken ##0000005080 A conditional branch finished with correctly predicted target and direction. Resolved taken #295,u,g,n,n,n,u,PM_PRED_BR_NTKN_COND_TGT_DIR,A conditional branch finished with correctly predicted target and direction. Resolved not taken ##0000005880 A conditional branch finished with correctly predicted target and direction. Resolved not taken #296,u,g,n,n,n,u,PM_MPRED_BR_NTKN_COND_TGT_DIR,A conditional branch finished with mispredicted target and direction. Resolved not taken ##0000005884 A conditional branch finished with mispredicted target and direction. Resolved not taken #297,u,g,n,n,n,u,PM_BR_PRED_TKN_COND_DIR_LBHT_LSEL,A conditional branch finished with correctly predicted direction using the Local Branch History Table selected by the local selector. Resolved taken ##0000005088 A conditional branch finished with correctly predicted direction using the Local Branch History Table selected by the local selector. Resolved taken #298,u,g,n,n,n,u,PM_BR_PRED_TKN_COND_DIR_LBHT_GSEL,A conditional branch finished with correctly predicted direction using the Local Branch History Table selected with the global selector. Resolved taken ##0000005888 A conditional branch finished with correctly predicted direction using the Local Branch History Table selected with the global selector. Resolved taken #299,u,g,n,n,n,u,PM_BR_PRED_TKN_COND_DIR_GBHT,A conditional branch finished with correctly predicted direction using the Global Branch History Table. Resolved taken ##000000508C A conditional branch finished with correctly predicted direction using the Global Branch History Table. Resolved taken #300,u,g,n,n,n,u,PM_BR_PRED_TKN_COND_DIR_TAGE,A conditional branch finished with correctly predicted direction using a TAGE override. Resolved taken ##000000588C A conditional branch finished with correctly predicted direction using a TAGE override. Resolved taken #301,u,g,n,n,n,u,PM_BR_PRED_TKN_COND_DIR_TOP,A conditional branch finished with correctly predicted direction using a TOP override to the BHT. Resolved taken ##0000005090 A conditional branch finished with correctly predicted direction using a TOP override to the BHT. Resolved taken #302,u,g,n,n,n,u,PM_BR_PRED_TKN_COND_TGT_COUNT_LCC,A conditional branch finished with correctly predicted target using the local count cache. Resolved taken ##0000005890 A conditional branch finished with correctly predicted target using the local count cache. Resolved taken #303,u,g,n,n,n,u,PM_BR_PRED_TKN_COND_TGT_COUNT_GCC,A conditional branch finished with correctly predicted target using the global count cache. Resolved taken ##0000005094 A conditional branch finished with correctly predicted target using the global count cache. Resolved taken #304,u,g,n,n,n,u,PM_BR_PRED_TKN_COND_TGT_COUNT_TIP,A conditional branch finished with correctly predicted target using the count TIP override to the count cache. Resolved taken ##0000005894 A conditional branch finished with correctly predicted target using the count TIP override to the count cache. Resolved taken #305,u,g,n,n,n,u,PM_BR_PRED_TKN_TGT_LINK,A conditional or unconditional branch finished with correctly predicted target using the Link register (bclr[l]) and predicted by Link Stack (BH(1)=0). Resolved taken ##0000005098 A conditional or unconditional branch finished with correctly predicted target using the Link register (bclr[l]) and predicted by Link Stack (BH(1)=0). Resolved taken #306,u,g,n,n,n,u,PM_BR_PRED_NTKN_COND_DIR_LBHT_LSEL,A conditional branch finished with correctly predicted direction using the Local Branch History Table selected by the local selector. Resolved not taken ##0000005898 A conditional branch finished with correctly predicted direction using the Local Branch History Table selected by the local selector. Resolved not taken #307,u,g,n,n,n,u,PM_BR_PRED_NTKN_COND_DIR_LBHT_GSEL,A conditional branch finished with correctly predicted direction using the Local Branch History Table selected with the global selector. Resolved not taken ##000000509C A conditional branch finished with correctly predicted direction using the Local Branch History Table selected with the global selector. Resolved not taken #308,u,g,n,n,n,u,PM_BR_PRED_NTKN_COND_DIR_GBHT,A conditional branch finished with correctly predicted direction using the Global Branch History Table. Resolved not taken ##000000589C A conditional branch finished with correctly predicted direction using the Global Branch History Table. Resolved not taken #309,u,g,n,n,n,u,PM_BR_PRED_NTKN_COND_DIR_TAGE,A conditional branch finished with correctly predicted direction using a TAGE override. Resolved not taken ##00000050A0 A conditional branch finished with correctly predicted direction using a TAGE override. Resolved not taken #310,u,g,n,n,n,u,PM_BR_PRED_NTKN_COND_DIR_TOP,A conditional branch finished with correctly predicted direction using a TOP override to the BHT. Resolved not taken ##00000058A0 A conditional branch finished with correctly predicted direction using a TOP override to the BHT. Resolved not taken #311,u,g,n,n,n,u,PM_SHL_CREATED,An Store-Hit-Load Table entry was created as a result of an SHL Flush. ##00000050A4 An Store-Hit-Load Table entry was created as a result of an SHL Flush. #312,u,g,n,n,n,u,PM_SHL_ST_DEPENDENCY,A fetched instruction hit in the Store-Hit-Load Table. ##00000058A4 A fetched instruction hit in the Store-Hit-Load Table. #313,u,g,n,n,n,u,PM_IEADIR_HIT_IDIR_MISS,A fetch hit in the IEADIR but missed in the IDIR. This is usually due to IEADIR aliasing, but could be due to an IDIR invalidate that did not invalidate the corresponding IEADIR entry. ##00000050A8 A fetch hit in the IEADIR but missed in the IDIR. This is usually due to IEADIR aliasing, but could be due to an IDIR invalidate that did not invalidate the corresponding IEADIR entry. #314,u,g,n,n,n,u,PM_ICACHE_MISS_DUE_TO_CTXTTAG,A fetch missed the instruction cache due to a context tag miscompare. All other fields matched. This is similar to PM_IEA_TRACKING_TABLE_WRITE but is not restricted to context tags restricted to IEA Sharing and does not require IEA Sharing to be enabled. ##00000058A8 A fetch missed the instruction cache due to a context tag miscompare. All other fields matched. This is similar to PM_IEA_TRACKING_TABLE_WRITE but is not restricted to context tags restricted to IEA Sharing and does not require IEA Sharing to be enabled. #315,u,g,n,n,n,u,PM_BR_MPRED_TKN_COND_DIR_LBHT_LSEL,A conditional branch finished with mispredicted direction using the Local Branch History Table selected by the local selector. Resolved taken ##00000050AC A conditional branch finished with mispredicted direction using the Local Branch History Table selected by the local selector. Resolved taken #316,u,g,n,n,n,u,PM_BR_MPRED_TKN_COND_DIR_LBHT_GSEL,A conditional branch finished with mispredicted direction using the Local Branch History Table selected with the global selector. Resolved taken ##00000058AC A conditional branch finished with mispredicted direction using the Local Branch History Table selected with the global selector. Resolved taken #317,u,g,n,n,n,u,PM_BR_MPRED_TKN_COND_DIR_GBHT,A conditional branch finished with mispredicted direction using the Global Branch History Table. Resolved taken ##00000050B0 A conditional branch finished with mispredicted direction using the Global Branch History Table. Resolved taken #318,u,g,n,n,n,u,PM_BR_MPRED_TKN_COND_DIR_TAGE,A conditional branch finished with mispredicted direction using a TAGE override. Resolved taken ##00000058B0 A conditional branch finished with mispredicted direction using a TAGE override. Resolved taken #319,u,g,n,n,n,u,PM_BR_MPRED_TKN_COND_DIR_TOP,A conditional branch finished with mispredicted direction using a TOP override to the BHT. Resolved taken ##00000050B4 A conditional branch finished with mispredicted direction using a TOP override to the BHT. Resolved taken #320,u,g,n,n,n,u,PM_BR_MPRED_TKN_COND_TGT_COUNT_LCC,A conditional branch finished with mispredicted target using the local count cache. Resolved taken ##00000058B4 A conditional branch finished with mispredicted target using the local count cache. Resolved taken #321,u,g,n,n,n,u,PM_BR_MPRED_TKN_COND_TGT_COUNT_GCC,A conditional branch finished with mispredicted target using the global count cache. Resolved taken ##00000050B8 A conditional branch finished with mispredicted target using the global count cache. Resolved taken #322,u,g,n,n,n,u,PM_BR_MPRED_TKN_COND_TGT_COUNT_TIP,A conditional branch finished with mispredicted target using the count TIP override to the count cache. Resolved taken ##00000058B8 A conditional branch finished with mispredicted target using the count TIP override to the count cache. Resolved taken #323,u,g,n,n,n,u,PM_BR_MPRED_TKN_TGT_LINK,A conditional or unconditional branch finished with mispredicted target using the Link register. Resolved taken ##00000050BC A conditional or unconditional branch finished with mispredicted target using the Link register. Resolved taken #324,u,g,n,n,n,u,PM_BR_MPRED_NTKN_COND_DIR_LBHT_LSEL,A conditional branch finished with mispredicted direction using the Local Branch History Table selected by the local selector. Resolved not taken ##00000058BC A conditional branch finished with mispredicted direction using the Local Branch History Table selected by the local selector. Resolved not taken #325,u,g,n,n,n,u,PM_BR_MPRED_NTKN_COND_DIR_LBHT_GSEL,A conditional branch finished with mispredicted direction using the Local Branch History Table selected with the global selector. Resolved not taken ##000000E080 A conditional branch finished with mispredicted direction using the Local Branch History Table selected with the global selector. Resolved not taken #326,u,g,n,n,n,u,PM_BR_MPRED_NTKN_COND_DIR_GBHT,A conditional branch finished with mispredicted direction using the Global Branch History Table. Resolved not taken ##000000E880 A conditional branch finished with mispredicted direction using the Global Branch History Table. Resolved not taken #327,u,g,n,n,n,u,PM_BR_MPRED_NTKN_COND_DIR_TAGE,A conditional branch finished with mispredicted direction using a TAGE override. Resolved not taken ##000000E084 A conditional branch finished with mispredicted direction using a TAGE override. Resolved not taken #328,u,g,n,n,n,u,PM_BR_MPRED_NTKN_COND_DIR_TOP,A conditional branch finished with mispredicted direction using a TOP override to the BHT. Resolved not taken ##000000E884 A conditional branch finished with mispredicted direction using a TOP override to the BHT. Resolved not taken #329,u,g,n,n,n,u,PM_IEA_ALIAS_TABLE_WRITE,IFU EA Sharing was detected and the sharing info was written to the IFU Alias Table. ##000000E088 IFU EA Sharing was detected and the sharing info was written to the IFU Alias Table. #330,u,g,n,n,n,u,PM_IEA_ALIAS_TABLE_HIT,Instruction cache reload hit on the Alias Table and was written to the ICache as an IEA Shared entry. ##000000E888 Instruction cache reload hit on the Alias Table and was written to the ICache as an IEA Shared entry. #331,u,g,n,n,n,u,PM_IEA_TRACKING_TABLE_WRITE,Instruction cache miss occurred where ICache EA Sharing may be possible. i.e. All IDIR fields matched except the context tag and the incumbent context tag is compatible with IEA Sharing. ##000000E08C Instruction cache miss occurred where ICache EA Sharing may be possible. i.e. All IDIR fields matched except the context tag and the incumbent context tag is compatible with IEA Sharing. #332,u,g,n,n,n,u,PM_IEA_ICACHE_SHARED_HIT,Instruction cache hit occurred on an entry that is marked as IEA Sharing. This does not include ICache reload bypasses. ##000000E88C Instruction cache hit occurred on an entry that is marked as IEA Sharing. This does not include ICache reload bypasses. #333,u,g,n,n,n,u,PM_BR_BTAC_INV_TGT,BTAC predicts a target that is different from what the BHT and count cache predict. The BTAC entry is invalidated. Reported at fetch time ##000000E890 BTAC predicts a target that is different from what the BHT and count cache predict. The BTAC entry is invalidated. Reported at fetch time #334,u,g,n,n,n,u,PM_BR_BTAC_INV_DIR,BTAC predicts taken for a branch that the BHT predicts not taken, so that BTAC entry is invalidated. Reported at fetch time ##000000E094 BTAC predicts taken for a branch that the BHT predicts not taken, so that BTAC entry is invalidated. Reported at fetch time #335,u,g,n,n,n,u,PM_BR_PRED_COND_BTAC,A conditional branch finished with correctly predicted target or direction using the BTAC. Reported at fetch time ##000000E894 A conditional branch finished with correctly predicted target or direction using the BTAC. Reported at fetch time #336,u,g,n,n,n,u,PM_MPRED_BR_FIN,A conditional branch mispredicted its direction or target address. Counted at finish time ##000000E098 A conditional branch mispredicted its direction or target address. Counted at finish time #337,u,g,n,n,n,u,PM_BR_PRED_TKN_SWHINT,A software hinted branch finished and the branch resolved taken and the hint was correct. ##000000E898 A software hinted branch finished and the branch resolved taken and the hint was correct. #338,u,g,n,n,n,u,PM_BR_PRED_NTKN_SWHINT,A software hinted branch finished and the branch resolved not taken and the hint was correct. ##000000E09C A software hinted branch finished and the branch resolved not taken and the hint was correct. #339,u,g,n,n,n,u,PM_BR_MPRED_TKN_SWHINT,A software hinted branch finished and the branch resolved taken and the hint was incorrect. ##000000E89C A software hinted branch finished and the branch resolved taken and the hint was incorrect. #340,u,g,n,n,n,u,PM_BR_MPRED_NTKN_SWHINT,A software hinted branch finished and the branch resolved not taken and the hint was incorrect. ##000000E0A0 A software hinted branch finished and the branch resolved not taken and the hint was incorrect. #341,u,g,n,n,n,u,PM_BACK_BRANCH,Branch whose target address is lower than the program counter ##000000E0A4 Branch whose target address is lower than the program counter #342,u,g,n,n,n,u,PM_TLB_ACCESS_L3PREF,Incoming L3 prefetches that access the TLB (there is no L3 instruction prefetching in POWER10). L3 prefetches access the TLB directly, without accessing the ERAT ##0000008080 Incoming L3 prefetches that access the TLB (there is no L3 instruction prefetching in POWER10). L3 prefetches access the TLB directly, without accessing the ERAT #343,u,g,n,n,n,u,PM_TLB_CHILD_PURGE_CYC,Cycles spent in a TLB scrub. Counted for radix or HPT translations. Implies a parent eviction ##0000008880 Cycles spent in a TLB scrub. Counted for radix or HPT translations. Implies a parent eviction #344,u,g,n,n,n,u,PM_REJ_MMU,The MMU rejects a translation for any reason. This includes loads/stores/ifetches. ##0000008884 The MMU rejects a translation for any reason. This includes loads/stores/ifetches. #345,u,g,n,n,n,u,PM_REJ_EXEC_NTC_SLEEP_SELECT,The operation is rejected because it must be NTC to translate. This includes loads/stores/ifetches. ##0000008088 The operation is rejected because it must be NTC to translate. This includes loads/stores/ifetches. #346,u,g,n,n,n,u,PM_RDXWALK_INSTR_CYC,Cycles when an instruction(MMU type fetch) tablewalk is active. ##000000808C Cycles when an instruction(MMU type fetch) tablewalk is active. #347,u,g,n,n,n,u,PM_RDXWALK_DATA_CYC,Data Tablewalk Cycles. Cycles in which at least one tablewalk is in progress. This event includes data, demand and prefetch(MMU type LD, ST, L1 Prefetch). There can be up to 4 tablewalks in one cycle. ##000000888C Data Tablewalk Cycles. Cycles in which at least one tablewalk is in progress. This event includes data, demand and prefetch(MMU type LD, ST, L1 Prefetch). There can be up to 4 tablewalks in one cycle. #348,u,g,n,n,n,u,PM_REJ_TABLEWALK_L2_PDE_MERGE,A translation is rejected on a level 2 PDE boundary. This is only valid for radix. This is when the incoming translation matches on the 1G address boundary, but not a 2M address boundary. ##0000008090 A translation is rejected on a level 2 PDE boundary. This is only valid for radix. This is when the incoming translation matches on the 1G address boundary, but not a 2M address boundary. #349,u,g,n,n,n,u,PM_REJ_TABLEWALK_L3_PDE_MERGE,A translation is rejected on a level 3 PDE boundary. This is when the incoming translation matches on the 2M address boundary, but not the 64k address boundary. This is only valid in radix translations. ##0000008890 A translation is rejected on a level 3 PDE boundary. This is when the incoming translation matches on the 2M address boundary, but not the 64k address boundary. This is only valid in radix translations. #350,u,g,n,n,n,u,PM_REJ_TABLEWALK_PTE_MERGE,A translation is rejected on a PTE boundary. This indicates that the table walk merged due to a full 4k or 64k address match. This is valid for both Radix and HPT. In HPT this is both the parent hit, child miss case, and the parent miss case. ##0000008094 A translation is rejected on a PTE boundary. This indicates that the table walk merged due to a full 4k or 64k address match. This is valid for both Radix and HPT. In HPT this is both the parent hit, child miss case, and the parent miss case. #351,u,g,n,n,m,u,PM_MRK_DTABLEWALK_CYC,Cycles a data(MMU type LD, ST, L1 PF) tablewalk is in progress for a marked instruction. ##0000008894 Cycles a data(MMU type LD, ST, L1 PF) tablewalk is in progress for a marked instruction. #352,u,g,n,n,n,u,PM_XLATE_HPT_MODE_CYC,MMU reports every cycle the thread is in HPT translation mode (as opposed to radix mode) ##0000008098 MMU reports every cycle the thread is in HPT translation mode (as opposed to radix mode) #353,u,g,n,n,n,u,PM_XLATE_RADIX_MODE_CYC,MMU reports every cycle the thread is in radix translation mode (as opposed to HPT mode) ##0000008898 MMU reports every cycle the thread is in radix translation mode (as opposed to HPT mode) #354,u,g,n,n,n,u,PM_XLATE_L2_REQ,The MMU requested a line from L2 for translation. It may be satisfied from L2 and beyond. Includes speculative instructions. Includes instruction, prefetch and demand. ##000000809C The MMU requested a line from L2 for translation. It may be satisfied from L2 and beyond. Includes speculative instructions. Includes instruction, prefetch and demand. #355,u,g,n,n,n,u,PM_RDXTLB_ANY_NSTD_ANY_HST_HIT,Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup. If this event increments, one and only one of the following must also increment: PM_RDXTLB_ANY_NSTD_64K_HST_HIT, PM_RDXTLB_ANY_NSTD_2M_HST_HIT, or PM_RDXTLB_ANY_NSTD_1G_HST_HIT ##00000080A0 Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup. If this event increments, one and only one of the following must also increment: PM_RDXTLB_ANY_NSTD_64K_HST_HIT, PM_RDXTLB_ANY_NSTD_2M_HST_HIT, or PM_RDXTLB_ANY_NSTD_1G_HST_HIT #356,u,g,n,n,n,u,PM_RDXTLB_ANY_NSTD_4K_HST_HIT,Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup w/ the 4K page size. Due to P10 microarchitecture, this event will never increment. ##00000088A0 Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup w/ the 4K page size. Due to P10 microarchitecture, this event will never increment. #357,u,g,n,n,n,u,PM_RDXTLB_ANY_NSTD_64K_HST_HIT,Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup w/ the 64K page size. ##00000080A4 Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup w/ the 64K page size. #358,u,g,n,n,n,u,PM_RDXTLB_ANY_NSTD_2M_HST_HIT,Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup w/ the 2M page size. ##00000088A4 Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup w/ the 2M page size. #359,u,g,n,n,n,u,PM_RDXTLB_ANY_NSTD_1G_HST_HIT,Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup w/ the 1G page size. ##00000080A8 Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup w/ the 1G page size. #360,u,g,n,n,n,u,PM_RDXTLB_ANY_NSTD_ACC,Qualified as nested radix translations. There was a TLB lookup for any nested radix partition scoped translation. ##00000088A8 Qualified as nested radix translations. There was a TLB lookup for any nested radix partition scoped translation. #361,u,g,n,n,n,u,PM_RDXTLB_ANY_NSTD_MISS,Qualified as nested radix translations. There was a complete TLB miss on any intermediate TLB lookup. ##00000080AC Qualified as nested radix translations. There was a complete TLB miss on any intermediate TLB lookup. #362,u,g,n,n,n,u,PM_SNOOP_TLBIE_ARB_CYC,Cycles the MMU is in the process of arbitrating an incoming TLBIE snoop, but the snoop has not yet acquired the MML lock. ##0000009080 Cycles the MMU is in the process of arbitrating an incoming TLBIE snoop, but the snoop has not yet acquired the MML lock. #363,u,g,n,n,n,u,PM_SNOOP_TLBIE_TLB_INV_CYC,Cycles the MMU is in the process of walking the TLB for a TLBIE. From the time the probe is installed to the time the probe is uninstalled. ##0000009880 Cycles the MMU is in the process of walking the TLB for a TLBIE. From the time the probe is installed to the time the probe is uninstalled. #364,u,g,n,n,n,u,PM_SNOOP_TLBIE_NOT_MY_LPAR_CONTEXT_TABLE_HIT_CYC,Total duration of the snoop TLBIE when there is a context table hit, but a not-my-lpar (LSU is counting my-lpar case). ##0000009084 Total duration of the snoop TLBIE when there is a context table hit, but a not-my-lpar (LSU is counting my-lpar case). #365,u,g,n,n,n,u,PM_SNOOP_TLBIE_NOT_MY_LPAR_CONTEXT_TABLE_MISS_CYC,Total duration of the snoop TLBIE when there is a context table miss. ##0000009884 Total duration of the snoop TLBIE when there is a context table miss. #366,u,g,n,n,n,u,PM_SNOOP_TLBIE,Total number of TLBIE snoops ##0000009088 Total number of TLBIE snoops #367,u,g,n,n,n,u,PM_DTLB_ACCESS_ERAT_MISS,The TLB was read to satisfy a load or store ERAT miss. This includes demands and L1 prefetching data(MMU type LD, ST, L1PF) ##000000908C The TLB was read to satisfy a load or store ERAT miss. This includes demands and L1 prefetching data(MMU type LD, ST, L1PF) #368,u,g,n,n,n,u,PM_ITLB_ACCESS_ERAT_MISS,The TLB was read to satisfy an instruction ERAT miss. This includes demands and L1 prefetching for instruction (MMU Type Fetch) ##000000988C The TLB was read to satisfy an instruction ERAT miss. This includes demands and L1 prefetching for instruction (MMU Type Fetch) #369,u,g,n,n,n,u,PM_HPTWALK_INSTR_CYC,Cycles when an instruction tablewalk is active. This is qualified for HPT translations. ##0000009090 Cycles when an instruction tablewalk is active. This is qualified for HPT translations. #370,u,g,n,n,n,u,PM_HPTWALK_DATA_CYC,Data Tablewalk Cycles. Cycles in which at least one tablewalk is in progress. This event includes data and instruction, demand and prefetch. There can be up to 4 tablewalks in one cycle. (MMU Type LD, ST, L1PF) ##0000009890 Data Tablewalk Cycles. Cycles in which at least one tablewalk is in progress. This event includes data and instruction, demand and prefetch. There can be up to 4 tablewalks in one cycle. (MMU Type LD, ST, L1PF) #371,u,g,n,n,n,u,PM_REJ_PROBE_MATCH_PRS0,A load/store, fetch, or prefetch was rejected because it matched on a partition scoped probe. This is set for both Radix and HPT ##0000009094 A load/store, fetch, or prefetch was rejected because it matched on a partition scoped probe. This is set for both Radix and HPT #372,u,g,n,n,n,u,PM_REJ_PROBE_MATCH_PRS1,A load/store, fetch, or prefetch was rejected because it matched on a process scoped probe. This is Radix only ##0000009894 A load/store, fetch, or prefetch was rejected because it matched on a process scoped probe. This is Radix only #373,u,g,n,n,n,u,PM_REJ_PROBE_MATCH_MML,A load/store, fetch, or prefetch was rejected because it matched on the MML lock. This is set for both Radix and HPT ##0000009098 A load/store, fetch, or prefetch was rejected because it matched on the MML lock. This is set for both Radix and HPT #374,u,g,n,n,n,u,PM_REJ_PIPE_COLLISION_2ND_RELOAD,A load/store or fetch was rejected because there was a collision in the MMU pipeline with a 2nd pass & a reload. ##0000009898 A load/store or fetch was rejected because there was a collision in the MMU pipeline with a 2nd pass & a reload. #375,u,g,n,n,n,u,PM_REJ_XMQ_FULL,A translation was rejected because the MMU was full. ##000000909C A translation was rejected because the MMU was full. #376,u,g,n,n,n,u,PM_BLOCK_ERAT_WRITE,A valid translation reloaded the ERAT with block write enabled. ##000000989C A valid translation reloaded the ERAT with block write enabled. #377,u,g,n,n,n,u,PM_2ND_PASS_RADIX,The 2nd pass for Radix was initiated. ##00000090A0 The 2nd pass for Radix was initiated. #378,u,g,n,n,n,u,PM_2ND_PASS_HPT,The 2nd pass for HPT was initiated. This doesn't include VA hash mispredicts. ##00000098A0 The 2nd pass for HPT was initiated. This doesn't include VA hash mispredicts. #379,u,g,n,n,n,u,PM_VA_HASH_MPRED,The 1st pass for HPT was rejected due to VA hash mispredicts. ##00000090A4 The 1st pass for HPT was rejected due to VA hash mispredicts. #380,u,g,n,n,n,u,PM_CHILD_PURGE_HIT,Total amount of congruence classes that found at least 1 invalidation match for a child purge. ##000000A080 Total amount of congruence classes that found at least 1 invalidation match for a child purge. #381,u,g,n,n,n,u,PM_TLBIE_INV_CC_PRS0_COMPOSITE_CHILD_HASH,Congruence classes that found at least 1 invalidation match for a partition scoped hash match. ##000000A084 Congruence classes that found at least 1 invalidation match for a partition scoped hash match. #382,u,g,n,n,n,u,PM_TLBIE_INV_CC_PRS0_COMPOSITE_PARENT_HASH,Congruence classes that found at least 1 invalidation match for a partition scoped parent hash match. ##000000A884 Congruence classes that found at least 1 invalidation match for a partition scoped parent hash match. #383,u,g,n,n,n,u,PM_TLBIE_INV_ATTEMPT_CC_PRS0_COMPOSITE_CHILD,A partition scoped child hash invalidation was sent to the TLB. ##000000A088 A partition scoped child hash invalidation was sent to the TLB. #384,u,g,n,n,n,u,PM_TLBIE_INV_ATTEMPT_CC_PRS0_COMPOSITE_PARENT,A partition scoped parent hash invalidation was sent to the TLB. ##000000A888 A partition scoped parent hash invalidation was sent to the TLB. #385,u,g,n,n,n,u,PM_TLBIE_INV_ATTEMPT_HPT_PRECISE,Precise TLBIES sent to TLB in HPT. ##000000A08C Precise TLBIES sent to TLB in HPT. #386,u,g,n,n,n,u,PM_TLBIE_INV_CC_HPT_PRECISE,Precise TLBIEs sent to TLB for HPT invalidations and had at least 1 matching entry in the congruence class. ##000000A88C Precise TLBIEs sent to TLB for HPT invalidations and had at least 1 matching entry in the congruence class. #387,u,g,n,n,n,u,PM_CASE_A_HIT_MTPID,mtpid instruction found a Case A Context Table Hit. ##000000A090 mtpid instruction found a Case A Context Table Hit. #388,u,g,n,n,n,u,PM_CASE_A_HIT_MTLPID,mtlpid instruction found a Case A Context Table Hit. ##000000A890 mtlpid instruction found a Case A Context Table Hit. #389,u,g,n,n,n,u,PM_CASE_B_HIT_MTLPID,A mtlpid instruction found a Case B Context table hit. ##000000A094 A mtlpid instruction found a Case B Context table hit. #390,u,g,n,n,n,u,PM_CASE_C_HIT_MTPID,A mtpid instruction found a Case C Context table hit. ##000000A894 A mtpid instruction found a Case C Context table hit. #391,u,g,n,n,n,u,PM_CASE_A_MISS_MTPID,A mtpid instruction found a Case A context table miss ##000000A098 A mtpid instruction found a Case A context table miss #392,u,g,n,n,n,u,PM_CASE_A_MISS_MTLPID,A mtlpid instruction found a Case A Context table miss ##000000A898 A mtlpid instruction found a Case A Context table miss #393,u,g,n,n,n,u,PM_CASE_B_MISS_MTLPID,A mtlpid instruction found a Case B Context table miss ##000000A09C A mtlpid instruction found a Case B Context table miss #394,u,g,n,n,n,u,PM_CASE_C_MISS_MTPID,A mtpid instruction found a Case C Context table miss. ##000000A89C A mtpid instruction found a Case C Context table miss. #395,u,g,n,n,n,u,PM_MTPID,The thread executed a mtpid instruction. ##000000A0A0 The thread executed a mtpid instruction. #396,u,g,n,n,n,u,PM_MTLPID,The thread executed a mtlpid instruction. ##000000A8A0 The thread executed a mtlpid instruction. #397,u,g,n,n,n,u,PM_CASE_A_SNOOP_TLBIE_HIT,A snoop hit on a Case A context tag. ##000000A0A4 A snoop hit on a Case A context tag. #398,u,g,n,n,n,u,PM_CASE_B_SNOOP_TLBIE_HIT,A snoop hit on a Case B Context tag. ##000000A8A4 A snoop hit on a Case B Context tag. #399,u,g,n,n,n,u,PM_CASE_C_SNOOP_TLBIE_HIT,A snoop hit on a Case C context tag. ##000000A0A8 A snoop hit on a Case C context tag. #400,u,g,n,n,n,u,PM_CASE_D_SNOOP_TLBIE_HIT,A snoop hit on a Case D context tag. ##000000A8A8 A snoop hit on a Case D context tag. #401,u,g,n,n,n,u,PM_SNOOP_TLBIE_NOT_MY_LPAR_CONTEXT_TABLE_HIT,A snoop found a not-my-lpar but found a context table hit. ##000000A0AC A snoop found a not-my-lpar but found a context table hit. #402,u,g,n,n,n,u,PM_SNOOP_TLBIE_NOT_MY_LPAR_CONTEXT_TABLE_MISS,A snoop found a not-my-lpar but found a context table miss. ##000000A8AC A snoop found a not-my-lpar but found a context table miss. #403,u,g,n,n,n,u,PM_LPAR_SNOOP_HIT,A snoop found a "my-lpar" match. ##000000A0B0 A snoop found a "my-lpar" match. #404,u,g,n,n,n,u,PM_L3_PF_ON_CHIP_MEM,L3 PF from on-chip memory. L3PF successfully read data and that data came from an on-chip memory. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##100000046080 L3 PF from on-chip memory. L3PF successfully read data and that data came from an on-chip memory. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #405,u,g,n,n,n,u,PM_L3_PF_OFF_CHIP_MEM,L3 PF from off-chip memory. L3PF successfully read data and that data came from off-chip memory. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##100000046880 L3 PF from off-chip memory. L3PF successfully read data and that data came from off-chip memory. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #406,u,g,n,n,n,u,PM_L3_LAT_CI_HIT,L3 Lateral Castins Hit. L3 inserted a line due to an incoming LCO and the line was already in the L3 (a "hit"). PM_L3_CI_HIT also increments when this does. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##110000046080 L3 Lateral Castins Hit. L3 inserted a line due to an incoming LCO and the line was already in the L3 (a "hit"). PM_L3_CI_HIT also increments when this does. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #407,u,g,n,n,n,u,PM_L3_LAT_CI_MISS,L3 Lateral Castins Miss. L3 inserted a line due to an incoming LCO and the line was new to the L3 (a "miss"). PM_L3_CI_MISS also increments when this does. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##110000046880 L3 Lateral Castins Miss. L3 inserted a line due to an incoming LCO and the line was new to the L3 (a "miss"). PM_L3_CI_MISS also increments when this does. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #408,u,g,n,n,n,u,PM_L3_TRANS_PF,L3 Transient prefetch received from L2. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##120000046880 L3 Transient prefetch received from L2. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #409,u,g,n,n,n,u,PM_RD_FORMING_SC,Doesn't occur. Deprecated. ##130000046080 Doesn't occur. Deprecated. #410,u,g,n,n,n,u,PM_RD_CLEARING_SC,Core TM load hits line in L3 in TM_SC state and causes it to be invalidated. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##130000046880 Core TM load hits line in L3 in TM_SC state and causes it to be invalidated. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #411,u,g,n,n,n,u,PM_SN_HIT,Snoop of L3 on Any port hits L3. Lossy - increments only once for all such snoops that occur on the same cycle. Up to 4 can happen in a cycle but only one increment occurs.Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##140000046080 Snoop of L3 on Any port hits L3. Lossy - increments only once for all such snoops that occur on the same cycle. Up to 4 can happen in a cycle but only one increment occurs.Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #412,u,g,n,n,n,u,PM_SN_MISS,Snoop of L3 on any port either misses L3 or collides with a machine working on the line. Lossy - increments only once for all such snoops that occur on the same cycle. Up to 4 can happen in a cycle but only one increment occurs.Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##140000046880 Snoop of L3 on any port either misses L3 or collides with a machine working on the line. Lossy - increments only once for all such snoops that occur on the same cycle. Up to 4 can happen in a cycle but only one increment occurs.Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #413,u,g,n,n,n,u,PM_L3_P0_CO_L31,L3 CO to L3.1 (LCO) from L3 CO machine 0-7. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##150000046080 L3 CO to L3.1 (LCO) from L3 CO machine 0-7. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #414,u,g,n,n,n,u,PM_L3_P1_CO_L31,L3 CO to L3.1 (LCO) from L3 CO machine 8-15. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##150000046880 L3 CO to L3.1 (LCO) from L3 CO machine 8-15. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #415,u,g,n,n,n,u,PM_L3_SN0_BUSY,Lifetime, sample of snooper machine 0 valid. Increments when L3 snoop machine 0 is valid. Can increment on the same clock as PM_L3_SN_USAGE. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##160000046080 Lifetime, sample of snooper machine 0 valid. Increments when L3 snoop machine 0 is valid. Can increment on the same clock as PM_L3_SN_USAGE. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #416,u,g,n,n,n,u,PM_L3_CO0_BUSY,Lifetime, sample of CO machine 0 valid. Increments when L3 CO machine 0 is valid. Can increment on the same clock as PM_L3_CI_USAGE. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##160000046880 Lifetime, sample of CO machine 0 valid. Increments when L3 CO machine 0 is valid. Can increment on the same clock as PM_L3_CI_USAGE. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #417,u,g,n,n,n,u,PM_L3_P2_CO_RTY,L3 CO received retry on fabric CRESP port 2 (memory only), every retry counted. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##170000046080 L3 CO received retry on fabric CRESP port 2 (memory only), every retry counted. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #418,u,g,n,n,n,u,PM_L3_P3_CO_RTY,L3 CO received retry on fabric CRESP port 3 (memory only), every retry counted. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##170000046880 L3 CO received retry on fabric CRESP port 3 (memory only), every retry counted. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #419,u,g,n,n,n,u,PM_L3_SYS_GUESS_WRONG,L3 Prefetch scope predictor selected VGS or RNS, but was wrong. Increments when data received for L3 PF machine 0 or 24. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##190000046080 L3 Prefetch scope predictor selected VGS or RNS, but was wrong. Increments when data received for L3 PF machine 0 or 24. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #420,u,g,n,n,n,u,PM_L3_PF0_BUSY,Lifetime, sample of L3 PF machine 0 busy. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##1A0000046080 Lifetime, sample of L3 PF machine 0 busy. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #421,u,g,n,n,n,u,PM_L3_RD0_BUSY,Lifetime, sample of L3 RD machine 0 busy. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##1A0000046880 Lifetime, sample of L3 RD machine 0 busy. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #422,u,g,n,n,n,u,PM_L3_PF_CPRED_DUALMCDATA,L3 prefetch request predicted dual MC data and LPC responded (good prediction). Lossy - increments only once when multiple L3PF's receive CRESP=good simultaneously, thus may undercount. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##1B0000046080 L3 prefetch request predicted dual MC data and LPC responded (good prediction). Lossy - increments only once when multiple L3PF's receive CRESP=good simultaneously, thus may undercount. Since the event happens in the 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #423,u,g,n,n,n,u,PM_L2_ST,All successful D-side store dispatches for this thread (L2 miss + L2 hits). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##010000046080 All successful D-side store dispatches for this thread (L2 miss + L2 hits). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #424,u,g,n,n,n,u,PM_L2_INST_MISS,All successful instruction (demand and prefetch) dispatches for this thread that missed in the L2. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##0F0000046080 All successful instruction (demand and prefetch) dispatches for this thread that missed in the L2. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #425,u,g,n,n,n,u,PM_L2_ALL_MISS,All successful instruction and data load and store (demand and prefetch) dispatches for this thread that missed in the L2. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##000000046080 All successful instruction and data load and store (demand and prefetch) dispatches for this thread that missed in the L2. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #426,u,g,n,n,n,u,PM_L2_ISIDE_MRU_TOUCH,I-side L2 MRU touch commands sent to the L2 for this thread. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##000000046880 I-side L2 MRU touch commands sent to the L2 for this thread. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #427,u,g,n,n,n,u,PM_L2_ST_HIT,All successful D-side store dispatches for this thread that were L2 hits. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##010000046880 All successful D-side store dispatches for this thread that were L2 hits. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #428,u,g,n,n,n,u,PM_L2_ST_DISP_FAIL_OTHER,All D-side store dispatch attempts for this thread that failed due to reason other than address collision (e.g. Read-Claim/Snoop machine not available). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##020000046080 All D-side store dispatch attempts for this thread that failed due to reason other than address collision (e.g. Read-Claim/Snoop machine not available). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #429,u,g,n,n,n,u,PM_L2_SN_M_WR_DONE,SNP dispatched for a write and was M (true M) ##030000046880 SNP dispatched for a write and was M (true M) #430,u,g,n,n,n,u,PM_L2_SN_M_RD_DONE,Snoop dispatched for a read and was M (true M). Since the event is time-sliced across all 4 threads, the event count should be multiplied by 4. ##030000046080 Snoop dispatched for a read and was M (true M). Since the event is time-sliced across all 4 threads, the event count should be multiplied by 4. #431,u,g,n,n,n,u,PM_L2_CHIP_PUMP,RC requests that were local (LNS, aka chip) pump attempts. Since the event is time-sliced across all 4 threads, the event count should be multiplied by 4. ##040000046080 RC requests that were local (LNS, aka chip) pump attempts. Since the event is time-sliced across all 4 threads, the event count should be multiplied by 4. #432,u,g,n,n,n,u,PM_L2_GROUP_PUMP,RC requests that were on group (GS or NNS, aka nodal) pump attempts. Since the event is time-sliced across all 4 threads, the event count should be multiplied by 4. ##040000046880 RC requests that were on group (GS or NNS, aka nodal) pump attempts. Since the event is time-sliced across all 4 threads, the event count should be multiplied by 4. #433,u,g,n,n,n,u,PM_L2_RTY_ST,RC retries on Power Bus for any store from core (excludes DCBFs). Since the event is time-sliced across all 4 threads, the event count should be multiplied by 4. ##0F0000046880 RC retries on Power Bus for any store from core (excludes DCBFs). Since the event is time-sliced across all 4 threads, the event count should be multiplied by 4. #434,u,g,n,n,n,u,PM_L2_ST_GATHER_ALL,Total number of store operations that gathered that can include (st, stqw) Note: stcx, stcxfk, stcxfnk, dcbz won’t ever gather). This signal can then be used in conjunction with PM_L2_ST_ALL to calculate the number of store operations that were gathered. Since the event is time-sliced across all 4 threads, the event count should be multiplied by 4. ##050000046080 Total number of store operations that gathered that can include (st, stqw) Note: stcx, stcxfk, stcxfnk, dcbz won’t ever gather). This signal can then be used in conjunction with PM_L2_ST_ALL to calculate the number of store operations that were gathered. Since the event is time-sliced across all 4 threads, the event count should be multiplied by 4. #435,u,g,n,n,n,u,PM_L2_SYS_PUMP,RC requests that were system pump attempts. Since the event is time-sliced across all 4 threads, the event count should be multiplied by 4. ##050000046880 RC requests that were system pump attempts. Since the event is time-sliced across all 4 threads, the event count should be multiplied by 4. #436,u,g,n,n,n,u,PM_L2_CO0_BUSY,CO mach 0 Busy. Used by PMU to sample ave CO lifetime (mach0 used as sample point). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##060000046080 CO mach 0 Busy. Used by PMU to sample ave CO lifetime (mach0 used as sample point). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #437,u,g,n,n,n,u,PM_TM_FOOTPR_OVERFLOW,TM Footprint Capacity Overflow. Includes load and store, due to capacity CO or full TMDIR/LVDIR. Event count should be multiplied by 2 since the data is coming from a 2:1 clock domain and the data is time sliced across all 4 threads. ##070000046080 TM Footprint Capacity Overflow. Includes load and store, due to capacity CO or full TMDIR/LVDIR. Event count should be multiplied by 2 since the data is coming from a 2:1 clock domain and the data is time sliced across all 4 threads. #438,u,g,n,n,n,u,PM_DUALMCDATA_REQ_USE_INTV_DATA,The L2 RC machine made a dualmcdata request to the PowerBus and the RC was sent both intervention data (which it used) and LPC data. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##080000046080 The L2 RC machine made a dualmcdata request to the PowerBus and the RC was sent both intervention data (which it used) and LPC data. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #439,u,g,n,n,n,u,PM_L2_CO_CACHE_READ,CO cache read request. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##090000046080 CO cache read request. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #440,u,g,n,n,n,u,PM_L2_TM_FOOTPR_OVERFLOW_ST_MULTI,Multiple TM threads were running and Store footprint was lost due to capacity Cast Out or full TMDIR/LVDIR. Event count should be multiplied by 2 since the data is coming from a 2:1 clock domain and the data is time sliced across all 4 threads. ##0A0000046080 Multiple TM threads were running and Store footprint was lost due to capacity Cast Out or full TMDIR/LVDIR. Event count should be multiplied by 2 since the data is coming from a 2:1 clock domain and the data is time sliced across all 4 threads. #441,u,g,n,n,n,u,PM_ST_DATA_FROM_DL2L3,Store data line missed in the local chiplet and was found in a different group's L2 or L3 (off-group L2/L3 intervention). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##0C0000046080 Store data line missed in the local chiplet and was found in a different group's L2 or L3 (off-group L2/L3 intervention). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #442,u,g,n,n,n,u,PM_ST_DATA_FROM_DMEM,Store data line missed in the local chiplet and was found in distant memory (off group). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. ##0C0000046880 Store data line missed in the local chiplet and was found in distant memory (off group). Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2. #443,u,g,n,n,n,u,PM_DATA_RADIX_PROCESS_L2_PTE_FROM_DISTANT,A data Page Table Entry was reloaded to a level 2 page walk cache from distant memory due to a process scoped demand miss. ##00000000004424A A data Page Table Entry was reloaded to a level 2 page walk cache from distant memory due to a process scoped demand miss. #444,u,g,n,n,n,u,PM_DATA_RADIX_PROCESS_L2_PDE_FROM_DISTANT,A data Page Directory Entry was reloaded to a level 2 page walk cache from distant memory due to a process scoped demand miss. ##00000000004424C A data Page Directory Entry was reloaded to a level 2 page walk cache from distant memory due to a process scoped demand miss. #445,u,g,n,n,n,u,PM_DATA_RADIX_PROCESS_L3_PTE_FROM_DISTANT,A data Page Table Entry was reloaded to a level 3 page walk cache from distant memory due to a process scoped demand miss. ##00000000004424E A data Page Table Entry was reloaded to a level 3 page walk cache from distant memory due to a process scoped demand miss. #446,u,g,n,n,n,u,PM_DATA_RADIX_PROCESS_L3_PDE_FROM_DISTANT,A data Page Directory Entry was reloaded to a level 3 page walk cache from distant memory due to a process scoped demand miss. ##000000000045240 A data Page Directory Entry was reloaded to a level 3 page walk cache from distant memory due to a process scoped demand miss. #447,u,g,n,n,n,u,PM_DATA_RADIX_PROCESS_L4_PTE_FROM_DISTANT,A data Page Table Entry was reloaded to a level 4 page walk cache from distant memory due to a process scoped demand miss. ##000000000045242 A data Page Table Entry was reloaded to a level 4 page walk cache from distant memory due to a process scoped demand miss. #448,u,g,n,n,n,u,PM_INST_RADIX_PROCESS_L2_PTE_FROM_DISTANT,An instruction Page Table Entry was reloaded to a level 2 page walk cache from distant memory due to a process scoped demand miss. ##000000000045246 An instruction Page Table Entry was reloaded to a level 2 page walk cache from distant memory due to a process scoped demand miss. #449,u,g,n,n,n,u,PM_INST_RADIX_PROCESS_L3_PTE_FROM_DISTANT,An instruction Page Table Entry was reloaded to a level 3 page walk cache from distant memory due to a process scoped demand miss. ##00000000004524A An instruction Page Table Entry was reloaded to a level 3 page walk cache from distant memory due to a process scoped demand miss. #450,u,g,n,n,n,u,PM_INST_RADIX_PROCESS_L3_PDE_FROM_DISTANT,An instruction Page Directory Entry was reloaded to a level 3 page walk cache from distant memory due to a process scoped demand miss. ##00000000004524C An instruction Page Directory Entry was reloaded to a level 3 page walk cache from distant memory due to a process scoped demand miss. #451,u,g,n,n,n,u,PM_INST_RADIX_PROCESS_L4_PTE_FROM_DISTANT,An instruction Page Table Entry was reloaded to a level 4 page walk cache from distant memory due to a process scoped demand miss. ##00000000004524E An instruction Page Table Entry was reloaded to a level 4 page walk cache from distant memory due to a process scoped demand miss. #452,u,g,n,n,n,u,PM_DATA_RADIX_PROCESS_L2_PTE_FROM_DISTANT_ALL,A data Page Table Entry was reloaded to a level 2 page walk cache from distant memory due to a process scoped demand or prefetch miss. ##00000000024424A A data Page Table Entry was reloaded to a level 2 page walk cache from distant memory due to a process scoped demand or prefetch miss. #453,u,g,n,n,n,u,PM_DATA_RADIX_PROCESS_L2_PDE_FROM_DISTANT_ALL,A data Page Directory Entry was reloaded to a level 2 page walk cache from distant memory due to a process scoped demand or prefetch miss. ##00000000024424C A data Page Directory Entry was reloaded to a level 2 page walk cache from distant memory due to a process scoped demand or prefetch miss. #454,u,g,n,n,n,u,PM_DATA_RADIX_PROCESS_L3_PTE_FROM_DISTANT_ALL,A data Page Table Entry was reloaded to a level 3 page walk cache from distant memory due to a process scoped demand or prefetch miss. ##00000000024424E A data Page Table Entry was reloaded to a level 3 page walk cache from distant memory due to a process scoped demand or prefetch miss. #455,u,g,n,n,n,u,PM_DATA_RADIX_PROCESS_L3_PDE_FROM_DISTANT_ALL,A data Page Directory Entry was reloaded to a level 3 page walk cache from distant memory due to a process scoped demand or prefetch miss. ##000000000245240 A data Page Directory Entry was reloaded to a level 3 page walk cache from distant memory due to a process scoped demand or prefetch miss. #456,u,g,n,n,n,u,PM_DATA_RADIX_PROCESS_L4_PTE_FROM_DISTANT_ALL,A data Page Table Entry was reloaded to a level 4 page walk cache from distant memory due to a process scoped demand or prefetch miss. ##000000000245242 A data Page Table Entry was reloaded to a level 4 page walk cache from distant memory due to a process scoped demand or prefetch miss. #457,u,g,n,n,n,u,PM_INST_RADIX_PROCESS_L2_PTE_FROM_DISTANT_ALL,An instruction Page Table Entry was reloaded to a level 2 page walk cache from distant memory due to a process scoped demand or prefetch miss. ##000000000145246 An instruction Page Table Entry was reloaded to a level 2 page walk cache from distant memory due to a process scoped demand or prefetch miss. #458,u,g,n,n,n,u,PM_INST_RADIX_PROCESS_L3_PTE_FROM_DISTANT_ALL,An instruction Page Table Entry was reloaded to a level 3 page walk cache from distant memory due to a process scoped demand or prefetch miss. ##00000000014524A An instruction Page Table Entry was reloaded to a level 3 page walk cache from distant memory due to a process scoped demand or prefetch miss. #459,u,g,n,n,n,u,PM_INST_RADIX_PROCESS_L3_PDE_FROM_DISTANT_ALL,An instruction Page Directory Entry was reloaded to a level 3 page walk cache from distant memory due to a process scoped demand or prefetch miss. ##00000000014524C An instruction Page Directory Entry was reloaded to a level 3 page walk cache from distant memory due to a process scoped demand or prefetch miss. #460,u,g,n,n,n,u,PM_INST_RADIX_PROCESS_L4_PTE_FROM_DISTANT_ALL,An instruction Page Table Entry was reloaded to a level 4 page walk cache from distant memory due to a process scoped demand or prefetch miss. ##00000000014524E An instruction Page Table Entry was reloaded to a level 4 page walk cache from distant memory due to a process scoped demand or prefetch miss. #461,u,g,n,n,n,u,PM_INST_FROM_L2,The processor's instruction cache was reloaded from the local core's L2 due to a demand miss. ##000300000004C040 The processor's instruction cache was reloaded from the local core's L2 due to a demand miss. #462,u,g,n,n,n,u,PM_IPTEG_FROM_L2,The processor's instruction page table entry was reloaded from the local core's L2 due to a demand miss. ##000320000004C040 The processor's instruction page table entry was reloaded from the local core's L2 due to a demand miss. #463,u,g,n,n,n,u,PM_DATA_FROM_L2,The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss. ##000340000004C040 The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss. #464,u,g,n,n,n,u,PM_DPTEG_FROM_L2,The processor's data page table entry was reloaded from the local core's L2 due to a demand miss. ##000360000004C040 The processor's data page table entry was reloaded from the local core's L2 due to a demand miss. #465,u,g,n,n,n,u,PM_INST_FROM_L2_ALL,The processor's instruction cache was reloaded from the local core's L2 due to a demand miss or prefetch reload. ##000300000014C040 The processor's instruction cache was reloaded from the local core's L2 due to a demand miss or prefetch reload. #466,u,g,n,n,n,u,PM_IPTEG_FROM_L2_ALL,The processor's instruction page table entry was reloaded from the local core's L2 due to a demand miss or prefetch reload. ##000320000014C040 The processor's instruction page table entry was reloaded from the local core's L2 due to a demand miss or prefetch reload. #467,u,g,n,n,n,u,PM_DATA_FROM_L2_ALL,The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss or prefetch reload. ##000340000024C040 The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss or prefetch reload. #468,u,g,n,n,n,u,PM_DPTEG_FROM_L2_ALL,The processor's data page table entry was reloaded from the local core's L2 due to a demand miss or prefetch reload. ##000360000024C040 The processor's data page table entry was reloaded from the local core's L2 due to a demand miss or prefetch reload. #469,u,g,n,n,n,u,PM_INST_FROM_L1MISS,The processor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss. ##003F00000004C040 The processor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss. #470,u,g,n,n,n,u,PM_IPTEG_FROM_L1MISS,The processor's instruction page table entry was reloaded from a source beyond the local core's L1 due to a demand miss. ##003F20000004C040 The processor's instruction page table entry was reloaded from a source beyond the local core's L1 due to a demand miss. #471,u,g,n,n,n,u,PM_DATA_FROM_L1MISS,The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss. ##003F40000004C040 The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss. #472,u,g,n,n,n,u,PM_DPTEG_FROM_L1MISS,The processor's data page table entry was reloaded from a source beyond the local core's L1 due to a demand miss. ##003F60000004C040 The processor's data page table entry was reloaded from a source beyond the local core's L1 due to a demand miss. #473,u,g,n,n,n,u,PM_INST_FROM_L1MISS_ALL,The processor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. ##003F00000014C040 The processor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. #474,u,g,n,n,n,u,PM_IPTEG_FROM_L1MISS_ALL,The processor's instruction page table entry was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. ##003F20000014C040 The processor's instruction page table entry was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. #475,u,g,n,n,n,u,PM_DATA_FROM_L1MISS_ALL,The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. ##003F40000024C040 The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. #476,u,g,n,n,n,u,PM_DPTEG_FROM_L1MISS_ALL,The processor's data page table entry was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. ##003F60000024C040 The processor's data page table entry was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. #477,u,g,n,n,n,u,PM_IPTEG_FROM_L2_NO_CONFLICT,The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. ##000020000004C040 The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. #478,u,g,n,n,n,u,PM_DATA_FROM_L2_NO_CONFLICT,The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. ##000040000004C040 The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. #479,u,g,n,n,n,u,PM_DPTEG_FROM_L2_NO_CONFLICT,The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. ##000060000004C040 The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. #480,u,g,n,n,n,u,PM_IPTEG_FROM_L2_NO_CONFLICT_ALL,The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. ##000020000014C040 The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. #481,u,g,n,n,n,u,PM_DATA_FROM_L2_NO_CONFLICT_ALL,The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. ##000040000024C040 The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. #482,u,g,n,n,n,u,PM_DPTEG_FROM_L2_NO_CONFLICT_ALL,The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. ##000060000024C040 The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. #483,u,g,n,n,n,u,PM_IPTEG_FROM_L2_MEPF,The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. ##004020000004C040 The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. #484,u,g,n,n,n,u,PM_DATA_FROM_L2_MEPF,The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. ##004040000004C040 The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. #485,u,g,n,n,n,u,PM_DPTEG_FROM_L2_MEPF,The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. ##004060000004C040 The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. #486,u,g,n,n,n,u,PM_IPTEG_FROM_L2_MEPF_ALL,The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. ##004020000014C040 The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. #487,u,g,n,n,n,u,PM_DATA_FROM_L2_MEPF_ALL,The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. ##004040000024C040 The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. #488,u,g,n,n,n,u,PM_DPTEG_FROM_L2_MEPF_ALL,The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. ##004060000024C040 The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. #489,u,g,n,n,n,u,PM_IPTEG_FROM_L2_LDHITST_CONFLICT,The processor's instruction page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. ##008020000004C040 The processor's instruction page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. #490,u,g,n,n,n,u,PM_DATA_FROM_L2_LDHITST_CONFLICT,The processor's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. ##008040000004C040 The processor's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. #491,u,g,n,n,n,u,PM_DPTEG_FROM_L2_LDHITST_CONFLICT,The processor's data page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. ##008060000004C040 The processor's data page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. #492,u,g,n,n,n,u,PM_IPTEG_FROM_L2_LDHITST_CONFLICT_ALL,The processor's instruction page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. ##008020000014C040 The processor's instruction page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. #493,u,g,n,n,n,u,PM_DATA_FROM_L2_LDHITST_CONFLICT_ALL,The processor's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. ##008040000024C040 The processor's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. #494,u,g,n,n,n,u,PM_DPTEG_FROM_L2_LDHITST_CONFLICT_ALL,The processor's data page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. ##008060000024C040 The processor's data page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. #495,u,g,n,n,n,u,PM_IPTEG_FROM_L2_OTHER_CONFLICT,The processor's instruction page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. ##00C020000004C040 The processor's instruction page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. #496,u,g,n,n,n,u,PM_DATA_FROM_L2_OTHER_CONFLICT,The processor's L1 data cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. ##00C040000004C040 The processor's L1 data cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. #497,u,g,n,n,n,u,PM_DPTEG_FROM_L2_OTHER_CONFLICT,The processor's data page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. ##00C060000004C040 The processor's data page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. #498,u,g,n,n,n,u,PM_IPTEG_FROM_L2_OTHER_CONFLICT_ALL,The processor's instruction page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. ##00C020000014C040 The processor's instruction page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. #499,u,g,n,n,n,u,PM_DATA_FROM_L2_OTHER_CONFLICT_ALL,The processor's L1 data cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. ##00C040000024C040 The processor's L1 data cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. #500,u,g,n,n,n,u,PM_DPTEG_FROM_L2_OTHER_CONFLICT_ALL,The processor's data page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. ##00C060000024C040 The processor's data page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. #501,u,g,n,n,n,u,PM_INST_FROM_L2MISS,The processor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss. ##000380000004C040 The processor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss. #502,u,g,n,n,n,u,PM_IPTEG_FROM_L2MISS,The processor's instruction page table entry was reloaded from a source beyond the local core's L2 due to a demand miss. ##0003A0000004C040 The processor's instruction page table entry was reloaded from a source beyond the local core's L2 due to a demand miss. #503,u,g,n,n,n,u,PM_DPTEG_FROM_L2MISS,The processor's data page table entry was reloaded from a source beyond the local core's L2 due to a demand miss. ##0003E0000004C040 The processor's data page table entry was reloaded from a source beyond the local core's L2 due to a demand miss. #504,u,g,n,n,n,u,PM_INST_FROM_L2MISS_ALL,The processor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. ##000380000014C040 The processor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. #505,u,g,n,n,n,u,PM_IPTEG_FROM_L2MISS_ALL,The processor's instruction page table entry was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. ##0003A0000014C040 The processor's instruction page table entry was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. #506,u,g,n,n,n,u,PM_DATA_FROM_L2MISS_ALL,The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. ##0003C0000024C040 The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. #507,u,g,n,n,n,u,PM_DPTEG_FROM_L2MISS_ALL,The processor's data page table entry was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. ##0003E0000024C040 The processor's data page table entry was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. #508,u,g,n,n,n,u,PM_INST_FROM_L3,The processor's instruction cache was reloaded from the local core's L3 due to a demand miss. ##010300000004C040 The processor's instruction cache was reloaded from the local core's L3 due to a demand miss. #509,u,g,n,n,n,u,PM_IPTEG_FROM_L3,The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss. ##010320000004C040 The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss. #510,u,g,n,n,n,u,PM_DATA_FROM_L3,The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss. ##010340000004C040 The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss. #511,u,g,n,n,n,u,PM_DPTEG_FROM_L3,The processor's data page table entry was reloaded from the local core's L3 due to a demand miss. ##010360000004C040 The processor's data page table entry was reloaded from the local core's L3 due to a demand miss. #512,u,g,n,n,n,u,PM_INST_FROM_L3_ALL,The processor's instruction cache was reloaded from the local core's L3 due to a demand miss or prefetch reload. ##010300000014C040 The processor's instruction cache was reloaded from the local core's L3 due to a demand miss or prefetch reload. #513,u,g,n,n,n,u,PM_IPTEG_FROM_L3_ALL,The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload. ##010320000014C040 The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload. #514,u,g,n,n,n,u,PM_DATA_FROM_L3_ALL,The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload. ##010340000024C040 The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload. #515,u,g,n,n,n,u,PM_DPTEG_FROM_L3_ALL,The processor's data page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload. ##010360000024C040 The processor's data page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload. #516,u,g,n,n,n,u,PM_IPTEG_FROM_L3_NO_CONFLICT,The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. ##010020000004C040 The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. #517,u,g,n,n,n,u,PM_DATA_FROM_L3_NO_CONFLICT,The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. ##010040000004C040 The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. #518,u,g,n,n,n,u,PM_DPTEG_FROM_L3_NO_CONFLICT,The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. ##010060000004C040 The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. #519,u,g,n,n,n,u,PM_IPTEG_FROM_L3_NO_CONFLICT_ALL,The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. ##010020000014C040 The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. #520,u,g,n,n,n,u,PM_DATA_FROM_L3_NO_CONFLICT_ALL,The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. ##010040000024C040 The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. #521,u,g,n,n,n,u,PM_DPTEG_FROM_L3_NO_CONFLICT_ALL,The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. ##010060000024C040 The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. #522,u,g,n,n,n,u,PM_IPTEG_FROM_L3_MEPF,The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. ##014020000004C040 The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. #523,u,g,n,n,n,u,PM_DATA_FROM_L3_MEPF,The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. ##014040000004C040 The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. #524,u,g,n,n,n,u,PM_DPTEG_FROM_L3_MEPF,The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. ##014060000004C040 The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. #525,u,g,n,n,n,u,PM_IPTEG_FROM_L3_MEPF_ALL,The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. ##014020000014C040 The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. #526,u,g,n,n,n,u,PM_DATA_FROM_L3_MEPF_ALL,The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. ##014040000024C040 The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. #527,u,g,n,n,n,u,PM_DPTEG_FROM_L3_MEPF_ALL,The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. ##014060000024C040 The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. #528,u,g,n,n,n,u,PM_IPTEG_FROM_L3_CONFLICT,The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss. ##01C020000004C040 The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss. #529,u,g,n,n,n,u,PM_DATA_FROM_L3_CONFLICT,The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss. ##01C040000004C040 The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss. #530,u,g,n,n,n,u,PM_DPTEG_FROM_L3_CONFLICT,The processor's data page table entry was reloaded from the local core's L3 due to a demand miss. ##01C060000004C040 The processor's data page table entry was reloaded from the local core's L3 due to a demand miss. #531,u,g,n,n,n,u,PM_IPTEG_FROM_L3_CONFLICT_ALL,The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload. ##01C020000014C040 The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload. #532,u,g,n,n,n,u,PM_DATA_FROM_L3_CONFLICT_ALL,The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload. ##01C040000024C040 The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload. #533,u,g,n,n,n,u,PM_DPTEG_FROM_L3_CONFLICT_ALL,The processor's data page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload. ##01C060000024C040 The processor's data page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload. #534,u,g,n,n,n,u,PM_IPTEG_FROM_L3MISS,The processor's instruction page table entry was reloaded from beyond the local core's L3 due to a demand miss. ##0007A0000004C040 The processor's instruction page table entry was reloaded from beyond the local core's L3 due to a demand miss. #535,u,g,n,n,n,u,PM_DPTEG_FROM_L3MISS,The processor's data page table entry was reloaded from beyond the local core's L3 due to a demand miss. ##0007E0000004C040 The processor's data page table entry was reloaded from beyond the local core's L3 due to a demand miss. #536,u,g,n,n,n,u,PM_INST_FROM_L3MISS_ALL,The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. ##000780000014C040 The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. #537,u,g,n,n,n,u,PM_IPTEG_FROM_L3MISS_ALL,The processor's instruction page table entry was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. ##0007A0000014C040 The processor's instruction page table entry was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. #538,u,g,n,n,n,u,PM_DATA_FROM_L3MISS_ALL,The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. ##0007C0000024C040 The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. #539,u,g,n,n,n,u,PM_DPTEG_FROM_L3MISS_ALL,The processor's data page table entry was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. ##0007E0000024C040 The processor's data page table entry was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. #540,u,g,n,n,n,u,PM_IPTEG_FROM_L21_REGENT_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. ##080020000004C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. #541,u,g,n,n,n,u,PM_DATA_FROM_L21_REGENT_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. ##080040000004C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. #542,u,g,n,n,n,u,PM_DPTEG_FROM_L21_REGENT_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. ##080060000004C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. #543,u,g,n,n,n,u,PM_IPTEG_FROM_L21_REGENT_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. ##080020000014C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. #544,u,g,n,n,n,u,PM_DATA_FROM_L21_REGENT_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. ##080040000024C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. #545,u,g,n,n,n,u,PM_DPTEG_FROM_L21_REGENT_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. ##080060000024C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. #546,u,g,n,n,n,u,PM_IPTEG_FROM_L21_REGENT_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. ##084020000004C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. #547,u,g,n,n,n,u,PM_DATA_FROM_L21_REGENT_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. ##084040000004C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. #548,u,g,n,n,n,u,PM_DPTEG_FROM_L21_REGENT_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. ##084060000004C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. #549,u,g,n,n,n,u,PM_IPTEG_FROM_L21_REGENT_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. ##084020000014C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. #550,u,g,n,n,n,u,PM_DATA_FROM_L21_REGENT_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. ##084040000024C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. #551,u,g,n,n,n,u,PM_DPTEG_FROM_L21_REGENT_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. ##084060000024C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. #552,u,g,n,n,n,u,PM_INST_FROM_L21_REGENT,The processor's instruction cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. ##080100000004C040 The processor's instruction cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. #553,u,g,n,n,n,u,PM_IPTEG_FROM_L21_REGENT,The processor's instruction page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. ##080120000004C040 The processor's instruction page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. #554,u,g,n,n,n,u,PM_DATA_FROM_L21_REGENT,The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. ##080140000004C040 The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. #555,u,g,n,n,n,u,PM_DPTEG_FROM_L21_REGENT,The processor's data page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. ##080160000004C040 The processor's data page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. #556,u,g,n,n,n,u,PM_INST_FROM_L21_REGENT_ALL,The processor's instruction cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. ##080100000014C040 The processor's instruction cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. #557,u,g,n,n,n,u,PM_IPTEG_FROM_L21_REGENT_ALL,The processor's instruction page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. ##080120000014C040 The processor's instruction page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. #558,u,g,n,n,n,u,PM_DATA_FROM_L21_REGENT_ALL,The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. ##080140000024C040 The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. #559,u,g,n,n,n,u,PM_DPTEG_FROM_L21_REGENT_ALL,The processor's data page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. ##080160000024C040 The processor's data page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. #560,u,g,n,n,n,u,PM_IPTEG_FROM_L31_REGENT_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. ##088020000004C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. #561,u,g,n,n,n,u,PM_DATA_FROM_L31_REGENT_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. ##088040000004C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. #562,u,g,n,n,n,u,PM_DPTEG_FROM_L31_REGENT_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. ##088060000004C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. #563,u,g,n,n,n,u,PM_IPTEG_FROM_L31_REGENT_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##088020000014C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. #564,u,g,n,n,n,u,PM_DATA_FROM_L31_REGENT_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##088040000024C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. #565,u,g,n,n,n,u,PM_DPTEG_FROM_L31_REGENT_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##088060000024C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. #566,u,g,n,n,n,u,PM_IPTEG_FROM_L31_REGENT_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. ##08C020000004C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. #567,u,g,n,n,n,u,PM_DATA_FROM_L31_REGENT_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. ##08C040000004C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. #568,u,g,n,n,n,u,PM_DPTEG_FROM_L31_REGENT_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. ##08C060000004C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. #569,u,g,n,n,n,u,PM_IPTEG_FROM_L31_REGENT_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##08C020000014C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. #570,u,g,n,n,n,u,PM_DATA_FROM_L31_REGENT_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##08C040000024C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. #571,u,g,n,n,n,u,PM_DPTEG_FROM_L31_REGENT_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##08C060000024C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. #572,u,g,n,n,n,u,PM_INST_FROM_L31_REGENT,The processor's instruction cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. ##088100000004C040 The processor's instruction cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. #573,u,g,n,n,n,u,PM_IPTEG_FROM_L31_REGENT,The processor's instruction page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. ##088120000004C040 The processor's instruction page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. #574,u,g,n,n,n,u,PM_DATA_FROM_L31_REGENT,The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. ##088140000004C040 The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. #575,u,g,n,n,n,u,PM_DPTEG_FROM_L31_REGENT,The processor's data page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. ##088160000004C040 The processor's data page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. #576,u,g,n,n,n,u,PM_INST_FROM_L31_REGENT_ALL,The processor's instruction cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##088100000014C040 The processor's instruction cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. #577,u,g,n,n,n,u,PM_IPTEG_FROM_L31_REGENT_ALL,The processor's instruction page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##088120000014C040 The processor's instruction page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. #578,u,g,n,n,n,u,PM_DATA_FROM_L31_REGENT_ALL,The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##088140000024C040 The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. #579,u,g,n,n,n,u,PM_DPTEG_FROM_L31_REGENT_ALL,The processor's data page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##088160000024C040 The processor's data page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. #580,u,g,n,n,n,u,PM_IPTEG_FROM_REGENT_L2L3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. ##080220000004C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. #581,u,g,n,n,n,u,PM_DATA_FROM_REGENT_L2L3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. ##080240000004C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. #582,u,g,n,n,n,u,PM_DPTEG_FROM_REGENT_L2L3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. ##080260000004C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. #583,u,g,n,n,n,u,PM_IPTEG_FROM_REGENT_L2L3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##080220000014C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. #584,u,g,n,n,n,u,PM_DATA_FROM_REGENT_L2L3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##080240000024C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. #585,u,g,n,n,n,u,PM_DPTEG_FROM_REGENT_L2L3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##080260000024C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. #586,u,g,n,n,n,u,PM_IPTEG_FROM_REGENT_L2L3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. ##084220000004C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. #587,u,g,n,n,n,u,PM_DATA_FROM_REGENT_L2L3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. ##084240000004C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. #588,u,g,n,n,n,u,PM_DPTEG_FROM_REGENT_L2L3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. ##084260000004C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. #589,u,g,n,n,n,u,PM_IPTEG_FROM_REGENT_L2L3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##084220000014C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. #590,u,g,n,n,n,u,PM_DATA_FROM_REGENT_L2L3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##084240000024C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. #591,u,g,n,n,n,u,PM_DPTEG_FROM_REGENT_L2L3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##084260000024C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. #592,u,g,n,n,n,u,PM_INST_FROM_REGENT_L2L3,The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. ##080300000004C040 The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. #593,u,g,n,n,n,u,PM_IPTEG_FROM_REGENT_L2L3,The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. ##080320000004C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. #594,u,g,n,n,n,u,PM_DATA_FROM_REGENT_L2L3,The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. ##080340000004C040 The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. #595,u,g,n,n,n,u,PM_DPTEG_FROM_REGENT_L2L3,The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. ##080360000004C040 The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. #596,u,g,n,n,n,u,PM_INST_FROM_REGENT_L2L3_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##080300000014C040 The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. #597,u,g,n,n,n,u,PM_IPTEG_FROM_REGENT_L2L3_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##080320000014C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. #598,u,g,n,n,n,u,PM_DATA_FROM_REGENT_L2L3_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##080340000024C040 The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. #599,u,g,n,n,n,u,PM_DPTEG_FROM_REGENT_L2L3_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. ##080360000024C040 The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. #600,u,g,n,n,n,u,PM_IPTEG_FROM_L21_NON_REGENT_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. ##0A0020000004C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. #601,u,g,n,n,n,u,PM_DATA_FROM_L21_NON_REGENT_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. ##0A0040000004C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. #602,u,g,n,n,n,u,PM_DPTEG_FROM_L21_NON_REGENT_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. ##0A0060000004C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. #603,u,g,n,n,n,u,PM_IPTEG_FROM_L21_NON_REGENT_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0020000014C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. #604,u,g,n,n,n,u,PM_DATA_FROM_L21_NON_REGENT_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0040000024C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. #605,u,g,n,n,n,u,PM_DPTEG_FROM_L21_NON_REGENT_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0060000024C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. #606,u,g,n,n,n,u,PM_IPTEG_FROM_L21_NON_REGENT_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. ##0A4020000004C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. #607,u,g,n,n,n,u,PM_DATA_FROM_L21_NON_REGENT_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. ##0A4040000004C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. #608,u,g,n,n,n,u,PM_DPTEG_FROM_L21_NON_REGENT_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. ##0A4060000004C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. #609,u,g,n,n,n,u,PM_IPTEG_FROM_L21_NON_REGENT_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A4020000014C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. #610,u,g,n,n,n,u,PM_DATA_FROM_L21_NON_REGENT_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A4040000024C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. #611,u,g,n,n,n,u,PM_DPTEG_FROM_L21_NON_REGENT_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A4060000024C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. #612,u,g,n,n,n,u,PM_INST_FROM_L21_NON_REGENT,The processor's instruction cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. ##0A0100000004C040 The processor's instruction cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. #613,u,g,n,n,n,u,PM_IPTEG_FROM_L21_NON_REGENT,The processor's instruction page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. ##0A0120000004C040 The processor's instruction page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. #614,u,g,n,n,n,u,PM_DATA_FROM_L21_NON_REGENT,The processor's L1 data cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. ##0A0140000004C040 The processor's L1 data cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. #615,u,g,n,n,n,u,PM_DPTEG_FROM_L21_NON_REGENT,The processor's data page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. ##0A0160000004C040 The processor's data page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. #616,u,g,n,n,n,u,PM_INST_FROM_L21_NON_REGENT_ALL,The processor's instruction cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0100000014C040 The processor's instruction cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. #617,u,g,n,n,n,u,PM_IPTEG_FROM_L21_NON_REGENT_ALL,The processor's instruction page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0120000014C040 The processor's instruction page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. #618,u,g,n,n,n,u,PM_DATA_FROM_L21_NON_REGENT_ALL,The processor's L1 data cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0140000024C040 The processor's L1 data cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. #619,u,g,n,n,n,u,PM_DPTEG_FROM_L21_NON_REGENT_ALL,The processor's data page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0160000024C040 The processor's data page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. #620,u,g,n,n,n,u,PM_IPTEG_FROM_L31_NON_REGENT_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. ##0A8020000004C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. #621,u,g,n,n,n,u,PM_DATA_FROM_L31_NON_REGENT_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. ##0A8040000004C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. #622,u,g,n,n,n,u,PM_DPTEG_FROM_L31_NON_REGENT_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. ##0A8060000004C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. #623,u,g,n,n,n,u,PM_IPTEG_FROM_L31_NON_REGENT_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A8020000014C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. #624,u,g,n,n,n,u,PM_DATA_FROM_L31_NON_REGENT_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A8040000024C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. #625,u,g,n,n,n,u,PM_DPTEG_FROM_L31_NON_REGENT_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A8060000024C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. #626,u,g,n,n,n,u,PM_IPTEG_FROM_L31_NON_REGENT_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. ##0AC020000004C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. #627,u,g,n,n,n,u,PM_DATA_FROM_L31_NON_REGENT_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. ##0AC040000004C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. #628,u,g,n,n,n,u,PM_DPTEG_FROM_L31_NON_REGENT_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. ##0AC060000004C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. #629,u,g,n,n,n,u,PM_IPTEG_FROM_L31_NON_REGENT_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0AC020000014C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. #630,u,g,n,n,n,u,PM_DATA_FROM_L31_NON_REGENT_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0AC040000024C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. #631,u,g,n,n,n,u,PM_DPTEG_FROM_L31_NON_REGENT_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0AC060000024C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. #632,u,g,n,n,n,u,PM_INST_FROM_L31_NON_REGENT,The processor's instruction cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. ##0A8100000004C040 The processor's instruction cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. #633,u,g,n,n,n,u,PM_IPTEG_FROM_L31_NON_REGENT,The processor's instruction page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. ##0A8120000004C040 The processor's instruction page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. #634,u,g,n,n,n,u,PM_DATA_FROM_L31_NON_REGENT,The processor's L1 data cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. ##0A8140000004C040 The processor's L1 data cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. #635,u,g,n,n,n,u,PM_DPTEG_FROM_L31_NON_REGENT,The processor's data page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. ##0A8160000004C040 The processor's data page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. #636,u,g,n,n,n,u,PM_INST_FROM_L31_NON_REGENT_ALL,The processor's instruction cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A8100000014C040 The processor's instruction cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. #637,u,g,n,n,n,u,PM_IPTEG_FROM_L31_NON_REGENT_ALL,The processor's instruction page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A8120000014C040 The processor's instruction page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. #638,u,g,n,n,n,u,PM_DATA_FROM_L31_NON_REGENT_ALL,The processor's L1 data cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A8140000024C040 The processor's L1 data cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. #639,u,g,n,n,n,u,PM_DPTEG_FROM_L31_NON_REGENT_ALL,The processor's data page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A8160000024C040 The processor's data page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. #640,u,g,n,n,n,u,PM_IPTEG_FROM_NON_REGENT_L2L3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. ##0A0220000004C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. #641,u,g,n,n,n,u,PM_DATA_FROM_NON_REGENT_L2L3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. ##0A0240000004C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. #642,u,g,n,n,n,u,PM_DPTEG_FROM_NON_REGENT_L2L3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. ##0A0260000004C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. #643,u,g,n,n,n,u,PM_IPTEG_FROM_NON_REGENT_L2L3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0220000014C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. #644,u,g,n,n,n,u,PM_DATA_FROM_NON_REGENT_L2L3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0240000024C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. #645,u,g,n,n,n,u,PM_DPTEG_FROM_NON_REGENT_L2L3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0260000024C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. #646,u,g,n,n,n,u,PM_IPTEG_FROM_NON_REGENT_L2L3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. ##0A4220000004C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. #647,u,g,n,n,n,u,PM_DATA_FROM_NON_REGENT_L2L3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. ##0A4240000004C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. #648,u,g,n,n,n,u,PM_DPTEG_FROM_NON_REGENT_L2L3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. ##0A4260000004C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. #649,u,g,n,n,n,u,PM_IPTEG_FROM_NON_REGENT_L2L3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A4220000014C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. #650,u,g,n,n,n,u,PM_DATA_FROM_NON_REGENT_L2L3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A4240000024C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. #651,u,g,n,n,n,u,PM_DPTEG_FROM_NON_REGENT_L2L3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A4260000024C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. #652,u,g,n,n,n,u,PM_INST_FROM_NON_REGENT_L2L3,The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. ##0A0300000004C040 The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. #653,u,g,n,n,n,u,PM_IPTEG_FROM_NON_REGENT_L2L3,The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. ##0A0320000004C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. #654,u,g,n,n,n,u,PM_DATA_FROM_NON_REGENT_L2L3,The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. ##0A0340000004C040 The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. #655,u,g,n,n,n,u,PM_DPTEG_FROM_NON_REGENT_L2L3,The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. ##0A0360000004C040 The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. #656,u,g,n,n,n,u,PM_INST_FROM_NON_REGENT_L2L3_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0300000014C040 The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. #657,u,g,n,n,n,u,PM_IPTEG_FROM_NON_REGENT_L2L3_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0320000014C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. #658,u,g,n,n,n,u,PM_DATA_FROM_NON_REGENT_L2L3_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0340000024C040 The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. #659,u,g,n,n,n,u,PM_DPTEG_FROM_NON_REGENT_L2L3_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. ##0A0360000024C040 The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. #660,u,g,n,n,n,u,PM_INST_FROM_LMEM,The processor's instruction cache was reloaded from the local chip's memory due to a demand miss. ##094100000004C040 The processor's instruction cache was reloaded from the local chip's memory due to a demand miss. #661,u,g,n,n,n,u,PM_IPTEG_FROM_LMEM,The processor's instruction page table entry was reloaded from the local chip's memory due to a demand miss. ##094020000004C040 The processor's instruction page table entry was reloaded from the local chip's memory due to a demand miss. #662,u,g,n,n,n,u,PM_DATA_FROM_LMEM,The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss. ##094040000004C040 The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss. #663,u,g,n,n,n,u,PM_DPTEG_FROM_LMEM,The processor's data page table entry was reloaded from the local chip's memory due to a demand miss. ##094060000004C040 The processor's data page table entry was reloaded from the local chip's memory due to a demand miss. #664,u,g,n,n,n,u,PM_INST_FROM_LMEM_ALL,The processor's instruction cache was reloaded from the local chip's memory due to a demand miss or prefetch reload. ##094100000014C040 The processor's instruction cache was reloaded from the local chip's memory due to a demand miss or prefetch reload. #665,u,g,n,n,n,u,PM_IPTEG_FROM_LMEM_ALL,The processor's instruction page table entry was reloaded from the local chip's memory due to a demand miss or prefetch reload. ##094020000014C040 The processor's instruction page table entry was reloaded from the local chip's memory due to a demand miss or prefetch reload. #666,u,g,n,n,n,u,PM_DATA_FROM_LMEM_ALL,The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss or prefetch reload. ##094040000024C040 The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss or prefetch reload. #667,u,g,n,n,n,u,PM_DPTEG_FROM_LMEM_ALL,The processor's data page table entry was reloaded from the local chip's memory due to a demand miss or prefetch reload. ##094060000024C040 The processor's data page table entry was reloaded from the local chip's memory due to a demand miss or prefetch reload. #668,u,g,n,n,n,u,PM_IPTEG_FROM_L_OC_CACHE,The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss. ##098020000004C040 The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss. #669,u,g,n,n,n,u,PM_DATA_FROM_L_OC_CACHE,The processor's L1 data cache was reloaded from the local chip's OpenCapp cache due to a demand miss. ##098040000004C040 The processor's L1 data cache was reloaded from the local chip's OpenCapp cache due to a demand miss. #670,u,g,n,n,n,u,PM_DPTEG_FROM_L_OC_CACHE,The processor's data page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss. ##098060000004C040 The processor's data page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss. #671,u,g,n,n,n,u,PM_IPTEG_FROM_L_OC_CACHE_ALL,The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. ##098020000014C040 The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. #672,u,g,n,n,n,u,PM_DATA_FROM_L_OC_CACHE_ALL,The processor's L1 data cache was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. ##098040000024C040 The processor's L1 data cache was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. #673,u,g,n,n,n,u,PM_DPTEG_FROM_L_OC_CACHE_ALL,The processor's data page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. ##098060000024C040 The processor's data page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. #674,u,g,n,n,n,u,PM_IPTEG_FROM_L_OC_MEM,The processor's instruction page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss. ##09C020000004C040 The processor's instruction page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss. #675,u,g,n,n,n,u,PM_DATA_FROM_L_OC_MEM,The processor's L1 data cache was reloaded from the local chip's OpenCapp memory due to a demand miss. ##09C040000004C040 The processor's L1 data cache was reloaded from the local chip's OpenCapp memory due to a demand miss. #676,u,g,n,n,n,u,PM_DPTEG_FROM_L_OC_MEM,The processor's data page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss. ##09C060000004C040 The processor's data page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss. #677,u,g,n,n,n,u,PM_IPTEG_FROM_L_OC_MEM_ALL,The processor's instruction page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. ##09C020000014C040 The processor's instruction page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. #678,u,g,n,n,n,u,PM_DATA_FROM_L_OC_MEM_ALL,The processor's L1 data cache was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. ##09C040000024C040 The processor's L1 data cache was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. #679,u,g,n,n,n,u,PM_DPTEG_FROM_L_OC_MEM_ALL,The processor's data page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. ##09C060000024C040 The processor's data page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. #680,u,g,n,n,n,u,PM_INST_FROM_L_OC_ANY,The processor's instruction cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. ##098100000004C040 The processor's instruction cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. #681,u,g,n,n,n,u,PM_IPTEG_FROM_L_OC_ANY,The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. ##098120000004C040 The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. #682,u,g,n,n,n,u,PM_DATA_FROM_L_OC_ANY,The processor's L1 data cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. ##098140000004C040 The processor's L1 data cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. #683,u,g,n,n,n,u,PM_DPTEG_FROM_L_OC_ANY,The processor's data page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. ##098160000004C040 The processor's data page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. #684,u,g,n,n,n,u,PM_INST_FROM_L_OC_ANY_ALL,The processor's instruction cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##098100000014C040 The processor's instruction cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #685,u,g,n,n,n,u,PM_IPTEG_FROM_L_OC_ANY_ALL,The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##098120000014C040 The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #686,u,g,n,n,n,u,PM_DATA_FROM_L_OC_ANY_ALL,The processor's L1 data cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##098140000024C040 The processor's L1 data cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #687,u,g,n,n,n,u,PM_DPTEG_FROM_L_OC_ANY_ALL,The processor's data page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##098160000024C040 The processor's data page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #688,u,g,n,n,n,u,PM_IPTEG_FROM_RL2_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. ##0C0020000004C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. #689,u,g,n,n,n,u,PM_DATA_FROM_RL2_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. ##0C0040000004C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. #690,u,g,n,n,n,u,PM_DPTEG_FROM_RL2_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. ##0C0060000004C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. #691,u,g,n,n,n,u,PM_IPTEG_FROM_RL2_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. ##0C0020000014C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. #692,u,g,n,n,n,u,PM_DATA_FROM_RL2_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. ##0C0040000024C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. #693,u,g,n,n,n,u,PM_DPTEG_FROM_RL2_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. ##0C0060000024C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. #694,u,g,n,n,n,u,PM_IPTEG_FROM_RL2_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. ##0C4020000004C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. #695,u,g,n,n,n,u,PM_DATA_FROM_RL2_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. ##0C4040000004C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. #696,u,g,n,n,n,u,PM_DPTEG_FROM_RL2_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. ##0C4060000004C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. #697,u,g,n,n,n,u,PM_IPTEG_FROM_RL2_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. ##0C4020000014C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. #698,u,g,n,n,n,u,PM_DATA_FROM_RL2_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. ##0C4040000024C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. #699,u,g,n,n,n,u,PM_DPTEG_FROM_RL2_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. ##0C4060000024C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. #700,u,g,n,n,n,u,PM_INST_FROM_RL2,The processor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss. ##0C0100000004C040 The processor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss. #701,u,g,n,n,n,u,PM_IPTEG_FROM_RL2,The processor's instruction page table entry was reloaded from another core's L2 from a remote chip due to a demand miss. ##0C0120000004C040 The processor's instruction page table entry was reloaded from another core's L2 from a remote chip due to a demand miss. #702,u,g,n,n,n,u,PM_DATA_FROM_RL2,The processor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss. ##0C0140000004C040 The processor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss. #703,u,g,n,n,n,u,PM_DPTEG_FROM_RL2,The processor's data page table entry was reloaded from another core's L2 from a remote chip due to a demand miss. ##0C0160000004C040 The processor's data page table entry was reloaded from another core's L2 from a remote chip due to a demand miss. #704,u,g,n,n,n,u,PM_INST_FROM_RL2_ALL,The processor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. ##0C0100000014C040 The processor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. #705,u,g,n,n,n,u,PM_IPTEG_FROM_RL2_ALL,The processor's instruction page table entry was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. ##0C0120000014C040 The processor's instruction page table entry was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. #706,u,g,n,n,n,u,PM_DATA_FROM_RL2_ALL,The processor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. ##0C0140000024C040 The processor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. #707,u,g,n,n,n,u,PM_DPTEG_FROM_RL2_ALL,The processor's data page table entry was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. ##0C0160000024C040 The processor's data page table entry was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. #708,u,g,n,n,n,u,PM_IPTEG_FROM_RL3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. ##0C8020000004C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. #709,u,g,n,n,n,u,PM_DATA_FROM_RL3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. ##0C8040000004C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. #710,u,g,n,n,n,u,PM_DPTEG_FROM_RL3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. ##0C8060000004C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. #711,u,g,n,n,n,u,PM_IPTEG_FROM_RL3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. ##0C8020000014C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. #712,u,g,n,n,n,u,PM_DATA_FROM_RL3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. ##0C8040000024C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. #713,u,g,n,n,n,u,PM_DPTEG_FROM_RL3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. ##0C8060000024C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. #714,u,g,n,n,n,u,PM_IPTEG_FROM_RL3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. ##0CC020000004C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. #715,u,g,n,n,n,u,PM_DATA_FROM_RL3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. ##0CC040000004C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. #716,u,g,n,n,n,u,PM_DPTEG_FROM_RL3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. ##0CC060000004C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. #717,u,g,n,n,n,u,PM_IPTEG_FROM_RL3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. ##0CC020000014C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. #718,u,g,n,n,n,u,PM_DATA_FROM_RL3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. ##0CC040000024C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. #719,u,g,n,n,n,u,PM_DPTEG_FROM_RL3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. ##0CC060000024C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. #720,u,g,n,n,n,u,PM_INST_FROM_RL3,The processor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss. ##0C8100000004C040 The processor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss. #721,u,g,n,n,n,u,PM_IPTEG_FROM_RL3,The processor's instruction page table entry was reloaded from another core's L3 from a remote chip due to a demand miss. ##0C8120000004C040 The processor's instruction page table entry was reloaded from another core's L3 from a remote chip due to a demand miss. #722,u,g,n,n,n,u,PM_DATA_FROM_RL3,The processor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss. ##0C8140000004C040 The processor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss. #723,u,g,n,n,n,u,PM_DPTEG_FROM_RL3,The processor's data page table entry was reloaded from another core's L3 from a remote chip due to a demand miss. ##0C8160000004C040 The processor's data page table entry was reloaded from another core's L3 from a remote chip due to a demand miss. #724,u,g,n,n,n,u,PM_INST_FROM_RL3_ALL,The processor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. ##0C8100000014C040 The processor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. #725,u,g,n,n,n,u,PM_IPTEG_FROM_RL3_ALL,The processor's instruction page table entry was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. ##0C8120000014C040 The processor's instruction page table entry was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. #726,u,g,n,n,n,u,PM_DATA_FROM_RL3_ALL,The processor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. ##0C8140000024C040 The processor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. #727,u,g,n,n,n,u,PM_DPTEG_FROM_RL3_ALL,The processor's data page table entry was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. ##0C8160000024C040 The processor's data page table entry was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. #728,u,g,n,n,n,u,PM_IPTEG_FROM_RL2L3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. ##0C0220000004C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. #729,u,g,n,n,n,u,PM_DATA_FROM_RL2L3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. ##0C0240000004C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. #730,u,g,n,n,n,u,PM_DPTEG_FROM_RL2L3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. ##0C0260000004C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. #731,u,g,n,n,n,u,PM_IPTEG_FROM_RL2L3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. ##0C0220000014C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. #732,u,g,n,n,n,u,PM_DATA_FROM_RL2L3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. ##0C0240000024C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. #733,u,g,n,n,n,u,PM_DPTEG_FROM_RL2L3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. ##0C0260000024C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. #734,u,g,n,n,n,u,PM_IPTEG_FROM_RL2L3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. ##0C4220000004C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. #735,u,g,n,n,n,u,PM_DATA_FROM_RL2L3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. ##0C4240000004C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. #736,u,g,n,n,n,u,PM_DPTEG_FROM_RL2L3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. ##0C4260000004C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. #737,u,g,n,n,n,u,PM_IPTEG_FROM_RL2L3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. ##0C4220000014C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. #738,u,g,n,n,n,u,PM_DATA_FROM_RL2L3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. ##0C4240000024C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. #739,u,g,n,n,n,u,PM_DPTEG_FROM_RL2L3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. ##0C4260000024C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. #740,u,g,n,n,n,u,PM_INST_FROM_RL2L3,The processor's instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. ##0C0300000004C040 The processor's instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. #741,u,g,n,n,n,u,PM_IPTEG_FROM_RL2L3,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. ##0C0320000004C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. #742,u,g,n,n,n,u,PM_DATA_FROM_RL2L3,The processor's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. ##0C0340000004C040 The processor's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. #743,u,g,n,n,n,u,PM_DPTEG_FROM_RL2L3,The processor's data page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. ##0C0360000004C040 The processor's data page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. #744,u,g,n,n,n,u,PM_INST_FROM_RL2L3_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. ##0C0300000014C040 The processor's instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. #745,u,g,n,n,n,u,PM_IPTEG_FROM_RL2L3_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. ##0C0320000014C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. #746,u,g,n,n,n,u,PM_DATA_FROM_RL2L3_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. ##0C0340000024C040 The processor's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. #747,u,g,n,n,n,u,PM_DPTEG_FROM_RL2L3_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. ##0C0360000024C040 The processor's data page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. #748,u,g,n,n,n,u,PM_INST_FROM_RMEM,The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss. ##0D4100000004C040 The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss. #749,u,g,n,n,n,u,PM_IPTEG_FROM_RMEM,The processor's instruction page table entry was reloaded from remote memory (MC slow) due to a demand miss. ##0D4020000004C040 The processor's instruction page table entry was reloaded from remote memory (MC slow) due to a demand miss. #750,u,g,n,n,n,u,PM_DATA_FROM_RMEM,The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss. ##0D4040000004C040 The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss. #751,u,g,n,n,n,u,PM_DPTEG_FROM_RMEM,The processor's data page table entry was reloaded from remote memory (MC slow) due to a demand miss. ##0D4060000004C040 The processor's data page table entry was reloaded from remote memory (MC slow) due to a demand miss. #752,u,g,n,n,n,u,PM_INST_FROM_RMEM_ALL,The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. ##0D4100000014C040 The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. #753,u,g,n,n,n,u,PM_IPTEG_FROM_RMEM_ALL,The processor's instruction page table entry was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. ##0D4020000014C040 The processor's instruction page table entry was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. #754,u,g,n,n,n,u,PM_DATA_FROM_RMEM_ALL,The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. ##0D4040000024C040 The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. #755,u,g,n,n,n,u,PM_DPTEG_FROM_RMEM_ALL,The processor's data page table entry was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. ##0D4060000024C040 The processor's data page table entry was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. #756,u,g,n,n,n,u,PM_IPTEG_FROM_R_OC_CACHE,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss. ##0D8020000004C040 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss. #757,u,g,n,n,n,u,PM_DATA_FROM_R_OC_CACHE,The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache due to a demand miss. ##0D8040000004C040 The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache due to a demand miss. #758,u,g,n,n,n,u,PM_DPTEG_FROM_R_OC_CACHE,The processor's data page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss. ##0D8060000004C040 The processor's data page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss. #759,u,g,n,n,n,u,PM_IPTEG_FROM_R_OC_CACHE_ALL,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. ##0D8020000014C040 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. #760,u,g,n,n,n,u,PM_DATA_FROM_R_OC_CACHE_ALL,The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. ##0D8040000024C040 The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. #761,u,g,n,n,n,u,PM_DPTEG_FROM_R_OC_CACHE_ALL,The processor's data page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. ##0D8060000024C040 The processor's data page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. #762,u,g,n,n,n,u,PM_IPTEG_FROM_R_OC_MEM,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss. ##0DC020000004C040 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss. #763,u,g,n,n,n,u,PM_DATA_FROM_R_OC_MEM,The processor's L1 data cache was reloaded from a remote chip's OpenCapp memory due to a demand miss. ##0DC040000004C040 The processor's L1 data cache was reloaded from a remote chip's OpenCapp memory due to a demand miss. #764,u,g,n,n,n,u,PM_DPTEG_FROM_R_OC_MEM,The processor's data page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss. ##0DC060000004C040 The processor's data page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss. #765,u,g,n,n,n,u,PM_IPTEG_FROM_R_OC_MEM_ALL,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. ##0DC020000014C040 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. #766,u,g,n,n,n,u,PM_DATA_FROM_R_OC_MEM_ALL,The processor's L1 data cache was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. ##0DC040000024C040 The processor's L1 data cache was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. #767,u,g,n,n,n,u,PM_DPTEG_FROM_R_OC_MEM_ALL,The processor's data page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. ##0DC060000024C040 The processor's data page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. #768,u,g,n,n,n,u,PM_INST_FROM_R_OC_ANY,The processor's instruction cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. ##0D8100000004C040 The processor's instruction cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. #769,u,g,n,n,n,u,PM_IPTEG_FROM_R_OC_ANY,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. ##0D8120000004C040 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. #770,u,g,n,n,n,u,PM_DATA_FROM_R_OC_ANY,The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. ##0D8140000004C040 The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. #771,u,g,n,n,n,u,PM_DPTEG_FROM_R_OC_ANY,The processor's data page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. ##0D8160000004C040 The processor's data page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. #772,u,g,n,n,n,u,PM_INST_FROM_R_OC_ANY_ALL,The processor's instruction cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##0D8100000014C040 The processor's instruction cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #773,u,g,n,n,n,u,PM_IPTEG_FROM_R_OC_ANY_ALL,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##0D8120000014C040 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #774,u,g,n,n,n,u,PM_DATA_FROM_R_OC_ANY_ALL,The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##0D8140000024C040 The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #775,u,g,n,n,n,u,PM_DPTEG_FROM_R_OC_ANY_ALL,The processor's data page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##0D8160000024C040 The processor's data page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #776,u,g,n,n,n,u,PM_IPTEG_FROM_DL2_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. ##0E0020000004C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. #777,u,g,n,n,n,u,PM_DATA_FROM_DL2_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. ##0E0040000004C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. #778,u,g,n,n,n,u,PM_DPTEG_FROM_DL2_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. ##0E0060000004C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. #779,u,g,n,n,n,u,PM_IPTEG_FROM_DL2_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. ##0E0020000014C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. #780,u,g,n,n,n,u,PM_DATA_FROM_DL2_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. ##0E0040000024C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. #781,u,g,n,n,n,u,PM_DPTEG_FROM_DL2_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. ##0E0060000024C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. #782,u,g,n,n,n,u,PM_IPTEG_FROM_DL2_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. ##0E4020000004C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. #783,u,g,n,n,n,u,PM_DATA_FROM_DL2_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. ##0E4040000004C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. #784,u,g,n,n,n,u,PM_DPTEG_FROM_DL2_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. ##0E4060000004C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. #785,u,g,n,n,n,u,PM_IPTEG_FROM_DL2_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. ##0E4020000014C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. #786,u,g,n,n,n,u,PM_DATA_FROM_DL2_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. ##0E4040000024C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. #787,u,g,n,n,n,u,PM_DPTEG_FROM_DL2_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. ##0E4060000024C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. #788,u,g,n,n,n,u,PM_INST_FROM_DL2,The processor's instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss. ##0E0100000004C040 The processor's instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss. #789,u,g,n,n,n,u,PM_IPTEG_FROM_DL2,The processor's instruction page table entry was reloaded from another core's L2 from a distant chip due to a demand miss. ##0E0120000004C040 The processor's instruction page table entry was reloaded from another core's L2 from a distant chip due to a demand miss. #790,u,g,n,n,n,u,PM_DATA_FROM_DL2,The processor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss. ##0E0140000004C040 The processor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss. #791,u,g,n,n,n,u,PM_DPTEG_FROM_DL2,The processor's data page table entry was reloaded from another core's L2 from a distant chip due to a demand miss. ##0E0160000004C040 The processor's data page table entry was reloaded from another core's L2 from a distant chip due to a demand miss. #792,u,g,n,n,n,u,PM_INST_FROM_DL2_ALL,The processor's instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. ##0E0100000014C040 The processor's instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. #793,u,g,n,n,n,u,PM_IPTEG_FROM_DL2_ALL,The processor's instruction page table entry was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. ##0E0120000014C040 The processor's instruction page table entry was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. #794,u,g,n,n,n,u,PM_DATA_FROM_DL2_ALL,The processor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. ##0E0140000024C040 The processor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. #795,u,g,n,n,n,u,PM_DPTEG_FROM_DL2_ALL,The processor's data page table entry was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. ##0E0160000024C040 The processor's data page table entry was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. #796,u,g,n,n,n,u,PM_IPTEG_FROM_DL3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. ##0E8020000004C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. #797,u,g,n,n,n,u,PM_DATA_FROM_DL3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. ##0E8040000004C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. #798,u,g,n,n,n,u,PM_DPTEG_FROM_DL3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. ##0E8060000004C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. #799,u,g,n,n,n,u,PM_IPTEG_FROM_DL3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. ##0E8020000014C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. #800,u,g,n,n,n,u,PM_DATA_FROM_DL3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. ##0E8040000024C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. #801,u,g,n,n,n,u,PM_DPTEG_FROM_DL3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. ##0E8060000024C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. #802,u,g,n,n,n,u,PM_IPTEG_FROM_DL3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. ##0EC020000004C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. #803,u,g,n,n,n,u,PM_DATA_FROM_DL3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. ##0EC040000004C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. #804,u,g,n,n,n,u,PM_DPTEG_FROM_DL3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. ##0EC060000004C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. #805,u,g,n,n,n,u,PM_IPTEG_FROM_DL3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. ##0EC020000014C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. #806,u,g,n,n,n,u,PM_DATA_FROM_DL3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. ##0EC040000024C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. #807,u,g,n,n,n,u,PM_DPTEG_FROM_DL3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. ##0EC060000024C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. #808,u,g,n,n,n,u,PM_INST_FROM_DL3,The processor's instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss. ##0E8100000004C040 The processor's instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss. #809,u,g,n,n,n,u,PM_IPTEG_FROM_DL3,The processor's instruction page table entry was reloaded from another core's L3 from a distant chip due to a demand miss. ##0E8120000004C040 The processor's instruction page table entry was reloaded from another core's L3 from a distant chip due to a demand miss. #810,u,g,n,n,n,u,PM_DATA_FROM_DL3,The processor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss. ##0E8140000004C040 The processor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss. #811,u,g,n,n,n,u,PM_DPTEG_FROM_DL3,The processor's data page table entry was reloaded from another core's L3 from a distant chip due to a demand miss. ##0E8160000004C040 The processor's data page table entry was reloaded from another core's L3 from a distant chip due to a demand miss. #812,u,g,n,n,n,u,PM_INST_FROM_DL3_ALL,The processor's instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. ##0E8100000014C040 The processor's instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. #813,u,g,n,n,n,u,PM_IPTEG_FROM_DL3_ALL,The processor's instruction page table entry was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. ##0E8120000014C040 The processor's instruction page table entry was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. #814,u,g,n,n,n,u,PM_DATA_FROM_DL3_ALL,The processor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. ##0E8140000024C040 The processor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. #815,u,g,n,n,n,u,PM_DPTEG_FROM_DL3_ALL,The processor's data page table entry was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. ##0E8160000024C040 The processor's data page table entry was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. #816,u,g,n,n,n,u,PM_IPTEG_FROM_DL2L3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. ##0E0220000004C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. #817,u,g,n,n,n,u,PM_DATA_FROM_DL2L3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. ##0E0240000004C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. #818,u,g,n,n,n,u,PM_DPTEG_FROM_DL2L3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. ##0E0260000004C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. #819,u,g,n,n,n,u,PM_IPTEG_FROM_DL2L3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. ##0E0220000014C040 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. #820,u,g,n,n,n,u,PM_DATA_FROM_DL2L3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. ##0E0240000024C040 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. #821,u,g,n,n,n,u,PM_DPTEG_FROM_DL2L3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. ##0E0260000024C040 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. #822,u,g,n,n,n,u,PM_IPTEG_FROM_DL2L3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. ##0E4220000004C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. #823,u,g,n,n,n,u,PM_DATA_FROM_DL2L3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. ##0E4240000004C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. #824,u,g,n,n,n,u,PM_DPTEG_FROM_DL2L3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. ##0E4260000004C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. #825,u,g,n,n,n,u,PM_IPTEG_FROM_DL2L3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. ##0E4220000014C040 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. #826,u,g,n,n,n,u,PM_DATA_FROM_DL2L3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. ##0E4240000024C040 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. #827,u,g,n,n,n,u,PM_DPTEG_FROM_DL2L3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. ##0E4260000024C040 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. #828,u,g,n,n,n,u,PM_INST_FROM_DL2L3,The processor's instruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. ##0E0300000004C040 The processor's instruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. #829,u,g,n,n,n,u,PM_IPTEG_FROM_DL2L3,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. ##0E0320000004C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. #830,u,g,n,n,n,u,PM_DATA_FROM_DL2L3,The processor's L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. ##0E0340000004C040 The processor's L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. #831,u,g,n,n,n,u,PM_DPTEG_FROM_DL2L3,The processor's data page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. ##0E0360000004C040 The processor's data page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. #832,u,g,n,n,n,u,PM_INST_FROM_DL2L3_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. ##0E0300000014C040 The processor's instruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. #833,u,g,n,n,n,u,PM_IPTEG_FROM_DL2L3_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. ##0E0320000014C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. #834,u,g,n,n,n,u,PM_DATA_FROM_DL2L3_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. ##0E0340000024C040 The processor's L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. #835,u,g,n,n,n,u,PM_DPTEG_FROM_DL2L3_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. ##0E0360000024C040 The processor's data page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. #836,u,g,n,n,n,u,PM_INST_FROM_DMEM,The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss. ##0F4100000004C040 The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss. #837,u,g,n,n,n,u,PM_IPTEG_FROM_DMEM,The processor's instruction page table entry was reloaded from distant memory (MC slow) due to a demand miss. ##0F4020000004C040 The processor's instruction page table entry was reloaded from distant memory (MC slow) due to a demand miss. #838,u,g,n,n,n,u,PM_DATA_FROM_DMEM,The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss. ##0F4040000004C040 The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss. #839,u,g,n,n,n,u,PM_DPTEG_FROM_DMEM,The processor's data page table entry was reloaded from distant memory (MC slow) due to a demand miss. ##0F4060000004C040 The processor's data page table entry was reloaded from distant memory (MC slow) due to a demand miss. #840,u,g,n,n,n,u,PM_INST_FROM_DMEM_ALL,The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. ##0F4100000014C040 The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. #841,u,g,n,n,n,u,PM_IPTEG_FROM_DMEM_ALL,The processor's instruction page table entry was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. ##0F4020000014C040 The processor's instruction page table entry was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. #842,u,g,n,n,n,u,PM_DATA_FROM_DMEM_ALL,The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. ##0F4040000024C040 The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. #843,u,g,n,n,n,u,PM_DPTEG_FROM_DMEM_ALL,The processor's data page table entry was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. ##0F4060000024C040 The processor's data page table entry was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. #844,u,g,n,n,n,u,PM_IPTEG_FROM_D_OC_CACHE,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss. ##0F8020000004C040 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss. #845,u,g,n,n,n,u,PM_DATA_FROM_D_OC_CACHE,The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache due to a demand miss. ##0F8040000004C040 The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache due to a demand miss. #846,u,g,n,n,n,u,PM_DPTEG_FROM_D_OC_CACHE,The processor's data page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss. ##0F8060000004C040 The processor's data page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss. #847,u,g,n,n,n,u,PM_IPTEG_FROM_D_OC_CACHE_ALL,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. ##0F8020000014C040 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. #848,u,g,n,n,n,u,PM_DATA_FROM_D_OC_CACHE_ALL,The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. ##0F8040000024C040 The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. #849,u,g,n,n,n,u,PM_DPTEG_FROM_D_OC_CACHE_ALL,The processor's data page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. ##0F8060000024C040 The processor's data page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. #850,u,g,n,n,n,u,PM_IPTEG_FROM_D_OC_MEM,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss. ##0FC020000004C040 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss. #851,u,g,n,n,n,u,PM_DATA_FROM_D_OC_MEM,The processor's L1 data cache was reloaded from a distant chip's OpenCapp memory due to a demand miss. ##0FC040000004C040 The processor's L1 data cache was reloaded from a distant chip's OpenCapp memory due to a demand miss. #852,u,g,n,n,n,u,PM_DPTEG_FROM_D_OC_MEM,The processor's data page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss. ##0FC060000004C040 The processor's data page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss. #853,u,g,n,n,n,u,PM_IPTEG_FROM_D_OC_MEM_ALL,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. ##0FC020000014C040 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. #854,u,g,n,n,n,u,PM_DATA_FROM_D_OC_MEM_ALL,The processor's L1 data cache was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. ##0FC040000024C040 The processor's L1 data cache was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. #855,u,g,n,n,n,u,PM_DPTEG_FROM_D_OC_MEM_ALL,The processor's data page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. ##0FC060000024C040 The processor's data page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. #856,u,g,n,n,n,u,PM_INST_FROM_D_OC_ANY,The processor's instruction cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. ##0F8100000004C040 The processor's instruction cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. #857,u,g,n,n,n,u,PM_IPTEG_FROM_D_OC_ANY,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. ##0F8120000004C040 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. #858,u,g,n,n,n,u,PM_DATA_FROM_D_OC_ANY,The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. ##0F8140000004C040 The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. #859,u,g,n,n,n,u,PM_DPTEG_FROM_D_OC_ANY,The processor's data page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. ##0F8160000004C040 The processor's data page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. #860,u,g,n,n,n,u,PM_INST_FROM_D_OC_ANY_ALL,The processor's instruction cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##0F8100000014C040 The processor's instruction cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #861,u,g,n,n,n,u,PM_IPTEG_FROM_D_OC_ANY_ALL,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##0F8120000014C040 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #862,u,g,n,n,n,u,PM_DATA_FROM_D_OC_ANY_ALL,The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##0F8140000024C040 The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #863,u,g,n,n,n,u,PM_DPTEG_FROM_D_OC_ANY_ALL,The processor's data page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. ##0F8160000024C040 The processor's data page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. #864,u,g,n,n,n,u,PM_INST_FROM_ONCHIP_CACHE,The processor's instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss. ##080B00000004C040 The processor's instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss. #865,u,g,n,n,n,u,PM_IPTEG_FROM_ONCHIP_CACHE,The processor's instruction page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss. ##080B20000004C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss. #866,u,g,n,n,n,u,PM_DATA_FROM_ONCHIP_CACHE,The processor's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss. ##080B40000004C040 The processor's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss. #867,u,g,n,n,n,u,PM_DPTEG_FROM_ONCHIP_CACHE,The processor's data page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss. ##080B60000004C040 The processor's data page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss. #868,u,g,n,n,n,u,PM_INST_FROM_ONCHIP_CACHE_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. ##080B00000014C040 The processor's instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. #869,u,g,n,n,n,u,PM_IPTEG_FROM_ONCHIP_CACHE_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. ##080B20000014C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. #870,u,g,n,n,n,u,PM_DATA_FROM_ONCHIP_CACHE_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. ##080B40000024C040 The processor's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. #871,u,g,n,n,n,u,PM_DPTEG_FROM_ONCHIP_CACHE_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. ##080B60000024C040 The processor's data page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. #872,u,g,n,n,n,u,PM_INST_FROM_OFFCHIP_CACHE,The processor's instruction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss. ##0C0B00000004C040 The processor's instruction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss. #873,u,g,n,n,n,u,PM_IPTEG_FROM_OFFCHIP_CACHE,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss. ##0C0B20000004C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss. #874,u,g,n,n,n,u,PM_DATA_FROM_OFFCHIP_CACHE,The processor's L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss. ##0C0B40000004C040 The processor's L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss. #875,u,g,n,n,n,u,PM_DPTEG_FROM_OFFCHIP_CACHE,The processor's data page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss. ##0C0B60000004C040 The processor's data page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss. #876,u,g,n,n,n,u,PM_INST_FROM_OFFCHIP_CACHE_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. ##0C0B00000014C040 The processor's instruction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. #877,u,g,n,n,n,u,PM_IPTEG_FROM_OFFCHIP_CACHE_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. ##0C0B20000014C040 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. #878,u,g,n,n,n,u,PM_DATA_FROM_OFFCHIP_CACHE_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. ##0C0B40000024C040 The processor's L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. #879,u,g,n,n,n,u,PM_DPTEG_FROM_OFFCHIP_CACHE_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. ##0C0B60000024C040 The processor's data page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. #880,u,g,n,n,n,u,PM_INST_FROM_ANY_MEMORY,The processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss. ##095900000004C040 The processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss. #881,u,g,n,n,n,u,PM_IPTEG_FROM_ANY_MEMORY,The processor's instruction page table entry was reloaded from any chip's memory (MC slow) due to a demand miss. ##095820000004C040 The processor's instruction page table entry was reloaded from any chip's memory (MC slow) due to a demand miss. #882,u,g,n,n,n,u,PM_DATA_FROM_ANY_MEMORY,The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss. ##095840000004C040 The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss. #883,u,g,n,n,n,u,PM_DPTEG_FROM_ANY_MEMORY,The processor's data page table entry was reloaded from any chip's memory (MC slow) due to a demand miss. ##095860000004C040 The processor's data page table entry was reloaded from any chip's memory (MC slow) due to a demand miss. #884,u,g,n,n,n,u,PM_INST_FROM_ANY_MEMORY_ALL,The processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. ##095900000014C040 The processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. #885,u,g,n,n,n,u,PM_IPTEG_FROM_ANY_MEMORY_ALL,The processor's instruction page table entry was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. ##095820000014C040 The processor's instruction page table entry was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. #886,u,g,n,n,n,u,PM_DATA_FROM_ANY_MEMORY_ALL,The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. ##095840000024C040 The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. #887,u,g,n,n,n,u,PM_DPTEG_FROM_ANY_MEMORY_ALL,The processor's data page table entry was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. ##095860000024C040 The processor's data page table entry was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. #888,u,g,n,n,m,u,PM_MRK_INST_FROM_L2,The processor's instruction cache was reloaded from the local core's L2 due to a demand miss for a marked instruction. ##000300000004C142 The processor's instruction cache was reloaded from the local core's L2 due to a demand miss for a marked instruction. #889,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2,The processor's instruction page table entry was reloaded from the local core's L2 due to a demand miss for a marked instruction. ##000320000004C142 The processor's instruction page table entry was reloaded from the local core's L2 due to a demand miss for a marked instruction. #890,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2,The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss for a marked instruction. ##000340000004C142 The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss for a marked instruction. #891,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2,The processor's data page table entry was reloaded from the local core's L2 due to a demand miss for a marked instruction. ##000360000004C142 The processor's data page table entry was reloaded from the local core's L2 due to a demand miss for a marked instruction. #892,u,g,n,n,m,u,PM_MRK_INST_FROM_L2_ALL,The processor's instruction cache was reloaded from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##000300000014C142 The processor's instruction cache was reloaded from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #893,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_ALL,The processor's instruction page table entry was reloaded from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##000320000014C142 The processor's instruction page table entry was reloaded from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #894,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_ALL,The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##000340000024C142 The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #895,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_ALL,The processor's data page table entry was reloaded from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##000360000024C142 The processor's data page table entry was reloaded from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #896,u,g,n,n,m,u,PM_MRK_INST_FROM_L1MISS,The processor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss for a marked instruction. ##003F00000004C142 The processor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss for a marked instruction. #897,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L1MISS,The processor's instruction page table entry was reloaded from a source beyond the local core's L1 due to a demand miss for a marked instruction. ##003F20000004C142 The processor's instruction page table entry was reloaded from a source beyond the local core's L1 due to a demand miss for a marked instruction. #898,u,g,n,n,m,u,PM_MRK_DATA_FROM_L1MISS,The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss for a marked instruction. ##003F40000004C142 The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss for a marked instruction. #899,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L1MISS,The processor's data page table entry was reloaded from a source beyond the local core's L1 due to a demand miss for a marked instruction. ##003F60000004C142 The processor's data page table entry was reloaded from a source beyond the local core's L1 due to a demand miss for a marked instruction. #900,u,g,n,n,m,u,PM_MRK_INST_FROM_L1MISS_ALL,The processor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload for a marked instruction. ##003F00000014C142 The processor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload for a marked instruction. #901,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L1MISS_ALL,The processor's instruction page table entry was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload for a marked instruction. ##003F20000014C142 The processor's instruction page table entry was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload for a marked instruction. #902,u,g,n,n,m,u,PM_MRK_DATA_FROM_L1MISS_ALL,The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload for a marked instruction. ##003F40000024C142 The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload for a marked instruction. #903,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L1MISS_ALL,The processor's data page table entry was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload for a marked instruction. ##003F60000024C142 The processor's data page table entry was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload for a marked instruction. #904,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_NO_CONFLICT,The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss for a marked instruction. ##000020000004C142 The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss for a marked instruction. #905,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_NO_CONFLICT,The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss for a marked instruction. ##000040000004C142 The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss for a marked instruction. #906,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_NO_CONFLICT,The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss for a marked instruction. ##000060000004C142 The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss for a marked instruction. #907,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_NO_CONFLICT_ALL,The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##000020000014C142 The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #908,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_NO_CONFLICT_ALL,The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##000040000024C142 The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #909,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_NO_CONFLICT_ALL,The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##000060000024C142 The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #910,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_MEPF,The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss for a marked instruction. ##004020000004C142 The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss for a marked instruction. #911,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_MEPF,The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss for a marked instruction. ##004040000004C142 The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss for a marked instruction. #912,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_MEPF,The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss for a marked instruction. ##004060000004C142 The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss for a marked instruction. #913,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_MEPF_ALL,The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##004020000014C142 The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #914,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_MEPF_ALL,The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##004040000024C142 The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #915,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_MEPF_ALL,The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##004060000024C142 The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #916,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_LDHITST_CONFLICT,The processor's instruction page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. ##008020000004C142 The processor's instruction page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. #917,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_LDHITST_CONFLICT,The processor's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. ##008040000004C142 The processor's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. #918,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_LDHITST_CONFLICT,The processor's data page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. ##008060000004C142 The processor's data page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. #919,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_LDHITST_CONFLICT_ALL,The processor's instruction page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##008020000014C142 The processor's instruction page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #920,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_LDHITST_CONFLICT_ALL,The processor's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##008040000024C142 The processor's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #921,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_LDHITST_CONFLICT_ALL,The processor's data page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##008060000024C142 The processor's data page table entry was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #922,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_OTHER_CONFLICT,The processor's instruction page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. ##00C020000004C142 The processor's instruction page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. #923,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_OTHER_CONFLICT,The processor's L1 data cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. ##00C040000004C142 The processor's L1 data cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. #924,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_OTHER_CONFLICT,The processor's data page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. ##00C060000004C142 The processor's data page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss for a marked instruction. #925,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_OTHER_CONFLICT_ALL,The processor's instruction page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##00C020000014C142 The processor's instruction page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #926,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_OTHER_CONFLICT_ALL,The processor's L1 data cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##00C040000024C142 The processor's L1 data cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #927,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_OTHER_CONFLICT_ALL,The processor's data page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##00C060000024C142 The processor's data page table entry was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #928,u,g,n,n,m,u,PM_MRK_INST_FROM_L2MISS,The processor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction. ##000380000004C142 The processor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction. #929,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2MISS,The processor's instruction page table entry was reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction. ##0003A0000004C142 The processor's instruction page table entry was reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction. #930,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2MISS,The processor's data page table entry was reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction. ##0003E0000004C142 The processor's data page table entry was reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction. #931,u,g,n,n,m,u,PM_MRK_INST_FROM_L2MISS_ALL,The processor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##000380000014C142 The processor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #932,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2MISS_ALL,The processor's instruction page table entry was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##0003A0000014C142 The processor's instruction page table entry was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #933,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2MISS_ALL,The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##0003C0000024C142 The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #934,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2MISS_ALL,The processor's data page table entry was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload for a marked instruction. ##0003E0000024C142 The processor's data page table entry was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload for a marked instruction. #935,u,g,n,n,m,u,PM_MRK_INST_FROM_L3,The processor's instruction cache was reloaded from the local core's L3 due to a demand miss for a marked instruction. ##010300000004C142 The processor's instruction cache was reloaded from the local core's L3 due to a demand miss for a marked instruction. #936,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3,The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss for a marked instruction. ##010320000004C142 The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss for a marked instruction. #937,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3,The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss for a marked instruction. ##010340000004C142 The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss for a marked instruction. #938,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3,The processor's data page table entry was reloaded from the local core's L3 due to a demand miss for a marked instruction. ##010360000004C142 The processor's data page table entry was reloaded from the local core's L3 due to a demand miss for a marked instruction. #939,u,g,n,n,m,u,PM_MRK_INST_FROM_L3_ALL,The processor's instruction cache was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##010300000014C142 The processor's instruction cache was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #940,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_ALL,The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##010320000014C142 The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #941,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_ALL,The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##010340000024C142 The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #942,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_ALL,The processor's data page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##010360000024C142 The processor's data page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #943,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_NO_CONFLICT,The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss for a marked instruction. ##010020000004C142 The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss for a marked instruction. #944,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_NO_CONFLICT,The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss for a marked instruction. ##010040000004C142 The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss for a marked instruction. #945,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_NO_CONFLICT,The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss for a marked instruction. ##010060000004C142 The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss for a marked instruction. #946,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_NO_CONFLICT_ALL,The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##010020000014C142 The processor's instruction page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #947,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_NO_CONFLICT_ALL,The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##010040000024C142 The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #948,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_NO_CONFLICT_ALL,The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##010060000024C142 The processor's data page table entry was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #949,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_MEPF,The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss for a marked instruction. ##014020000004C142 The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss for a marked instruction. #950,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_MEPF,The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss for a marked instruction. ##014040000004C142 The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss for a marked instruction. #951,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_MEPF,The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss for a marked instruction. ##014060000004C142 The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss for a marked instruction. #952,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_MEPF_ALL,The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##014020000014C142 The processor's instruction page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #953,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_MEPF_ALL,The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##014040000024C142 The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #954,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_MEPF_ALL,The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##014060000024C142 The processor's data page table entry was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #955,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_CONFLICT,The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss for a marked instruction. ##01C020000004C142 The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss for a marked instruction. #956,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_CONFLICT,The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss for a marked instruction. ##01C040000004C142 The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss for a marked instruction. #957,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_CONFLICT,The processor's data page table entry was reloaded from the local core's L3 due to a demand miss for a marked instruction. ##01C060000004C142 The processor's data page table entry was reloaded from the local core's L3 due to a demand miss for a marked instruction. #958,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_CONFLICT_ALL,The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##01C020000014C142 The processor's instruction page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #959,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_CONFLICT_ALL,The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##01C040000024C142 The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #960,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_CONFLICT_ALL,The processor's data page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##01C060000024C142 The processor's data page table entry was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #961,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3MISS,The processor's instruction page table entry was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction. ##0007A0000004C142 The processor's instruction page table entry was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction. #962,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3MISS,The processor's data page table entry was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction. ##0007E0000004C142 The processor's data page table entry was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction. #963,u,g,n,n,m,u,PM_MRK_INST_FROM_L3MISS_ALL,The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##000780000014C142 The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #964,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3MISS_ALL,The processor's instruction page table entry was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##0007A0000014C142 The processor's instruction page table entry was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #965,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3MISS_ALL,The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##0007C0000024C142 The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #966,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3MISS_ALL,The processor's data page table entry was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload for a marked instruction. ##0007E0000024C142 The processor's data page table entry was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload for a marked instruction. #967,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. ##080020000004C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. #968,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. ##080040000004C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. #969,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. ##080060000004C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. #970,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080020000014C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #971,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080040000024C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #972,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080060000024C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #973,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. ##084020000004C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. #974,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. ##084040000004C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. #975,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. ##084060000004C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. #976,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##084020000014C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #977,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##084040000024C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #978,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##084060000024C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #979,u,g,n,n,m,u,PM_MRK_INST_FROM_L21_REGENT,The processor's instruction cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. ##080100000004C142 The processor's instruction cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. #980,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT,The processor's instruction page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. ##080120000004C142 The processor's instruction page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. #981,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT,The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. ##080140000004C142 The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. #982,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT,The processor's data page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. ##080160000004C142 The processor's data page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction. #983,u,g,n,n,m,u,PM_MRK_INST_FROM_L21_REGENT_ALL,The processor's instruction cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080100000014C142 The processor's instruction cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #984,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_ALL,The processor's instruction page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080120000014C142 The processor's instruction page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #985,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_ALL,The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080140000024C142 The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #986,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_ALL,The processor's data page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080160000024C142 The processor's data page table entry was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #987,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##088020000004C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. #988,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##088040000004C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. #989,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##088060000004C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. #990,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##088020000014C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #991,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##088040000024C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #992,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##088060000024C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #993,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##08C020000004C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. #994,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##08C040000004C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. #995,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##08C060000004C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. #996,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##08C020000014C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #997,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##08C040000024C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #998,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##08C060000024C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #999,u,g,n,n,m,u,PM_MRK_INST_FROM_L31_REGENT,The processor's instruction cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##088100000004C142 The processor's instruction cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. #1000,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT,The processor's instruction page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##088120000004C142 The processor's instruction page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. #1001,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT,The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##088140000004C142 The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. #1002,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT,The processor's data page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##088160000004C142 The processor's data page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction. #1003,u,g,n,n,m,u,PM_MRK_INST_FROM_L31_REGENT_ALL,The processor's instruction cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##088100000014C142 The processor's instruction cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #1004,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_ALL,The processor's instruction page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##088120000014C142 The processor's instruction page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #1005,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_ALL,The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##088140000024C142 The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #1006,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_ALL,The processor's data page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##088160000024C142 The processor's data page table entry was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #1007,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##080220000004C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. #1008,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##080240000004C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. #1009,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##080260000004C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. #1010,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080220000014C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #1011,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080240000024C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #1012,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080260000024C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #1013,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##084220000004C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. #1014,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##084240000004C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. #1015,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##084260000004C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. #1016,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##084220000014C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #1017,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##084240000024C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #1018,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##084260000024C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #1019,u,g,n,n,m,u,PM_MRK_INST_FROM_REGENT_L2L3,The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##080300000004C142 The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. #1020,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3,The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##080320000004C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. #1021,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3,The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##080340000004C142 The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. #1022,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3,The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. ##080360000004C142 The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction. #1023,u,g,n,n,m,u,PM_MRK_INST_FROM_REGENT_L2L3_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080300000014C142 The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #1024,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080320000014C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #1025,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080340000024C142 The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #1026,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. ##080360000024C142 The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction. #1027,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0020000004C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. #1028,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0040000004C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. #1029,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0060000004C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. #1030,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0020000014C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1031,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0040000024C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1032,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0060000024C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1033,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A4020000004C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. #1034,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A4040000004C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. #1035,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A4060000004C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. #1036,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A4020000014C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1037,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A4040000024C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1038,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A4060000024C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1039,u,g,n,n,m,u,PM_MRK_INST_FROM_L21_NON_REGENT,The processor's instruction cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0100000004C142 The processor's instruction cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. #1040,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT,The processor's instruction page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0120000004C142 The processor's instruction page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. #1041,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT,The processor's L1 data cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0140000004C142 The processor's L1 data cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. #1042,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT,The processor's data page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0160000004C142 The processor's data page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction. #1043,u,g,n,n,m,u,PM_MRK_INST_FROM_L21_NON_REGENT_ALL,The processor's instruction cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0100000014C142 The processor's instruction cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1044,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_ALL,The processor's instruction page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0120000014C142 The processor's instruction page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1045,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_ALL,The processor's L1 data cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0140000024C142 The processor's L1 data cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1046,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_ALL,The processor's data page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0160000024C142 The processor's data page table entry was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1047,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A8020000004C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1048,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A8040000004C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1049,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A8060000004C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1050,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A8020000014C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1051,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A8040000024C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1052,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A8060000024C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1053,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0AC020000004C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1054,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0AC040000004C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1055,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0AC060000004C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1056,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0AC020000014C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1057,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0AC040000024C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1058,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0AC060000024C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1059,u,g,n,n,m,u,PM_MRK_INST_FROM_L31_NON_REGENT,The processor's instruction cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A8100000004C142 The processor's instruction cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1060,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT,The processor's instruction page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A8120000004C142 The processor's instruction page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1061,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT,The processor's L1 data cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A8140000004C142 The processor's L1 data cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1062,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT,The processor's data page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A8160000004C142 The processor's data page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1063,u,g,n,n,m,u,PM_MRK_INST_FROM_L31_NON_REGENT_ALL,The processor's instruction cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A8100000014C142 The processor's instruction cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1064,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_ALL,The processor's instruction page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A8120000014C142 The processor's instruction page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1065,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_ALL,The processor's L1 data cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A8140000024C142 The processor's L1 data cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1066,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_ALL,The processor's data page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A8160000024C142 The processor's data page table entry was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1067,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0220000004C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1068,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0240000004C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1069,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0260000004C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1070,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0220000014C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1071,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0240000024C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1072,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0260000024C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1073,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A4220000004C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1074,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A4240000004C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1075,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A4260000004C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1076,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A4220000014C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1077,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A4240000024C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1078,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A4260000024C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1079,u,g,n,n,m,u,PM_MRK_INST_FROM_NON_REGENT_L2L3,The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0300000004C142 The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1080,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3,The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0320000004C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1081,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3,The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0340000004C142 The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1082,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3,The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. ##0A0360000004C142 The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction. #1083,u,g,n,n,m,u,PM_MRK_INST_FROM_NON_REGENT_L2L3_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0300000014C142 The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1084,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0320000014C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1085,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0340000024C142 The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1086,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. ##0A0360000024C142 The processor's data page table entry was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction. #1087,u,g,n,n,m,u,PM_MRK_INST_FROM_LMEM,The processor's instruction cache was reloaded from the local chip's memory due to a demand miss for a marked instruction. ##094100000004C142 The processor's instruction cache was reloaded from the local chip's memory due to a demand miss for a marked instruction. #1088,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_LMEM,The processor's instruction page table entry was reloaded from the local chip's memory due to a demand miss for a marked instruction. ##094020000004C142 The processor's instruction page table entry was reloaded from the local chip's memory due to a demand miss for a marked instruction. #1089,u,g,n,n,m,u,PM_MRK_DATA_FROM_LMEM,The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss for a marked instruction. ##094040000004C142 The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss for a marked instruction. #1090,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_LMEM,The processor's data page table entry was reloaded from the local chip's memory due to a demand miss for a marked instruction. ##094060000004C142 The processor's data page table entry was reloaded from the local chip's memory due to a demand miss for a marked instruction. #1091,u,g,n,n,m,u,PM_MRK_INST_FROM_LMEM_ALL,The processor's instruction cache was reloaded from the local chip's memory due to a demand miss or prefetch reload for a marked instruction. ##094100000014C142 The processor's instruction cache was reloaded from the local chip's memory due to a demand miss or prefetch reload for a marked instruction. #1092,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_LMEM_ALL,The processor's instruction page table entry was reloaded from the local chip's memory due to a demand miss or prefetch reload for a marked instruction. ##094020000014C142 The processor's instruction page table entry was reloaded from the local chip's memory due to a demand miss or prefetch reload for a marked instruction. #1093,u,g,n,n,m,u,PM_MRK_DATA_FROM_LMEM_ALL,The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss or prefetch reload for a marked instruction. ##094040000024C142 The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss or prefetch reload for a marked instruction. #1094,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_LMEM_ALL,The processor's data page table entry was reloaded from the local chip's memory due to a demand miss or prefetch reload for a marked instruction. ##094060000024C142 The processor's data page table entry was reloaded from the local chip's memory due to a demand miss or prefetch reload for a marked instruction. #1095,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_CACHE,The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss for a marked instruction. ##098020000004C142 The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss for a marked instruction. #1096,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_CACHE,The processor's L1 data cache was reloaded from the local chip's OpenCapp cache due to a demand miss for a marked instruction. ##098040000004C142 The processor's L1 data cache was reloaded from the local chip's OpenCapp cache due to a demand miss for a marked instruction. #1097,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_CACHE,The processor's data page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss for a marked instruction. ##098060000004C142 The processor's data page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss for a marked instruction. #1098,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_CACHE_ALL,The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. ##098020000014C142 The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. #1099,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_CACHE_ALL,The processor's L1 data cache was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. ##098040000024C142 The processor's L1 data cache was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. #1100,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_CACHE_ALL,The processor's data page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. ##098060000024C142 The processor's data page table entry was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. #1101,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_MEM,The processor's instruction page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss for a marked instruction. ##09C020000004C142 The processor's instruction page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss for a marked instruction. #1102,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_MEM,The processor's L1 data cache was reloaded from the local chip's OpenCapp memory due to a demand miss for a marked instruction. ##09C040000004C142 The processor's L1 data cache was reloaded from the local chip's OpenCapp memory due to a demand miss for a marked instruction. #1103,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_MEM,The processor's data page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss for a marked instruction. ##09C060000004C142 The processor's data page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss for a marked instruction. #1104,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_MEM_ALL,The processor's instruction page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. ##09C020000014C142 The processor's instruction page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. #1105,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_MEM_ALL,The processor's L1 data cache was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. ##09C040000024C142 The processor's L1 data cache was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. #1106,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_MEM_ALL,The processor's data page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. ##09C060000024C142 The processor's data page table entry was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. #1107,u,g,n,n,m,u,PM_MRK_INST_FROM_L_OC_ANY,The processor's instruction cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##098100000004C142 The processor's instruction cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1108,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_ANY,The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##098120000004C142 The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1109,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_ANY,The processor's L1 data cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##098140000004C142 The processor's L1 data cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1110,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_ANY,The processor's data page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##098160000004C142 The processor's data page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1111,u,g,n,n,m,u,PM_MRK_INST_FROM_L_OC_ANY_ALL,The processor's instruction cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##098100000014C142 The processor's instruction cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1112,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_ANY_ALL,The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##098120000014C142 The processor's instruction page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1113,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_ANY_ALL,The processor's L1 data cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##098140000024C142 The processor's L1 data cache was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1114,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_ANY_ALL,The processor's data page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##098160000024C142 The processor's data page table entry was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1115,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. ##0C0020000004C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. #1116,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. ##0C0040000004C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. #1117,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. ##0C0060000004C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. #1118,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0020000014C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1119,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0040000024C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1120,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0060000024C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1121,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. ##0C4020000004C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. #1122,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. ##0C4040000004C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. #1123,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. ##0C4060000004C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction. #1124,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C4020000014C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1125,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C4040000024C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1126,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C4060000024C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1127,u,g,n,n,m,u,PM_MRK_INST_FROM_RL2,The processor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss for a marked instruction. ##0C0100000004C142 The processor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss for a marked instruction. #1128,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2,The processor's instruction page table entry was reloaded from another core's L2 from a remote chip due to a demand miss for a marked instruction. ##0C0120000004C142 The processor's instruction page table entry was reloaded from another core's L2 from a remote chip due to a demand miss for a marked instruction. #1129,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2,The processor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss for a marked instruction. ##0C0140000004C142 The processor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss for a marked instruction. #1130,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2,The processor's data page table entry was reloaded from another core's L2 from a remote chip due to a demand miss for a marked instruction. ##0C0160000004C142 The processor's data page table entry was reloaded from another core's L2 from a remote chip due to a demand miss for a marked instruction. #1131,u,g,n,n,m,u,PM_MRK_INST_FROM_RL2_ALL,The processor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0100000014C142 The processor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1132,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_ALL,The processor's instruction page table entry was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0120000014C142 The processor's instruction page table entry was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1133,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_ALL,The processor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0140000024C142 The processor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1134,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_ALL,The processor's data page table entry was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0160000024C142 The processor's data page table entry was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1135,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. ##0C8020000004C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. #1136,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. ##0C8040000004C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. #1137,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. ##0C8060000004C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. #1138,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C8020000014C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1139,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C8040000024C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1140,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C8060000024C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1141,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. ##0CC020000004C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. #1142,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. ##0CC040000004C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. #1143,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. ##0CC060000004C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction. #1144,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0CC020000014C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1145,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0CC040000024C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1146,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0CC060000024C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1147,u,g,n,n,m,u,PM_MRK_INST_FROM_RL3,The processor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss for a marked instruction. ##0C8100000004C142 The processor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss for a marked instruction. #1148,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3,The processor's instruction page table entry was reloaded from another core's L3 from a remote chip due to a demand miss for a marked instruction. ##0C8120000004C142 The processor's instruction page table entry was reloaded from another core's L3 from a remote chip due to a demand miss for a marked instruction. #1149,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3,The processor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss for a marked instruction. ##0C8140000004C142 The processor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss for a marked instruction. #1150,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3,The processor's data page table entry was reloaded from another core's L3 from a remote chip due to a demand miss for a marked instruction. ##0C8160000004C142 The processor's data page table entry was reloaded from another core's L3 from a remote chip due to a demand miss for a marked instruction. #1151,u,g,n,n,m,u,PM_MRK_INST_FROM_RL3_ALL,The processor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C8100000014C142 The processor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1152,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_ALL,The processor's instruction page table entry was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C8120000014C142 The processor's instruction page table entry was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1153,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_ALL,The processor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C8140000024C142 The processor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1154,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_ALL,The processor's data page table entry was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C8160000024C142 The processor's data page table entry was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1155,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. ##0C0220000004C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. #1156,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. ##0C0240000004C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. #1157,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. ##0C0260000004C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. #1158,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0220000014C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1159,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0240000024C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1160,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0260000024C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1161,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. ##0C4220000004C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. #1162,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. ##0C4240000004C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. #1163,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. ##0C4260000004C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. #1164,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C4220000014C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1165,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C4240000024C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1166,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C4260000024C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1167,u,g,n,n,m,u,PM_MRK_INST_FROM_RL2L3,The processor's instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. ##0C0300000004C142 The processor's instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. #1168,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. ##0C0320000004C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. #1169,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3,The processor's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. ##0C0340000004C142 The processor's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. #1170,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3,The processor's data page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. ##0C0360000004C142 The processor's data page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction. #1171,u,g,n,n,m,u,PM_MRK_INST_FROM_RL2L3_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0300000014C142 The processor's instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1172,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0320000014C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1173,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0340000024C142 The processor's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1174,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. ##0C0360000024C142 The processor's data page table entry was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction. #1175,u,g,n,n,m,u,PM_MRK_INST_FROM_RMEM,The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss for a marked instruction. ##0D4100000004C142 The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss for a marked instruction. #1176,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RMEM,The processor's instruction page table entry was reloaded from remote memory (MC slow) due to a demand miss for a marked instruction. ##0D4020000004C142 The processor's instruction page table entry was reloaded from remote memory (MC slow) due to a demand miss for a marked instruction. #1177,u,g,n,n,m,u,PM_MRK_DATA_FROM_RMEM,The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss for a marked instruction. ##0D4040000004C142 The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss for a marked instruction. #1178,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RMEM,The processor's data page table entry was reloaded from remote memory (MC slow) due to a demand miss for a marked instruction. ##0D4060000004C142 The processor's data page table entry was reloaded from remote memory (MC slow) due to a demand miss for a marked instruction. #1179,u,g,n,n,m,u,PM_MRK_INST_FROM_RMEM_ALL,The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##0D4100000014C142 The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1180,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RMEM_ALL,The processor's instruction page table entry was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##0D4020000014C142 The processor's instruction page table entry was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1181,u,g,n,n,m,u,PM_MRK_DATA_FROM_RMEM_ALL,The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##0D4040000024C142 The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1182,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RMEM_ALL,The processor's data page table entry was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##0D4060000024C142 The processor's data page table entry was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1183,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_CACHE,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss for a marked instruction. ##0D8020000004C142 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss for a marked instruction. #1184,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_CACHE,The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache due to a demand miss for a marked instruction. ##0D8040000004C142 The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache due to a demand miss for a marked instruction. #1185,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_CACHE,The processor's data page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss for a marked instruction. ##0D8060000004C142 The processor's data page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss for a marked instruction. #1186,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_CACHE_ALL,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. ##0D8020000014C142 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. #1187,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_CACHE_ALL,The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. ##0D8040000024C142 The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. #1188,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_CACHE_ALL,The processor's data page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. ##0D8060000024C142 The processor's data page table entry was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. #1189,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_MEM,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss for a marked instruction. ##0DC020000004C142 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss for a marked instruction. #1190,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_MEM,The processor's L1 data cache was reloaded from a remote chip's OpenCapp memory due to a demand miss for a marked instruction. ##0DC040000004C142 The processor's L1 data cache was reloaded from a remote chip's OpenCapp memory due to a demand miss for a marked instruction. #1191,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_MEM,The processor's data page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss for a marked instruction. ##0DC060000004C142 The processor's data page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss for a marked instruction. #1192,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_MEM_ALL,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. ##0DC020000014C142 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. #1193,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_MEM_ALL,The processor's L1 data cache was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. ##0DC040000024C142 The processor's L1 data cache was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. #1194,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_MEM_ALL,The processor's data page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. ##0DC060000024C142 The processor's data page table entry was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. #1195,u,g,n,n,m,u,PM_MRK_INST_FROM_R_OC_ANY,The processor's instruction cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##0D8100000004C142 The processor's instruction cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1196,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_ANY,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##0D8120000004C142 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1197,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_ANY,The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##0D8140000004C142 The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1198,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_ANY,The processor's data page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##0D8160000004C142 The processor's data page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1199,u,g,n,n,m,u,PM_MRK_INST_FROM_R_OC_ANY_ALL,The processor's instruction cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##0D8100000014C142 The processor's instruction cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1200,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_ANY_ALL,The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##0D8120000014C142 The processor's instruction page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1201,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_ANY_ALL,The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##0D8140000024C142 The processor's L1 data cache was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1202,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_ANY_ALL,The processor's data page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##0D8160000024C142 The processor's data page table entry was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1203,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. ##0E0020000004C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. #1204,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. ##0E0040000004C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. #1205,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. ##0E0060000004C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. #1206,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0020000014C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1207,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0040000024C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1208,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0060000024C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1209,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. ##0E4020000004C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. #1210,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. ##0E4040000004C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. #1211,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. ##0E4060000004C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction. #1212,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E4020000014C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1213,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E4040000024C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1214,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E4060000024C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1215,u,g,n,n,m,u,PM_MRK_INST_FROM_DL2,The processor's instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss for a marked instruction. ##0E0100000004C142 The processor's instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss for a marked instruction. #1216,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2,The processor's instruction page table entry was reloaded from another core's L2 from a distant chip due to a demand miss for a marked instruction. ##0E0120000004C142 The processor's instruction page table entry was reloaded from another core's L2 from a distant chip due to a demand miss for a marked instruction. #1217,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2,The processor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss for a marked instruction. ##0E0140000004C142 The processor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss for a marked instruction. #1218,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2,The processor's data page table entry was reloaded from another core's L2 from a distant chip due to a demand miss for a marked instruction. ##0E0160000004C142 The processor's data page table entry was reloaded from another core's L2 from a distant chip due to a demand miss for a marked instruction. #1219,u,g,n,n,m,u,PM_MRK_INST_FROM_DL2_ALL,The processor's instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0100000014C142 The processor's instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1220,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_ALL,The processor's instruction page table entry was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0120000014C142 The processor's instruction page table entry was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1221,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_ALL,The processor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0140000024C142 The processor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1222,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_ALL,The processor's data page table entry was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0160000024C142 The processor's data page table entry was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1223,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. ##0E8020000004C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. #1224,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. ##0E8040000004C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. #1225,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. ##0E8060000004C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. #1226,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E8020000014C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1227,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E8040000024C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1228,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E8060000024C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1229,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. ##0EC020000004C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. #1230,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. ##0EC040000004C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. #1231,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. ##0EC060000004C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction. #1232,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0EC020000014C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1233,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0EC040000024C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1234,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0EC060000024C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1235,u,g,n,n,m,u,PM_MRK_INST_FROM_DL3,The processor's instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss for a marked instruction. ##0E8100000004C142 The processor's instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss for a marked instruction. #1236,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3,The processor's instruction page table entry was reloaded from another core's L3 from a distant chip due to a demand miss for a marked instruction. ##0E8120000004C142 The processor's instruction page table entry was reloaded from another core's L3 from a distant chip due to a demand miss for a marked instruction. #1237,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3,The processor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss for a marked instruction. ##0E8140000004C142 The processor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss for a marked instruction. #1238,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3,The processor's data page table entry was reloaded from another core's L3 from a distant chip due to a demand miss for a marked instruction. ##0E8160000004C142 The processor's data page table entry was reloaded from another core's L3 from a distant chip due to a demand miss for a marked instruction. #1239,u,g,n,n,m,u,PM_MRK_INST_FROM_DL3_ALL,The processor's instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E8100000014C142 The processor's instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1240,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_ALL,The processor's instruction page table entry was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E8120000014C142 The processor's instruction page table entry was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1241,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_ALL,The processor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E8140000024C142 The processor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1242,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_ALL,The processor's data page table entry was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E8160000024C142 The processor's data page table entry was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1243,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_SHR,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. ##0E0220000004C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. #1244,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_SHR,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. ##0E0240000004C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. #1245,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_SHR,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. ##0E0260000004C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. #1246,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_SHR_ALL,The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0220000014C142 The processor's instruction page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1247,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_SHR_ALL,The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0240000024C142 The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1248,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_SHR_ALL,The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0260000024C142 The processor's data page table entry was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1249,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_MOD,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. ##0E4220000004C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. #1250,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_MOD,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. ##0E4240000004C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. #1251,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_MOD,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. ##0E4260000004C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. #1252,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_MOD_ALL,The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E4220000014C142 The processor's instruction page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1253,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_MOD_ALL,The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E4240000024C142 The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1254,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_MOD_ALL,The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E4260000024C142 The processor's data page table entry was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1255,u,g,n,n,m,u,PM_MRK_INST_FROM_DL2L3,The processor's instruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. ##0E0300000004C142 The processor's instruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. #1256,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. ##0E0320000004C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. #1257,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3,The processor's L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. ##0E0340000004C142 The processor's L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. #1258,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3,The processor's data page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. ##0E0360000004C142 The processor's data page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction. #1259,u,g,n,n,m,u,PM_MRK_INST_FROM_DL2L3_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0300000014C142 The processor's instruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1260,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0320000014C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1261,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0340000024C142 The processor's L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1262,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. ##0E0360000024C142 The processor's data page table entry was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction. #1263,u,g,n,n,m,u,PM_MRK_INST_FROM_DMEM,The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss for a marked instruction. ##0F4100000004C142 The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss for a marked instruction. #1264,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DMEM,The processor's instruction page table entry was reloaded from distant memory (MC slow) due to a demand miss for a marked instruction. ##0F4020000004C142 The processor's instruction page table entry was reloaded from distant memory (MC slow) due to a demand miss for a marked instruction. #1265,u,g,n,n,m,u,PM_MRK_DATA_FROM_DMEM,The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss for a marked instruction. ##0F4040000004C142 The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss for a marked instruction. #1266,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DMEM,The processor's data page table entry was reloaded from distant memory (MC slow) due to a demand miss for a marked instruction. ##0F4060000004C142 The processor's data page table entry was reloaded from distant memory (MC slow) due to a demand miss for a marked instruction. #1267,u,g,n,n,m,u,PM_MRK_INST_FROM_DMEM_ALL,The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##0F4100000014C142 The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1268,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DMEM_ALL,The processor's instruction page table entry was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##0F4020000014C142 The processor's instruction page table entry was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1269,u,g,n,n,m,u,PM_MRK_DATA_FROM_DMEM_ALL,The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##0F4040000024C142 The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1270,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DMEM_ALL,The processor's data page table entry was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##0F4060000024C142 The processor's data page table entry was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1271,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_CACHE,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss for a marked instruction. ##0F8020000004C142 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss for a marked instruction. #1272,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_CACHE,The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache due to a demand miss for a marked instruction. ##0F8040000004C142 The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache due to a demand miss for a marked instruction. #1273,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_CACHE,The processor's data page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss for a marked instruction. ##0F8060000004C142 The processor's data page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss for a marked instruction. #1274,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_CACHE_ALL,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. ##0F8020000014C142 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. #1275,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_CACHE_ALL,The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. ##0F8040000024C142 The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. #1276,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_CACHE_ALL,The processor's data page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. ##0F8060000024C142 The processor's data page table entry was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload for a marked instruction. #1277,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_MEM,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss for a marked instruction. ##0FC020000004C142 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss for a marked instruction. #1278,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_MEM,The processor's L1 data cache was reloaded from a distant chip's OpenCapp memory due to a demand miss for a marked instruction. ##0FC040000004C142 The processor's L1 data cache was reloaded from a distant chip's OpenCapp memory due to a demand miss for a marked instruction. #1279,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_MEM,The processor's data page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss for a marked instruction. ##0FC060000004C142 The processor's data page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss for a marked instruction. #1280,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_MEM_ALL,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. ##0FC020000014C142 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. #1281,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_MEM_ALL,The processor's L1 data cache was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. ##0FC040000024C142 The processor's L1 data cache was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. #1282,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_MEM_ALL,The processor's data page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. ##0FC060000024C142 The processor's data page table entry was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload for a marked instruction. #1283,u,g,n,n,m,u,PM_MRK_INST_FROM_D_OC_ANY,The processor's instruction cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##0F8100000004C142 The processor's instruction cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1284,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_ANY,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##0F8120000004C142 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1285,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_ANY,The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##0F8140000004C142 The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1286,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_ANY,The processor's data page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss for a marked instruction. ##0F8160000004C142 The processor's data page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss for a marked instruction. #1287,u,g,n,n,m,u,PM_MRK_INST_FROM_D_OC_ANY_ALL,The processor's instruction cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##0F8100000014C142 The processor's instruction cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1288,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_ANY_ALL,The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##0F8120000014C142 The processor's instruction page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1289,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_ANY_ALL,The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##0F8140000024C142 The processor's L1 data cache was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1290,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_ANY_ALL,The processor's data page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. ##0F8160000024C142 The processor's data page table entry was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload for a marked instruction. #1291,u,g,n,n,m,u,PM_MRK_INST_FROM_ONCHIP_CACHE,The processor's instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss for a marked instruction. ##080B00000004C142 The processor's instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss for a marked instruction. #1292,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_ONCHIP_CACHE,The processor's instruction page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss for a marked instruction. ##080B20000004C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss for a marked instruction. #1293,u,g,n,n,m,u,PM_MRK_DATA_FROM_ONCHIP_CACHE,The processor's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss for a marked instruction. ##080B40000004C142 The processor's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss for a marked instruction. #1294,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_ONCHIP_CACHE,The processor's data page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss for a marked instruction. ##080B60000004C142 The processor's data page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss for a marked instruction. #1295,u,g,n,n,m,u,PM_MRK_INST_FROM_ONCHIP_CACHE_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload for a marked instruction. ##080B00000014C142 The processor's instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload for a marked instruction. #1296,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_ONCHIP_CACHE_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload for a marked instruction. ##080B20000014C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload for a marked instruction. #1297,u,g,n,n,m,u,PM_MRK_DATA_FROM_ONCHIP_CACHE_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload for a marked instruction. ##080B40000024C142 The processor's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload for a marked instruction. #1298,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_ONCHIP_CACHE_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload for a marked instruction. ##080B60000024C142 The processor's data page table entry was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload for a marked instruction. #1299,u,g,n,n,m,u,PM_MRK_INST_FROM_OFFCHIP_CACHE,The processor's instruction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss for a marked instruction. ##0C0B00000004C142 The processor's instruction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss for a marked instruction. #1300,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_OFFCHIP_CACHE,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss for a marked instruction. ##0C0B20000004C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss for a marked instruction. #1301,u,g,n,n,m,u,PM_MRK_DATA_FROM_OFFCHIP_CACHE,The processor's L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss for a marked instruction. ##0C0B40000004C142 The processor's L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss for a marked instruction. #1302,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_OFFCHIP_CACHE,The processor's data page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss for a marked instruction. ##0C0B60000004C142 The processor's data page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss for a marked instruction. #1303,u,g,n,n,m,u,PM_MRK_INST_FROM_OFFCHIP_CACHE_ALL,The processor's instruction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload for a marked instruction. ##0C0B00000014C142 The processor's instruction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload for a marked instruction. #1304,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_OFFCHIP_CACHE_ALL,The processor's instruction page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload for a marked instruction. ##0C0B20000014C142 The processor's instruction page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload for a marked instruction. #1305,u,g,n,n,m,u,PM_MRK_DATA_FROM_OFFCHIP_CACHE_ALL,The processor's L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload for a marked instruction. ##0C0B40000024C142 The processor's L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload for a marked instruction. #1306,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_OFFCHIP_CACHE_ALL,The processor's data page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload for a marked instruction. ##0C0B60000024C142 The processor's data page table entry was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload for a marked instruction. #1307,u,g,n,n,m,u,PM_MRK_INST_FROM_ANY_MEMORY,The processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss for a marked instruction. ##095900000004C142 The processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss for a marked instruction. #1308,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_ANY_MEMORY,The processor's instruction page table entry was reloaded from any chip's memory (MC slow) due to a demand miss for a marked instruction. ##095820000004C142 The processor's instruction page table entry was reloaded from any chip's memory (MC slow) due to a demand miss for a marked instruction. #1309,u,g,n,n,m,u,PM_MRK_DATA_FROM_ANY_MEMORY,The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss for a marked instruction. ##095840000004C142 The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss for a marked instruction. #1310,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_ANY_MEMORY,The processor's data page table entry was reloaded from any chip's memory (MC slow) due to a demand miss for a marked instruction. ##095860000004C142 The processor's data page table entry was reloaded from any chip's memory (MC slow) due to a demand miss for a marked instruction. #1311,u,g,n,n,m,u,PM_MRK_INST_FROM_ANY_MEMORY_ALL,The processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##095900000014C142 The processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1312,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_ANY_MEMORY_ALL,The processor's instruction page table entry was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##095820000014C142 The processor's instruction page table entry was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1313,u,g,n,n,m,u,PM_MRK_DATA_FROM_ANY_MEMORY_ALL,The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##095840000024C142 The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1314,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_ANY_MEMORY_ALL,The processor's data page table entry was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. ##095860000024C142 The processor's data page table entry was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload for a marked instruction. #1315,u,g,n,n,m,u,PM_MRK_INST_FROM_L2_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local core's L2 due to a demand miss. Divide this count by PM_MRK_INST_FROM_L2 to obtain the average L2 latency for instruction reloads. ##000300000004C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local core's L2 due to a demand miss. Divide this count by PM_MRK_INST_FROM_L2 to obtain the average L2 latency for instruction reloads. #1316,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2 to obtain the average L2 latency for instruction page table reloads. ##000320000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2 to obtain the average L2 latency for instruction page table reloads. #1317,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2 to obtain the average L2 latency for data reloads. ##000340000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2 to obtain the average L2 latency for data reloads. #1318,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2 to obtain the average L2 latency for data page table reloads. ##000360000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2 to obtain the average L2 latency for data page table reloads. #1319,u,g,n,n,m,u,PM_MRK_INST_FROM_L2_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L2_ALL to obtain the average L2_ALL latency for instruction reloads. ##000300000014C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L2_ALL to obtain the average L2_ALL latency for instruction reloads. #1320,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2_ALL to obtain the average L2_ALL latency for instruction page table reloads. ##000320000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2_ALL to obtain the average L2_ALL latency for instruction page table reloads. #1321,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2_ALL to obtain the average L2_ALL latency for data reloads. ##000340000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2_ALL to obtain the average L2_ALL latency for data reloads. #1322,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2_ALL to obtain the average L2_ALL latency for data page table reloads. ##000360000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2_ALL to obtain the average L2_ALL latency for data page table reloads. #1323,u,g,n,n,m,u,PM_MRK_INST_FROM_L1MISS_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a source beyond the local core's L1 due to a demand miss. Divide this count by PM_MRK_INST_FROM_L1MISS to obtain the average L1MISS latency for instruction reloads. ##003F00000004C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a source beyond the local core's L1 due to a demand miss. Divide this count by PM_MRK_INST_FROM_L1MISS to obtain the average L1MISS latency for instruction reloads. #1324,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L1MISS_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a source beyond the local core's L1 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L1MISS to obtain the average L1MISS latency for instruction page table reloads. ##003F20000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a source beyond the local core's L1 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L1MISS to obtain the average L1MISS latency for instruction page table reloads. #1325,u,g,n,n,m,u,PM_MRK_DATA_FROM_L1MISS_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a source beyond the local core's L1 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L1MISS to obtain the average L1MISS latency for data reloads. ##003F40000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a source beyond the local core's L1 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L1MISS to obtain the average L1MISS latency for data reloads. #1326,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L1MISS_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a source beyond the local core's L1 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L1MISS to obtain the average L1MISS latency for data page table reloads. ##003F60000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a source beyond the local core's L1 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L1MISS to obtain the average L1MISS latency for data page table reloads. #1327,u,g,n,n,m,u,PM_MRK_INST_FROM_L1MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L1MISS_ALL to obtain the average L1MISS_ALL latency for instruction reloads. ##003F00000014C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L1MISS_ALL to obtain the average L1MISS_ALL latency for instruction reloads. #1328,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L1MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L1MISS_ALL to obtain the average L1MISS_ALL latency for instruction page table reloads. ##003F20000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L1MISS_ALL to obtain the average L1MISS_ALL latency for instruction page table reloads. #1329,u,g,n,n,m,u,PM_MRK_DATA_FROM_L1MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L1MISS_ALL to obtain the average L1MISS_ALL latency for data reloads. ##003F40000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L1MISS_ALL to obtain the average L1MISS_ALL latency for data reloads. #1330,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L1MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L1MISS_ALL to obtain the average L1MISS_ALL latency for data page table reloads. ##003F60000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L1MISS_ALL to obtain the average L1MISS_ALL latency for data page table reloads. #1331,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_NO_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2_NO_CONFLICT to obtain the average L2_NO_CONFLICT latency for instruction page table reloads. ##000020000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2_NO_CONFLICT to obtain the average L2_NO_CONFLICT latency for instruction page table reloads. #1332,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2_NO_CONFLICT to obtain the average L2_NO_CONFLICT latency for data reloads. ##000040000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2_NO_CONFLICT to obtain the average L2_NO_CONFLICT latency for data reloads. #1333,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_NO_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2_NO_CONFLICT to obtain the average L2_NO_CONFLICT latency for data page table reloads. ##000060000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2_NO_CONFLICT to obtain the average L2_NO_CONFLICT latency for data page table reloads. #1334,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_NO_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2_NO_CONFLICT_ALL to obtain the average L2_NO_CONFLICT_ALL latency for instruction page table reloads. ##000020000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2_NO_CONFLICT_ALL to obtain the average L2_NO_CONFLICT_ALL latency for instruction page table reloads. #1335,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_NO_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2_NO_CONFLICT_ALL to obtain the average L2_NO_CONFLICT_ALL latency for data reloads. ##000040000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2_NO_CONFLICT_ALL to obtain the average L2_NO_CONFLICT_ALL latency for data reloads. #1336,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_NO_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2_NO_CONFLICT_ALL to obtain the average L2_NO_CONFLICT_ALL latency for data page table reloads. ##000060000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2_NO_CONFLICT_ALL to obtain the average L2_NO_CONFLICT_ALL latency for data page table reloads. #1337,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_MEPF_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2_MEPF to obtain the average L2_MEPF latency for instruction page table reloads. ##004020000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2_MEPF to obtain the average L2_MEPF latency for instruction page table reloads. #1338,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_MEPF_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2_MEPF to obtain the average L2_MEPF latency for data reloads. ##004040000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2_MEPF to obtain the average L2_MEPF latency for data reloads. #1339,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_MEPF_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2_MEPF to obtain the average L2_MEPF latency for data page table reloads. ##004060000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2_MEPF to obtain the average L2_MEPF latency for data page table reloads. #1340,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_MEPF_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2_MEPF_ALL to obtain the average L2_MEPF_ALL latency for instruction page table reloads. ##004020000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2_MEPF_ALL to obtain the average L2_MEPF_ALL latency for instruction page table reloads. #1341,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_MEPF_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2_MEPF_ALL to obtain the average L2_MEPF_ALL latency for data reloads. ##004040000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2_MEPF_ALL to obtain the average L2_MEPF_ALL latency for data reloads. #1342,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_MEPF_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2_MEPF_ALL to obtain the average L2_MEPF_ALL latency for data page table reloads. ##004060000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2_MEPF_ALL to obtain the average L2_MEPF_ALL latency for data page table reloads. #1343,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_LDHITST_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2_LDHITST_CONFLICT to obtain the average L2_LDHITST_CONFLICT latency for instruction page table reloads. ##008020000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2_LDHITST_CONFLICT to obtain the average L2_LDHITST_CONFLICT latency for instruction page table reloads. #1344,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_LDHITST_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2_LDHITST_CONFLICT to obtain the average L2_LDHITST_CONFLICT latency for data reloads. ##008040000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2_LDHITST_CONFLICT to obtain the average L2_LDHITST_CONFLICT latency for data reloads. #1345,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_LDHITST_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2_LDHITST_CONFLICT to obtain the average L2_LDHITST_CONFLICT latency for data page table reloads. ##008060000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2_LDHITST_CONFLICT to obtain the average L2_LDHITST_CONFLICT latency for data page table reloads. #1346,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_LDHITST_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2_LDHITST_CONFLICT_ALL to obtain the average L2_LDHITST_CONFLICT_ALL latency for instruction page table reloads. ##008020000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2_LDHITST_CONFLICT_ALL to obtain the average L2_LDHITST_CONFLICT_ALL latency for instruction page table reloads. #1347,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_LDHITST_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2_LDHITST_CONFLICT_ALL to obtain the average L2_LDHITST_CONFLICT_ALL latency for data reloads. ##008040000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2_LDHITST_CONFLICT_ALL to obtain the average L2_LDHITST_CONFLICT_ALL latency for data reloads. #1348,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_LDHITST_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2_LDHITST_CONFLICT_ALL to obtain the average L2_LDHITST_CONFLICT_ALL latency for data page table reloads. ##008060000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2_LDHITST_CONFLICT_ALL to obtain the average L2_LDHITST_CONFLICT_ALL latency for data page table reloads. #1349,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_OTHER_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2_OTHER_CONFLICT to obtain the average L2_OTHER_CONFLICT latency for instruction page table reloads. ##00C020000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2_OTHER_CONFLICT to obtain the average L2_OTHER_CONFLICT latency for instruction page table reloads. #1350,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_OTHER_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2_OTHER_CONFLICT to obtain the average L2_OTHER_CONFLICT latency for data reloads. ##00C040000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2_OTHER_CONFLICT to obtain the average L2_OTHER_CONFLICT latency for data reloads. #1351,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_OTHER_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2_OTHER_CONFLICT to obtain the average L2_OTHER_CONFLICT latency for data page table reloads. ##00C060000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2_OTHER_CONFLICT to obtain the average L2_OTHER_CONFLICT latency for data page table reloads. #1352,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2_OTHER_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2_OTHER_CONFLICT_ALL to obtain the average L2_OTHER_CONFLICT_ALL latency for instruction page table reloads. ##00C020000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2_OTHER_CONFLICT_ALL to obtain the average L2_OTHER_CONFLICT_ALL latency for instruction page table reloads. #1353,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2_OTHER_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2_OTHER_CONFLICT_ALL to obtain the average L2_OTHER_CONFLICT_ALL latency for data reloads. ##00C040000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2_OTHER_CONFLICT_ALL to obtain the average L2_OTHER_CONFLICT_ALL latency for data reloads. #1354,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2_OTHER_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2_OTHER_CONFLICT_ALL to obtain the average L2_OTHER_CONFLICT_ALL latency for data page table reloads. ##00C060000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2_OTHER_CONFLICT_ALL to obtain the average L2_OTHER_CONFLICT_ALL latency for data page table reloads. #1355,u,g,n,n,m,u,PM_MRK_INST_FROM_L2MISS_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a source beyond the local core's L2 due to a demand miss. Divide this count by PM_MRK_INST_FROM_L2MISS to obtain the average L2MISS latency for instruction reloads. ##000380000004C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a source beyond the local core's L2 due to a demand miss. Divide this count by PM_MRK_INST_FROM_L2MISS to obtain the average L2MISS latency for instruction reloads. #1356,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2MISS_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a source beyond the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2MISS to obtain the average L2MISS latency for instruction page table reloads. ##0003A0000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a source beyond the local core's L2 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L2MISS to obtain the average L2MISS latency for instruction page table reloads. #1357,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2MISS_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a source beyond the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2MISS to obtain the average L2MISS latency for data reloads. ##0003C0000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a source beyond the local core's L2 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L2MISS to obtain the average L2MISS latency for data reloads. #1358,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2MISS_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a source beyond the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2MISS to obtain the average L2MISS latency for data page table reloads. ##0003E0000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a source beyond the local core's L2 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L2MISS to obtain the average L2MISS latency for data page table reloads. #1359,u,g,n,n,m,u,PM_MRK_INST_FROM_L2MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L2MISS_ALL to obtain the average L2MISS_ALL latency for instruction reloads. ##000380000014C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L2MISS_ALL to obtain the average L2MISS_ALL latency for instruction reloads. #1360,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L2MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2MISS_ALL to obtain the average L2MISS_ALL latency for instruction page table reloads. ##0003A0000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L2MISS_ALL to obtain the average L2MISS_ALL latency for instruction page table reloads. #1361,u,g,n,n,m,u,PM_MRK_DATA_FROM_L2MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2MISS_ALL to obtain the average L2MISS_ALL latency for data reloads. ##0003C0000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L2MISS_ALL to obtain the average L2MISS_ALL latency for data reloads. #1362,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L2MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2MISS_ALL to obtain the average L2MISS_ALL latency for data page table reloads. ##0003E0000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L2MISS_ALL to obtain the average L2MISS_ALL latency for data page table reloads. #1363,u,g,n,n,m,u,PM_MRK_INST_FROM_L3_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_INST_FROM_L3 to obtain the average L3 latency for instruction reloads. ##010300000004C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_INST_FROM_L3 to obtain the average L3 latency for instruction reloads. #1364,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L3 to obtain the average L3 latency for instruction page table reloads. ##010320000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L3 to obtain the average L3 latency for instruction page table reloads. #1365,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L3 to obtain the average L3 latency for data reloads. ##010340000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L3 to obtain the average L3 latency for data reloads. #1366,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L3 to obtain the average L3 latency for data page table reloads. ##010360000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L3 to obtain the average L3 latency for data page table reloads. #1367,u,g,n,n,m,u,PM_MRK_INST_FROM_L3_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L3_ALL to obtain the average L3_ALL latency for instruction reloads. ##010300000014C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L3_ALL to obtain the average L3_ALL latency for instruction reloads. #1368,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L3_ALL to obtain the average L3_ALL latency for instruction page table reloads. ##010320000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L3_ALL to obtain the average L3_ALL latency for instruction page table reloads. #1369,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L3_ALL to obtain the average L3_ALL latency for data reloads. ##010340000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L3_ALL to obtain the average L3_ALL latency for data reloads. #1370,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L3_ALL to obtain the average L3_ALL latency for data page table reloads. ##010360000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L3_ALL to obtain the average L3_ALL latency for data page table reloads. #1371,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_NO_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L3_NO_CONFLICT to obtain the average L3_NO_CONFLICT latency for instruction page table reloads. ##010020000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L3_NO_CONFLICT to obtain the average L3_NO_CONFLICT latency for instruction page table reloads. #1372,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L3_NO_CONFLICT to obtain the average L3_NO_CONFLICT latency for data reloads. ##010040000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L3_NO_CONFLICT to obtain the average L3_NO_CONFLICT latency for data reloads. #1373,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_NO_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L3_NO_CONFLICT to obtain the average L3_NO_CONFLICT latency for data page table reloads. ##010060000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L3_NO_CONFLICT to obtain the average L3_NO_CONFLICT latency for data page table reloads. #1374,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_NO_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L3_NO_CONFLICT_ALL to obtain the average L3_NO_CONFLICT_ALL latency for instruction page table reloads. ##010020000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L3_NO_CONFLICT_ALL to obtain the average L3_NO_CONFLICT_ALL latency for instruction page table reloads. #1375,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_NO_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L3_NO_CONFLICT_ALL to obtain the average L3_NO_CONFLICT_ALL latency for data reloads. ##010040000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L3_NO_CONFLICT_ALL to obtain the average L3_NO_CONFLICT_ALL latency for data reloads. #1376,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_NO_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L3_NO_CONFLICT_ALL to obtain the average L3_NO_CONFLICT_ALL latency for data page table reloads. ##010060000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L3_NO_CONFLICT_ALL to obtain the average L3_NO_CONFLICT_ALL latency for data page table reloads. #1377,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_MEPF_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L3_MEPF to obtain the average L3_MEPF latency for instruction page table reloads. ##014020000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L3_MEPF to obtain the average L3_MEPF latency for instruction page table reloads. #1378,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_MEPF_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L3_MEPF to obtain the average L3_MEPF latency for data reloads. ##014040000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L3_MEPF to obtain the average L3_MEPF latency for data reloads. #1379,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_MEPF_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L3_MEPF to obtain the average L3_MEPF latency for data page table reloads. ##014060000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L3_MEPF to obtain the average L3_MEPF latency for data page table reloads. #1380,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_MEPF_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L3_MEPF_ALL to obtain the average L3_MEPF_ALL latency for instruction page table reloads. ##014020000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L3_MEPF_ALL to obtain the average L3_MEPF_ALL latency for instruction page table reloads. #1381,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_MEPF_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L3_MEPF_ALL to obtain the average L3_MEPF_ALL latency for data reloads. ##014040000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L3_MEPF_ALL to obtain the average L3_MEPF_ALL latency for data reloads. #1382,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_MEPF_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L3_MEPF_ALL to obtain the average L3_MEPF_ALL latency for data page table reloads. ##014060000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L3_MEPF_ALL to obtain the average L3_MEPF_ALL latency for data page table reloads. #1383,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L3_CONFLICT to obtain the average L3_CONFLICT latency for instruction page table reloads. ##01C020000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L3_CONFLICT to obtain the average L3_CONFLICT latency for instruction page table reloads. #1384,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L3_CONFLICT to obtain the average L3_CONFLICT latency for data reloads. ##01C040000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L3_CONFLICT to obtain the average L3_CONFLICT latency for data reloads. #1385,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_CONFLICT_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L3_CONFLICT to obtain the average L3_CONFLICT latency for data page table reloads. ##01C060000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L3 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L3_CONFLICT to obtain the average L3_CONFLICT latency for data page table reloads. #1386,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L3_CONFLICT_ALL to obtain the average L3_CONFLICT_ALL latency for instruction page table reloads. ##01C020000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L3_CONFLICT_ALL to obtain the average L3_CONFLICT_ALL latency for instruction page table reloads. #1387,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L3_CONFLICT_ALL to obtain the average L3_CONFLICT_ALL latency for data reloads. ##01C040000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L3_CONFLICT_ALL to obtain the average L3_CONFLICT_ALL latency for data reloads. #1388,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3_CONFLICT_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L3_CONFLICT_ALL to obtain the average L3_CONFLICT_ALL latency for data page table reloads. ##01C060000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L3_CONFLICT_ALL to obtain the average L3_CONFLICT_ALL latency for data page table reloads. #1389,u,g,n,n,m,u,PM_MRK_INST_FROM_L3MISS_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from beyond the local core's L3 due to a demand miss. Divide this count by PM_MRK_INST_FROM_L3MISS to obtain the average L3MISS latency for instruction reloads. ##000780000004C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from beyond the local core's L3 due to a demand miss. Divide this count by PM_MRK_INST_FROM_L3MISS to obtain the average L3MISS latency for instruction reloads. #1390,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3MISS_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from beyond the local core's L3 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L3MISS to obtain the average L3MISS latency for instruction page table reloads. ##0007A0000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from beyond the local core's L3 due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L3MISS to obtain the average L3MISS latency for instruction page table reloads. #1391,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3MISS_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from beyond the local core's L3 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L3MISS to obtain the average L3MISS latency for data reloads. ##0007C0000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from beyond the local core's L3 due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L3MISS to obtain the average L3MISS latency for data reloads. #1392,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3MISS_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from beyond the local core's L3 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L3MISS to obtain the average L3MISS latency for data page table reloads. ##0007E0000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from beyond the local core's L3 due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L3MISS to obtain the average L3MISS latency for data page table reloads. #1393,u,g,n,n,m,u,PM_MRK_INST_FROM_L3MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L3MISS_ALL to obtain the average L3MISS_ALL latency for instruction reloads. ##000780000014C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L3MISS_ALL to obtain the average L3MISS_ALL latency for instruction reloads. #1394,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L3MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L3MISS_ALL to obtain the average L3MISS_ALL latency for instruction page table reloads. ##0007A0000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L3MISS_ALL to obtain the average L3MISS_ALL latency for instruction page table reloads. #1395,u,g,n,n,m,u,PM_MRK_DATA_FROM_L3MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L3MISS_ALL to obtain the average L3MISS_ALL latency for data reloads. ##0007C0000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L3MISS_ALL to obtain the average L3MISS_ALL latency for data reloads. #1396,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L3MISS_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L3MISS_ALL to obtain the average L3MISS_ALL latency for data page table reloads. ##0007E0000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L3MISS_ALL to obtain the average L3MISS_ALL latency for data page table reloads. #1397,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT_SHR to obtain the average L21_REGENT_SHR latency for instruction page table reloads. ##080020000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT_SHR to obtain the average L21_REGENT_SHR latency for instruction page table reloads. #1398,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_REGENT_SHR to obtain the average L21_REGENT_SHR latency for data reloads. ##080040000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_REGENT_SHR to obtain the average L21_REGENT_SHR latency for data reloads. #1399,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT_SHR to obtain the average L21_REGENT_SHR latency for data page table reloads. ##080060000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT_SHR to obtain the average L21_REGENT_SHR latency for data page table reloads. #1400,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT_SHR_ALL to obtain the average L21_REGENT_SHR_ALL latency for instruction page table reloads. ##080020000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT_SHR_ALL to obtain the average L21_REGENT_SHR_ALL latency for instruction page table reloads. #1401,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_REGENT_SHR_ALL to obtain the average L21_REGENT_SHR_ALL latency for data reloads. ##080040000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_REGENT_SHR_ALL to obtain the average L21_REGENT_SHR_ALL latency for data reloads. #1402,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT_SHR_ALL to obtain the average L21_REGENT_SHR_ALL latency for data page table reloads. ##080060000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT_SHR_ALL to obtain the average L21_REGENT_SHR_ALL latency for data page table reloads. #1403,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT_MOD to obtain the average L21_REGENT_MOD latency for instruction page table reloads. ##084020000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT_MOD to obtain the average L21_REGENT_MOD latency for instruction page table reloads. #1404,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_REGENT_MOD to obtain the average L21_REGENT_MOD latency for data reloads. ##084040000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_REGENT_MOD to obtain the average L21_REGENT_MOD latency for data reloads. #1405,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT_MOD to obtain the average L21_REGENT_MOD latency for data page table reloads. ##084060000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT_MOD to obtain the average L21_REGENT_MOD latency for data page table reloads. #1406,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT_MOD_ALL to obtain the average L21_REGENT_MOD_ALL latency for instruction page table reloads. ##084020000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT_MOD_ALL to obtain the average L21_REGENT_MOD_ALL latency for instruction page table reloads. #1407,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_REGENT_MOD_ALL to obtain the average L21_REGENT_MOD_ALL latency for data reloads. ##084040000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_REGENT_MOD_ALL to obtain the average L21_REGENT_MOD_ALL latency for data reloads. #1408,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT_MOD_ALL to obtain the average L21_REGENT_MOD_ALL latency for data page table reloads. ##084060000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT_MOD_ALL to obtain the average L21_REGENT_MOD_ALL latency for data page table reloads. #1409,u,g,n,n,m,u,PM_MRK_INST_FROM_L21_REGENT_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_L21_REGENT to obtain the average L21_REGENT latency for instruction reloads. ##080100000004C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_L21_REGENT to obtain the average L21_REGENT latency for instruction reloads. #1410,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT to obtain the average L21_REGENT latency for instruction page table reloads. ##080120000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT to obtain the average L21_REGENT latency for instruction page table reloads. #1411,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_REGENT to obtain the average L21_REGENT latency for data reloads. ##080140000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_REGENT to obtain the average L21_REGENT latency for data reloads. #1412,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT to obtain the average L21_REGENT latency for data page table reloads. ##080160000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT to obtain the average L21_REGENT latency for data page table reloads. #1413,u,g,n,n,m,u,PM_MRK_INST_FROM_L21_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L21_REGENT_ALL to obtain the average L21_REGENT_ALL latency for instruction reloads. ##080100000014C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L21_REGENT_ALL to obtain the average L21_REGENT_ALL latency for instruction reloads. #1414,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT_ALL to obtain the average L21_REGENT_ALL latency for instruction page table reloads. ##080120000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_REGENT_ALL to obtain the average L21_REGENT_ALL latency for instruction page table reloads. #1415,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_REGENT_ALL to obtain the average L21_REGENT_ALL latency for data reloads. ##080140000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_REGENT_ALL to obtain the average L21_REGENT_ALL latency for data reloads. #1416,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT_ALL to obtain the average L21_REGENT_ALL latency for data page table reloads. ##080160000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_REGENT_ALL to obtain the average L21_REGENT_ALL latency for data page table reloads. #1417,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT_SHR to obtain the average L31_REGENT_SHR latency for instruction page table reloads. ##088020000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT_SHR to obtain the average L31_REGENT_SHR latency for instruction page table reloads. #1418,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_REGENT_SHR to obtain the average L31_REGENT_SHR latency for data reloads. ##088040000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_REGENT_SHR to obtain the average L31_REGENT_SHR latency for data reloads. #1419,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT_SHR to obtain the average L31_REGENT_SHR latency for data page table reloads. ##088060000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT_SHR to obtain the average L31_REGENT_SHR latency for data page table reloads. #1420,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT_SHR_ALL to obtain the average L31_REGENT_SHR_ALL latency for instruction page table reloads. ##088020000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT_SHR_ALL to obtain the average L31_REGENT_SHR_ALL latency for instruction page table reloads. #1421,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_REGENT_SHR_ALL to obtain the average L31_REGENT_SHR_ALL latency for data reloads. ##088040000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_REGENT_SHR_ALL to obtain the average L31_REGENT_SHR_ALL latency for data reloads. #1422,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT_SHR_ALL to obtain the average L31_REGENT_SHR_ALL latency for data page table reloads. ##088060000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT_SHR_ALL to obtain the average L31_REGENT_SHR_ALL latency for data page table reloads. #1423,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT_MOD to obtain the average L31_REGENT_MOD latency for instruction page table reloads. ##08C020000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT_MOD to obtain the average L31_REGENT_MOD latency for instruction page table reloads. #1424,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_REGENT_MOD to obtain the average L31_REGENT_MOD latency for data reloads. ##08C040000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_REGENT_MOD to obtain the average L31_REGENT_MOD latency for data reloads. #1425,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT_MOD to obtain the average L31_REGENT_MOD latency for data page table reloads. ##08C060000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT_MOD to obtain the average L31_REGENT_MOD latency for data page table reloads. #1426,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT_MOD_ALL to obtain the average L31_REGENT_MOD_ALL latency for instruction page table reloads. ##08C020000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT_MOD_ALL to obtain the average L31_REGENT_MOD_ALL latency for instruction page table reloads. #1427,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_REGENT_MOD_ALL to obtain the average L31_REGENT_MOD_ALL latency for data reloads. ##08C040000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_REGENT_MOD_ALL to obtain the average L31_REGENT_MOD_ALL latency for data reloads. #1428,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT_MOD_ALL to obtain the average L31_REGENT_MOD_ALL latency for data page table reloads. ##08C060000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT_MOD_ALL to obtain the average L31_REGENT_MOD_ALL latency for data page table reloads. #1429,u,g,n,n,m,u,PM_MRK_INST_FROM_L31_REGENT_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_L31_REGENT to obtain the average L31_REGENT latency for instruction reloads. ##088100000004C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_L31_REGENT to obtain the average L31_REGENT latency for instruction reloads. #1430,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT to obtain the average L31_REGENT latency for instruction page table reloads. ##088120000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT to obtain the average L31_REGENT latency for instruction page table reloads. #1431,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_REGENT to obtain the average L31_REGENT latency for data reloads. ##088140000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_REGENT to obtain the average L31_REGENT latency for data reloads. #1432,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT to obtain the average L31_REGENT latency for data page table reloads. ##088160000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT to obtain the average L31_REGENT latency for data page table reloads. #1433,u,g,n,n,m,u,PM_MRK_INST_FROM_L31_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L31_REGENT_ALL to obtain the average L31_REGENT_ALL latency for instruction reloads. ##088100000014C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L31_REGENT_ALL to obtain the average L31_REGENT_ALL latency for instruction reloads. #1434,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT_ALL to obtain the average L31_REGENT_ALL latency for instruction page table reloads. ##088120000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_REGENT_ALL to obtain the average L31_REGENT_ALL latency for instruction page table reloads. #1435,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_REGENT_ALL to obtain the average L31_REGENT_ALL latency for data reloads. ##088140000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_REGENT_ALL to obtain the average L31_REGENT_ALL latency for data reloads. #1436,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT_ALL to obtain the average L31_REGENT_ALL latency for data page table reloads. ##088160000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_REGENT_ALL to obtain the average L31_REGENT_ALL latency for data page table reloads. #1437,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3_SHR to obtain the average REGENT_L2L3_SHR latency for instruction page table reloads. ##080220000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3_SHR to obtain the average REGENT_L2L3_SHR latency for instruction page table reloads. #1438,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3_SHR to obtain the average REGENT_L2L3_SHR latency for data reloads. ##080240000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3_SHR to obtain the average REGENT_L2L3_SHR latency for data reloads. #1439,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3_SHR to obtain the average REGENT_L2L3_SHR latency for data page table reloads. ##080260000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3_SHR to obtain the average REGENT_L2L3_SHR latency for data page table reloads. #1440,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3_SHR_ALL to obtain the average REGENT_L2L3_SHR_ALL latency for instruction page table reloads. ##080220000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3_SHR_ALL to obtain the average REGENT_L2L3_SHR_ALL latency for instruction page table reloads. #1441,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3_SHR_ALL to obtain the average REGENT_L2L3_SHR_ALL latency for data reloads. ##080240000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3_SHR_ALL to obtain the average REGENT_L2L3_SHR_ALL latency for data reloads. #1442,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3_SHR_ALL to obtain the average REGENT_L2L3_SHR_ALL latency for data page table reloads. ##080260000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3_SHR_ALL to obtain the average REGENT_L2L3_SHR_ALL latency for data page table reloads. #1443,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3_MOD to obtain the average REGENT_L2L3_MOD latency for instruction page table reloads. ##084220000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3_MOD to obtain the average REGENT_L2L3_MOD latency for instruction page table reloads. #1444,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3_MOD to obtain the average REGENT_L2L3_MOD latency for data reloads. ##084240000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3_MOD to obtain the average REGENT_L2L3_MOD latency for data reloads. #1445,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3_MOD to obtain the average REGENT_L2L3_MOD latency for data page table reloads. ##084260000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3_MOD to obtain the average REGENT_L2L3_MOD latency for data page table reloads. #1446,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3_MOD_ALL to obtain the average REGENT_L2L3_MOD_ALL latency for instruction page table reloads. ##084220000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3_MOD_ALL to obtain the average REGENT_L2L3_MOD_ALL latency for instruction page table reloads. #1447,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3_MOD_ALL to obtain the average REGENT_L2L3_MOD_ALL latency for data reloads. ##084240000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3_MOD_ALL to obtain the average REGENT_L2L3_MOD_ALL latency for data reloads. #1448,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3_MOD_ALL to obtain the average REGENT_L2L3_MOD_ALL latency for data page table reloads. ##084260000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3_MOD_ALL to obtain the average REGENT_L2L3_MOD_ALL latency for data page table reloads. #1449,u,g,n,n,m,u,PM_MRK_INST_FROM_REGENT_L2L3_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_REGENT_L2L3 to obtain the average REGENT_L2L3 latency for instruction reloads. ##080300000004C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_REGENT_L2L3 to obtain the average REGENT_L2L3 latency for instruction reloads. #1450,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3 to obtain the average REGENT_L2L3 latency for instruction page table reloads. ##080320000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3 to obtain the average REGENT_L2L3 latency for instruction page table reloads. #1451,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3 to obtain the average REGENT_L2L3 latency for data reloads. ##080340000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3 to obtain the average REGENT_L2L3 latency for data reloads. #1452,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3 to obtain the average REGENT_L2L3 latency for data page table reloads. ##080360000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3 to obtain the average REGENT_L2L3 latency for data page table reloads. #1453,u,g,n,n,m,u,PM_MRK_INST_FROM_REGENT_L2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_REGENT_L2L3_ALL to obtain the average REGENT_L2L3_ALL latency for instruction reloads. ##080300000014C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_REGENT_L2L3_ALL to obtain the average REGENT_L2L3_ALL latency for instruction reloads. #1454,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_REGENT_L2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3_ALL to obtain the average REGENT_L2L3_ALL latency for instruction page table reloads. ##080320000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_REGENT_L2L3_ALL to obtain the average REGENT_L2L3_ALL latency for instruction page table reloads. #1455,u,g,n,n,m,u,PM_MRK_DATA_FROM_REGENT_L2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3_ALL to obtain the average REGENT_L2L3_ALL latency for data reloads. ##080340000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_REGENT_L2L3_ALL to obtain the average REGENT_L2L3_ALL latency for data reloads. #1456,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_REGENT_L2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3_ALL to obtain the average REGENT_L2L3_ALL latency for data page table reloads. ##080360000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_REGENT_L2L3_ALL to obtain the average REGENT_L2L3_ALL latency for data page table reloads. #1457,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT_SHR to obtain the average L21_NON_REGENT_SHR latency for instruction page table reloads. ##0A0020000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT_SHR to obtain the average L21_NON_REGENT_SHR latency for instruction page table reloads. #1458,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT_SHR to obtain the average L21_NON_REGENT_SHR latency for data reloads. ##0A0040000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT_SHR to obtain the average L21_NON_REGENT_SHR latency for data reloads. #1459,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT_SHR to obtain the average L21_NON_REGENT_SHR latency for data page table reloads. ##0A0060000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT_SHR to obtain the average L21_NON_REGENT_SHR latency for data page table reloads. #1460,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT_SHR_ALL to obtain the average L21_NON_REGENT_SHR_ALL latency for instruction page table reloads. ##0A0020000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT_SHR_ALL to obtain the average L21_NON_REGENT_SHR_ALL latency for instruction page table reloads. #1461,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT_SHR_ALL to obtain the average L21_NON_REGENT_SHR_ALL latency for data reloads. ##0A0040000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT_SHR_ALL to obtain the average L21_NON_REGENT_SHR_ALL latency for data reloads. #1462,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT_SHR_ALL to obtain the average L21_NON_REGENT_SHR_ALL latency for data page table reloads. ##0A0060000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT_SHR_ALL to obtain the average L21_NON_REGENT_SHR_ALL latency for data page table reloads. #1463,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT_MOD to obtain the average L21_NON_REGENT_MOD latency for instruction page table reloads. ##0A4020000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT_MOD to obtain the average L21_NON_REGENT_MOD latency for instruction page table reloads. #1464,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT_MOD to obtain the average L21_NON_REGENT_MOD latency for data reloads. ##0A4040000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT_MOD to obtain the average L21_NON_REGENT_MOD latency for data reloads. #1465,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT_MOD to obtain the average L21_NON_REGENT_MOD latency for data page table reloads. ##0A4060000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT_MOD to obtain the average L21_NON_REGENT_MOD latency for data page table reloads. #1466,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT_MOD_ALL to obtain the average L21_NON_REGENT_MOD_ALL latency for instruction page table reloads. ##0A4020000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT_MOD_ALL to obtain the average L21_NON_REGENT_MOD_ALL latency for instruction page table reloads. #1467,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT_MOD_ALL to obtain the average L21_NON_REGENT_MOD_ALL latency for data reloads. ##0A4040000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT_MOD_ALL to obtain the average L21_NON_REGENT_MOD_ALL latency for data reloads. #1468,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT_MOD_ALL to obtain the average L21_NON_REGENT_MOD_ALL latency for data page table reloads. ##0A4060000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT_MOD_ALL to obtain the average L21_NON_REGENT_MOD_ALL latency for data page table reloads. #1469,u,g,n,n,m,u,PM_MRK_INST_FROM_L21_NON_REGENT_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_L21_NON_REGENT to obtain the average L21_NON_REGENT latency for instruction reloads. ##0A0100000004C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_L21_NON_REGENT to obtain the average L21_NON_REGENT latency for instruction reloads. #1470,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT to obtain the average L21_NON_REGENT latency for instruction page table reloads. ##0A0120000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT to obtain the average L21_NON_REGENT latency for instruction page table reloads. #1471,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT to obtain the average L21_NON_REGENT latency for data reloads. ##0A0140000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT to obtain the average L21_NON_REGENT latency for data reloads. #1472,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT to obtain the average L21_NON_REGENT latency for data page table reloads. ##0A0160000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT to obtain the average L21_NON_REGENT latency for data page table reloads. #1473,u,g,n,n,m,u,PM_MRK_INST_FROM_L21_NON_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L21_NON_REGENT_ALL to obtain the average L21_NON_REGENT_ALL latency for instruction reloads. ##0A0100000014C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L21_NON_REGENT_ALL to obtain the average L21_NON_REGENT_ALL latency for instruction reloads. #1474,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L21_NON_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT_ALL to obtain the average L21_NON_REGENT_ALL latency for instruction page table reloads. ##0A0120000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L21_NON_REGENT_ALL to obtain the average L21_NON_REGENT_ALL latency for instruction page table reloads. #1475,u,g,n,n,m,u,PM_MRK_DATA_FROM_L21_NON_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT_ALL to obtain the average L21_NON_REGENT_ALL latency for data reloads. ##0A0140000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L21_NON_REGENT_ALL to obtain the average L21_NON_REGENT_ALL latency for data reloads. #1476,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L21_NON_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT_ALL to obtain the average L21_NON_REGENT_ALL latency for data page table reloads. ##0A0160000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L21_NON_REGENT_ALL to obtain the average L21_NON_REGENT_ALL latency for data page table reloads. #1477,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT_SHR to obtain the average L31_NON_REGENT_SHR latency for instruction page table reloads. ##0A8020000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT_SHR to obtain the average L31_NON_REGENT_SHR latency for instruction page table reloads. #1478,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT_SHR to obtain the average L31_NON_REGENT_SHR latency for data reloads. ##0A8040000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT_SHR to obtain the average L31_NON_REGENT_SHR latency for data reloads. #1479,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT_SHR to obtain the average L31_NON_REGENT_SHR latency for data page table reloads. ##0A8060000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT_SHR to obtain the average L31_NON_REGENT_SHR latency for data page table reloads. #1480,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT_SHR_ALL to obtain the average L31_NON_REGENT_SHR_ALL latency for instruction page table reloads. ##0A8020000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT_SHR_ALL to obtain the average L31_NON_REGENT_SHR_ALL latency for instruction page table reloads. #1481,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT_SHR_ALL to obtain the average L31_NON_REGENT_SHR_ALL latency for data reloads. ##0A8040000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT_SHR_ALL to obtain the average L31_NON_REGENT_SHR_ALL latency for data reloads. #1482,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT_SHR_ALL to obtain the average L31_NON_REGENT_SHR_ALL latency for data page table reloads. ##0A8060000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT_SHR_ALL to obtain the average L31_NON_REGENT_SHR_ALL latency for data page table reloads. #1483,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT_MOD to obtain the average L31_NON_REGENT_MOD latency for instruction page table reloads. ##0AC020000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT_MOD to obtain the average L31_NON_REGENT_MOD latency for instruction page table reloads. #1484,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT_MOD to obtain the average L31_NON_REGENT_MOD latency for data reloads. ##0AC040000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT_MOD to obtain the average L31_NON_REGENT_MOD latency for data reloads. #1485,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT_MOD to obtain the average L31_NON_REGENT_MOD latency for data page table reloads. ##0AC060000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT_MOD to obtain the average L31_NON_REGENT_MOD latency for data page table reloads. #1486,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT_MOD_ALL to obtain the average L31_NON_REGENT_MOD_ALL latency for instruction page table reloads. ##0AC020000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT_MOD_ALL to obtain the average L31_NON_REGENT_MOD_ALL latency for instruction page table reloads. #1487,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT_MOD_ALL to obtain the average L31_NON_REGENT_MOD_ALL latency for data reloads. ##0AC040000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT_MOD_ALL to obtain the average L31_NON_REGENT_MOD_ALL latency for data reloads. #1488,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT_MOD_ALL to obtain the average L31_NON_REGENT_MOD_ALL latency for data page table reloads. ##0AC060000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT_MOD_ALL to obtain the average L31_NON_REGENT_MOD_ALL latency for data page table reloads. #1489,u,g,n,n,m,u,PM_MRK_INST_FROM_L31_NON_REGENT_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_L31_NON_REGENT to obtain the average L31_NON_REGENT latency for instruction reloads. ##0A8100000004C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_L31_NON_REGENT to obtain the average L31_NON_REGENT latency for instruction reloads. #1490,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT to obtain the average L31_NON_REGENT latency for instruction page table reloads. ##0A8120000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT to obtain the average L31_NON_REGENT latency for instruction page table reloads. #1491,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT to obtain the average L31_NON_REGENT latency for data reloads. ##0A8140000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT to obtain the average L31_NON_REGENT latency for data reloads. #1492,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT to obtain the average L31_NON_REGENT latency for data page table reloads. ##0A8160000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT to obtain the average L31_NON_REGENT latency for data page table reloads. #1493,u,g,n,n,m,u,PM_MRK_INST_FROM_L31_NON_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L31_NON_REGENT_ALL to obtain the average L31_NON_REGENT_ALL latency for instruction reloads. ##0A8100000014C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L31_NON_REGENT_ALL to obtain the average L31_NON_REGENT_ALL latency for instruction reloads. #1494,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L31_NON_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT_ALL to obtain the average L31_NON_REGENT_ALL latency for instruction page table reloads. ##0A8120000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L31_NON_REGENT_ALL to obtain the average L31_NON_REGENT_ALL latency for instruction page table reloads. #1495,u,g,n,n,m,u,PM_MRK_DATA_FROM_L31_NON_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT_ALL to obtain the average L31_NON_REGENT_ALL latency for data reloads. ##0A8140000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L31_NON_REGENT_ALL to obtain the average L31_NON_REGENT_ALL latency for data reloads. #1496,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L31_NON_REGENT_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT_ALL to obtain the average L31_NON_REGENT_ALL latency for data page table reloads. ##0A8160000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L31_NON_REGENT_ALL to obtain the average L31_NON_REGENT_ALL latency for data page table reloads. #1497,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_SHR to obtain the average NON_REGENT_L2L3_SHR latency for instruction page table reloads. ##0A0220000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_SHR to obtain the average NON_REGENT_L2L3_SHR latency for instruction page table reloads. #1498,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3_SHR to obtain the average NON_REGENT_L2L3_SHR latency for data reloads. ##0A0240000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3_SHR to obtain the average NON_REGENT_L2L3_SHR latency for data reloads. #1499,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_SHR to obtain the average NON_REGENT_L2L3_SHR latency for data page table reloads. ##0A0260000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_SHR to obtain the average NON_REGENT_L2L3_SHR latency for data page table reloads. #1500,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_SHR_ALL to obtain the average NON_REGENT_L2L3_SHR_ALL latency for instruction page table reloads. ##0A0220000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_SHR_ALL to obtain the average NON_REGENT_L2L3_SHR_ALL latency for instruction page table reloads. #1501,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3_SHR_ALL to obtain the average NON_REGENT_L2L3_SHR_ALL latency for data reloads. ##0A0240000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3_SHR_ALL to obtain the average NON_REGENT_L2L3_SHR_ALL latency for data reloads. #1502,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_SHR_ALL to obtain the average NON_REGENT_L2L3_SHR_ALL latency for data page table reloads. ##0A0260000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_SHR_ALL to obtain the average NON_REGENT_L2L3_SHR_ALL latency for data page table reloads. #1503,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_MOD to obtain the average NON_REGENT_L2L3_MOD latency for instruction page table reloads. ##0A4220000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_MOD to obtain the average NON_REGENT_L2L3_MOD latency for instruction page table reloads. #1504,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3_MOD to obtain the average NON_REGENT_L2L3_MOD latency for data reloads. ##0A4240000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3_MOD to obtain the average NON_REGENT_L2L3_MOD latency for data reloads. #1505,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_MOD to obtain the average NON_REGENT_L2L3_MOD latency for data page table reloads. ##0A4260000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_MOD to obtain the average NON_REGENT_L2L3_MOD latency for data page table reloads. #1506,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_MOD_ALL to obtain the average NON_REGENT_L2L3_MOD_ALL latency for instruction page table reloads. ##0A4220000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_MOD_ALL to obtain the average NON_REGENT_L2L3_MOD_ALL latency for instruction page table reloads. #1507,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3_MOD_ALL to obtain the average NON_REGENT_L2L3_MOD_ALL latency for data reloads. ##0A4240000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3_MOD_ALL to obtain the average NON_REGENT_L2L3_MOD_ALL latency for data reloads. #1508,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_MOD_ALL to obtain the average NON_REGENT_L2L3_MOD_ALL latency for data page table reloads. ##0A4260000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_MOD_ALL to obtain the average NON_REGENT_L2L3_MOD_ALL latency for data page table reloads. #1509,u,g,n,n,m,u,PM_MRK_INST_FROM_NON_REGENT_L2L3_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_NON_REGENT_L2L3 to obtain the average NON_REGENT_L2L3 latency for instruction reloads. ##0A0300000004C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_INST_FROM_NON_REGENT_L2L3 to obtain the average NON_REGENT_L2L3 latency for instruction reloads. #1510,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3 to obtain the average NON_REGENT_L2L3 latency for instruction page table reloads. ##0A0320000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3 to obtain the average NON_REGENT_L2L3 latency for instruction page table reloads. #1511,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3 to obtain the average NON_REGENT_L2L3 latency for data reloads. ##0A0340000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3 to obtain the average NON_REGENT_L2L3 latency for data reloads. #1512,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3 to obtain the average NON_REGENT_L2L3 latency for data page table reloads. ##0A0360000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3 to obtain the average NON_REGENT_L2L3 latency for data page table reloads. #1513,u,g,n,n,m,u,PM_MRK_INST_FROM_NON_REGENT_L2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_NON_REGENT_L2L3_ALL to obtain the average NON_REGENT_L2L3_ALL latency for instruction reloads. ##0A0300000014C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_NON_REGENT_L2L3_ALL to obtain the average NON_REGENT_L2L3_ALL latency for instruction reloads. #1514,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_ALL to obtain the average NON_REGENT_L2L3_ALL latency for instruction page table reloads. ##0A0320000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_NON_REGENT_L2L3_ALL to obtain the average NON_REGENT_L2L3_ALL latency for instruction page table reloads. #1515,u,g,n,n,m,u,PM_MRK_DATA_FROM_NON_REGENT_L2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3_ALL to obtain the average NON_REGENT_L2L3_ALL latency for data reloads. ##0A0340000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_NON_REGENT_L2L3_ALL to obtain the average NON_REGENT_L2L3_ALL latency for data reloads. #1516,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_ALL to obtain the average NON_REGENT_L2L3_ALL latency for data page table reloads. ##0A0360000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_NON_REGENT_L2L3_ALL to obtain the average NON_REGENT_L2L3_ALL latency for data page table reloads. #1517,u,g,n,n,m,u,PM_MRK_INST_FROM_LMEM_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local chip's memory due to a demand miss. Divide this count by PM_MRK_INST_FROM_LMEM to obtain the average LMEM latency for instruction reloads. ##094100000004C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local chip's memory due to a demand miss. Divide this count by PM_MRK_INST_FROM_LMEM to obtain the average LMEM latency for instruction reloads. #1518,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_LMEM_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_LMEM to obtain the average LMEM latency for instruction page table reloads. ##094020000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_LMEM to obtain the average LMEM latency for instruction page table reloads. #1519,u,g,n,n,m,u,PM_MRK_DATA_FROM_LMEM_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_LMEM to obtain the average LMEM latency for data reloads. ##094040000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_LMEM to obtain the average LMEM latency for data reloads. #1520,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_LMEM_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_LMEM to obtain the average LMEM latency for data page table reloads. ##094060000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_LMEM to obtain the average LMEM latency for data page table reloads. #1521,u,g,n,n,m,u,PM_MRK_INST_FROM_LMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local chip's memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_LMEM_ALL to obtain the average LMEM_ALL latency for instruction reloads. ##094100000014C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local chip's memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_LMEM_ALL to obtain the average LMEM_ALL latency for instruction reloads. #1522,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_LMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_LMEM_ALL to obtain the average LMEM_ALL latency for instruction page table reloads. ##094020000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_LMEM_ALL to obtain the average LMEM_ALL latency for instruction page table reloads. #1523,u,g,n,n,m,u,PM_MRK_DATA_FROM_LMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_LMEM_ALL to obtain the average LMEM_ALL latency for data reloads. ##094040000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_LMEM_ALL to obtain the average LMEM_ALL latency for data reloads. #1524,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_LMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_LMEM_ALL to obtain the average LMEM_ALL latency for data page table reloads. ##094060000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_LMEM_ALL to obtain the average LMEM_ALL latency for data page table reloads. #1525,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_CACHE_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L_OC_CACHE to obtain the average L_OC_CACHE latency for instruction page table reloads. ##098020000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L_OC_CACHE to obtain the average L_OC_CACHE latency for instruction page table reloads. #1526,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_CACHE_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L_OC_CACHE to obtain the average L_OC_CACHE latency for data reloads. ##098040000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L_OC_CACHE to obtain the average L_OC_CACHE latency for data reloads. #1527,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_CACHE_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L_OC_CACHE to obtain the average L_OC_CACHE latency for data page table reloads. ##098060000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L_OC_CACHE to obtain the average L_OC_CACHE latency for data page table reloads. #1528,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L_OC_CACHE_ALL to obtain the average L_OC_CACHE_ALL latency for instruction page table reloads. ##098020000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L_OC_CACHE_ALL to obtain the average L_OC_CACHE_ALL latency for instruction page table reloads. #1529,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L_OC_CACHE_ALL to obtain the average L_OC_CACHE_ALL latency for data reloads. ##098040000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L_OC_CACHE_ALL to obtain the average L_OC_CACHE_ALL latency for data reloads. #1530,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L_OC_CACHE_ALL to obtain the average L_OC_CACHE_ALL latency for data page table reloads. ##098060000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L_OC_CACHE_ALL to obtain the average L_OC_CACHE_ALL latency for data page table reloads. #1531,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_MEM_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L_OC_MEM to obtain the average L_OC_MEM latency for instruction page table reloads. ##09C020000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L_OC_MEM to obtain the average L_OC_MEM latency for instruction page table reloads. #1532,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_MEM_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L_OC_MEM to obtain the average L_OC_MEM latency for data reloads. ##09C040000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L_OC_MEM to obtain the average L_OC_MEM latency for data reloads. #1533,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_MEM_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L_OC_MEM to obtain the average L_OC_MEM latency for data page table reloads. ##09C060000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L_OC_MEM to obtain the average L_OC_MEM latency for data page table reloads. #1534,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_MEM_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L_OC_MEM_ALL to obtain the average L_OC_MEM_ALL latency for instruction page table reloads. ##09C020000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L_OC_MEM_ALL to obtain the average L_OC_MEM_ALL latency for instruction page table reloads. #1535,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_MEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L_OC_MEM_ALL to obtain the average L_OC_MEM_ALL latency for data reloads. ##09C040000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L_OC_MEM_ALL to obtain the average L_OC_MEM_ALL latency for data reloads. #1536,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_MEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L_OC_MEM_ALL to obtain the average L_OC_MEM_ALL latency for data page table reloads. ##09C060000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L_OC_MEM_ALL to obtain the average L_OC_MEM_ALL latency for data page table reloads. #1537,u,g,n,n,m,u,PM_MRK_INST_FROM_L_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_INST_FROM_L_OC_ANY to obtain the average L_OC_ANY latency for instruction reloads. ##098100000004C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_INST_FROM_L_OC_ANY to obtain the average L_OC_ANY latency for instruction reloads. #1538,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L_OC_ANY to obtain the average L_OC_ANY latency for instruction page table reloads. ##098120000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_L_OC_ANY to obtain the average L_OC_ANY latency for instruction page table reloads. #1539,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L_OC_ANY to obtain the average L_OC_ANY latency for data reloads. ##098140000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_L_OC_ANY to obtain the average L_OC_ANY latency for data reloads. #1540,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L_OC_ANY to obtain the average L_OC_ANY latency for data page table reloads. ##098160000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_L_OC_ANY to obtain the average L_OC_ANY latency for data page table reloads. #1541,u,g,n,n,m,u,PM_MRK_INST_FROM_L_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L_OC_ANY_ALL to obtain the average L_OC_ANY_ALL latency for instruction reloads. ##098100000014C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_L_OC_ANY_ALL to obtain the average L_OC_ANY_ALL latency for instruction reloads. #1542,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_L_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L_OC_ANY_ALL to obtain the average L_OC_ANY_ALL latency for instruction page table reloads. ##098120000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_L_OC_ANY_ALL to obtain the average L_OC_ANY_ALL latency for instruction page table reloads. #1543,u,g,n,n,m,u,PM_MRK_DATA_FROM_L_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L_OC_ANY_ALL to obtain the average L_OC_ANY_ALL latency for data reloads. ##098140000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_L_OC_ANY_ALL to obtain the average L_OC_ANY_ALL latency for data reloads. #1544,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_L_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L_OC_ANY_ALL to obtain the average L_OC_ANY_ALL latency for data page table reloads. ##098160000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from the local chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_L_OC_ANY_ALL to obtain the average L_OC_ANY_ALL latency for data page table reloads. #1545,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2_SHR to obtain the average RL2_SHR latency for instruction page table reloads. ##0C0020000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2_SHR to obtain the average RL2_SHR latency for instruction page table reloads. #1546,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2_SHR to obtain the average RL2_SHR latency for data reloads. ##0C0040000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2_SHR to obtain the average RL2_SHR latency for data reloads. #1547,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2_SHR to obtain the average RL2_SHR latency for data page table reloads. ##0C0060000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2_SHR to obtain the average RL2_SHR latency for data page table reloads. #1548,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2_SHR_ALL to obtain the average RL2_SHR_ALL latency for instruction page table reloads. ##0C0020000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2_SHR_ALL to obtain the average RL2_SHR_ALL latency for instruction page table reloads. #1549,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2_SHR_ALL to obtain the average RL2_SHR_ALL latency for data reloads. ##0C0040000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2_SHR_ALL to obtain the average RL2_SHR_ALL latency for data reloads. #1550,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2_SHR_ALL to obtain the average RL2_SHR_ALL latency for data page table reloads. ##0C0060000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2_SHR_ALL to obtain the average RL2_SHR_ALL latency for data page table reloads. #1551,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2_MOD to obtain the average RL2_MOD latency for instruction page table reloads. ##0C4020000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2_MOD to obtain the average RL2_MOD latency for instruction page table reloads. #1552,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2_MOD to obtain the average RL2_MOD latency for data reloads. ##0C4040000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2_MOD to obtain the average RL2_MOD latency for data reloads. #1553,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2_MOD to obtain the average RL2_MOD latency for data page table reloads. ##0C4060000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2_MOD to obtain the average RL2_MOD latency for data page table reloads. #1554,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2_MOD_ALL to obtain the average RL2_MOD_ALL latency for instruction page table reloads. ##0C4020000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2_MOD_ALL to obtain the average RL2_MOD_ALL latency for instruction page table reloads. #1555,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2_MOD_ALL to obtain the average RL2_MOD_ALL latency for data reloads. ##0C4040000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2_MOD_ALL to obtain the average RL2_MOD_ALL latency for data reloads. #1556,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2_MOD_ALL to obtain the average RL2_MOD_ALL latency for data page table reloads. ##0C4060000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2_MOD_ALL to obtain the average RL2_MOD_ALL latency for data page table reloads. #1557,u,g,n,n,m,u,PM_MRK_INST_FROM_RL2_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_RL2 to obtain the average RL2 latency for instruction reloads. ##0C0100000004C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_RL2 to obtain the average RL2 latency for instruction reloads. #1558,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2 to obtain the average RL2 latency for instruction page table reloads. ##0C0120000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2 to obtain the average RL2 latency for instruction page table reloads. #1559,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2 to obtain the average RL2 latency for data reloads. ##0C0140000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2 to obtain the average RL2 latency for data reloads. #1560,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2 to obtain the average RL2 latency for data page table reloads. ##0C0160000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2 to obtain the average RL2 latency for data page table reloads. #1561,u,g,n,n,m,u,PM_MRK_INST_FROM_RL2_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_RL2_ALL to obtain the average RL2_ALL latency for instruction reloads. ##0C0100000014C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_RL2_ALL to obtain the average RL2_ALL latency for instruction reloads. #1562,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2_ALL to obtain the average RL2_ALL latency for instruction page table reloads. ##0C0120000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2_ALL to obtain the average RL2_ALL latency for instruction page table reloads. #1563,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2_ALL to obtain the average RL2_ALL latency for data reloads. ##0C0140000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2_ALL to obtain the average RL2_ALL latency for data reloads. #1564,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2_ALL to obtain the average RL2_ALL latency for data page table reloads. ##0C0160000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2_ALL to obtain the average RL2_ALL latency for data page table reloads. #1565,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL3_SHR to obtain the average RL3_SHR latency for instruction page table reloads. ##0C8020000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL3_SHR to obtain the average RL3_SHR latency for instruction page table reloads. #1566,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL3_SHR to obtain the average RL3_SHR latency for data reloads. ##0C8040000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL3_SHR to obtain the average RL3_SHR latency for data reloads. #1567,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL3_SHR to obtain the average RL3_SHR latency for data page table reloads. ##0C8060000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL3_SHR to obtain the average RL3_SHR latency for data page table reloads. #1568,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL3_SHR_ALL to obtain the average RL3_SHR_ALL latency for instruction page table reloads. ##0C8020000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL3_SHR_ALL to obtain the average RL3_SHR_ALL latency for instruction page table reloads. #1569,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL3_SHR_ALL to obtain the average RL3_SHR_ALL latency for data reloads. ##0C8040000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL3_SHR_ALL to obtain the average RL3_SHR_ALL latency for data reloads. #1570,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL3_SHR_ALL to obtain the average RL3_SHR_ALL latency for data page table reloads. ##0C8060000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL3_SHR_ALL to obtain the average RL3_SHR_ALL latency for data page table reloads. #1571,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL3_MOD to obtain the average RL3_MOD latency for instruction page table reloads. ##0CC020000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL3_MOD to obtain the average RL3_MOD latency for instruction page table reloads. #1572,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL3_MOD to obtain the average RL3_MOD latency for data reloads. ##0CC040000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL3_MOD to obtain the average RL3_MOD latency for data reloads. #1573,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL3_MOD to obtain the average RL3_MOD latency for data page table reloads. ##0CC060000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL3_MOD to obtain the average RL3_MOD latency for data page table reloads. #1574,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL3_MOD_ALL to obtain the average RL3_MOD_ALL latency for instruction page table reloads. ##0CC020000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL3_MOD_ALL to obtain the average RL3_MOD_ALL latency for instruction page table reloads. #1575,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL3_MOD_ALL to obtain the average RL3_MOD_ALL latency for data reloads. ##0CC040000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL3_MOD_ALL to obtain the average RL3_MOD_ALL latency for data reloads. #1576,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL3_MOD_ALL to obtain the average RL3_MOD_ALL latency for data page table reloads. ##0CC060000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL3_MOD_ALL to obtain the average RL3_MOD_ALL latency for data page table reloads. #1577,u,g,n,n,m,u,PM_MRK_INST_FROM_RL3_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_RL3 to obtain the average RL3 latency for instruction reloads. ##0C8100000004C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_RL3 to obtain the average RL3 latency for instruction reloads. #1578,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL3 to obtain the average RL3 latency for instruction page table reloads. ##0C8120000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL3 to obtain the average RL3 latency for instruction page table reloads. #1579,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL3 to obtain the average RL3 latency for data reloads. ##0C8140000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL3 to obtain the average RL3 latency for data reloads. #1580,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL3 to obtain the average RL3 latency for data page table reloads. ##0C8160000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL3 to obtain the average RL3 latency for data page table reloads. #1581,u,g,n,n,m,u,PM_MRK_INST_FROM_RL3_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_RL3_ALL to obtain the average RL3_ALL latency for instruction reloads. ##0C8100000014C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_RL3_ALL to obtain the average RL3_ALL latency for instruction reloads. #1582,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL3_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL3_ALL to obtain the average RL3_ALL latency for instruction page table reloads. ##0C8120000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL3_ALL to obtain the average RL3_ALL latency for instruction page table reloads. #1583,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL3_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL3_ALL to obtain the average RL3_ALL latency for data reloads. ##0C8140000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL3_ALL to obtain the average RL3_ALL latency for data reloads. #1584,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL3_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL3_ALL to obtain the average RL3_ALL latency for data page table reloads. ##0C8160000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL3_ALL to obtain the average RL3_ALL latency for data page table reloads. #1585,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2L3_SHR to obtain the average RL2L3_SHR latency for instruction page table reloads. ##0C0220000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2L3_SHR to obtain the average RL2L3_SHR latency for instruction page table reloads. #1586,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2L3_SHR to obtain the average RL2L3_SHR latency for data reloads. ##0C0240000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2L3_SHR to obtain the average RL2L3_SHR latency for data reloads. #1587,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2L3_SHR to obtain the average RL2L3_SHR latency for data page table reloads. ##0C0260000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2L3_SHR to obtain the average RL2L3_SHR latency for data page table reloads. #1588,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2L3_SHR_ALL to obtain the average RL2L3_SHR_ALL latency for instruction page table reloads. ##0C0220000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2L3_SHR_ALL to obtain the average RL2L3_SHR_ALL latency for instruction page table reloads. #1589,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2L3_SHR_ALL to obtain the average RL2L3_SHR_ALL latency for data reloads. ##0C0240000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2L3_SHR_ALL to obtain the average RL2L3_SHR_ALL latency for data reloads. #1590,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2L3_SHR_ALL to obtain the average RL2L3_SHR_ALL latency for data page table reloads. ##0C0260000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2L3_SHR_ALL to obtain the average RL2L3_SHR_ALL latency for data page table reloads. #1591,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2L3_MOD to obtain the average RL2L3_MOD latency for instruction page table reloads. ##0C4220000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2L3_MOD to obtain the average RL2L3_MOD latency for instruction page table reloads. #1592,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2L3_MOD to obtain the average RL2L3_MOD latency for data reloads. ##0C4240000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2L3_MOD to obtain the average RL2L3_MOD latency for data reloads. #1593,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2L3_MOD to obtain the average RL2L3_MOD latency for data page table reloads. ##0C4260000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2L3_MOD to obtain the average RL2L3_MOD latency for data page table reloads. #1594,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2L3_MOD_ALL to obtain the average RL2L3_MOD_ALL latency for instruction page table reloads. ##0C4220000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2L3_MOD_ALL to obtain the average RL2L3_MOD_ALL latency for instruction page table reloads. #1595,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2L3_MOD_ALL to obtain the average RL2L3_MOD_ALL latency for data reloads. ##0C4240000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2L3_MOD_ALL to obtain the average RL2L3_MOD_ALL latency for data reloads. #1596,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2L3_MOD_ALL to obtain the average RL2L3_MOD_ALL latency for data page table reloads. ##0C4260000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2L3_MOD_ALL to obtain the average RL2L3_MOD_ALL latency for data page table reloads. #1597,u,g,n,n,m,u,PM_MRK_INST_FROM_RL2L3_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_RL2L3 to obtain the average RL2L3 latency for instruction reloads. ##0C0300000004C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_RL2L3 to obtain the average RL2L3 latency for instruction reloads. #1598,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2L3 to obtain the average RL2L3 latency for instruction page table reloads. ##0C0320000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RL2L3 to obtain the average RL2L3 latency for instruction page table reloads. #1599,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2L3 to obtain the average RL2L3 latency for data reloads. ##0C0340000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RL2L3 to obtain the average RL2L3 latency for data reloads. #1600,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2L3 to obtain the average RL2L3 latency for data page table reloads. ##0C0360000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RL2L3 to obtain the average RL2L3 latency for data page table reloads. #1601,u,g,n,n,m,u,PM_MRK_INST_FROM_RL2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_RL2L3_ALL to obtain the average RL2L3_ALL latency for instruction reloads. ##0C0300000014C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_RL2L3_ALL to obtain the average RL2L3_ALL latency for instruction reloads. #1602,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RL2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2L3_ALL to obtain the average RL2L3_ALL latency for instruction page table reloads. ##0C0320000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RL2L3_ALL to obtain the average RL2L3_ALL latency for instruction page table reloads. #1603,u,g,n,n,m,u,PM_MRK_DATA_FROM_RL2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2L3_ALL to obtain the average RL2L3_ALL latency for data reloads. ##0C0340000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RL2L3_ALL to obtain the average RL2L3_ALL latency for data reloads. #1604,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RL2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2L3_ALL to obtain the average RL2L3_ALL latency for data page table reloads. ##0C0360000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RL2L3_ALL to obtain the average RL2L3_ALL latency for data page table reloads. #1605,u,g,n,n,m,u,PM_MRK_INST_FROM_RMEM_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from remote memory (MC slow) due to a demand miss. Divide this count by PM_MRK_INST_FROM_RMEM to obtain the average RMEM latency for instruction reloads. ##0D4100000004C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from remote memory (MC slow) due to a demand miss. Divide this count by PM_MRK_INST_FROM_RMEM to obtain the average RMEM latency for instruction reloads. #1606,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RMEM_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from remote memory (MC slow) due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RMEM to obtain the average RMEM latency for instruction page table reloads. ##0D4020000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from remote memory (MC slow) due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_RMEM to obtain the average RMEM latency for instruction page table reloads. #1607,u,g,n,n,m,u,PM_MRK_DATA_FROM_RMEM_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from remote memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RMEM to obtain the average RMEM latency for data reloads. ##0D4040000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from remote memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DATA_FROM_RMEM to obtain the average RMEM latency for data reloads. #1608,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RMEM_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from remote memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RMEM to obtain the average RMEM latency for data page table reloads. ##0D4060000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from remote memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_RMEM to obtain the average RMEM latency for data page table reloads. #1609,u,g,n,n,m,u,PM_MRK_INST_FROM_RMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_RMEM_ALL to obtain the average RMEM_ALL latency for instruction reloads. ##0D4100000014C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_RMEM_ALL to obtain the average RMEM_ALL latency for instruction reloads. #1610,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_RMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RMEM_ALL to obtain the average RMEM_ALL latency for instruction page table reloads. ##0D4020000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_RMEM_ALL to obtain the average RMEM_ALL latency for instruction page table reloads. #1611,u,g,n,n,m,u,PM_MRK_DATA_FROM_RMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RMEM_ALL to obtain the average RMEM_ALL latency for data reloads. ##0D4040000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_RMEM_ALL to obtain the average RMEM_ALL latency for data reloads. #1612,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_RMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RMEM_ALL to obtain the average RMEM_ALL latency for data page table reloads. ##0D4060000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_RMEM_ALL to obtain the average RMEM_ALL latency for data page table reloads. #1613,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_CACHE_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_R_OC_CACHE to obtain the average R_OC_CACHE latency for instruction page table reloads. ##0D8020000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_R_OC_CACHE to obtain the average R_OC_CACHE latency for instruction page table reloads. #1614,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_CACHE_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DATA_FROM_R_OC_CACHE to obtain the average R_OC_CACHE latency for data reloads. ##0D8040000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DATA_FROM_R_OC_CACHE to obtain the average R_OC_CACHE latency for data reloads. #1615,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_CACHE_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_R_OC_CACHE to obtain the average R_OC_CACHE latency for data page table reloads. ##0D8060000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_R_OC_CACHE to obtain the average R_OC_CACHE latency for data page table reloads. #1616,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_R_OC_CACHE_ALL to obtain the average R_OC_CACHE_ALL latency for instruction page table reloads. ##0D8020000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_R_OC_CACHE_ALL to obtain the average R_OC_CACHE_ALL latency for instruction page table reloads. #1617,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_R_OC_CACHE_ALL to obtain the average R_OC_CACHE_ALL latency for data reloads. ##0D8040000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_R_OC_CACHE_ALL to obtain the average R_OC_CACHE_ALL latency for data reloads. #1618,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_R_OC_CACHE_ALL to obtain the average R_OC_CACHE_ALL latency for data page table reloads. ##0D8060000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_R_OC_CACHE_ALL to obtain the average R_OC_CACHE_ALL latency for data page table reloads. #1619,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_MEM_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_R_OC_MEM to obtain the average R_OC_MEM latency for instruction page table reloads. ##0DC020000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_R_OC_MEM to obtain the average R_OC_MEM latency for instruction page table reloads. #1620,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_MEM_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_R_OC_MEM to obtain the average R_OC_MEM latency for data reloads. ##0DC040000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_R_OC_MEM to obtain the average R_OC_MEM latency for data reloads. #1621,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_MEM_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_R_OC_MEM to obtain the average R_OC_MEM latency for data page table reloads. ##0DC060000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_R_OC_MEM to obtain the average R_OC_MEM latency for data page table reloads. #1622,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_MEM_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_R_OC_MEM_ALL to obtain the average R_OC_MEM_ALL latency for instruction page table reloads. ##0DC020000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_R_OC_MEM_ALL to obtain the average R_OC_MEM_ALL latency for instruction page table reloads. #1623,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_MEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_R_OC_MEM_ALL to obtain the average R_OC_MEM_ALL latency for data reloads. ##0DC040000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_R_OC_MEM_ALL to obtain the average R_OC_MEM_ALL latency for data reloads. #1624,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_MEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_R_OC_MEM_ALL to obtain the average R_OC_MEM_ALL latency for data page table reloads. ##0DC060000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_R_OC_MEM_ALL to obtain the average R_OC_MEM_ALL latency for data page table reloads. #1625,u,g,n,n,m,u,PM_MRK_INST_FROM_R_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_INST_FROM_R_OC_ANY to obtain the average R_OC_ANY latency for instruction reloads. ##0D8100000004C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_INST_FROM_R_OC_ANY to obtain the average R_OC_ANY latency for instruction reloads. #1626,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_R_OC_ANY to obtain the average R_OC_ANY latency for instruction page table reloads. ##0D8120000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_R_OC_ANY to obtain the average R_OC_ANY latency for instruction page table reloads. #1627,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_R_OC_ANY to obtain the average R_OC_ANY latency for data reloads. ##0D8140000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_R_OC_ANY to obtain the average R_OC_ANY latency for data reloads. #1628,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_R_OC_ANY to obtain the average R_OC_ANY latency for data page table reloads. ##0D8160000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_R_OC_ANY to obtain the average R_OC_ANY latency for data page table reloads. #1629,u,g,n,n,m,u,PM_MRK_INST_FROM_R_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_R_OC_ANY_ALL to obtain the average R_OC_ANY_ALL latency for instruction reloads. ##0D8100000014C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_R_OC_ANY_ALL to obtain the average R_OC_ANY_ALL latency for instruction reloads. #1630,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_R_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_R_OC_ANY_ALL to obtain the average R_OC_ANY_ALL latency for instruction page table reloads. ##0D8120000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_R_OC_ANY_ALL to obtain the average R_OC_ANY_ALL latency for instruction page table reloads. #1631,u,g,n,n,m,u,PM_MRK_DATA_FROM_R_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_R_OC_ANY_ALL to obtain the average R_OC_ANY_ALL latency for data reloads. ##0D8140000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_R_OC_ANY_ALL to obtain the average R_OC_ANY_ALL latency for data reloads. #1632,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_R_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_R_OC_ANY_ALL to obtain the average R_OC_ANY_ALL latency for data page table reloads. ##0D8160000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a remote chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_R_OC_ANY_ALL to obtain the average R_OC_ANY_ALL latency for data page table reloads. #1633,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2_SHR to obtain the average DL2_SHR latency for instruction page table reloads. ##0E0020000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2_SHR to obtain the average DL2_SHR latency for instruction page table reloads. #1634,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2_SHR to obtain the average DL2_SHR latency for data reloads. ##0E0040000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2_SHR to obtain the average DL2_SHR latency for data reloads. #1635,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2_SHR to obtain the average DL2_SHR latency for data page table reloads. ##0E0060000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2_SHR to obtain the average DL2_SHR latency for data page table reloads. #1636,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2_SHR_ALL to obtain the average DL2_SHR_ALL latency for instruction page table reloads. ##0E0020000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2_SHR_ALL to obtain the average DL2_SHR_ALL latency for instruction page table reloads. #1637,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2_SHR_ALL to obtain the average DL2_SHR_ALL latency for data reloads. ##0E0040000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2_SHR_ALL to obtain the average DL2_SHR_ALL latency for data reloads. #1638,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2_SHR_ALL to obtain the average DL2_SHR_ALL latency for data page table reloads. ##0E0060000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2_SHR_ALL to obtain the average DL2_SHR_ALL latency for data page table reloads. #1639,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2_MOD to obtain the average DL2_MOD latency for instruction page table reloads. ##0E4020000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2_MOD to obtain the average DL2_MOD latency for instruction page table reloads. #1640,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2_MOD to obtain the average DL2_MOD latency for data reloads. ##0E4040000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2_MOD to obtain the average DL2_MOD latency for data reloads. #1641,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2_MOD to obtain the average DL2_MOD latency for data page table reloads. ##0E4060000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2_MOD to obtain the average DL2_MOD latency for data page table reloads. #1642,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2_MOD_ALL to obtain the average DL2_MOD_ALL latency for instruction page table reloads. ##0E4020000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2_MOD_ALL to obtain the average DL2_MOD_ALL latency for instruction page table reloads. #1643,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2_MOD_ALL to obtain the average DL2_MOD_ALL latency for data reloads. ##0E4040000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2_MOD_ALL to obtain the average DL2_MOD_ALL latency for data reloads. #1644,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2_MOD_ALL to obtain the average DL2_MOD_ALL latency for data page table reloads. ##0E4060000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2_MOD_ALL to obtain the average DL2_MOD_ALL latency for data page table reloads. #1645,u,g,n,n,m,u,PM_MRK_INST_FROM_DL2_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_DL2 to obtain the average DL2 latency for instruction reloads. ##0E0100000004C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_DL2 to obtain the average DL2 latency for instruction reloads. #1646,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2 to obtain the average DL2 latency for instruction page table reloads. ##0E0120000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2 to obtain the average DL2 latency for instruction page table reloads. #1647,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2 to obtain the average DL2 latency for data reloads. ##0E0140000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2 to obtain the average DL2 latency for data reloads. #1648,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2 to obtain the average DL2 latency for data page table reloads. ##0E0160000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2 to obtain the average DL2 latency for data page table reloads. #1649,u,g,n,n,m,u,PM_MRK_INST_FROM_DL2_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_DL2_ALL to obtain the average DL2_ALL latency for instruction reloads. ##0E0100000014C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_DL2_ALL to obtain the average DL2_ALL latency for instruction reloads. #1650,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2_ALL to obtain the average DL2_ALL latency for instruction page table reloads. ##0E0120000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2_ALL to obtain the average DL2_ALL latency for instruction page table reloads. #1651,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2_ALL to obtain the average DL2_ALL latency for data reloads. ##0E0140000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2_ALL to obtain the average DL2_ALL latency for data reloads. #1652,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2_ALL to obtain the average DL2_ALL latency for data page table reloads. ##0E0160000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2_ALL to obtain the average DL2_ALL latency for data page table reloads. #1653,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL3_SHR to obtain the average DL3_SHR latency for instruction page table reloads. ##0E8020000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL3_SHR to obtain the average DL3_SHR latency for instruction page table reloads. #1654,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL3_SHR to obtain the average DL3_SHR latency for data reloads. ##0E8040000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL3_SHR to obtain the average DL3_SHR latency for data reloads. #1655,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL3_SHR to obtain the average DL3_SHR latency for data page table reloads. ##0E8060000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL3_SHR to obtain the average DL3_SHR latency for data page table reloads. #1656,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL3_SHR_ALL to obtain the average DL3_SHR_ALL latency for instruction page table reloads. ##0E8020000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL3_SHR_ALL to obtain the average DL3_SHR_ALL latency for instruction page table reloads. #1657,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL3_SHR_ALL to obtain the average DL3_SHR_ALL latency for data reloads. ##0E8040000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL3_SHR_ALL to obtain the average DL3_SHR_ALL latency for data reloads. #1658,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL3_SHR_ALL to obtain the average DL3_SHR_ALL latency for data page table reloads. ##0E8060000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL3_SHR_ALL to obtain the average DL3_SHR_ALL latency for data page table reloads. #1659,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL3_MOD to obtain the average DL3_MOD latency for instruction page table reloads. ##0EC020000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL3_MOD to obtain the average DL3_MOD latency for instruction page table reloads. #1660,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL3_MOD to obtain the average DL3_MOD latency for data reloads. ##0EC040000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL3_MOD to obtain the average DL3_MOD latency for data reloads. #1661,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL3_MOD to obtain the average DL3_MOD latency for data page table reloads. ##0EC060000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL3_MOD to obtain the average DL3_MOD latency for data page table reloads. #1662,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL3_MOD_ALL to obtain the average DL3_MOD_ALL latency for instruction page table reloads. ##0EC020000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL3_MOD_ALL to obtain the average DL3_MOD_ALL latency for instruction page table reloads. #1663,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL3_MOD_ALL to obtain the average DL3_MOD_ALL latency for data reloads. ##0EC040000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL3_MOD_ALL to obtain the average DL3_MOD_ALL latency for data reloads. #1664,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL3_MOD_ALL to obtain the average DL3_MOD_ALL latency for data page table reloads. ##0EC060000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL3_MOD_ALL to obtain the average DL3_MOD_ALL latency for data page table reloads. #1665,u,g,n,n,m,u,PM_MRK_INST_FROM_DL3_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_DL3 to obtain the average DL3 latency for instruction reloads. ##0E8100000004C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_DL3 to obtain the average DL3 latency for instruction reloads. #1666,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL3 to obtain the average DL3 latency for instruction page table reloads. ##0E8120000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL3 to obtain the average DL3 latency for instruction page table reloads. #1667,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL3 to obtain the average DL3 latency for data reloads. ##0E8140000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL3 to obtain the average DL3 latency for data reloads. #1668,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL3 to obtain the average DL3 latency for data page table reloads. ##0E8160000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL3 to obtain the average DL3 latency for data page table reloads. #1669,u,g,n,n,m,u,PM_MRK_INST_FROM_DL3_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_DL3_ALL to obtain the average DL3_ALL latency for instruction reloads. ##0E8100000014C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_DL3_ALL to obtain the average DL3_ALL latency for instruction reloads. #1670,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL3_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL3_ALL to obtain the average DL3_ALL latency for instruction page table reloads. ##0E8120000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL3_ALL to obtain the average DL3_ALL latency for instruction page table reloads. #1671,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL3_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL3_ALL to obtain the average DL3_ALL latency for data reloads. ##0E8140000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL3_ALL to obtain the average DL3_ALL latency for data reloads. #1672,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL3_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL3_ALL to obtain the average DL3_ALL latency for data page table reloads. ##0E8160000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL3_ALL to obtain the average DL3_ALL latency for data page table reloads. #1673,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2L3_SHR to obtain the average DL2L3_SHR latency for instruction page table reloads. ##0E0220000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2L3_SHR to obtain the average DL2L3_SHR latency for instruction page table reloads. #1674,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2L3_SHR to obtain the average DL2L3_SHR latency for data reloads. ##0E0240000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2L3_SHR to obtain the average DL2L3_SHR latency for data reloads. #1675,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_SHR_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2L3_SHR to obtain the average DL2L3_SHR latency for data page table reloads. ##0E0260000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2L3_SHR to obtain the average DL2L3_SHR latency for data page table reloads. #1676,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2L3_SHR_ALL to obtain the average DL2L3_SHR_ALL latency for instruction page table reloads. ##0E0220000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2L3_SHR_ALL to obtain the average DL2L3_SHR_ALL latency for instruction page table reloads. #1677,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2L3_SHR_ALL to obtain the average DL2L3_SHR_ALL latency for data reloads. ##0E0240000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2L3_SHR_ALL to obtain the average DL2L3_SHR_ALL latency for data reloads. #1678,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_SHR_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2L3_SHR_ALL to obtain the average DL2L3_SHR_ALL latency for data page table reloads. ##0E0260000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2L3_SHR_ALL to obtain the average DL2L3_SHR_ALL latency for data page table reloads. #1679,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2L3_MOD to obtain the average DL2L3_MOD latency for instruction page table reloads. ##0E4220000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2L3_MOD to obtain the average DL2L3_MOD latency for instruction page table reloads. #1680,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2L3_MOD to obtain the average DL2L3_MOD latency for data reloads. ##0E4240000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2L3_MOD to obtain the average DL2L3_MOD latency for data reloads. #1681,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_MOD_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2L3_MOD to obtain the average DL2L3_MOD latency for data page table reloads. ##0E4260000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2L3_MOD to obtain the average DL2L3_MOD latency for data page table reloads. #1682,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2L3_MOD_ALL to obtain the average DL2L3_MOD_ALL latency for instruction page table reloads. ##0E4220000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2L3_MOD_ALL to obtain the average DL2L3_MOD_ALL latency for instruction page table reloads. #1683,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2L3_MOD_ALL to obtain the average DL2L3_MOD_ALL latency for data reloads. ##0E4240000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2L3_MOD_ALL to obtain the average DL2L3_MOD_ALL latency for data reloads. #1684,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_MOD_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2L3_MOD_ALL to obtain the average DL2L3_MOD_ALL latency for data page table reloads. ##0E4260000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2L3_MOD_ALL to obtain the average DL2L3_MOD_ALL latency for data page table reloads. #1685,u,g,n,n,m,u,PM_MRK_INST_FROM_DL2L3_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_DL2L3 to obtain the average DL2L3 latency for instruction reloads. ##0E0300000004C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_DL2L3 to obtain the average DL2L3 latency for instruction reloads. #1686,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2L3 to obtain the average DL2L3 latency for instruction page table reloads. ##0E0320000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DL2L3 to obtain the average DL2L3 latency for instruction page table reloads. #1687,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2L3 to obtain the average DL2L3 latency for data reloads. ##0E0340000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DL2L3 to obtain the average DL2L3 latency for data reloads. #1688,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2L3 to obtain the average DL2L3 latency for data page table reloads. ##0E0360000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DL2L3 to obtain the average DL2L3 latency for data page table reloads. #1689,u,g,n,n,m,u,PM_MRK_INST_FROM_DL2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_DL2L3_ALL to obtain the average DL2L3_ALL latency for instruction reloads. ##0E0300000014C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_DL2L3_ALL to obtain the average DL2L3_ALL latency for instruction reloads. #1690,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DL2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2L3_ALL to obtain the average DL2L3_ALL latency for instruction page table reloads. ##0E0320000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DL2L3_ALL to obtain the average DL2L3_ALL latency for instruction page table reloads. #1691,u,g,n,n,m,u,PM_MRK_DATA_FROM_DL2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2L3_ALL to obtain the average DL2L3_ALL latency for data reloads. ##0E0340000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DL2L3_ALL to obtain the average DL2L3_ALL latency for data reloads. #1692,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DL2L3_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2L3_ALL to obtain the average DL2L3_ALL latency for data page table reloads. ##0E0360000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DL2L3_ALL to obtain the average DL2L3_ALL latency for data page table reloads. #1693,u,g,n,n,m,u,PM_MRK_INST_FROM_DMEM_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from distant memory (MC slow) due to a demand miss. Divide this count by PM_MRK_INST_FROM_DMEM to obtain the average DMEM latency for instruction reloads. ##0F4100000004C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from distant memory (MC slow) due to a demand miss. Divide this count by PM_MRK_INST_FROM_DMEM to obtain the average DMEM latency for instruction reloads. #1694,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DMEM_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from distant memory (MC slow) due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DMEM to obtain the average DMEM latency for instruction page table reloads. ##0F4020000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from distant memory (MC slow) due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_DMEM to obtain the average DMEM latency for instruction page table reloads. #1695,u,g,n,n,m,u,PM_MRK_DATA_FROM_DMEM_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from distant memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DMEM to obtain the average DMEM latency for data reloads. ##0F4040000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from distant memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DATA_FROM_DMEM to obtain the average DMEM latency for data reloads. #1696,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DMEM_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from distant memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DMEM to obtain the average DMEM latency for data page table reloads. ##0F4060000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from distant memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_DMEM to obtain the average DMEM latency for data page table reloads. #1697,u,g,n,n,m,u,PM_MRK_INST_FROM_DMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_DMEM_ALL to obtain the average DMEM_ALL latency for instruction reloads. ##0F4100000014C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_DMEM_ALL to obtain the average DMEM_ALL latency for instruction reloads. #1698,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_DMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DMEM_ALL to obtain the average DMEM_ALL latency for instruction page table reloads. ##0F4020000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_DMEM_ALL to obtain the average DMEM_ALL latency for instruction page table reloads. #1699,u,g,n,n,m,u,PM_MRK_DATA_FROM_DMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DMEM_ALL to obtain the average DMEM_ALL latency for data reloads. ##0F4040000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_DMEM_ALL to obtain the average DMEM_ALL latency for data reloads. #1700,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_DMEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DMEM_ALL to obtain the average DMEM_ALL latency for data page table reloads. ##0F4060000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_DMEM_ALL to obtain the average DMEM_ALL latency for data page table reloads. #1701,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_CACHE_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_D_OC_CACHE to obtain the average D_OC_CACHE latency for instruction page table reloads. ##0F8020000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_D_OC_CACHE to obtain the average D_OC_CACHE latency for instruction page table reloads. #1702,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_CACHE_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DATA_FROM_D_OC_CACHE to obtain the average D_OC_CACHE latency for data reloads. ##0F8040000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DATA_FROM_D_OC_CACHE to obtain the average D_OC_CACHE latency for data reloads. #1703,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_CACHE_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_D_OC_CACHE to obtain the average D_OC_CACHE latency for data page table reloads. ##0F8060000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_D_OC_CACHE to obtain the average D_OC_CACHE latency for data page table reloads. #1704,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_D_OC_CACHE_ALL to obtain the average D_OC_CACHE_ALL latency for instruction page table reloads. ##0F8020000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_D_OC_CACHE_ALL to obtain the average D_OC_CACHE_ALL latency for instruction page table reloads. #1705,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_D_OC_CACHE_ALL to obtain the average D_OC_CACHE_ALL latency for data reloads. ##0F8040000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_D_OC_CACHE_ALL to obtain the average D_OC_CACHE_ALL latency for data reloads. #1706,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_D_OC_CACHE_ALL to obtain the average D_OC_CACHE_ALL latency for data page table reloads. ##0F8060000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp cache due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_D_OC_CACHE_ALL to obtain the average D_OC_CACHE_ALL latency for data page table reloads. #1707,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_MEM_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_D_OC_MEM to obtain the average D_OC_MEM latency for instruction page table reloads. ##0FC020000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_D_OC_MEM to obtain the average D_OC_MEM latency for instruction page table reloads. #1708,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_MEM_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_D_OC_MEM to obtain the average D_OC_MEM latency for data reloads. ##0FC040000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_D_OC_MEM to obtain the average D_OC_MEM latency for data reloads. #1709,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_MEM_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_D_OC_MEM to obtain the average D_OC_MEM latency for data page table reloads. ##0FC060000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_D_OC_MEM to obtain the average D_OC_MEM latency for data page table reloads. #1710,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_MEM_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_D_OC_MEM_ALL to obtain the average D_OC_MEM_ALL latency for instruction page table reloads. ##0FC020000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_D_OC_MEM_ALL to obtain the average D_OC_MEM_ALL latency for instruction page table reloads. #1711,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_MEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_D_OC_MEM_ALL to obtain the average D_OC_MEM_ALL latency for data reloads. ##0FC040000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_D_OC_MEM_ALL to obtain the average D_OC_MEM_ALL latency for data reloads. #1712,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_MEM_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_D_OC_MEM_ALL to obtain the average D_OC_MEM_ALL latency for data page table reloads. ##0FC060000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_D_OC_MEM_ALL to obtain the average D_OC_MEM_ALL latency for data page table reloads. #1713,u,g,n,n,m,u,PM_MRK_INST_FROM_D_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_INST_FROM_D_OC_ANY to obtain the average D_OC_ANY latency for instruction reloads. ##0F8100000004C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_INST_FROM_D_OC_ANY to obtain the average D_OC_ANY latency for instruction reloads. #1714,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_D_OC_ANY to obtain the average D_OC_ANY latency for instruction page table reloads. ##0F8120000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_D_OC_ANY to obtain the average D_OC_ANY latency for instruction page table reloads. #1715,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_D_OC_ANY to obtain the average D_OC_ANY latency for data reloads. ##0F8140000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DATA_FROM_D_OC_ANY to obtain the average D_OC_ANY latency for data reloads. #1716,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_ANY_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_D_OC_ANY to obtain the average D_OC_ANY latency for data page table reloads. ##0F8160000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_D_OC_ANY to obtain the average D_OC_ANY latency for data page table reloads. #1717,u,g,n,n,m,u,PM_MRK_INST_FROM_D_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_D_OC_ANY_ALL to obtain the average D_OC_ANY_ALL latency for instruction reloads. ##0F8100000014C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_D_OC_ANY_ALL to obtain the average D_OC_ANY_ALL latency for instruction reloads. #1718,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_D_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_D_OC_ANY_ALL to obtain the average D_OC_ANY_ALL latency for instruction page table reloads. ##0F8120000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_D_OC_ANY_ALL to obtain the average D_OC_ANY_ALL latency for instruction page table reloads. #1719,u,g,n,n,m,u,PM_MRK_DATA_FROM_D_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_D_OC_ANY_ALL to obtain the average D_OC_ANY_ALL latency for data reloads. ##0F8140000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_D_OC_ANY_ALL to obtain the average D_OC_ANY_ALL latency for data reloads. #1720,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_D_OC_ANY_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_D_OC_ANY_ALL to obtain the average D_OC_ANY_ALL latency for data page table reloads. ##0F8160000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from a distant chip's OpenCapp cache or memory due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_D_OC_ANY_ALL to obtain the average D_OC_ANY_ALL latency for data page table reloads. #1721,u,g,n,n,m,u,PM_MRK_INST_FROM_ONCHIP_CACHE_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_ONCHIP_CACHE to obtain the average ONCHIP_CACHE latency for instruction reloads. ##080B00000004C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_ONCHIP_CACHE to obtain the average ONCHIP_CACHE latency for instruction reloads. #1722,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_ONCHIP_CACHE_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_ONCHIP_CACHE to obtain the average ONCHIP_CACHE latency for instruction page table reloads. ##080B20000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_ONCHIP_CACHE to obtain the average ONCHIP_CACHE latency for instruction page table reloads. #1723,u,g,n,n,m,u,PM_MRK_DATA_FROM_ONCHIP_CACHE_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_ONCHIP_CACHE to obtain the average ONCHIP_CACHE latency for data reloads. ##080B40000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_ONCHIP_CACHE to obtain the average ONCHIP_CACHE latency for data reloads. #1724,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_ONCHIP_CACHE_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_ONCHIP_CACHE to obtain the average ONCHIP_CACHE latency for data page table reloads. ##080B60000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_ONCHIP_CACHE to obtain the average ONCHIP_CACHE latency for data page table reloads. #1725,u,g,n,n,m,u,PM_MRK_INST_FROM_ONCHIP_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_ONCHIP_CACHE_ALL to obtain the average ONCHIP_CACHE_ALL latency for instruction reloads. ##080B00000014C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_ONCHIP_CACHE_ALL to obtain the average ONCHIP_CACHE_ALL latency for instruction reloads. #1726,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_ONCHIP_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_ONCHIP_CACHE_ALL to obtain the average ONCHIP_CACHE_ALL latency for instruction page table reloads. ##080B20000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_ONCHIP_CACHE_ALL to obtain the average ONCHIP_CACHE_ALL latency for instruction page table reloads. #1727,u,g,n,n,m,u,PM_MRK_DATA_FROM_ONCHIP_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_ONCHIP_CACHE_ALL to obtain the average ONCHIP_CACHE_ALL latency for data reloads. ##080B40000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_ONCHIP_CACHE_ALL to obtain the average ONCHIP_CACHE_ALL latency for data reloads. #1728,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_ONCHIP_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_ONCHIP_CACHE_ALL to obtain the average ONCHIP_CACHE_ALL latency for data page table reloads. ##080B60000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_ONCHIP_CACHE_ALL to obtain the average ONCHIP_CACHE_ALL latency for data page table reloads. #1729,u,g,n,n,m,u,PM_MRK_INST_FROM_OFFCHIP_CACHE_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_OFFCHIP_CACHE to obtain the average OFFCHIP_CACHE latency for instruction reloads. ##0C0B00000004C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss. Divide this count by PM_MRK_INST_FROM_OFFCHIP_CACHE to obtain the average OFFCHIP_CACHE latency for instruction reloads. #1730,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_OFFCHIP_CACHE_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_OFFCHIP_CACHE to obtain the average OFFCHIP_CACHE latency for instruction page table reloads. ##0C0B20000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_OFFCHIP_CACHE to obtain the average OFFCHIP_CACHE latency for instruction page table reloads. #1731,u,g,n,n,m,u,PM_MRK_DATA_FROM_OFFCHIP_CACHE_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_OFFCHIP_CACHE to obtain the average OFFCHIP_CACHE latency for data reloads. ##0C0B40000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss. Divide this count by PM_MRK_DATA_FROM_OFFCHIP_CACHE to obtain the average OFFCHIP_CACHE latency for data reloads. #1732,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_OFFCHIP_CACHE_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_OFFCHIP_CACHE to obtain the average OFFCHIP_CACHE latency for data page table reloads. ##0C0B60000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_OFFCHIP_CACHE to obtain the average OFFCHIP_CACHE latency for data page table reloads. #1733,u,g,n,n,m,u,PM_MRK_INST_FROM_OFFCHIP_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_OFFCHIP_CACHE_ALL to obtain the average OFFCHIP_CACHE_ALL latency for instruction reloads. ##0C0B00000014C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_OFFCHIP_CACHE_ALL to obtain the average OFFCHIP_CACHE_ALL latency for instruction reloads. #1734,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_OFFCHIP_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_OFFCHIP_CACHE_ALL to obtain the average OFFCHIP_CACHE_ALL latency for instruction page table reloads. ##0C0B20000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_OFFCHIP_CACHE_ALL to obtain the average OFFCHIP_CACHE_ALL latency for instruction page table reloads. #1735,u,g,n,n,m,u,PM_MRK_DATA_FROM_OFFCHIP_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_OFFCHIP_CACHE_ALL to obtain the average OFFCHIP_CACHE_ALL latency for data reloads. ##0C0B40000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_OFFCHIP_CACHE_ALL to obtain the average OFFCHIP_CACHE_ALL latency for data reloads. #1736,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_OFFCHIP_CACHE_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_OFFCHIP_CACHE_ALL to obtain the average OFFCHIP_CACHE_ALL latency for data page table reloads. ##0C0B60000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_OFFCHIP_CACHE_ALL to obtain the average OFFCHIP_CACHE_ALL latency for data page table reloads. #1737,u,g,n,n,m,u,PM_MRK_INST_FROM_ANY_MEMORY_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from any chip's memory (MC slow) due to a demand miss. Divide this count by PM_MRK_INST_FROM_ANY_MEMORY to obtain the average ANY_MEMORY latency for instruction reloads. ##095900000004C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from any chip's memory (MC slow) due to a demand miss. Divide this count by PM_MRK_INST_FROM_ANY_MEMORY to obtain the average ANY_MEMORY latency for instruction reloads. #1738,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_ANY_MEMORY_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from any chip's memory (MC slow) due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_ANY_MEMORY to obtain the average ANY_MEMORY latency for instruction page table reloads. ##095820000004C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from any chip's memory (MC slow) due to a demand miss. Divide this count by PM_MRK_IPTEG_FROM_ANY_MEMORY to obtain the average ANY_MEMORY latency for instruction page table reloads. #1739,u,g,n,n,m,u,PM_MRK_DATA_FROM_ANY_MEMORY_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from any chip's memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DATA_FROM_ANY_MEMORY to obtain the average ANY_MEMORY latency for data reloads. ##095840000004C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from any chip's memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DATA_FROM_ANY_MEMORY to obtain the average ANY_MEMORY latency for data reloads. #1740,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_ANY_MEMORY_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from any chip's memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_ANY_MEMORY to obtain the average ANY_MEMORY latency for data page table reloads. ##095860000004C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from any chip's memory (MC slow) due to a demand miss. Divide this count by PM_MRK_DPTEG_FROM_ANY_MEMORY to obtain the average ANY_MEMORY latency for data page table reloads. #1741,u,g,n,n,m,u,PM_MRK_INST_FROM_ANY_MEMORY_ALL_CYC,Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_ANY_MEMORY_ALL to obtain the average ANY_MEMORY_ALL latency for instruction reloads. ##095900000014C144 Number of cycles when a marked instruction was waiting for an ICache miss that was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_INST_FROM_ANY_MEMORY_ALL to obtain the average ANY_MEMORY_ALL latency for instruction reloads. #1742,u,g,n,n,m,u,PM_MRK_IPTEG_FROM_ANY_MEMORY_ALL_CYC,Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_ANY_MEMORY_ALL to obtain the average ANY_MEMORY_ALL latency for instruction page table reloads. ##095820000014C144 Number of cycles when a marked instruction was waiting for an IPTEG miss that was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_IPTEG_FROM_ANY_MEMORY_ALL to obtain the average ANY_MEMORY_ALL latency for instruction page table reloads. #1743,u,g,n,n,m,u,PM_MRK_DATA_FROM_ANY_MEMORY_ALL_CYC,Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_ANY_MEMORY_ALL to obtain the average ANY_MEMORY_ALL latency for data reloads. ##095840000024C144 Number of cycles when a marked instruction was waiting for a data cache miss that was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DATA_FROM_ANY_MEMORY_ALL to obtain the average ANY_MEMORY_ALL latency for data reloads. #1744,u,g,n,n,m,u,PM_MRK_DPTEG_FROM_ANY_MEMORY_ALL_CYC,Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_ANY_MEMORY_ALL to obtain the average ANY_MEMORY_ALL latency for data page table reloads. ##095860000024C144 Number of cycles when a marked instruction was waiting for a DPTEG miss that was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload. Divide this count by PM_MRK_DPTEG_FROM_ANY_MEMORY_ALL to obtain the average ANY_MEMORY_ALL latency for data page table reloads. $$$$$$$$ { counter 5} #0,u,g,n,n,n,n,PM_RUN_INST_CMPL,Run_Instructions ##0000000 Number of run instructions completed $$$$$$$$ { counter 6} #0,u,g,n,n,n,n,PM_RUN_CYC,Run_cycles ##0000000 Processor cycle gated by the run latch