# IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # # bos72X src/bos/usr/sbin/perf/pmapi/events/POWER10.dms 1.2 # # # # OBJECT CODE ONLY SOURCE MATERIALS # # COPYRIGHT International Business Machines Corp. 2020,2021 # All Rights Reserved # # The source code for this program is not published or otherwise # divested of its trade secrets, irrespective of what has been # deposited with the U.S. Copyright Office. # # IBM_PROLOG_END_TAG # Global variables CACHE_LINE_SIZE = 128; MEM_LINE_SIZE = 128; # Derived metric descriptions @PMD_Run_Cycles;Run cycles per cycle;% @@PM_RUN_CYC / PM_CYC*100 @@@group=General @PMD_CPI;CPI;NA @@PM_CYC/PM_INST_CMPL @@@group=CPI @PMD_NOTHING_DISPATCHED_CPI;NOTHING_DISPATCHED_CPI;NA @@PM_DISP_STALL_CYC/PM_RUN_INST_CMPL @@@group=CPI @PMD_NOTHING_DISPATCHED_FLUSH_CPI;NOTHING_DISPATCHED_FLUSH_CPI;NA @@PM_DISP_STALL_FLUSH/PM_RUN_INST_CMPL @@@group=CPI @PMD_NOTHING_DISPATCHED_TRANSLATION_CPI;NOTHING_DISPATCHED_TRANSLATION_CPI;NA @@PM_DISP_STALL_TRANSLATION/PM_RUN_INST_CMPL @@@group=CPI @PMD_NOTHING_DISPATCHED_IERAT_ONLY_MISS_CPI;NOTHING_DISPATCHED_IERAT_ONLY_MISS_CPI;NA @@PM_DISP_STALL_IERAT_ONLY_MISS/PM_RUN_INST_CMPL @@@group=CPI @PMD_NOTHING_DISPATCHED_ITLB_MISS_CPI;NOTHING_DISPATCHED_ITLB_MISS_CPI;NA @@PM_DISP_STALL_ITLB_MISS/PM_RUN_INST_CMPL @@@group=CPI @PMD_NOTHING_DISPATCHED_IC_MISS_CPI;NOTHING_DISPATCHED_IC_MISS_CPI;NA @@PM_DISP_STALL_IC_MISS/PM_RUN_INST_CMPL @@@group=CPI @PMD_NOTHING_DISPATCHED_IC_L2_CPI;NOTHING_DISPATCHED_IC_L2_CPI;NA @@PM_DISP_STALL_IC_L2/PM_RUN_INST_CMPL @@@group=CPI @PMD_NOTHING_DISPATCHED_IC_L3_CPI;NOTHING_DISPATCHED_IC_L3_CPI;NA @@PM_DISP_STALL_IC_L3/PM_RUN_INST_CMPL @@@group=CPI @PMD_NOTHING_DISPATCHED_IC_L3MISS_CPI;NOTHING_DISPATCHED_IC_L3MISS_CPI;NA @@PM_DISP_STALL_IC_L3MISS/PM_RUN_INST_CMPL @@@group=CPI @PMD_NOTHING_DISPATCHED_BR_MPRED_ICMISS_CPI;NOTHING_DISPATCHED_BR_MPRED_ICMISS_CPI;NA @@PM_DISP_STALL_BR_MPRED_ICMISS/PM_RUN_INST_CMPL @@@group=CPI @PMD_NOTHING_DISPATCHED_BR_MPRED_IC_L2_CPI;NOTHING_DISPATCHED_BR_MPRED_IC_L2_CPI;NA @@PM_DISP_STALL_BR_MPRED_IC_L2/PM_RUN_INST_CMPL @@@group=CPI @PMD_NOTHING_DISPATCHED_BR_MPRED_IC_L3_CPI;NOTHING_DISPATCHED_BR_MPRED_IC_L3_CPI;NA @@PM_DISP_STALL_BR_MPRED_IC_L3/PM_RUN_INST_CMPL @@@group=CPI @PMD_NOTHING_DISPATCHED_BR_MPRED_IC_L3MISS_CPI;NOTHING_DISPATCHED_BR_MPRED_IC_L3MISS_CPI;NA @@PM_DISP_STALL_BR_MPRED_IC_L3MISS/PM_RUN_INST_CMPL @@@group=CPI @PMD_NOTHING_DISPATCHED_BR_MPRED_CPI;NOTHING_DISPATCHED_BR_MPRED_CPI;NA @@PM_DISP_STALL_BR_MPRED/PM_RUN_INST_CMPL @@@group=CPI @PMD_NOTHING_DISPATCHED_HELD_CPI;NOTHING_DISPATCHED_HELD_CPI;NA @@PM_DISP_STALL_HELD_CYC/PM_RUN_INST_CMPL @@@group=CPI @PMD_DISP_HELD_STALL_SYNC_CPI;DISP_HELD_STALL_SYNC_CPI;NA @@PM_DISP_STALL_HELD_SYNC_CYC/PM_RUN_INST_CMPL @@@group=CPI @PMD_DISP_HELD_STALL_SCOREBOARD_CPI;DISP_HELD_STALL_SCOREBOARD_CPI;NA @@PM_DISP_STALL_HELD_SCOREBOARD_CYC/PM_RUN_INST_CMPL @@@group=CPI @PMD_DISP_HELD_STALL_ISSQ_FULL_CPI;DISP_HELD_STALL_ISSQ_FULL_CPI;NA @@PM_DISP_STALL_HELD_ISSQ_FULL_CYC/PM_RUN_INST_CMPL @@@group=CPI @PMD_NOTHING_DISPATCHED_HELD_RENAME_CPI;NOTHING_DISPATCHED_HELD_RENAME_CPI;NA @@PM_DISP_STALL_HELD_RENAME_CYC/PM_RUN_INST_CMPL @@@group=CPI @PMD_NOTHING_DISPATCHED_HELD_STF_MAPPER_CPI;NOTHING_DISPATCHED_HELD_STF_MAPPER_CPI;NA @@PM_DISP_STALL_HELD_STF_MAPPER_CYC/PM_RUN_INST_CMPL @@@group=CPI @PMD_NOTHING_DISPATCHED_HELD_XVFC_MAPPER_CPI;NOTHING_DISPATCHED_HELD_XVFC_MAPPER_CPI;NA @@PM_DISP_STALL_HELD_XVFC_MAPPER_CYC/PM_RUN_INST_CMPL @@@group=CPI @PMD_NOTHING_DISPATCHED_HELD_OTHER_CPI;NOTHING_DISPATCHED_HELD_OTHER_CPI;NA @@PM_DISP_STALL_HELD_OTHER_CYC/PM_RUN_INST_CMPL @@@group=CPI @PMD_ISSUE_STALL_CPI;ISSUE_STALL_CPI;NA @@PM_ISSUE_STALL/PM_RUN_INST_CMPL @@@group=CPI @PMD_STALL_CPI;STALL_CPI;NA @@PM_EXEC_STALL/PM_RUN_INST_CMPL @@@group=CPI @PMD_NTC_FLUSH_STALL_CPI;NTC_FLUSH_STALL_CPI;NA @@PM_EXEC_STALL_NTC_FLUSH/PM_RUN_INST_CMPL @@@group=CPI @PMD_FIN_AT_DISP_STALL_CPI;FIN_AT_DISP_STALL_CPI;NA @@PM_EXEC_STALL_FIN_AT_DISP/PM_RUN_INST_CMPL @@@group=CPI @PMD_BRU_STALL_CPI;BRU_STALL_CPI;NA @@PM_EXEC_STALL_BRU/PM_RUN_INST_CMPL @@@group=CPI @PMD_SIMPLE_FX_STALL_CPI;SIMPLE_FX_STALL_CPI;NA @@PM_EXEC_STALL_SIMPLE_FX/PM_RUN_INST_CMPL @@@group=CPI @PMD_VSU_STALL_CPI;VSU_STALL_CPI;NA @@PM_EXEC_STALL_VSU/PM_RUN_INST_CMPL @@@group=CPI @PMD_TRANSLATION_STALL_CPI;TRANSLATION_STALL_CPI;NA @@PM_EXEC_STALL_TRANSLATION/PM_RUN_INST_CMPL @@@group=CPI @PMD_DERAT_ONLY_MISS_STALL_CPI;DERAT_ONLY_MISS_STALL_CPI;NA @@PM_EXEC_STALL_DERAT_ONLY_MISS/PM_RUN_INST_CMPL @@@group=CPI @PMD_DERAT_DTLB_MISS_STALL_CPI;DERAT_DTLB_MISS_STALL_CPI;NA @@PM_EXEC_STALL_DERAT_DTLB_MISS/PM_RUN_INST_CMPL @@@group=CPI @PMD_LSU_STALL_CPI;LSU_STALL_CPI;NA @@PM_EXEC_STALL_LSU/PM_RUN_INST_CMPL @@@group=CPI @PMD_LOAD_STALL_CPI;LOAD_STALL_CPI;NA @@PM_EXEC_STALL_LOAD/PM_RUN_INST_CMPL @@@group=CPI @PMD_DMISS_L2L3_STALL_CPI;DMISS_L2L3_STALL_CPI;NA @@PM_EXEC_STALL_DMISS_L2L3/PM_RUN_INST_CMPL @@@group=CPI @PMD_DMISS_L2L3_CONFLICT_STALL_CPI;DMISS_L2L3_CONFLICT_STALL_CPI;NA @@PM_EXEC_STALL_DMISS_L2L3_CONFLICT/PM_RUN_INST_CMPL @@@group=CPI @PMD_DMISS_L2L3_NOCONFLICT_STALL_CPI;DMISS_L2L3_NOCONFLICT_STALL_CPI;NA @@PM_EXEC_STALL_DMISS_L2L3_NOCONFLICT/PM_RUN_INST_CMPL @@@group=CPI @PMD_DMISS_L3MISS_STALL_CPI;DMISS_L3MISS_STALL_CPI;NA @@PM_EXEC_STALL_DMISS_L3MISS/PM_RUN_INST_CMPL @@@group=CPI @PMD_DMISS_L21_L31_STALL_CPI;DMISS_L21_L31_STALL_CPI;NA @@PM_EXEC_STALL_DMISS_L21_L31/PM_RUN_INST_CMPL @@@group=CPI @PMD_DMISS_LMEM_STALL_CPI;DMISS_LMEM_STALL_CPI;NA @@PM_EXEC_STALL_DMISS_LMEM/PM_RUN_INST_CMPL @@@group=CPI @PMD_DMISS_OFF_CHIP_STALL_CPI;DMISS_OFF_CHIP_STALL_CPI;NA @@PM_EXEC_STALL_DMISS_OFF_CHIP/PM_RUN_INST_CMPL @@@group=CPI @PMD_DMISS_OFF_NODE_STALL_CPI;DMISS_OFF_NODE_STALL_CPI;NA @@PM_EXEC_STALL_DMISS_OFF_NODE/PM_RUN_INST_CMPL @@@group=CPI @PMD_TLBIEL_STALL_CPI;TLBIEL_STALL_CPI;NA @@PM_EXEC_STALL_TLBIEL/PM_RUN_INST_CMPL @@@group=CPI @PMD_LOAD_FINISH_STALL_CPI;LOAD_FINISH_STALL_CPI;NA @@PM_EXEC_STALL_LOAD_FINISH/PM_RUN_INST_CMPL @@@group=CPI @PMD_STORE_STALL_CPI;STORE_STALL_CPI;NA @@PM_EXEC_STALL_STORE/PM_RUN_INST_CMPL @@@group=CPI @PMD_STORE_PIPE_STALL_CPI;STORE_PIPE_STALL_CPI;NA @@PM_EXEC_STALL_STORE_PIPE/PM_RUN_INST_CMPL @@@group=CPI @PMD_STORE_MISS_STALL_CPI;STORE_MISS_STALL_CPI;NA @@PM_EXEC_STALL_STORE_MISS/PM_RUN_INST_CMPL @@@group=CPI @PMD_TLBIE_STALL_CPI;TLBIE_STALL_CPI;NA @@PM_EXEC_STALL_TLBIE/PM_RUN_INST_CMPL @@@group=CPI @PMD_PTESYNC_STALL_CPI;PTESYNC_STALL_CPI;NA @@PM_EXEC_STALL_PTESYNC/PM_RUN_INST_CMPL @@@group=CPI @PMD_COMPLETION_STALL_CPI;COMPLETION_STALL_CPI;NA @@PM_CMPL_STALL/PM_RUN_INST_CMPL @@@group=CPI @PMD_EXCEPTION_COMPLETION_STALL_CPI;EXCEPTION_COMPLETION_STALL_CPI;NA @@PM_CMPL_STALL_EXCEPTION/PM_RUN_INST_CMPL @@@group=CPI @PMD_MEM_ECC_COMPLETION_STALL_CPI;MEM_ECC_COMPLETION_STALL_CPI;NA @@PM_CMPL_STALL_MEM_ECC/PM_RUN_INST_CMPL @@@group=CPI @PMD_STCX_COMPLETION_STALL_CPI;STCX_COMPLETION_STALL_CPI;NA @@PM_CMPL_STALL_STCX/PM_RUN_INST_CMPL @@@group=CPI @PMD_LWSYNC_COMPLETION_STALL_CPI;LWSYNC_COMPLETION_STALL_CPI;NA @@PM_CMPL_STALL_LWSYNC/PM_RUN_INST_CMPL @@@group=CPI @PMD_HWSYNC_COMPLETION_STALL_CPI;HWSYNC_COMPLETION_STALL_CPI;NA @@PM_CMPL_STALL_HWSYNC/PM_RUN_INST_CMPL @@@group=CPI @PMD_SPECIAL_COMPLETION_STALL_CPI;SPECIAL_COMPLETION_STALL_CPI;NA @@PM_CMPL_STALL_SPECIAL/PM_RUN_INST_CMPL @@@group=CPI @PMD_NTC_FIN_CPI;NTC_FIN_CPI;NA @@PM_NTC_FIN/PM_RUN_INST_CMPL @@@group=CPI @PMD_NOTHING_DISPATCHED_FETCH_CPI;NOTHING_DISPATCHED_FETCH_CPI;NA @@PM_DISP_STALL_FETCH/PM_RUN_INST_CMPL @@@group=CPI @PMD_NOTHING_DISPATCHED_HELD_HALT_CPI;NOTHING_DISPATCHED_HELD_HALT_CPI;NA @@PM_DISP_STALL_HELD_HALT_CYC/PM_RUN_INST_CMPL @@@group=CPI @PMD_Flush_Rate;Flush rate (%);% @@PM_FLUSH * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_ISU_Flush_Rate;ISU Flush rate. All flushes initiated by the Instruction Sequencing Unit (ISU);% @@PM_ISU_FLUSH *100 / PM_RUN_INST_CMPL @@@group=General @PMD_Br_Mpred_Flush_Rate;Branch Mispredict flushes per instruction;% @@PM_FLUSH_MPRED / PM_RUN_INST_CMPL * 100 @@@group=General @PMD_Branch_Misprediction_Rate;Branch misprediction flush rate. A flush occurred due to a mispredicted branch. Includes target and direction;NA @@PM_BR_MPRED_CMPL / PM_RUN_INST_CMPL @@@group=Others @PMD_L1_LD_Miss_Ratio;Percentage of L1 load misses per L1 load ref;% @@PM_LD_MISS_L1 / PM_LD_REF_L1 * 100 @@@group=General @PMD_L1_LD_Miss_Rate;Percentage of L1 demand load misses per run instruction;% @@PM_LD_MISS_L1 * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_L1_ST_Miss_Rate;Percentage of L1 store misses per run instruction;% @@PM_ST_MISS_L1 * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_DTLB_Miss_Rate;% DTLB miss rate per inst;% @@PM_DTLB_MISS * 100/ PM_RUN_INST_CMPL @@@group=General @PMD_DC_Reload_Collision_Rate;A load reading the L1 cache has a bank collisions with another load reading or a reload/dkill writing the L1 cache;% @@PM_DC_RELOAD_COLLISIONS * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_DC_Store_Write_Collision_Rate;A store writing the L1 cache at the same time as a reload or dkill writing the L1 cache that results in a bank collision.;% @@PM_DC_STORE_WRITE_COLLISIONS * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_Branch_miss_direction;Branch miss direction;NA @@(PM_MPRED_BR_TKN_COND_DIR + PM_MPRED_BR_NTKN_COND_DIR) / (PM_BR_FIN - PM_BR_TKN_UNCOND_FIN) @@@group=Branch @PMD_Branch_miss_direction_lbht_lsel;Branch miss direction lbht lsel;NA @@(PM_BR_MPRED_TKN_COND_DIR_LBHT_LSEL + PM_BR_MPRED_NTKN_COND_DIR_LBHT_LSEL) / (PM_BR_FIN - PM_BR_TKN_UNCOND_FIN) @@@group=Branch @PMD_Branch_miss_direction_lbht_gsel;Branch miss direction lbht gsel;NA @@(PM_BR_MPRED_TKN_COND_DIR_LBHT_GSEL + PM_BR_MPRED_NTKN_COND_DIR_LBHT_GSEL) / (PM_BR_FIN - PM_BR_TKN_UNCOND_FIN) @@@group=Branch @PMD_Branch_miss_direction_gbht;Branch miss direction gbht;NA @@(PM_BR_MPRED_TKN_COND_DIR_GBHT + PM_BR_MPRED_NTKN_COND_DIR_GBHT) / (PM_BR_FIN - PM_BR_TKN_UNCOND_FIN) @@@group=Branch @PMD_Branch_miss_direction_tage;Branch miss direction tage;NA @@(PM_BR_MPRED_TKN_COND_DIR_TAGE + PM_BR_MPRED_NTKN_COND_DIR_TAGE) / (PM_BR_FIN - PM_BR_TKN_UNCOND_FIN) @@@group=Branch @PMD_Branch_miss_direction_top;Branch miss direction top;NA @@(PM_BR_MPRED_TKN_COND_DIR_TOP + PM_BR_MPRED_NTKN_COND_DIR_TOP) / (PM_BR_FIN - PM_BR_TKN_UNCOND_FIN) @@@group=Branch @PMD_Branch_miss_hint;Branch miss hint;NA @@(PM_BR_MPRED_TKN_SWHINT + PM_BR_MPRED_NTKN_SWHINT) / (PM_BR_FIN - PM_BR_TKN_UNCOND_FIN) @@@group=Branch @PMD_Speculation;Instruction dispatch-to-completion ratio;NA @@PM_INST_DISP / PM_RUN_INST_CMPL @@@group=General @PMD_Average_Completed_Instruction_Set_Size;Avg. more than 1 instructions completed;NA @@PM_RUN_INST_CMPL / PM_1PLUS_PPC_CMPL @@@group=General @PMD_L2_LD_Miss_Rate;L2 dmand Load Miss Rate (per run instruction)(%);% @@PM_DATA_FROM_L2MISS * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_L3_LD_Miss_Rate_percent;L3 demand Load Miss Rate (per run instruction)(%);NA @@PM_DATA_FROM_L3MISS * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_L2_PTEG_Miss_Rate;L2 PTEG Miss Rate (per run instruction)(%);% @@PM_DPTEG_FROM_L2MISS * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_L1_Inst_Miss_Rate;Instruction Cache Miss Rate (Per run Instruction)(%);% @@PM_L1_ICACHE_MISS * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_L2_Inst_Miss_Rate;L2 Instruction Miss Rate (per instruction)(%);% @@PM_INST_FROM_L2MISS * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_L3_Inst_Miss_Rate;L3 Instruction Miss Rate (per instruction)(%);% @@PM_INST_FROM_L3MISS * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_IPC;Instructions per cycles;NA @@PM_INST_CMPL / PM_CYC @@@group=General @PMD_Cycles_Per_Completed_Instructions_Set;Cycles per instruction group;NA @@PM_CYC / PM_1PLUS_PPC_CMPL @@@group=General @PMD_Cycles_Atleast_One_Inst_Dispatched;Percentage Cycles atleast one instruction dispatched;% @@PM_1PLUS_PPC_DISP / PM_RUN_CYC * 100 @@@group=General @PMD_Loads_per_inst;PCT instruction loads;NA @@PM_LD_REF_L1 / PM_RUN_INST_CMPL @@@group=General @PMD_Stores_per_inst;PCT instruction stores;NA @@PM_ST_FIN / PM_RUN_INST_CMPL @@@group=General @PMD_dL1_Reload_FROM_L2_Rate;% of DL1 reloads from L2 per Inst;% @@PM_DATA_FROM_L2 * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_dL1_Reload_FROM_L2_Miss_Rate;% of DL1 reloads from L2 per Inst;% @@PM_DATA_FROM_L2MISS * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_dL1_Reload_FROM_RL2L3_MOD_Rate;% of DL1 reloads from Private L3, other core per Inst;% @@PM_DATA_FROM_RL2L3_MOD * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_dL1_Reload_FROM_RL2L3_SHR_Rate;% of DL1 reloads from Private L3, other core per Inst;% @@PM_DATA_FROM_RL2L3_SHR * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_dL1_Reload_FROM_L3_Rate;% of DL1 Reloads from L3 per Inst;% @@PM_DATA_FROM_L3 * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_dL1_Reload_FROM_L3_MEPF_Rate;% of DL1 Reloads that came from the L3 and were brought into the L3 by a prefetch, per instruction completed;% @@PM_DATA_FROM_L3_MEPF * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_dL1_Reload_FROM_L3_Miss_Rate;% of DL1 reloads from L3 per Inst;% @@PM_DATA_FROM_L3MISS * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_dL1_Reload_FROM_DL2L3_MOD_Rate;% of DL1 Reloads from Distant L2 or L3 (Modified) per Inst;% @@PM_DATA_FROM_DL2L3_MOD * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_dL1_Reload_FROM_DL2L3_SHR_Rate;% of DL1 Reloads from Distant L2 or L3 (Shared) per Inst;% @@PM_DATA_FROM_DL2L3_SHR * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_dL1_Reload_FROM_LMEM_Rate;% of DL1 Reloads from Local Memory per Inst;% @@PM_DATA_FROM_LMEM * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_dL1_Reload_FROM_RMEM_Rate;% of DL1 Reloads from Remote Memory per Inst;% @@PM_DATA_FROM_RMEM * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_dL1_Reload_FROM_DMEM_Rate;% of DL1 Reloads from Distant Memory per Inst;% @@PM_DATA_FROM_DMEM * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_L2_Latency;Marked L2 Load latency;NA @@PM_MRK_DATA_FROM_L2_CYC/ PM_MRK_DATA_FROM_L2 @@@group=Latency @PMD_L3_Latency;Marked L3 Load latency;NA @@PM_MRK_DATA_FROM_L3_CYC/ PM_MRK_DATA_FROM_L3 @@@group=Latency @PMD_RL2L3_MOD_Latency;Marked L2L3 remote Load latency;NA @@PM_MRK_DATA_FROM_RL2L3_MOD_CYC/ PM_MRK_DATA_FROM_RL2L3_MOD @@@group=Latency @PMD_RL2L3_SHR_Latency;Marked L2L3 remote Load latency;NA @@PM_MRK_DATA_FROM_RL2L3_SHR_CYC/ PM_MRK_DATA_FROM_RL2L3_SHR @@@group=Latency @PMD_DL2L3_MOD_Latency;Marked L2L3 remote Load latency;NA @@PM_MRK_DATA_FROM_DL2L3_MOD_CYC/ PM_MRK_DATA_FROM_DL2L3_MOD @@@group=Latency @PMD_DL2L3_SHR_Latency;Marked L2L3 distant Load latency;NA @@PM_MRK_DATA_FROM_DL2L3_SHR_CYC/ PM_MRK_DATA_FROM_DL2L3_SHR @@@group=Latency @PMD_LMEM_Latency;Marked Lmem Load latency;NA @@PM_MRK_DATA_FROM_LMEM_CYC/ PM_MRK_DATA_FROM_LMEM @@@group=Latency @PMD_RMEM_Latency;Marked Rmem Load latency;NA @@PM_MRK_DATA_FROM_RMEM_CYC/ PM_MRK_DATA_FROM_RMEM @@@group=Latency @PMD_DMEM_Latency;Marked Dmem Load latency;NA @@PM_MRK_DATA_FROM_DMEM_CYC/ PM_MRK_DATA_FROM_DMEM @@@group=Latency @PMD_MEM_LOCALITY;Memory locality;% @@PM_DATA_FROM_LMEM * 100/ (PM_DATA_FROM_LMEM + PM_DATA_FROM_RMEM + PM_DATA_FROM_DMEM) @@@group=General @PMD_LD_LMEM_PER_LD_RMEM;Number of loads from local memory per loads from remote memory;NA @@PM_DATA_FROM_LMEM / PM_DATA_FROM_RMEM @@@group=Memory @PMD_LD_LMEM_PER_LD_DMEM;Number of loads from local memory per loads from distant memory;NA @@PM_DATA_FROM_LMEM / PM_DATA_FROM_DMEM @@@group=Memory @PMD_LD_LMEM_PER_LD_MEM;Number of loads from local memory per loads from remote and distant memory;NA @@PM_DATA_FROM_LMEM / (PM_DATA_FROM_DMEM + PM_DATA_FROM_RMEM) @@@group=Memory @PMD_ITLB_Miss_Rate;% ITLB miss rate per inst;% @@PM_ITLB_MISS / PM_RUN_INST_CMPL *100 @@@group=General @PMD_PTEG_FROM_L2;% of DERAT reloads from L2;% @@PM_DPTEG_FROM_L2 * 100 / PM_DTLB_MISS @@@group=General @PMD_LD_RMEM_PER_LD_DMEM;Number of loads from remote memory per loads from distant memory;NA @@PM_DATA_FROM_RMEM / PM_DATA_FROM_DMEM @@@group=Memory @PMD_DERAT_4K_Miss_Rate;% DERAT miss rate for 4K page per inst;% @@PM_DERAT_MISS_4K * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_DERAT_64K_Miss_Rate;% DERAT miss ratio for 64K page per inst;% @@PM_DERAT_MISS_64K * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_PTEG_FROM_RMEM;% of DERAT reloads from Remote Memory;% @@PM_DPTEG_FROM_RMEM * 100 / PM_DTLB_MISS @@@group=General @PMD_PTEG_FROM_DMEM;% of DERAT reloads from Distant Memory;% @@PM_DPTEG_FROM_DMEM * 100 / PM_DTLB_MISS @@@group=General @PMD_PTEG_FROM_L2_Rate;% of DERAT reloads from L2 per inst;% @@PM_DPTEG_FROM_L2 * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_PTEG_FROM_L3_Rate;% of DERAT reloads from L3 per inst;% @@PM_DPTEG_FROM_L3 * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_PTEG_FROM_RL2L3_SHR_Rate;% of DERAT reloads from Remote L2 or L3 (Shared) per inst;% @@PM_DPTEG_FROM_RL2L3_SHR * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_PTEG_FROM_RL2L3_MOD_Rate;% of DERAT reloads from Remote L2 or L3 (Modified) per inst;% @@PM_DPTEG_FROM_RL2L3_MOD * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_PTEG_FROM_L3;% of DERAT reloads from L3;% @@PM_DPTEG_FROM_L3 * 100 / PM_DTLB_MISS @@@group=General @PMD_PTEG_FROM_RL2L3_SHR;% of DERAT reloads from Remote L2 or L3 (Shared);% @@PM_DPTEG_FROM_RL2L3_SHR * 100 / PM_DTLB_MISS @@@group=General @PMD_PTEG_FROM_RL2L3_MOD;% of DERAT reloads from Remote L2 or L3 (Modified);% @@PM_DPTEG_FROM_RL2L3_MOD * 100 / PM_DTLB_MISS @@@group=General @PMD_PTEG_FROM_DL2L3_MOD;% of DERAT reloads from Distant L2 or L3 (Modified);% @@PM_DPTEG_FROM_DL2L3_MOD * 100 / PM_DTLB_MISS @@@group=General @PMD_PTEG_FROM_DL2L3_SHR;% of DERAT reloads from Distant L2 or L3 (Shared);% @@PM_DPTEG_FROM_DL2L3_SHR * 100 / PM_DTLB_MISS @@@group=General @PMD_PTEG_FROM_LMEM;% of DERAT reloads from Local Memory;% @@PM_DPTEG_FROM_LMEM * 100 / PM_DTLB_MISS @@@group=General @PMD_PTEG_FROM_DL2L3_MOD_Rate;% of DERAT reloads from Distant L2 or L3 (Modified) per inst;% @@PM_DPTEG_FROM_DL2L3_MOD * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_PTEG_FROM_DL2L3_SHR_Rate;% of DERAT reloads from Distant L2 or L3 (Shared) per inst;% @@PM_DPTEG_FROM_DL2L3_SHR * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_PTEG_FROM_LMEM_Rate;% of DERAT reloads from Local Memory per inst;% @@PM_DPTEG_FROM_LMEM * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_PTEG_FROM_RMEM_Rate;% of DERAT reloads from Remote Memory per inst;% @@PM_DPTEG_FROM_RMEM * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_PTEG_FROM_DMEM_Rate;% of DERAT reloads from Distant Memory per inst;% @@PM_DPTEG_FROM_DMEM * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_INST_FROM_L2;% of ICache reloads from L2;% @@PM_INST_FROM_L2 * 100 / PM_L1_ICACHE_MISS @@@group=General @PMD_INST_FROM_L3;% of ICache reloads from L3;% @@PM_INST_FROM_L3 * 100 / PM_L1_ICACHE_MISS @@@group=General @PMD_INST_FROM_LMEM;% of ICache reloads from Local Memory;% @@PM_INST_FROM_LMEM * 100 / PM_L1_ICACHE_MISS @@@group=General @PMD_INST_FROM_RMEM;% of ICache reloads from Remote Memory;% @@PM_INST_FROM_RMEM * 100 / PM_L1_ICACHE_MISS @@@group=General @PMD_INST_FROM_DMEM;% of ICache reloads from Distant Memory;% @@PM_INST_FROM_DMEM * 100 / PM_L1_ICACHE_MISS @@@group=General @PMD_INST_FROM_L2_Rate;% of ICache reloads from L2 per Inst;% @@PM_INST_FROM_L2 * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_INST_FROM_L3_Rate;% of ICache reloads from L3 per Inst;% @@PM_INST_FROM_L3 * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_INST_FROM_LMEM_Rate;% of ICache reloads from Local Memory per Inst;% @@PM_INST_FROM_LMEM * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_INST_FROM_RMEM_Rate;% of ICache reloads from Remote Memory per Inst;% @@PM_INST_FROM_RMEM * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_INST_FROM_DMEM_Rate;% of ICache reloads from Distant Memory per Inst;% @@PM_INST_FROM_DMEM * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_Estimated_dL1Miss_Latency;average L1 miss latency using marked events;NA @@PM_MRK_LD_MISS_L1_CYC / PM_MRK_LD_MISS_L1 @@@group=Latency @PMD_RUN_CPI;Run cycles per run instruction;NA @@PM_RUN_CYC / PM_RUN_INST_CMPL @@@group=General @PMD_Custom_secs;cycles;NA @@PM_RUN_CYC @@@group=General @PMD_L2_LD_Miss_Ratio;L2 Load misses as a % of total L2 Load dispatches (per thread);% @@PM_L2_LD_MISS / PM_L2_LD * 100 @@@group=General @PMD_L2_ld_hit_frequency;Average number of cycles between L2 Load hits;NA @@(PM_L2_LD_HIT / PM_RUN_CYC) / 2 @@@group=L2_stats @PMD_L2_ld_miss_frequency;Average number of cycles between L2 Load misses;NA @@(PM_L2_LD_MISS / PM_RUN_CYC) / 2 @@@group=L2_stats @PMD_L2_ST_Miss_Ratio;L2 Store misses as a % of total L2 Store dispatches (per thread);% @@PM_L2_ST_MISS / PM_L2_ST * 100 @@@group=General @PMD_L2_INST_Miss_Ratio;L2 Inst misses as a % of total L2 Inst dispatches (per thread);% @@PM_L2_INST_MISS / PM_L2_INST * 100 @@@group=General @PMD_L2_IC_Inv_Rate;L2 Icache invalidates per run inst (per core);% @@(PM_L2_IC_INV / 2 ) / PM_RUN_INST_CMPL * 100 @@@group=General @PMD_L2_DC_Inv_Rate;L2 dcache invalidates per run inst (per core);% @@(PM_L2_DC_INV / 2 ) / PM_RUN_INST_CMPL * 100 @@@group=General @PMD_L2_Mod_CO;L2 COs that were in M,Me,Mu state as a % of all L2 COs;% @@PM_L2_CASTOUT_MOD / (PM_L2_CASTOUT_MOD + PM_L2_CASTOUT_SHR) * 100 @@@group=General @PMD_L2_Shr_CO;L2 COs that were in T,Te,Si,S state as a % of all L2 COs;% @@PM_L2_CASTOUT_SHR / (PM_L2_CASTOUT_MOD + PM_L2_CASTOUT_SHR) * 100 @@@group=General @PMD_L2_Local_Pred_Correct;L2 local pump prediction success;% @@PM_L2_LOC_GUESS_CORRECT / (PM_L2_LOC_GUESS_CORRECT + PM_L2_LOC_GUESS_WRONG) * 100 @@@group=General @PMD_L2_CO_M_Rd_Util;%L2 Modified CO Cache read Utilization (4 pclks per disp attempt);NA @@((PM_L2_CASTOUT_MOD/2)*4)/ ( PM_RUN_CYC) * 100 @@@group=L2_stats @PMD_L2_LDMISS_Wr_Util;L2 load misses that require a cache write (4 pclks per disp attempt) % of pclks;NA @@((( PM_L2_LD_DISP - PM_L2_LD_HIT)/2)*4)/ ( PM_RUN_CYC) * 100 @@@group=L2_stats @PMD_L2_ST_Wr_Util;L2 stores that require a cache write (4 pclks per disp attempt) % of pclks;NA @@((PM_L2_ST_DISP/2)*4)/ ( PM_RUN_CYC) * 100 @@@group=L2_stats @PMD_DPTEG_FROM_L2_Rate;Rate of DERAT reloads from L2;% @@PM_DPTEG_FROM_L2 * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_DPTEG_FROM_L3_Rate;Rate of DERAT reloads from L3;% @@PM_DPTEG_FROM_L3 * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_IPTEG_FROM_L2_Rate;Rate of IERAT reloads from L2;% @@PM_IPTEG_FROM_L2 * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_IPTEG_FROM_L3_Rate;Rate of IERAT reloads from L3;% @@PM_IPTEG_FROM_L3 * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_IPTEG_FROM_LMEM_Rate;Rate of IERAT reloads from local memory;% @@PM_IPTEG_FROM_LMEM * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_L3_WI_Usage;Average number of Write-in machines used. 1 of 8 WI machines is sampled every L3 cycle;NA @@(PM_L3_WI_USAGE / PM_RUN_CYC) * 8 @@@group=L3_stats @PMD_L3_ld_hit_frequency;Average number of cycles between L3 Load hits;NA @@(PM_L3_LD_HIT / PM_RUN_CYC) / 2 @@@group=L3_stats @PMD_L3_ld_miss_frequency;Average number of cycles between L3 Load misses;NA @@(PM_L3_LD_MISS / PM_RUN_CYC) / 2 @@@group=L3_stats @PMD_DERAT_Miss_Rate;DERAT Miss Rate (per run instruction)(%);% @@PM_DERAT_MISS * 100 / PM_RUN_INST_CMPL @@@group=General @PMD_L2_MISS_LATENCY;l2_miss_latency;NA @@PM_MRK_DATA_FROM_L2MISS_CYC/PM_MRK_DATA_FROM_L2MISS @@@group=Latency @PMD_L3_MEPF_LATENCY;l3_mepf_latency;NA @@PM_MRK_DATA_FROM_L3_MEPF_CYC/PM_MRK_DATA_FROM_L3_MEPF @@@group=Latency @PMD_L21_REGENT_SHR_LATENCY;l21_regent_shr_latency;NA @@PM_MRK_DATA_FROM_L21_REGENT_SHR_CYC/PM_MRK_DATA_FROM_L21_REGENT_SHR @@@group=Latency @PMD_L21_REGENT_MOD_LATENCY;l21_regent_mod_latency;NA @@PM_MRK_DATA_FROM_L21_REGENT_MOD_CYC/PM_MRK_DATA_FROM_L21_REGENT_MOD @@@group=Latency @PMD_L31_REGENT_SHR_LATENCY;l31_regent_shr_latency;NA @@PM_MRK_DATA_FROM_L31_REGENT_SHR_CYC/PM_MRK_DATA_FROM_L31_REGENT_SHR @@@group=Latency @PMD_L31_REGENT_MOD_LATENCY;l31_regent_mod_latency;NA @@PM_MRK_DATA_FROM_L31_REGENT_MOD_CYC/PM_MRK_DATA_FROM_L31_REGENT_MOD @@@group=Latency @PMD_L21_NON_REGENT_SHR_LATENCY;l21_non_regent_shr_latency;NA @@PM_MRK_DATA_FROM_L21_NON_REGENT_SHR_CYC/PM_MRK_DATA_FROM_L21_NON_REGENT_SHR @@@group=Latency @PMD_L21_NON_REGENT_MOD_LATENCY;l21_non_regent_mod_latency;NA @@PM_MRK_DATA_FROM_L21_NON_REGENT_MOD_CYC/PM_MRK_DATA_FROM_L21_NON_REGENT_MOD @@@group=Latency @PMD_L31_NON_REGENT_SHR_LATENCY;l31_non_regent_shr_latency;NA @@PM_MRK_DATA_FROM_L31_NON_REGENT_SHR_CYC/PM_MRK_DATA_FROM_L31_NON_REGENT_SHR @@@group=Latency @PMD_L31_NON_REGENT_MOD_LATENCY;l31_non_regent_mod_latency;NA @@PM_MRK_DATA_FROM_L31_NON_REGENT_MOD_CYC/PM_MRK_DATA_FROM_L31_NON_REGENT_MOD @@@group=Latency @PMD_ANY_MEMORY_LATENCY;any_memory_latency;NA @@PM_MRK_DATA_FROM_ANY_MEMORY_CYC/PM_MRK_DATA_FROM_ANY_MEMORY @@@group=Latency @PMD_LD_RATE;ld_rate;NA @@PM_LD_CMPL/PM_RUN_INST_CMPL @@@group=Latency @PMD_L21_REGENT_ALL_RATE_PERCENT;l21_regent_all_rate_percent;NA @@(PM_DATA_FROM_L21_REGENT_ALL/PM_RUN_INST_CMPL)*100 @@@group=Latency @PMD_L31_REGENT_ALL_RATE_PERCENT;l31_regent_all_rate_percent;NA @@(PM_DATA_FROM_L31_REGENT_ALL/PM_RUN_INST_CMPL)*100 @@@group=Latency @PMD_L21_NON_REGENT_ALL_RATE_PERCENT;l21_non_regent_all_rate_percent;NA @@(PM_DATA_FROM_L21_NON_REGENT_ALL/PM_RUN_INST_CMPL)*100 @@@group=Latency @PMD_L31_NON_REGENT_ALL_RATE_PERCENT;l31_non_regent_all_rate_percent;NA @@(PM_DATA_FROM_L31_NON_REGENT_ALL/PM_RUN_INST_CMPL)*100 @@@group=Latency @PMD_ANY_MEMORY_RATE_PERCENT;any_memory_rate_percent;NA @@(PM_DATA_FROM_ANY_MEMORY/PM_RUN_INST_CMPL)*100 @@@group=Latency @PMD_LMEM_RATE_PERCENT;lmem_rate_percent;NA @@(PM_DATA_FROM_LMEM/PM_RUN_INST_CMPL)*100 @@@group=Latency @PMD_PM_EXEC_STALL_DMISS_L2L3_DELTA;any_memory_per_l3_miss_percent;NA @@(PM_EXEC_STALL_DMISS_L2L3*PM_EXEC_STALL_LOAD_FINISH)/(PM_EXEC_STALL_LOAD - PM_EXEC_STALL_LOAD_FINISH - PM_EXEC_STALL_TLBIEL) @@@group=General @PMD_PM_EXEC_STALL_DMISS_L3MISS_DELTA;any_memory_per_l3_miss_percent;NA @@(PM_EXEC_STALL_DMISS_L3MISS*PM_EXEC_STALL_LOAD_FINISH)/(PM_EXEC_STALL_LOAD - PM_EXEC_STALL_LOAD_FINISH - PM_EXEC_STALL_TLBIEL) @@@group=General