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cJK`8!!}Aa컁N cE9 88~ 8$8nKAcc89889> cJK`8!Aa}N 8i88T8~ K-Acc88899> cJK=`8!Aa}N c`e9> c`889K`8!a상}N A @ lilac_tu2A L| N dusbTU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG exectu()exectu()EXECTU: Invalid TUEXECTU: Calling TU OpenEXECTU: Calling TU CLOSEEXECTU: TU CLOSE SucceededEXECTU: TU OPEN Succeeded, State = %dEXECTU: Calling TU02 - IO Register TestEXECTU: Calling TU01 - PCI Register TestEXECTU: TU is 1: Status = %d, State = %dEXECTU: TU is 2: Status = %d, State = %dEXECTU: TU is 3: Status = %d, State = %dEXECTU: Unknown TU %d called: status = %dEXECTU: Calling TU03 - EEPROM Register Test EXECTU: TU is 0, already in diagnose state. status = %dEXECTU: TU is 0, already in diagnose state. status = %d EXECTU: TU is not 0, and not in correct state, state = %d. status = %dEXECTU: TU is not 0, and not in correct state, state = %d. status = %d @(#)12 1.3 src/bos/diag/tu/lilac/lilac_exectu.c, tu_lilac, bos72V, v2020_01A1 12/11/19 13:41:25 dusbTU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_01: %sTU_01: %s --DONETU_01: 0x%02x 0x%08xlilac_tu01_config_regs.clilac_tu01_config_regs.clilac_tu01_config_regs.clilac_tu01_config_regs.clilac_tu01_config_regs.clilac_tu01_config_regs.clilac_tu01_config_regs.clilac_tu01_config_regs.cTU_01: WRITE: 0x%02x 0x%08xTU_01: COMPARE: 0x%02x 0x%08xTU_01_PCIcfg and Register TestTU_01: Saving PCI CFG registersWARNING: AERR CE: Bad TLP FoundWARNING: AERR CE: Bad DLLP FoundTU_01: PCI PWR Cap: 0x%02x 0x%08xTU_01: PCI MSI Cap: 0x%02x 0x%08xTU_01: PCIe AER Cap: 0x%03x 0x%08xTU_01: Comparing PCI CFG registersTU_01: PCI MSI-X Cap: 0x%02x 0x%08xTU_01: Writing to PCI CFG registersCFG_REG: PCI MSIX Cap: Enabled = NoTU_01: PCIe DevSN Cap: 0x%03x 0x%08xCFG_REG: PCI MSIX Cap: Enabled = YesCFG_REG: PCIe DevSN Cap: 0x%08x %08xTU_01: PCI Express Cap: 0x%02x 0x%08xDIAG ERROR: AERR UE: ECRC Error FoundWARNING: AERR CE: REPLAY_NUM RolloverWARNING: AERR CE: Receiver Error FoundWARNING: AERR CE: Replay Timer TimeoutCFG_REG: PCI MSIX Cap: PBA BIR = 0x%02xDIAG ERROR: AERR UE: Poisoned TLP FoundDIAG ERROR: AERR UE: Malformed TLP FoundDIAG ERROR: AERR UE: ACS Violation FoundCFG_REG: PCI MSIX Cap: Table BIR = 0x%02xDIAG ERROR: AERR UE: MC Blocked TLP FoundCFG_REG: PCI MSIX Cap: PBA offset = 0x%08xCFG_REG: PCI MSIX Cap: Table size = 0x%04xPCIE ERROR: CFG_REG: PCIe Cap: Fatal errorDIAG ERROR: AERR UE: Completer Abort FoundCFG_REG: PCI PCIe Cap: Max Link Width = x%dWARNING: AERR CE: Header Log Overflow FoundCFG_REG: PCI MSIX Cap: Table offset = 0x%08xDIAG ERROR: AERR UE: Receiver Overflow FoundCFG_REG: PCI PCIe Cap: AUX Power Present = NoDIAG ERROR: AERR UE: Completion Timeout FoundTU_01: PCI Config Space Read Complete, rc = %dCFG_REG: PCI PCIe Cap: AUX Power Present = YesPCIE ERROR: CFG_REG: PCIe Cap: Non-fatal errorDIAG ERROR: AERR UE: Surprise Down Error FoundCFG_REG: PCI PCIe Cap: Current Link Width = x%dCFG_REG: PCI PCIe Cap: Max Link Speed = Unknownpci_config_read[%02x] = 0x%08x Line: %d File:%s PCIE ERROR: CFG_REG: PCIe Cap: Correctable errorCFG_REG: PCI PCIe Cap: Max Link Speed = 2.5 GT/sCFG_REG: PCI PCIe Cap: Max Link Speed = 5.0 GT/sCFG_REG: PCI PCIe Cap: Max Link Speed = 8.0 GT/sDIAG ERROR: AERR UE: Unexpected Completion FoundWARNING: AERR CE: Advisory Non-Fatal Error FoundWARNING: AERR CE: Corrected Internal Error FoundCFG_REG: PCI PCIe Cap: Max Link Speed = 16.0 GT/sPCIE ERROR: CFG_REG: PCIe Cap: Error(s) detected: DIAG ERROR: AERR UE: AtomicOp Egress Blocked FoundCFG_REG: PCI PCIe Cap: Current Link Speed = UnknownDIAG ERROR: AERR UE: Data Link Protocol Error FoundDIAG ERROR: AERR UE: TLP Prefix Blocked Error FoundCFG_REG: PCI PCIe Cap: Interrupt Message Number = %dCFG_REG: PCI PCIe Cap: Current Link Speed = 2.5 GT/sCFG_REG: PCI PCIe Cap: Current Link Speed = 5.0 GT/sCFG_REG: PCI PCIe Cap: Current Link Speed = 8.0 GT/sDIAG ERROR: AERR UE: Unsupported Request Error FoundTU_01: Unknown PCI Capability 0x%08x at Offset 0x%02xCFG_REG: PCI PCIe Cap: Max Payload Current = %d bytesCFG_REG: PCI PCIe Cap: Current Link Speed = 16.0 GT/sEEH Error during PCI Config Reg Read Line: %d File:%s Error pci_config_read[%02x] = 0x%08x Line: %d File:%s DIAG ERROR: AERR UE: Flow Control Protocol Error FoundUnknown PCI Extended Capability 0x%08x at Offset 0x%03xCFG_REG: PCI PCIe Cap: Max Payload Supported = %d bytesDIAG ERROR: AERR UE: Uncorrectable Internal Error FoundPCIE ERROR: CFG_REG: PCIe Cap: Unsupported Request errorCFG_REG: PCI MSIX Cap: Function mask = All vectors maskedCFG_REG: PCI PCIe CAP: No errors found in status registerWARNING: PCIe Correctable Error found in AERR Capability:PCI Config Reg Write Error Offset=0x%03x Line: %d File:%s EEH Error pci_config_read[%02x] = 0x%08x Line: %d File:%s Error during PCI Extended Config Reg Read Line: %d File:%s CFG_REG: PCI MSIX Cap: Function mask = Using vector mask bitsDIAG ERROR: PCIe Unrecoverable Error found in AERR Capability:CFG_REG: PCI PCIe Cap: Current Max Read Request Size = %d bytesEEH Error during pci_config_read[%02x] = 0x%08x Line: %d File:%s CFG_REG: PCIe Advanced Error Reporting Cap: Header Log Register: PCIE ERROR: CFG_REG: PCIe Cap: Payload not configured to maximum value.CFG_REG: PCIe Advanced Error Reporting Cap: Header Log Register: 0x%08xCFG_REG: PCIe Advanced Error Reporting Cap: Header Log Register: 0x%08xCFG_REG: PCIe Advanced Error Reporting Cap: Header Log Register: 0x%08xCFG_REG: PCIe Advanced Error Reporting Cap: Header Log Register: 0x%08xCFG_REG: PCIe Advanced Error Reporting Cap: First Error Pointer = 0x%02xCFG_REG: PCIe Advanced Error Reporting Cap: PASS, No UE errors found in AERRCFG_REG: PCIe Advanced Error Reporting Cap: PASS, No CE errors found in AERRData ambiguity at Offset 0x%03x. Expected 0x%08x, Received 0x%08x Line: %d File:%s @(#)17 1.2 src/bos/diag/tu/lilac/lilac_tu01_config_regs.c, tu_lilac, bos72V, v2020_01A1 12/11/19 13:41:30dusbTU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG lilac_functions.clilac_functions.clilac_functions.clilac_functions.clilac_functions.clilac_functions.clilac_functions.clilac_functions.clilac_functions.clilac_functions.clilac_functions.clilac_functions.clilac_functions.clilac_functions.clilac_functions.clilac_functions.clilac_functions.clilac_functions.clilac_functions.clilac_functions.clilac_functions.clilac_functions.clilac_functions.clilac_functions.clilac_functions.cWaiting 1 Second...RESET: XHCI R/S = %dRESET: XHCI R/S = %dRESET: XHCI Halt = %dRESET: XHCI Halt = %dRESET: XHCI Status = 0x%08xRESET: XHCI Status = 0x%08xRESET: ** RESET COMPLETE **HEALTH: XHCI Status = 0x%08xRESET: XHCI Max Ports = 0x%08xRESET: Adapter Reset Complete.RESET: XHCI Command Register = 0x%08xRESET: XHCI Command Register = 0x%08xRESET: XHCI Command Register = 0x%08xRESET: Activated Software Reset. rc = %dRESET: Waiting for adapter to come onlineRESET: Set Max Device Slots Enabled. rc = %dRESET: Beginning USB Adapter Reset, Adapter = %sRESET: Enable Busmaster. CMD STATUS REG = 0x%08xRESET: Disable Busmaster. CMD STATUS REG = 0x%08xRESET: Checking Controller Not Ready (CNR) register.RESET: Checking Controller Not Ready (CNR) register.RESET: EEH error occurred during mem_read Line: %d File:%s RESET: EEH error occurred during mem_read Line: %d File:%s RESET: EEH error occurred during mem_read Line: %d File:%s RESET: EEH error occurred during mem_read Line: %d File:%s RESET: EEH error occurred during mem_read Line: %d File:%s HEALTH: EEH error occurred during mem_read Line: %d File:%s RESET: EEH error occurred during HC reset. Line: %d File:%s RESET: Controller Not Ready HCRST is 0x%08x after %d retries.RESET: EEH error occurred after adapter reset. Line: %d File:%s RESET: Controller Not Ready (CNR)/Status is 0x%08x after %d retries.RESET: Controller Not Ready (CNR)/Status is 0x%08x after %d retries.RESET: CNR bit never cleared. Adapter busy. Status=0x%08x Line: %d File:%s RESET: CNR bit never cleared. Adapter busy. Status=0x%08x Line: %d File:%s RESET: HCRST bit never cleared. Adapter busy. USB_CMD=0x%08x Line: %d File:%s RESET: EEH error occurred while setting Max Device Slots Enabled. Line: %d File:%s RESET: mem_read of XHCI status register failed. rc=0x%x offset=0x%08x Line: %d File:%s RESET: mem_read of XHCI status register failed. rc=0x%x offset=0x%08x Line: %d File:%s HEALTH: mem_read of XHCI status register failed. rc=0x%x offset=0x%08x Line: %d File:%s RESET: mem_read of XHCI Command register failed. rc=0x%x offset=0x%08x Line: %d File:%s RESET: Adapter not in correct state. Adapter busy. R/S = %d, HCH = %d Line: %d File:%s RESET: mem_read of XHCI Command register failed. rc=0x%x offset=0x%08x Line: %d File:%s RESET: Adapter not in correct state. Adapter busy. R/S = %d, HCH = %d Line: %d File:%s RESET: mem_read of XHCI Max Ports register failed. rc=0x%x offset=0x%08x Line: %d File:%s HEALTH: Adapter detected internal hardware error. XHCI USB_STATUS = 0x%08x Line: %d File:%s HEALTH: Adapter detected internal hardware error. XHCI USB_STATUS = 0x%08x Line: %d File:%s RESET: Adapter Reset via XHCI Command register failed. rc=0x%x offset=0x%08x Line: %d File:%s RESET: Error setting MaxSlotsEn via XHCI CONFIG register. rc=0x%x offset=0x%08x Line: %d File:%s @(#)13 1.2 src/bos/diag/tu/lilac/lilac_functions.c, tu_lilac, bos72V, v2020_01A1 12/11/19 13:41:26RESET: mem_read of XHCI command register failed after adapter reset. rc=0x%x offset=0x%08x Line: %d File:%s 9P9p99999:::09P9P9P9P9P9P9P:H:`:x:::9P9P9P9P9P9P9P9P9P9P9P9P9P9P9P9P9P9P9P9P9P9P9P9P9P9P:H:`:x:::;::;;;(;8;H;X;h;;;;;;;;x;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;x;;;;;(L(T(\(d(l(t(|((((L(L(L(L(L(L(L(((((((L(L(L(L(L(L(L(L(L(L(L(L(L(L(L(L(L(L(L(L(L(L(L(L(L(L((((((dusb%s :TU_MSG EEH error. ERRNUM = %d ERRNUM = %d ERRNUM = %d ERRNUM = %d ERRNUM = %d ERRNUM = %d ERRNUM = %d ERRNUM = %d ERRNUM = %d ERRNUM = %d ERRNUM = %d ERRNUM = %d ERRNUM = %d ERRNUM = %d ERRNUM = %d ERRNUM = %d ERRNUM = %d ERRNUM = %d Invalid TU error Invalid TU error FAILING SIZE = 0x%08x ACTUAL VALUE = 0x%08x ACTUAL VALUE = 0x%08x ACTUAL VALUE = 0x%08x TU RETURN CODE = 0x%08x TU RETURN CODE = 0x%08x TU RETURN CODE = 0x%08x TU RETURN CODE = 0x%08x TU RETURN CODE = 0x%08x TU RETURN CODE = 0x%08x TU RETURN CODE = 0x%08x TU RETURN CODE = 0x%08x Pdiag_open error found. TU RETURN CODE = 0x%08x TU RETURN CODE = 0x%08x TU RETURN CODE = 0x%08x TU RETURN CODE = 0x%08x TU RETURN CODE = 0x%08x TU RETURN CODE = 0x%08x TU RETURN CODE = 0x%08x TU RETURN CODE = 0x%08x TU RETURN CODE = 0x%08x TU RETURN CODE = 0x%08x TU RETURN CODE = 0x%08x TU RETURN CODE = 0x%08x TU RETURN CODE = 0x%08x TU RETURN CODE = 0x%08x TU RETURN CODE = 0x%08x TU RETURN CODE = 0x%08x TU RETURN CODE = 0x%08x TU RETURN CODE = 0x%08x TU RETURN CODE = 0x%08x COMPARISON MASK = 0x%8X EXPECTED VALUE = 0x%08x TU RETURN CODE = 0x%08x EXPECTED VALUE = 0x%08x TU RETURN CODE = 0x%08x TU RETURN CODE = 0x%08x TU RETURN CODE = 0x%08x TU RETURN CODE = 0x%08x TU RETURN CODE = 0x%08x EXPECTED VALUE = 0x%08x TU RETURN CODE = 0x%08x TU RETURN CODE = 0x%08x TU RETURN CODE = 0x%08x Pdiag_close error found. FAILING ADDRESS = 0x%08x FAILING ADDRESS = 0x%08x FAILING ADDRESS = 0x%08x FAILING ADDRESS = 0x%08x Device Busy Error found. FAILING ADDRESS = 0x%08x FAILING ADDRESS = 0x%08x COMPARISON MASK = 0x%08x COMPARISON MASK = 0x%08x COMPARISON MASK = 0x%08x COMPARISON MASK = 0x%08x FAILING ADDRESS = 0x%08x ACTUAL VALUE = 0x%08x%08x FIRST ACTUAL VALUE = 0x%08x FIRST ACTUAL VALUE = 0x%08x EXPECTED VALUE = 0x%08x%08x PDIAGEX RETURN CODE = 0x%08x PDIAGEX RETURN CODE = 0x%08x PDIAGEX RETURN CODE = 0x%08x PDIAGEX RETURN CODE = 0x%08x PDIAGEX RETURN CODE = 0x%08x PDIAGEX RETURN CODE = 0x%08x PDIAGEX RETURN CODE = 0x%08x PDIAGEX RETURN CODE = 0x%08x PDIAGEX RETURN CODE = 0x%08x PDIAGEX RETURN CODE = 0x%08x PDIAGEX RETURN CODE = 0x%08x PDIAGEX RETURN CODE = 0x%08x PDIAGEX RETURN CODE = 0x%08x PDIAGEX RETURN CODE = 0x%08x PDIAGEX RETURN CODE = 0x%08x PDIAGEX RETURN CODE = 0x%08x Error waiting for interrupt. PDIAGEX RETURN CODE = 0x%08x PDIAGEX RETURN CODE = 0x%08x PDIAGEX RETURN CODE = 0x%08x PDIAGEX RETURN CODE = 0x%08x PDIAGEX RETURN CODE = 0x%08x PDIAGEX RETURN CODE = 0x%08x PDIAGEX RETURN CODE = 0x%08x FAILING BUS ADDRESS = 0x%08x PDIAGEX RETURN CODE = 0x%08x FAILING BUS ADDRESS = 0x%08x PDIAGEX RETURN CODE = 0x%08x COMPARISON MASK = 0x%08x%08x FIRST EXPECTED VALUE = 0x%08x FIRST EXPECTED VALUE = 0x%08x No data received error found. ATTEMPTED WRITE VALUE = 0x%08x ATTEMPTED WRITE VALUE = 0x%08x Memory Allocation Error found. Pdiag_restore_state error found. FAILING VIRTUAL ADDRESS = 0x%08x FAILING VIRTUAL ADDRESS = 0x%08x Pdiag_dd_dma_enable error found. FAILING VIRTUAL ADDRESS = 0x%08x Pdiag_diagnose_state error found. Pdiag set EEH option error found. Pdiag set slot reset error found. Pdiag read slot reset error found. Memory data ambiguity error found. Device initialization error found. FIRST ATTEMPTED WRITE VALUE = 0x%08x Pdiag DMA setup operation error found. Pdiag_dd_read_IO operation error found. IO register data ambiguity error found. IO register data ambiguity error found. Data pattern data ambiguity error found. Pdiag DMA complete operation error found. Pdiag_restore_multifunc_state error found. Pdiag_diagnose_multifunc_state error found. Pdiag shared slot list request error found. pdiag_dd_read memory operation error found. Config register data ambiguity error found. PCI Configuration Register read error found. Pdiag_dd_write memory operation error found. PCI Configuration Register write error found. Pdiag configuration services open error found. Pdiag configuration services close error found. Pdiag config services get attribute error found. Pdiag config services free attribute error found. pdiag_dd_write_IO register operation error found. FAILING OFFSET RANGE, START = 0x%08x, END = 0x%08x ERR Handler msg=%s major_rc=%08x tu_rc->minor_rc=%08xFAILING BUS ADDRESS RANGE, START = 0x%08x, END = 0x%08x FAILING VIRTUAL ADDRESS_RANGE, START = 0x%08x, END = 0x%08x FAILING VIRTUAL ADDRESS RANGE, START = 0x%08x, END = 0x%08x FAILING VIRTUAL ADDRESS RANGE, START = 0x%08x, END = 0x%08x @(#)21 1.3 src/bos/diag/tu/lilac/lilac_tu_errors.c, tu_lilac, bos72V, v2020_01A1 12/11/19 13:41:33So o<oXoxoxoxoxoxoxoxoxooxooooooooxoxoxooxSSSSSoooooxoxoooooSSoooSSSSSSSSoooooTDU\VVW`X XYdZZ[h\\]^@^_`DaabcLd effg g g g g g4h0i,jXkXkllm@%sdusb/dev0x00%s/%sbus_idTU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG connwhereTU_00 OpenTU_00 OpenTU_00 OpenTU_00 OpenTU_00 OpenTU_00 OpenTU_00 OpenTU_00 OpenTU_00 OpenTU_00 OpenTU_00 Openintr_msi_1parent_namebus_mem_addrbus_mem_addr2dma_lvl = %dbus_mem_lengthslot_num = %dbus_id = 0x%xbus_type = %dlilac_tu_open.clilac_tu_open.clilac_tu_open.cDebug Build DDSlilac_tu_open.clilac_tu_open.clilac_tu_open.clilac_tu_open.clilac_tu_open.clilac_tu_open.cOnboard USB 3.0Unknown Adapterlilac_tu_open.clilac_tu_open.cmaxmaster = %dTU_OPEN: rc = %dintr_flags = %ddata_prt = 0x%xdma_chan_id = %ddma_flags = 0x%xbus_intr_lvl = %dintr_priority = %dparent_name = '%s'bus_io_addr = 0x%xdma_bus_mem = 0x%xregs_handle = 0x%xmsix_handle = 0x%xbus_io_length = 0x%xbus_mem_addr = 0x%xbus_mem_length= 0x%xdma_bus_length= 0x%xTU_OPEN: REG width: 0x%xTU_OPEN: Device name: %sTU_OPEN: Clean up calledTU_OPEN: MSIX width: 0x%xTU_OPEN: build_dds rc = %d4-Port USB 3.0 PCIe Adapter2-Port USB 3.0 PCIe AdapterTU_OPEN: parent_name = '%s' TU_OPEN: Device ID Read (%08x) TU_OPEN: DDS: build_dds completeTU_OPEN: DDS: regbase_hi = 0x%08xTU_OPEN: Build_dds failed, rc = %dTU_OPEN: DDS: regbase_low = 0x%08xTU_OPEN: DDS: msixbase_hi = 0x%08xTU_OPEN: DDS: msixbase_low = 0x%08xTU_OPEN: DDS: msixbase_width = 0x%xTU_OPEN: Busmaster and MMIO DisabledTU_OPEN: DDS: bus_id = 0x%x, rc = %dTU_OPEN: DDS: slot_num = %x, rc = %dTU_OPEN: tu_data->regs_handle = 0x%08xTU_OPEN: tu_data->msix_handle = 0x%08xTU_OPEN: DDS: parent_name = '%s', rc=%dTU_OPEN: DDS: bus_intr_lvl = %x, rc = %dOpen REG failed = 0x%08x Line: %d File:%s TU_OPEN: DDS: config close failed. rc = %dBUILD DDS FAILED = 0x%08x Line: %d File:%s Open MSIX failed = 0x%08x Line: %d File:%s TU_OPEN: DDS: regbase_width = 0x%x, rc = %dTU_OPEN: DDS: bus_mem_addr = 0x%llx, rc = %dTU_OPEN: Unable to exit diagnose state. rc=%dTU_OPEN: DDS: bus_mem_addr2 = 0x%llx, rc = %dPDIAGEX RETURN CODE = 0x%08x Line: %d File:%s PDIAGEX RETURN CODE = 0x%08x Line: %d File:%s PDIAGEX RETURN CODE = 0x%08x Line: %d File:%s TU_OPEN: Busmaster enabled. CMDSTATUS = 0x%08xTU_OPEN: Set diagnose state for resource_name=%sTU_OPEN: REG addr hi: 0x%x TU_OPEN: REG addr low: 0x%xTU_OPEN: REG addr hi: 0x%x TU_OPEN: REG addr low: 0x%xbus_mem_addr = 0 Check your ODM data Line: %d File:%s TU_OPEN: Clean up pdiag XHCI regs handle failed. rc=%dTU_OPEN: Clean up pdiag MSIX regs handle failed. rc=%dbus_mem_addr2 = 0 Check your ODM data Line: %d File:%s EEH error occurred during config read Line: %d File:%s This is wrong card with dev_id = %08x Line: %d File:%s TU_OPEN: MSIX addr hi: 0x%x TU_OPEN: MSIX addr low: 0x%xTU_OPEN: MSIX addr hi: 0x%x TU_OPEN: MSIX addr low: 0x%xTU_OPEN mdd_fd open failed. rc = 0x%08x Line: %d File:%s TU_OPEN: Diagnostics started @ %4d-%02d-%02d_%02d.%02d.%02d@(#)17 1.4 src/bos/diag/tu/lilac/lilac_tu_open.c, tu_lilac, bos72V, v2020_01A1 12/11/19 13:41:35%sdusbTU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_CLOSE%s --DONElilac_tu_close.clilac_tu_close.clilac_tu_close.cRestore state rc=%x rc=%d TU_CLOSE: Close regs handle failed=0x%xTU_CLOSE: Close msix handle failed=0x%xTU_CLOSE: pdiag_restore_state failed. rc=0x%x Line: %d File:%s TU_CLOSE: close regs_handle FAILED. Handle=0x%08x PDIAGEX RETURN CODE = 0x%08x Line: %d File:%s TU_CLOSE: close msix_handle FAILED. Handle=0x%08x PDIAGEX RETURN CODE = 0x%08x Line: %d File:%s @(#)20 1.2 src/bos/diag/tu/lilac/lilac_tu_close.c, tu_lilac, bos72V, v2020_01A1 12/11/19 13:41:32dusbTU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_03: %slilac_tu03_vpd.clilac_tu03_vpd.clilac_tu03_vpd.clilac_tu03_vpd.clilac_tu03_vpd.clilac_tu03_vpd.clilac_tu03_vpd.clilac_tu03_vpd.clilac_tu03_vpd.clilac_tu03_vpd.clilac_tu03_vpd.clilac_tu03_vpd.clilac_tu03_vpd.clilac_tu03_vpd.clilac_tu03_vpd.clilac_tu03_vpd.clilac_tu03_vpd.clilac_tu03_vpd.clilac_tu03_vpd.cTU_03: Reading VPD DataCHECK_VPD: RO Size = %dTU_03_VPD Test and Validation CHECK_VPD: Total Keywords = %dCHECK_VPD: Function Description: %sCHECK_VPD: Function Description: %sCHECK_VPD: Parsing RW portion of VPDCHECK_VPD: RO Size = %d RW Size = %dREAD_EEPROM: 0x%03x 0x%02x Loop Count=%dCHECK_VPD: Done parsing RW portion of VPDTU_03: New EEPROM value for FLADJ = 0x%02xCHECK_VPD: Parsing and validating VPD dataTU_03: New PCI Config value for FLADJ = 0x%02xTU_03: Original EEPROM value for FLADJ = 0x%02xInvalid Checksum, Checksum = %d Line:%d File:%s TU_03: Original PCI Config value for FLADJ = 0x%02xCHECK_VPD: 0x%x - %s %-32s Writeable = %d Size = %dTU_03: Read Adapter Customization Fields from EEPROMEEH error occurred during VPD Read Line: %d File:%s EEH error occurred during VPD Read Line: %d File:%s EEH error occurred during VPD Read Line: %d File:%s EEH error occurred during VPD Read Line: %d File:%s EEH error occurred during VPD Read Line: %d File:%s CHECK_VPD: 0x%x - %s 0x%-32x Writeable = %d Size = %dREAD ERROR: pci_config[%02x] = 0x%08x Line: %d File:%s READ ERROR: pci_config[%02x] = 0x%08x Line: %d File:%s TU_03: Integrated USB does not have VPD. Skipping test.WRITE ERROR: pci_config[%02x] = 0x%02x Line: %d File:%s WRITE ERROR: pci_config[%02x] = 0x%08x Line: %d File:%s WRITE ERROR: pci_config[%02x] = 0x%08x Line: %d File:%s CHECK_VPD: Done parsing RO portion of VPD, Checksum = 0x%xUnexpected VPD value. Offset 0x00 = 0x%08x Line:%d File:%s Unexpected VPD value. Offset 0x%x = 0x%08x Line:%d File:%s Unexpected VPD value. Offset 0x%x = 0x%08x Line:%d File:%s Unexpected VPD value. Offset 0x%x = 0x%08x Line:%d File:%s WRITE_EEPROM: Write Complete, Register = 0x%08x, Retries = %dEEH error occurred during TU_03 device check. Line: %d File:%s Error allocating memory for adapter description Line:%d File:%s Not enough room to store additional VPD KWs. Current num_keywords = %d Line:%d File:%s Not enough room to store additional VPD KWs. Current num_keywords = %d Line:%d File:%s @(#)19 1.3 src/bos/diag/tu/lilac/lilac_tu03_vpd.c, tu_lilac, bos72V, v2020_01A1 12/11/19 13:41:31dusbTU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_MSG TU_02: %s8UUUU3333TU_02: %s --DONETU_02_IO Reg Testlilac_tu02_io_regs.clilac_tu02_io_regs.clilac_tu02_io_regs.clilac_tu02_io_regs.clilac_tu02_io_regs.clilac_tu02_io_regs.clilac_tu02_io_regs.clilac_tu02_io_regs.clilac_tu02_io_regs.clilac_tu02_io_regs.clilac_tu02_io_regs.clilac_tu02_io_regs.cTU_02: 0x%03x 0x%08xlilac_tu02_io_regs.clilac_tu02_io_regs.clilac_tu02_io_regs.clilac_tu02_io_regs.clilac_tu02_io_regs.clilac_tu02_io_regs.clilac_tu02_io_regs.clilac_tu02_io_regs.clilac_tu02_io_regs.cTU_02: XHCI Version: %x.%xTU_02: MSIX: 0x%04x 0x%08xTU_02: XHCI Status = 0x%08xTU_02: XHCI CAPS: 0x%02x 0x%08xTU_02: XHCI OPER: 0x%02x 0x%08xTU_02: XHCI PORTSC: 0x%04x 0x%08xTU_02: XHCI EXT CAPS: 0x%04x 0x%08xTU_02: XHCI Capablity Register Length = %dTU_02: New Value XHCI Register Offset: 0x%x 0x%08xEEH error occurred during mem_read Line: %d File:%s EEH error occurred during mem_read Line: %d File:%s EEH error occurred during mem_read Line: %d File:%s EEH error occurred during mem_read Line: %d File:%s EEH error occurred during mem_read Line: %d File:%s EEH error occurred during mem_read Line: %d File:%s EEH error occurred during mem_read Line: %d File:%s TU_02: offset=0x%08x received=0x%08x expected=0x%08xEEH error occurred during mem_write Line: %d File:%s EEH error occurred during mem_write Line: %d File:%s TU_02: Writing Value XHCI Register Offset: 0x%x 0x%08xTU_02: Original Value XHCI Register Offset: 0x%x 0x%08xEEH error occurred during mem_read to MSIX table Line: %d File:%s TU_02: Returning Original Value to XHCI Register Offset: 0x%x 0x%08xIO REG TEST FAILED During mem_write rc=%04x offset=%04x Line: %d File:%s IO REG TEST FAILED during mem_read rc=0x%x offset=0x%08x Line: %d File:%s IO REG TEST FAILED during mem_read rc=0x%x offset=0x%08x Line: %d File:%s IO REG TEST FAILED during mem_read rc=0x%x offset=0x%08x Line: %d File:%s IO REG TEST FAILED during mem_read rc=0x%x offset=0x%08x Line: %d File:%s IO REG TEST FAILED during mem_read rc=0x%x offset=0x%08x Line: %d File:%s IO REG TEST FAILED during mem_read rc=0x%x offset=0x%08x Line: %d File:%s IO REG TEST FAILED during mem_read rc=0x%x offset=0x%08x Line: %d File:%s IO REG TEST FAILED during mem_write rc=0x%x offset=0x%08x Line: %d File:%s MSIX REG TEST FAILED during mem_read rc=0x%x offset=0x%08x Line: %d File:%s @(#)18 1.2 src/bos/diag/tu/lilac/lilac_tu02_io_regs.c, tu_lilac, bos72V, v2020_01A1 12/11/19 13:41:30IO REG TEST FAILED, Data anomaly rc=0x%x offset=0x%08x received=0x%08x expected=0x%08x Line: %d File:%s  k\ l l    8 /0 D R U¨ `$<ZP:___fill@"@errno@close@ .@malloc@ calloc@ free@ strlen@ open@ strtoul@ strchr@ sprintf@ time@ snprintf@ usleep@ tolower@ fgets@ rewind@ F@ ioctl@ strtoull@ dt@ R@ q@ @ @ @ @ @ @ @ @ @ ,@ exectu kP!  ,t ,x ,| , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , - - - -  - - - - -  -$ -( -, -0 -4 -8 -< -@ -D -H -L -P -T -X -\ -` -d -h -l -p -t -x -| - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - . . . .  . . . . .  .$ .( ., .0 .4 .8 .< .@ .D .H .L .P .T .X .\ .` .d .h .l .p .t .x .| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . / / B B B B B B B B B B B B C C C C  C C C C C  C$ C( C, C0 C4 C8 C< C@ CD CH CL CP CT CX C\ C` Cd Ch Cl Cp Ct Cx C| C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C D D D D  D D D D D  D$ D( D, D0 D4 D8 D< D@ DD DH DL DP DT DX D\ kP kT k\ k` kd kh kl kp kt kx k| k k k k k k k k k  k k k  k k k# k" k k k  k% k$ k k k! k k  k k k k k  k l l l l  l l l /usr/lib:/lib:/usr/lpp/xlC/liblibc.ashr.olibdiag.ashr.o/unixlibpdiag.ashr.o@VPDlibtu_lilac/5765E6200/520 ___strcpy_system_configuration localtimepdiag_dd_watch_for_interruptpdiag_dd_writepdiag_dd_readpdiag_pcicfg_write pdiag_closepdiag_open_64pdiag_restore_statepdiag_diagnose_statepdiag_cs_free_attrpdiag_cs_get_attrpdiag_cs_closepdiag_cs_open