/* IBM_PROLOG_BEGIN_TAG */
/* This is an automatically generated prolog. */
/* */
/* bos72Q src/bos/kernel/sys/POWER/machine.h 1.55.2.11 */
/* */
/* Licensed Materials - Property of IBM */
/* */
/* COPYRIGHT International Business Machines Corp. 1987,2019 */
/* All Rights Reserved */
/* */
/* US Government Users Restricted Rights - Use, duplication or */
/* disclosure restricted by GSA ADP Schedule Contract with IBM Corp. */
/* */
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/* @(#)96 1.55.2.11 src/bos/kernel/sys/POWER/machine.h, sysml, bos72Q, q2019_14A6 3/10/19 20:42:38 */
#ifndef _H_MACHINE
#define _H_MACHINE
#ifdef __cplusplus
extern "C" {
#endif
/*
* COMPONENT_NAME: (SYSML) Kernel Assembler
*
* FUNCTIONS:
*
* ORIGINS: 27, 3
*
* (C) COPYRIGHT International Business Machines Corp. 1987, 1994
* All Rights Reserved
* Licensed Materials - Property of IBM
*
* US Government Users Restricted Rights - Use, duplication or
* disclosure restricted by GSA ADP Schedule Contract with IBM Corp.
*
* This include file defines mask bits and other special values
* for machine-dependent control registers, and other values
* specific to the platform.
*
* This version is for R2.
*
* NOTE: A parallel assembler version of this .h file is in
* .../sys/ml/machine.m4.
*
*/
#include <sys/types.h>
/*
* Definitions for byte order,
* according to byte significance from low address to high.
*/
#define LITTLE_ENDIAN 1234 /* least-significant byte first (vax) */
#define BIG_ENDIAN 4321 /* most-significant byte first (IBM, net) */
#define PDP_ENDIAN 3412 /* LSB first in word, MSW first in long (pdp) */
#define BYTE_ORDER BIG_ENDIAN
/*
* Default value to place into a register when it isn't supposed
* to contain a useful value (killed registers on return from
* system call, for example)
*/
#define DEFAULT_GPR 0xDEADBEEF
/*
* Machine Status Register (MSR)
*/
#define MSR_TS_SUSP 0x200000000 /* TS: TM State: Supended */
#define MSR_TS_TRANS 0x400000000 /* TS: TM State: Transactional */
#define MSR_TS 0x600000000 /* TS: TM State Field of MSR */
#define MSR_TM 0x100000000 /* TM enable */
#define MSR_VMX 0x2000000/* VMX enable */
#define MSR_VSX 0x800000 /* VSX enable */
#define MSR_EE 0x8000 /* External interrupt enable */
#define MSR_PR 0x4000 /* Problem state */
#define MSR_FP 0x2000 /* Floating point available */
#define MSR_ME 0x1000 /* Machine check enable */
#define MSR_FE 0x0800 /* Floating point exception enable (PWR) */
#define MSR_FE0 0x0800 /* Floating point xcp mode bit0 (PPC) */
#define MSR_SE 0x0400 /* Single Step Trace Enable (RS2/PPC) */
#define MSR_BE 0x0200 /* Branch Trace Enable (RS2/PPC) */
#define MSR_IE 0x0100 /* Flt-pt imprecise int enable (RS2) */
#define MSR_FE1 0x0100 /* Floating point xcp mode bit1 (PPC) */
#define MSR_AL 0x0000 /* Obsolete - alignment check (PWR) */
#define MSR_RSVD 0x0080 /* Reserved */
#define MSR_IP 0x0040 /* Interrupt prefix active */
#define MSR_IR 0x0020 /* Instruction relocate on */
#define MSR_DR 0x0010 /* Data relocate on */
#define MSR_PM 0x0004 /* Performance Monitoring (RS2) */
#define MSR_RI 0x0002 /* Recoverable interrupt (PPC) */
#define MSR_HYPERVISOR 0x1000000000000000LL /* Hypervisor Modr (GP) */
#ifdef __64BIT_KERNEL
#define MSR_SF 0x8000000000000000L
#define MSR_ISF 0x2000000000000000L
#define DEFAULT_MSR (MSR_SF|MSR_ISF|MSR_EE|MSR_ME|MSR_IR|MSR_DR|MSR_RI)
#define DEFAULT_USER_MSR \
(MSR_ISF|MSR_PR|MSR_EE|MSR_ME|MSR_IR|MSR_DR|MSR_RI)
#define DISABLED_NORI_MSR \
(MSR_SF|MSR_ISF|MSR_ME|MSR_IR|MSR_DR)
#define MSR_SF_H 0xA0000000 /* Upper half of msr for 64-bit PPC */
#else
#define DEFAULT_MSR (MSR_EE|MSR_ME|MSR_IR|MSR_DR|MSR_RI)
#define DEFAULT_USER_MSR (DEFAULT_MSR | MSR_PR)
#define MSR_SF_H 0x80000000 /* Upper half of msr for 64-bit PPC */
#endif
/*
* Condition Register (CR)
*/
#define CR_LT 0x80000000 /* Less Than, field 0 */
#define CR_GT 0x40000000 /* Greater Than, field 0 */
#define CR_EQ 0x20000000 /* Equal, field 0 */
#define CR_SO 0x10000000 /* Summary Overflow, field 0 */
#define CR_FX 0x08000000 /* Floating point exception */
#define CR_FEX 0x04000000 /* Floating point enabled exception */
#define CR_VX 0x02000000 /* Floating point invalid operation */
#define CR_OX 0x01000000 /* Copy of FPSCR(OX) */
/* Macro to access field n of CR value cr: */
#define CR_FIELD(n,cr) ((cr << (n << 2)) & 0xF0000000)
/*
* Fixed Point Exception Register (XER)
*/
#define XER_SO 0x80000000 /* Summary overflow */
#define XER_OV 0x40000000 /* Overflow */
#define XER_CA 0x20000000 /* Carry */
/* Macros to access comparison byte and length for lsx, lscbx, stsx */
#define XER_COMP_BYTE(xer) ((xer >> 8) & 0x000000FF)
#define XER_LENGTH(xer) (xer & 0x0000007F)
/*
* Data Storage Interrupt Status Register (DSISR)
*/
#define DSISR_IO 0x80000000 /* I/O exception */
#define DSISR_PFT 0x40000000 /* No valid PFT for page */
#define DSISR_LOCK 0x20000000 /* Access denied: data locking (PWR) */
#define DSISR_FPIO 0x10000000 /* FP load/store to I/O space (PWR) */
#define DSISR_PROT 0x08000000 /* Protection exception */
#define DSISR_LOOP 0x04000000 /* PFT search > 127 entries (RS1) */
#define DSISR_DRST 0x04000000 /* lwarx, etc to Direct Store (PPC) */
#define DSISR_ST 0x02000000 /* 1 => store, 0 => load */
#define DSISR_SEGB 0x01000000 /* Crosses segment boundary, (PWR) */
/* from T=0 to T=1 */
#define DSISR_DAC 0x00400000 /* Data Address Cmp/ACCR (PPC < P5++)*/
#define DSISR_DABR 0x00400000 /* DABR exception (RS2/PPC) */
#define DSISR_STAB 0x00200000 /* stab fault (PPC < P5++)*/
#define DSISR_SKEY 0x00200000 /* Storage Key Violation (P5++)*/
#define DSISR_EAR 0x00100000 /* eciwx with EAR enable = 0 (PPC) */
#define DSISR_IMP_DSI 0x00020000 /* Implicit PTE miss, HSLB mode (P9) */
#define DSISR_COPV 0x00004000 /* Coprocessor Access Violation (P7) */
#define DSISR_CSMV 0x00000010 /* CSM violation w. copy/paste (P9) */
#define DSISR_COPYV 0x00000008 /* Inval accel. access w. copy (P9) */
#define DSISR_AO_INV 0x00000004 /* Atomic Op Inval Funct code (P9) */
/*
* System Recall Register 1 (SRR1)
*
* Note: This register is used for various purposes, depending on the
* type of interrupt, thus the prefix of the name will vary.
*/
#define SRR_IS_PFT 0x40000000 /* No valid PFT for page */
#define SRR_IS_ISPEC 0x20000000 /* I-fetch from special segmnt (PWR) */
#define SRR_IS_IIO 0x10000000 /* I-fetch from I/O space */
#define SRR_IS_GUARD 0x10000000 /* I-fetch from guarded storage */
#define SRR_IS_PROT 0x08000000 /* Protection exception */
#define SRR_IS_LOOP 0x04000000 /* PFT search > 127 entries (RS1) */
#define SRR_PR_TM_BAD 0x00200000 /* Trans Memory Bad Thing Exception */
#define SRR_PR_FPEN 0x00100000 /* FP Enabled Interrupt exception */
#define SRR_PR_INVAL 0x00080000 /* Invalid operation */
#define SRR_PR_PRIV 0x00040000 /* Privileged instruction */
#define SRR_PR_TRAP 0x00020000 /* Trap instruction */
#define SRR_PR_IMPRE 0x00010000 /* Imprecise Interrupt (PPC) */
/*
* VMX Status and Control Register
*/
#define VSCR_SAT 0x00000001 /* VMX Saturation sticky bit */
#define VSCR_NJ 0x00010000 /* VMX Non-Java Mode */
/*******************************************************************************
* Data Streams Control Register (DSCR) - Power6 and later CPUs
* ============================================================
*
* |<----------------------- v2.07 --------------------------->|
* | |<------ v2.06_2 ------>|
* | | |<--- v2.06_1 --->|
* | | | |<-- v2.06 -->|
* | | | | |<v2.05->|
* +-----|----+----+---+---+----+----+-------|-----|---|----|---+----|
* | /// |SWTE|HWTE|STE|LTE|SWUE|HWUE|UNITCNT| URG |LSD|SNSE|SSE|DPFD|
* |-----|----|----|---|---|----|----|-------|-----|---|----|---|----|
* (0 38 39 40 41 42 43 44 45 54 55 57 58 59 60 63)
*
* _Bit(s) Name Description_
*
* 39 SWTE Software Transient Enable
* Applies the transient attribute to s/w-defined
* streams.
*
* 40 HWTE Hardware Transient Enable
* Applies the transient attribute to h/w-detected
* streams.
*
* 41 STE Store Transient Enable
* Applies the transient attribute to store streams.
*
* 42 LTE Load Transient Enable
* Applies the transient attribute to load streams.
*
* 43 SWUE Software Unit Count Enable
* Applies the unit count to s/w-defined streams.
*
* 44 HWUE Hardware Unit Count Enable
* Applies the unit count to h/w-detected streams.
*
* 45:54 UNITCNT Unit Count
* Number of units in a data stream.
*
* 55:57 URG Depth Attainment Urgency
* 58 LSD Load Stream Disable (used to be DLDP: Disable Load
* Prefetch)
*
* 59 SNSE Stride-N Stream Enable (P7 - Arch v2.06 and up)
*
* 60 SSE Store Stream Enable
* Enables hardware detection and initiation of store
* streams.
*
* 61:63 DPFD Default Prefetch Depth
* Depth value applied for hardware-detected streams
* and software-defined streams for which a dcbt with
* TH=1010 is _not_ used in their description. Values
* and their meanings are as follows.
*
*/
#define DSCR_DPFD_SHIFT (0)
#define DSCR_DPFD_MASK (0x7)
#define DPFD_DEFAULT 0
#define DPFD_NONE 1
#define DPFD_SHALLOWEST 2
#define DPFD_SHALLOW 3
#define DPFD_MEDIUM 4
#define DPFD_DEEP 5
#define DPFD_DEEPER 6
#define DPFD_DEEPEST 7
#define DSCR_SSE (1<<3)
#define DSCR_SNSE (1<<4)
/*
* Bit 58 field was renamed from DLDP to LSD in the Power ISA.
* Keeping old definition for source compatibility.
*/
#define DSCR_DLDP (1<<5)
#define DSCR_LSD DSCR_DLDP
/*
* Bits 55:57 Depth Attainment Urgency (URG)
*/
#define DSCR_URG_SHIFT (6)
#define DSCR_URG_MASK (0x7)
#define URG_DEFAULT (0<<DSCR_URG_SHIFT)
#define URG_NOT_URGENT (1<<DSCR_URG_SHIFT)
#define URG_LEAST_URGENT (2<<DSCR_URG_SHIFT)
#define URG_LESS_URGENT (3<<DSCR_URG_SHIFT)
#define URG_MEDIUM (4<<DSCR_URG_SHIFT)
#define URG_URGENT (5<<DSCR_URG_SHIFT)
#define URG_MORE_URGENT (6<<DSCR_URG_SHIFT)
#define URG_MOST_URGENT (7<<DSCR_URG_SHIFT)
/*
* Bits 45:54 Unit Count (UNITCNT)
*/
#define DSCR_UNITCNT_SHIFT (9)
#define DSCR_UNITCNT_MASK (0x3FF)
#define DSCR_UNITCNT(_cnt) ((_cnt & DSCR_UNITCNT_MASK) << DSCR_UNITCNT_SHIFT)
/*
* Bits 44 (HWUE) through 39 (SWTE)
*/
#define DSCR_HWUE (1<<19)
#define DSCR_SWUE (1<<20)
#define DSCR_LTE (1<<21)
#define DSCR_STE (1<<22)
#define DSCR_HWTE (1<<23)
#define DSCR_SWTE (1<<24)
/*
* Inclusive Bit Masks for DSCR by Power ISA Version
*
* NOTE: V206_1 for 2.06+ has the same mask as base 2.06 because we
* provided early support for the LSD bit under the name DLDP.
*/
#define DSCR_MASK 0x0F /* Only for bits valid in DSCR */
#define DSCR_MASKV205 DSCR_MASK /* Mask for V205 */
#define DSCR_MASKV206 0x3F /* Mask for V206 */
#define DSCR_MASKV206_1 0x3F /* Mask for V206_1 */
#define DSCR_MASKV206_2 0x1FF /* Mask for V206_2 */
#define DSCR_MASKV207 0x1FFFFFF /* Mask for V207 */
/*
* Structures used to query the Data Streams Properties
*/
struct dscr_properties {
#define DSCR_PROP_VER0 0x44530000 /* 'D''S'00 */
#define DSCR_PROP_VER1 0x44530001 /* 'D''S'01 */
#define DSCR_PROP_VER2 0x44530002 /* 'D''S'02 */
#define DSCR_PROP_VER DSCR_PROP_VER2
unsigned int version;
unsigned int number_of_streams; /* Number of HW streams */
long long platform_default_pd; /* Platform default */
long long os_default_pd; /* Operating System default */
#define DSCR_V205 0x205
#define DSCR_V206 0x206
#define DSCR_V206_1 0x10206
#define DSCR_V206_2 0x20206
#define DSCR_V207 0x207
int dscr_version; /* Architecture version */
#define DSCR_SYS_AUTO_OFF 0
#define DSCR_SYS_AUTO_ON 1
unsigned int dscr_control; /*
*system wide dscr control
*(read only)
*/
#define DSCR_PROP_SMTS 5 /* size of dscr_smt array*/
long long dscr_smt[DSCR_PROP_SMTS];/* DSCR/SMT matrix */
long long dscr_mask;
};
#define DSCR_PROP_VER0_SIZE (offsetof(struct dscr_properties, dscr_version))
#define DSCR_PROP_VER1_SIZE (offsetof(struct dscr_properties, dscr_smt))
#define DSCR_PROP_VER2_SIZE (sizeof(struct dscr_properties))
#define DSCR_PROP_SIZE DSCR_PROP_VER2_SIZE
/*
* Function to read/write the Data Streams Control Register
*/
int dscr_ctl(int op, void *buf_p, int size);
/*
* The op parameter is one of the values below:
*/
#define DSCR_WRITE 1 /* Stores new value from input buffer into *
* process context and in the DSCR. */
#define DSCR_READ 2 /* Reads current value of DSCR and returns it *
* in output buffer. */
#define DSCR_GET_PROPERTIES 3 /* Reads number of HW streams, *
* Firmware default Prefetch Depth *
* and OS default Prefetch Depth from kernel *
* memory and returns it in output buffer */
#define DSCR_SET_DEFAULT 4 /* Set Operating System default for DSCR */
/*
* Transaction EXception And Summary Register (TEXASR) Fields
*/
#define TEXASR_FC 0xFE00000000000000L /* Failure Code */
#define TEXASR_PERSISTENT 0x0100000000000000L /* Failure is persistent*/
#define TEXASR_DISALLOW 0x0080000000000000L /* Instruction access */
/* type not permitted */
#define TEXASR_NEST_OV 0x0040000000000000L /* Maximum transaction */
/* level exceeded */
#define TEXASR_FOOT_OV 0x0020000000000000L /* Tracking limit */
/* exceeded */
#define TEXASR_SELF_CONF 0x0010000000000000L /* Self-Induced Conflict*/
#define TEXASR_NON_TR_CONF 0x0008000000000000L /* Non-Tranactional */
/* Conflict */
#define TEXASR_TR_CONF 0x0004000000000000L /* Conflict occured with*/
/* anoter transaction */
#define TEXASR_TLB_INV_CONF 0x0002000000000000L /* Translation */
/* Invalidation Conflict*/
#define TEXASR_IMP_SPEC 0x0001000000000000L /* Implementation */
/* Specific Condition */
/* Caused Failure */
#define TEXASR_ABORT 0x0000000100000000L /* Abort caused via TM */
/* instruction */
#define TEXASR_SUSPENDED 0x0000000080000000L /* Failure recorded in */
/* suspended state */
#define TEXASR_USER_STATE 0x0000000040000000L /* Thread in user state */
/* at time of failure */
#define TEXASR_PR 0x0000000030000000L /* Thread was in PR sate*/
/* at time of failure */
#define TEXASR_FS 0x0000000008000000L /* Failure Summary (FS) */
#define TEXASR_TFIAR_EXACT 0x0000000004000000L /* Value in TFIAR is */
/* exact */
#define TEXASR_ROT 0x0000000002000000L /* ROT initiated */
#define TEXASR_TL 0x0000000000000FFFL /* Transaction Level */
/* (TL) */
/*
* TEXASR Failure Codes
*
* NOTE: The low order bit of the failure code is placed into the
* persistent field of the TEXASR register. Therefore, for
* persistent failure types, this bit must be set in the
* failure code below and for transient failure types it
* must not be set.
*/
/*
* Persistent Failure Codes
*/
#define TM_PERSISTENT 0x01 /* Persistent Field in the Failure Code */
#define TM_ILL_SC 0x03 /* The transaction attempted to call a */
/* system call that is not supported */
/* when in transactional mode. */
#define TM_PROC_TERMINATED 0x05 /* The process was terminated. */
#define TM_THREAD_FORKED 0x07 /* The thread was forked. */
#define TM_THREAD_TERMINATED 0x09 /* The process-thread was terminated. */
#define TM_PROG_EXEC 0x0B /* Program was exec'd resulting in the */
/* TM unit being disowned. */
#define TM_LIBC 0x0D /* The program made a call to a libc */
/* function resulting in transaction */
/* failure. */
#define TM_PTH_PREEMPTED 0x0F /* A transactional pthread was */
/* preempted by the pthreads scheduler */
#define TM_SYNC_SIGNAL 0x11 /* The transaction was failed due to */
/* delivery of a synchronous signal. */
#define TM_BAD_THING 0x13 /* Transaction received a TM Bad Thing */
/* Exception type of Program Interrupt. */
#define TM_INV_OP 0x15 /* The program attempted to execute an */
/* instruction that is either invalid */
/* or only supported via emulation */
/* while in transactional mode. */
#define TM_ALIGN_INT 0x17 /* The program caused an alignment */
/* interrupt while in transactional */
/* mode. */
/*
* Transient Failure Codes
*/
#define TM_PREEMPTED 0x02 /* The transaction failued due to a */
/* context switch */
#define TM_NOT_FP_OWNER 0x04 /* The process-thread did not own the */
/* F.P. unit and attempted a F.P. */
/* operation or access */
#define TM_NOT_VMX_OWNER 0x06 /* The process-thread did not own the */
/* VMX unit and attempted a VMX */
/* operation or access */
#define TM_NOT_VSX_OWNER 0x08 /* The process-thread did not own the */
/* VSX unit and attempted a VSX */
/* operation or access */
#define TM_NOT_FAC_OWNER 0x0A /* The process-thread did not own a */
/* Facility and attempted an operation/ */
/* access resulting in a Facility */
/* Unavailable Interrupt. */
#define TM_CPU_SPARED 0x0C /* The transaction failed due to a CPU */
/* sparing operation on the CPU it was */
/* running on. */
#define TM_THREAD_SUSP 0x0E /* The transaction was failed due to */
/* the process-thread being suspended. */
#define TM_SIG_DELIVERED 0x10 /* The transaction was failed due to */
/* signal delivery. */
#define TM_THREAD_START 0x12 /* The transaction was failed upon the */
/* start of of a thread. */
#define TM_KDB_ENTERED 0x14 /* KDB was entered */
/*
* Reserved Failure Codes
*
* The following failure codes are reserved for future use by AIX:
* 0x16, and 0x18 through 0x3F.
*
* The failure codes 0x40 through 0xDF are free for use by applications.
*
* The failure codes 0xE0 through 0xFF are reserved for use by the
* Hypervisor and have the following meaning:
* Transient Hypervsor Failure Codes:
* 0xE0 - The transaction has failed due to processor dispatch cycle.
* 0xE2 - The transaction has failed due to late binding of the FP facility
*
* Persistent Hypervisor Failure Codes:
* 0xFF - The transaction has failed due to LPAR termination (will not
* be visible to the partition).
*
* Note that when the failure code is set to 0x00 the failure was not
* explicitly forced by AIX or the Hypervisor.
*/
/*
* VR Save Register (VRSAVE)
*
* Note: The AIX ABI specifies that an ABI-compliant
* program must not use or alter VRSAVE.
* As such the internal usage of VRSAVE by the AIX kernel
* is subject to change.
*/
#define VRSAVE_NONE 0x0000 /* The process-thread has never used VMX, */
/* VSX, or TM. */
#define VRSAVE_VX 0x0001 /* The process-thread has used VMX or VSX. */
#define VRSAVE_TM 0x0002 /* The process-thread has used TM. */
/************************************************************/
#ifdef _KERNEL
/*
* MACROS to determine the type of RS/6000 machine
*/
extern int mach_model;
#define MACH_RS1() (!(mach_model & 0x06000000))
#define MACH_RSC() (mach_model & 0x02000000)
extern int fp_ie_impl; /* nonzero if ie implemented */
#define FP_IE_IMPL (fp_ie_impl != 0)
#endif /* _KERNEL */
#ifdef _KERNSYS
#ifdef _POWER_PC
#ifdef _POWER_601
/*
* The following macro can be used to generate a BUID 7f segment
* register value given a real address
*/
#define BUID_7F_SRVAL(raddr) (0x87F00000 | (((uint)(raddr)) >> 28))
#endif /* _POWER_601 */
/*
* DBATU Data BAT Upper
* +---------------------------------------------------------------+
* | Effective Address | rsvd | Block Size |V|V|
* | BEPI | | BL |S|P|
* | | | | | | | | | | |1|1|1|1|1|1|1|1|1|1|2|2|2|2|2|2|2|2|2|2|3|3|
* |0|1|2|3|4|5|6|7|8|9|0|1|2|3|4|5|6|7|8|9|0|1|2|3|4|5|6|7|8|9|0|1|
* +---------------------------------------------------------------+
*
* DBATL Data BAT Lower
* +---------------------------------------------------------------+
* | Real Address | rsvd |W I M G| |P P|
* | BRPN | | | | |
* | | | | | | | | | | |1|1|1|1|1|1|1|1|1|1|2|2|2|2|2|2|2|2|2|2|3|3|
* |0|1|2|3|4|5|6|7|8|9|0|1|2|3|4|5|6|7|8|9|0|1|2|3|4|5|6|7|8|9|0|1|
* +---------------------------------------------------------------+
*/
/*
* The following defines are all valid values for the data BAT
* BL field
*/
#define BT_256M 0x1FFC /* 256 Meg block */
#define BT_128M 0x0FFC /* 128 Meg block */
#define BT_64M 0x07FC /* 64 Meg block */
#define BT_32M 0x03FC /* 32 Meg block */
#define BT_16M 0x01FC /* 16 Meg block */
#define BT_8M 0x00FC /* 8 Meg block */
#define BT_4M 0x007C /* 4 Meg block */
#define BT_2M 0x003C /* 2 Meg block */
#define BT_1M 0x001C /* 1 Meg block */
#define BT_512K 0x000C /* 512 K block */
#define BT_256K 0x0004 /* 256 K block */
#define BT_128K 0x0000 /* 128 K block */
/*
* The following defines are for data BAT PP (access protection)
*/
#define BT_NOACCESS 0x0 /* BAT no access */
#define BT_RDONLY 0x1 /* read only access */
#define BT_WRITE 0x2 /* read write access */
/*
* The following defines are for the data BAT Vs Vp fields
*/
#define BT_VS 0x2 /* BAT valid in kernel mode */
#define BT_VP 0x1 /* BAT valid in user mode */
/*
* The following values can be used to generate data BAT values
* raddr - real address
* size - BL field (use BT_XXX defines above)
* val - BAT (use BT_XXX defines above)
* eaddr - effective address to map
* wimg - storage attributes
* pp - access protection (use BT_XXX defines above)
*/
#define DBATU(eaddr, size, val) (((eaddr) & 0xFFFE0000) | (size) | (val))
#define DBATL(raddr, wimg, pp) (((raddr) & 0xFFFE0000) | ((wimg) << 3) | (pp))
/*
* The DBATU_D and DBATL_D macros are for access of 64bit I/O
*/
#define DBATU_D(eaddr, size, val) \
((unsigned long long)((unsigned long long)(eaddr) & \
(unsigned long long)0xFFFFFFFFFFFE0000ULL) | \
(unsigned long long)(size) | (unsigned long long)(val))
#define DBATL_D(raddr, wimg, pp) \
((unsigned long long)((((raddr) & \
((unsigned long long)0xFFFFFFFFFFFE0000ULL))) | \
((unsigned long long)(wimg) << 3) | \
((unsigned long long)(pp))))
/*
* This macro can returns the segment number that a data BAT maps
*/
#define BAT_ESEG(dbatu) (((uint)(dbatu) >> 28))
#define MIN_BAT_SIZE 0x00020000 /* Minimium BAT size (128K) */
#define MAX_BAT_SIZE 0x10000000 /* Maximium BAT size (256M) */
/*
* ASR (Low 32-bits)
* +---------------------------------------------------------------+
* | V|
* | | | |
* | | | | | | | | | | |1|1|1|1|1|1|1|1|1|1|2|2|2|2|2|2|2|2|2|2|3|3|
* |0|1|2|3|4|5|6|7|8|9|0|1|2|3|4|5|6|7|8|9|0|1|2|3|4|5|6|7|8|9|0|1|
* +---------------------------------------------------------------+
*
* Power PC ASR SPR is used to anchor a segment table. It contains the
* segment table's real address. A valid bit enables the segment table
* lookup to proceed.
*/
#define ASR_VALID (1LL)
#define SLB_SIZE_MIN 32 /* min architected slb size */
#define SLB_SIZE_MAX 64 /* max slb size (for static arrays) */
#define SLB_SIZE SLB_SIZE_MAX
#ifndef __64BIT_KERNEL
#define USER_SLB_START 16 /* First slb index loaded */
#define SLBR_TESID 1 /* temporary ESID used slb_reload */
#else /* ... __64BIT_KERNEL */
#define MAX_SLB_INDEX 63 /* Last index */
#define SLB_NUM_MASK 0xcff /* mask for largest architected SLB */
#define SLB_VALID 0x08000000 /* SLB valid bit */
#define SLB_E_RSVD 0x07fffc00 /* reserved bits in slbmte */
#define SLB_Ks 0x800 /* Ks bit in SLB vmhandle */
#define SLB_Kp 0x400 /* Kp bit in SLB vmhandle */
#define SLB_N 0x200 /* N (no-execute) bit in SLB vmhandle*/
#define SLB_C 0x80 /* Class bit in SLB vmhandle */
#define SLB_L_BIT 0x0100UL /* L (large pg) bit in SLB vmhandle */
#define SLB_TA 0x0040UL /* Tags Active mode (not AIX) */
#define SLB_LP_BITS 0x0030UL /* LP (pg sz) bits in SLB vmhandle */
#define SLB_PSIZE_MASK 0x0130UL /* mask for SLB page size bits */
#define SLB_BITS_MASK (SLB_Ks | SLB_Kp | SLB_N | SLB_C | SLB_TA |\
SLB_PSIZE_MASK)
#define SLBE(_esid, _index) ((_esid)|SLB_VALID|(_index))
/* The bits in an STE (segment table entry) mostly mirror those in an SLBE, but
* the following are software managed STE bits only and so are not included in
* the SLB_BITS_MASK above. These bits can be added to a vmhandle_t only for
* the purposes of adding that handle to an STE. These bits should not be used
* in any vmhandle outside of an STE.
*/
#define SLB_SW_STEPIN 0x1UL /* s/w bit for STE pinned in STAB */
#define SLB_SW_RSVD1 0x2UL /* s/w bit reserved for future use */
#define SLB_SW_RSVD2 0x4UL /* s/w bit reserved for future use */
#define SLB_SW_RSVD3 0x8UL /* s/w bit reserved for future use */
#define SLB_SW_MASK 0xFUL /* mask for s/w managed bits */
#define VALID_HANDLE_SSLB(_handle) (!((_handle) & 0x0f))
#define HANDLE_CLASS_SSLB 0x80UL /* C-bit */
#ifndef _HSLB
#define SLB_TEMP0_INDEX 0xB
#define SLB_TEMP1_INDEX 0xC
#define SLB_TEMP2_INDEX 0xD
#define SLB_TEMP3_INDEX 0xE
#else
#define SLB_TEMP0_INDEX (HSLB_MODE(HWSLB)? 0 : 0xB)
#define SLB_TEMP1_INDEX (HSLB_MODE(HWSLB)? 1 : 0xC)
#define SLB_TEMP2_INDEX (HSLB_MODE(HWSLB)? 2 : 0xD)
#define SLB_TEMP3_INDEX (HSLB_MODE(HWSLB)? 3 : 0xE)
#endif
/* slbie format:
*
* [ 0:35 esid | 36 class bit | 37:38 seg size bits | 39:63 unused ]
*
* +-------------------------------------------------------------------+
* |
* | esid |C| B| unused
* | 11111111112222222222333333|3|33|3444444444455555555556666
* |012345678901234567890123456789012345|6|78|9012345678901234567890123
* +-------------------------------------------------------------------+
*/
#define SLBIE_RB(_eaddr, _C, _B) \
((_eaddr) | ((_C) << (63-36)) | ((_B) << (63-38)))
#endif /* !__64BIT_KERNEL */
/*
* Primitive functions for kernel debugger to do MMIOs
*/
long long read_mmio(long, unsigned long long);
void write_mmio(long, unsigned long long, unsigned long long);
/*
* Macro to test DSCR support
*/
extern struct dscr_properties dscr_info;
extern int hw_streams_supported;
#endif /* _POWER_PC */
#endif /* _KERNSYS */
/*
* In IA64, the alignment of a long long differs between 32 and 64 bit.
* In 64 bit, the alignment is on an 8 byte boundary but in 32 bit
* the alignment is on a 4 byte boundary. This causes some structure
* that are defined both in user space and on the kernel to misalign.
* The __INTPAD macro is used to force an alignment to the next 4 byte
* boundary.
*
* Note that this problem does not occur on POWER archtecture so this
* macro generates nothing in the POWER machine.h.
*/
#define __INTPAD(nm)
#ifdef _KERNEL
/*
* The following definitions are for facility kernel services
*/
#define FAC_VMX_UNIT (MSR_VMX)
#define FAC_VSX_UNIT (MSR_VSX|MSR_VMX|MSR_FP)
#define FAC_MASK (FAC_VMX_UNIT|FAC_VSX_UNIT)
int facility_enable(uint64_t facility);
int facility_disable(uint64_t facility);
/*
* vsx_enable and vsx_disable
*
* vsx_enable
* Syntax:
* #include <sys/machine.h>
* char vsx_enable ()
*
* Description: The vsx_enable kernel service communicates to the hypervisor
* that the vector and vector-scalar registers are in use.
*
* Execution Environment: The vsx_enable kernel service can be called
* from the process or interrupt environment.
*
* vsx_enable must be called while disabled at INTMAX.
*
* Return Values: The vsx_enable service returns the current PVPA setting that
* comminucates to the hypervisor that the vector and
* vector-scalar registers are in use.
*
* Note: This service used to be named vx_enable.
*
* vsx_disable
* Syntax:
* #include <sys/machine.h>
* void vsx_disable (old)
* char old;
*
* Parameters:
* old Specifies the value returned by the vsx_enable service.
*
* Description: The vsx_disable kernel service communicates to the hypervisor
* that the vector and vector-scalar registers are no longer in
* use.
*
* Execution Environment: The vsx_disable kernel service can be called
* from the process or interrupt environment.
*
* vsx_disable must be called while disabled at INTMAX.
*
* Return Values: The vsx_disable service has no return values.
*
* Note: This service used to be named vx_disable.
*/
char vsx_enable(void);
void vsx_disable(char old);
#endif /* _KERNEL */
/*
* ue_load
* Syntax:
* #include <sys/machine.h>
* uint64_t ue_load(addr)
* void *addr;
*
* Parameters:
* addr Specifies the address to load from.
*
* Description: The ue_load subroutine loads 8 bytes from memory and reports
* back to the caller when a uncorrectable error is encountered
* in memory when the load operation is performed. Upon finding
* an uncorrectable error, ue_load will return with a value of
* all ones.
*
* When ue_load reports that an uncorrectable error has been
* encountered, the caller should not attempt to directly access
* the memory. The bsterile subroutine or xmbsterile kernel
* service can be used to clear the uncorrectable error before
* attempting to directly access the memory.
*
* Execution Environment: The ue_load subroutine can be called from either
* a 32 or 64 bit execution environment.
*
* Return Values:
* All 1s - An uncorrectable error has been detected.
* All other values - Value read from the specified memory
* address.
*/
uint64_t ue_load(void *);
#if __64BIT__
#pragma mc_func ue_load { "48016683" } /* bla 0x16680 */
#pragma reg_killed_by ue_load gr3
#else
#pragma mc_func ue_load { "480116C3" } /* bla 0x116C0 */
#pragma reg_killed_by ue_load gr3,gr4
#endif /* __64BIT__ */
/*
* ue_query
* Syntax:
* #include <sys/machine.h>
* void *ue_query(buf, len)
* void *buf;
* size_t len;
*
* Parameters:
* buf Specifies the address of the buffer to query.
* len Indicates the length of the buffer in bytes.
*
* Description: The ue_query subroutine determines if there are any
* uncorrectable errors present in the memory consumed by the
* specified buffer. Upon finding an uncorrectable error, the
* ue_query subroutine returns the address of the beginning of the
* cache line containing the uncorrectable error. If the buffer is
* not cache aligned and the uncorrectable error is in the first
* cache line consumed by the buffer, the ue_query subrouine will
* return the address of the beginning of the buffer.
*
* Execution Environment: The ue_query subroutine can be called from either
* a 32 or 64 bit execution environment.
*
* Return Values:
* 0 - No uncorrectable errors detected.
* Non-zero - An uncorrectable error has been detected. Indicates
* the cache line containing the first uncorrectable error
* or the beginning of the buffer when the first error is
* in the first cache line and the buffer is not cache
* aligned.
*/
void *ue_query(void *, unsigned long);
#pragma mc_func ue_query { "480166B3" } /* bla 0x166B0 */
#pragma reg_killed_by ue_query gr3,gr4,gr5,cr0
#ifdef __cplusplus
}
#endif
#endif /* _H_MACHINE */