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U> VP WH' Xp Y" Z/6 [f \o ]p ^5 _U2 `Y a b!o c" d> e f>s g( h/ i" j/. k*^ l m>0 n\o o# pM q{> rN sN t|X u~ v}T w} xDP yC z0 {L |W }u ~N ` B NX Y C xE C D SG  Xa E    , HD H S s* 2   /  o pt  f b uK  D  K  R  Y  l o ol o pL r \0 f  u  w  l w k  q  x n yv  s  y  nŒ y u  {  ł n yƀ  }  ȃ  nɖ y   o˝  ̝ v8 ͯ ~5 zδ / ϸ A  S p O Tf Rһ  ӟ 0  NR /ա S S% y  ן 2  PZ T٫ T U  {  ܡ P6 T݇ T 1  W  } P Tc T   3  Y P `? `   ?  } \ Rn > = > _ k( i D DC < M \ 6p 9  !Z "0] # $J %: &Y 'Ao (U )v *V~ +E , -V .: /]5 0; 1K 2T 3Yp 4' 5 6 7  8@ 9~ :$S ;x < = > ?~Y @$ A! B  C%+ D8Q E7 F G  HZ IXW JK KQ LKN MJ NY Oh? PJ Q R SC T!N Up VVM W4 XV YV0 ZO [E \9 ]|W ^u _uJ ` aF b? c: d E e!f f_ gH hl1 iW jc kgZ l` mj# nk o3 p. qK r%f sr t4 u4 vW5 w x[ y, z-6 {(d |( }( ~3  T0 ~ U  U Z = 1 X Cycles D cache prefetch filter has 1 and only 1 stream entryNot usedZero cycle branch not takenZero cycle branch takenNo instructions were completingNo instructions dispatchedCycles exactly 1 castout buffer occupiedNumber of time 1 instructions are dispatchedCycles with 1 and only 1 outstanding missSingle-thread mode cyclesCycles 1 write-through buffer usedCycles exactly 2 castout buffers occupiedNumber of time 2 instructions are dispatchedCycles with 2 and only 2 outstanding missesThread 1 and 2 both run latches setCycles 2 write-through buffers usedCycles exactly 3 castout buffers occupiedNumber of time 3 instructions are dispatchedCycles with 3 and only 3 outstanding missesTimes the 4 basic blocks were usedCycles 4 and only 4 castout buffers usedNumber of time 4 instructions are dispatchedCycles with 4 and only 4 outstanding missesInstr load op completed on 6xx bus & bus op to receive instrBus retried transaction that change trans. typeAbsolute branchesProcessor address bus transactions that were ARTRY'dAn alignment interrupt was executedAll castoutsA master-generated Bus operation received an ARespin (ARI) retryA master-generated Bus operation received an AStatin (ASI) retryBIU forwards non-critical data from the linefill bufferMaster generated load operation is not retriedMaster generated load is retriedBIU retries but DU lost reservationMaster generated store operation is not retried6xx master transaction retried on bus for store opA master-generated store stalled for a store bufferB pipe instr completedBranch to counter takenBranch to link register takenCycles branch queue fullNumber of cycles the branch unit is idleCycles the branch unit is waiting for its operandBranches completedInstructions dispatched to the branch unitBRU produced a resultBranches incorrectly predictedA conditional branch was predictedBTAC HitsBTAC MissesNumber of cycles BTC/BTL is blocked from dispatchA burst read caused an L2 accessA burst read caused an L2 missL2 burst read miss & another processor has a modified copyBurst reads which were streamed in fastl2 modeBus cycles after an internal bus request without a qualified bus grantConditional branch dispatchedA conditional branch was resolved at dispatchInstructions dipatched to the MCIMCIU produced a resultChain PMC1 to PMC8Chain PMC2 to PMC1Chain PMC3 to PMC2Chain PMC4 to PMC3Chain PMC5 to PMC4Chain PMC6 to PMC5Chain PMC7 to PMC6Chain PMC8 to PMC7Cycles a cache inhibited store is waiting on a cache inhibited storeCycles completion unit is stalled for a load instructionCycles completion unit is stalled for a store instructionCycles completion unit is stalled for an unfinished instructionBranches conditional not takenBranches conditional takenCore-originated stores and copybacksNumber of CRB busy block entriesCR logical unit produced a resultProcessor cyclesCycles 0 instructions dispatchedNumber cycles that 1 store buffer is occupiedCycles 1 instructions dispatchedCycles 2 instructions dispatchedCycles 3 instructions dispatchedCycles 4 instructions dispatchedCycles not gated by 'run'Cycles not gated by 'run' or thread activeData table walksCycles doing data tablewalksData bus transactions which finish with pipelining 1 deepData bus transactions which finish with pipelining 2 deepData bus transactions which finish with pipelining 3 deepData bus transations that use Data Bus Write Only reorder featureD cache accesses retried due to castout buffers being busyAliased hit in D cacheNumber of D cache hit under missesD cache missesD cache prefetch buffer invalidatesCycles demand miss blocked with 1 or more prefetches outstandingCycles D cache prefetch filter has 2 stream entriesCycles D cache prefilter has 3 and only 3 stream entriesD cache prefetch filter has 4 and only 4 stream entriesD cache prefetch hitD cache prefetch request and data in L2D cache lines inval in L2 due to prefetch LD dataD cache prefetch stream allocations blockedD cache prefetched and usedD cache request hit on prefetch bufferFetch corrections made at decode stateDemand fetch blocked by outstanding prefetchDispatch buffer is empty this cycleFetch corrections made at DISP stageCycles DISP unit is stalled due to counter-link interlockCycles DISP unit is stalled waiting for instructionsCycles DISP unit is stalled due to no CR rename buffer availableCycles DISP unit is stalled due to no FPR rename buffer availableCycles DISP unit is stalled due to no GPR rename buffer availableCycles DISP unit is stalled due to no reorder buffer entry availableCycles DISP unit is stalled due to no unit availableData SLB missesData TLB missesDU0 requested a store address translationDU1 requested a store address translationThe ECAM/RCAM logic detected an offset hit from DUCycles MSR(EE) bit offCycles MSR(EE) bit off and external interrupt pendingEIEIO instructions completedCycles EIEIO waits on a storeThread prefetch buffer empty on switchNumber of entries in the completion bufferFPU executed multiply-add instructionExternal interruptsStrobes to external interfaceFetch corrections made at dispatch stageFloating Point Unit 0 busyFloating-point unit produced a resultFPU0 received denormalized dataFPU0 executed FEST instructionFPU0 executed FRSP or FCONV instructionsFPU0 executed FSQRT instructionFPU0 executed FADD, FCMP or FMULFPU0 executed FDIV instructionFPU0 executed multiply-add instructionFPU0 executed FMOV or FEST instructionsFPU0 executed FPSCR instructionFPU1 busyFPU1 produced a resultFPU1 received denormalized dataFPU1 idleFloating-point instructions completed (no loads or stores)FPU received denormalized dataInstructions dispatched to the FPUFPU executed FPSCR instructionFPU executed FCMP instructionFPU executed FADD or FMUL instructionFPU executed FDIV instructionFPU executed FEST instructionFPU produced a resultFPU executed FSQRT instructionNumber of cycles the FP unit is idleNumber of cycles the FPU instruction queue is fullFPU executed a load floating point instructionNumber of FPU loads and stores issued by LSU to DUNumber of FPU successful out-of-order instruction schedulingCycles the FPU was stalledFPU executed FRSP or FCONV instructionsFXU0 produced a resultFXU1 idleFXU1 produced a resultFXU2 is busyFXU2 idleFXU2 produced a resultInteger instructions completed (no loads or stores)FXU idleInstructions deleted on global cancelFXU group x40FXU group x41L1 D cache group x50L1 D group x51L1 D cache group x52E=DS group x54TLB/SLB group x55L2 cache group x56L2 cache group x57L2 cache group x58SLB group x5cL2 cache group x60L2 cache group x61L2 cache group x62L2 cache group x63L2 cache group x64L2 cache group x65L2 cache group x66L2 cache group x67Line buffer group x69line buffer group x6aline buffer group x6bline buffer group x6c6XX bus group x6d6XX bus group x6e6XX bus group x6fFPU group x70FPU group x71cycles spent in high priorityNumber of I=1 store operations to busNumber of instruction breakpoint hitsIABR matchEmpty instruction bufferICBI instructions completedThe IC was accessed and a block was fetchedInstruction cache missesAn I cache miss line was brought in and usedI cache prefetched and usedIERAT miss countIERAT miss latencyIERAT reference countInstructions completedInstructions completed gated by IMRInstructions dispatchedInstructions written into the load queueInstructions written into the store queueInstructions not dispatched beyond branchInstruction table walksCycles doing instruction tablewalksCycles of store stalls due to interleave conflictNumber of I/O interruptsInstruction SLB missesIsync durationInstruction TLB missesL1 I cache misses on branch target prefetchL1 D cache miss countL1 D cache miss latencyL1 I cache miss countL1 I cache miss latencyL1 I cache reference countRWITM caused an L2 accessNumber of cycles the L2_INT pin is highNumber of times the L2_INT pin transitions from zero to oneL2 miss on both threads countL2 miss on both threads durationNumber of cache inhibit (I=1) loadsLoads completedLoads in the completion buffer at global cancelLoad instr dispatchedCycles of load missesLoad miss linefills brought into the D cache in a shared stateLoad miss linefills brought into the D cache in an Exclusive (E) stateLoad D cache misses with lateral L2 cache intervention and exceeding thresholdLoad D cache misses without lateral L2 cache intervention and exceeding thresholdL1 D cache load missesLoad miss occurred in L1, but hit in L2Load instruction is the next instr. to completeCycles load stalls due to interleave conflictCycles load stalls due to store conflictLink register stack is fullLink register stack errorcycles spent in low priorityNumber of entries in load queueLoad queue is fullLDU0 received data (for a load)LSU0 issued a tagged load request to D cacheLSU0 issued a tagged store request to D cacheCycles LSU1 idleLSU1 issued a tagged load request to D cacheLSU1 issued a tagged store request to D cacheInstructions dispatched to the LSUInstructions executed by LSUCycles LSU is idleCycles LSU is stalled due to address collisionsCycles LSU is stalled due to BIU or cache busyCycles LSU is stalled due to full load queueCycles LSU is stalled due to MMU busyCycles LSU is stalled due to operands not availableCycles LSU is stalled due to snoop busyCycles LSU is stalled due to full store queueNumber of cycles MCIU0 is idleCycles the MCIU was stalledNumber of cycles the MCIU is idleCycles spent in medium priorityMFSPR dispatchedMisaligned loads that are cache hits for both the 1st and 2nd accessesM pipe instr completedGlobal cancel due to mispredicted branchMTSPR instructions dispatchedNo events countedCycles in which another thread is readyPrefetch matches a demand missReservations successfully obtainedReservations requestedRetry 6xx bus operationR pipe instr completedCycles the SCIU0 was stalledNumber of cycles the SCIU1 is idleSystem callsInstructions dispatched to the SCIU0 unitSCIU0 produced a resultInstructions dispatched to the SCIU1 unitSCIU1 produced a resultCycles the SFX1 was stalledSnoop requests receivedSnoop based L1/L2 transitions from eXclusive to SharedSnoop hitsSnoop based L1 transitions from M to E or SSnoop operation which accessed the L2Snoop hits in L2Snoop based L2 transitions E or S to ISnoop based L2 transitions from M to E or SSnoop based L2 transitions from M to ICycles snoop push buffer usedSnoop pushes from the dedicated snoop push bufferA snoop caused a push or an interventionS pipe instr completedNumber of entries in store queueStore queue is fullCache inhibited (I=1) stores before gatheringStore instruction completedStores in the completion buffer at global cancelStore conditional failedStore instructions dispatchedNumber of store bytes gatheredNumber of store doublewords gatheredNumber of store halfwords gatheredNumber of store words gatheredL1 store hitsL1 D cache store missesRWITM caused L2 missRWITM in L2 with interventionStorage latencyStore D cache misses with lateral L2 cache intervention and exceeding thresholdStore D cache misses without lateral L2 cache intervention and exceeding thresholdSYNC instructions completedExecuting a single instruction serializationPipeline flushing operationsCycles a sync instr is at bottom of the completion bufferSync rerun operationsPLS_mode S pipe instr completedL2 access caused by tagged burst readL2 misses caused by tagged burst readL2 misses with intervention caused by tagged burst readLSU1 receives data from memory sideTagged store completedTagged RWITM caused L2 accessTagged RWITM caused L2 missA RWITM in the L2 with interventionTime Base bit transitionThrashing counts < 2 instr between switchesThrashing counts < 4 instr between switchesThrashing counts < 8 instr between switchesThread 0 run cyclesThread 1 run cyclesThread switch countThread switch caused by dormant thread DSIThread switch caused by ERAT missThread switch caused by L1 data fetch missThread switch caused by L1 data store missThread switch caused by L1 instr missThread switch caused by L2 data returned in non-active threadThread switch caused by L2 DF Multiple missThread switch caused by L2 DS Multiple missThread switch caused by L2 fetch missThread switch caused by L2 instr missThread switch caused by L2 missThread switch caused by L2 store missThread switch caused by miss on load multiple/stringThread switch caused by MISCThread switch caused by miss on first of store doubleThread switch caused by miss on first of two unaligned loadThread switch caused by miss on second of store doubleThread switch caused by miss on second of two unaligned loadThread switch caused by priorityThread switch caused by SCOM cmdThread switch caused by miss on store multiple/stringThread switch caused by SW threadswitchThread switch caused by thread timeoutThread switch caused by TLB/SLB missThread switch caused by TLB Multiple missThread switch durationCycles a tlbsync instr is at bottom of completion bufferTLBSYNC rerun operationsTLB missesTLB miss latencySelected counts from trace_cnt(0)Selected counts from trace_cnt(1)Unaligned loadsUnaligned storesBranches unconditionalundefined thread switch countNumber of W=1 storesWrite-hit-on shared Kill broadcastsSuspendedCycles BIQ or IDU fullCycles CR logical operation mapper fullL2 prefetch cloned with L3D cache new prefetch stream allocatedCycles FPR mapper fullFPU0 executed add, mult, sub, cmp or sel instructionCycles GCT emptyInstruction fetched from memoryLRQ unaligned load flushesSRQ store forwardedMarked data loaded from L3Marked group dispatchedMarked L1 D cache load missesMarked store instruction completedRun cyclesCycles FPU0 issue queue fullFPU0 executed single precision instructionFPU0 stalled in pipe3FPU0 executed store instructionFPU1 executed add, mult, sub, cmp or sel instructionFPU1 executed FDIV instructionFPU1 executed multiply-add instructionFPU1 executed FSQRT instructionCycles FPU1 issue queue fullFPU1 executed single precision instructionFPU1 stalled in pipe3FPU1 executed store instructionCycles GCT fullGroup dispatch rejectedGroup dispatch validInstruction prefetched installed in prefetch bufferInstruction prefetch requestsTranslation written to ieratCycles at least 1 instruction fetchedL1 reload data source validL2 slice A transition from modified to invalidL2 slice A transition from modified to taggedL2 slice A transition from shared to invalidL2 slice A transition from shared to modifiedL2 slice B transition from modified to invalidL2 slice B transition from modified to taggedL2 slice B transition from shared to invalidL2 slice B transition from shared to modifiedL2 slice C transition from modified to invalidL2 slice C transition from modified to taggedL2 slice C transition from shared to invalidL2 slice C transition from shared to modifiedL3 bank 0 directory missesL3 bank 0 directory referencesL3 bank 1 directory missesL3 bank 1 directory referencesCycles LR/CTR mapper fullLSU0 DERAT missesLSU0 LRQ flushesLSU0 SRQ flushesLSU0 unaligned load flushesLSU0 unaligned store flushesLSU0 SRQ store forwardedLSU1 DERAT missesLSU1 LRQ flushesLSU1 SRQ flushesLSU1 unaligned load flushesLSU1 unaligned store flushesLSU1 SRQ store forwardedCycles LMQ fullLMQ LHR mergesLRQ slot 0 allocatedLRQ slot 0 validSRQ slot 0 allocatedSRQ slot 0 validMarked IMR reloadedLSU0 L1 D cache load missesLSU1 L1 D cache load missesMarked STCX failedMarked L1 D cache store missesSnoop TLBIESTCX failedCycles XER mapper fullData loaded from L3Data loaded from memoryFPU stalled in pipe3Group dispatchesInstruction fetched from L2.5/L2.75SRQ unaligned store flushesCycles LMQ and SRQ emptyMarked instruction BRU processing finishedMarked data loaded from memoryThreshold timeoutWork heldOne or more PPC instruction completedData loaded from L2.5 sharedFPU executed add, mult, sub, cmp or sel instructionCycles FPU issue queue fullFPU executed single precision instructionGroup dispatch successGroup marked in IDUInstruction fetched from L3SRQ flushesMarked data loaded from L2.5 sharedMarked group completion timeoutData loaded from L2.75 sharedFPU executed store instructionFXU busyInstruction fetched from L1DERAT missesLRQ flushesMarked data loaded from L2.75 sharedMarked instruction FXU processing finishedMarked group issuedMarked store sent to GPSCycles 1 instruction in CLBCycles 2 instructions in CLBCycles 3 instructions in CLBCycles 4 instructions in CLBCycles 5 instructions in CLBCycles 6 instructions in CLBCycles 7 instructions in CLBCycles 8 instructions in CLBBranches issuedBranch mispredictions due to CR bit settingBranch mispredictions due to target addressCycles CR issue queue fullL1 D cache entries invalidated from L2Out of prefetch streamsFabric command issuedFabric command retriedLSU0 executed Floating Point load instructionLSU1 executed Floating Point load instructionFPU0 produced a resultFPU1 executed FEST instructionFPU1 produced a resultFPU0 executing FMOV or FEST instructionsFPU1 executed FRSP or FCONV instructionsCycles FXU0/LS0 queue fullFXU0 produced a resultFXU1 produced a resultCycles GPR mapper fullCycles group dispatch blocked by scoreboardL1 cache data prefetchesCycles writing to instruction L1L2 slice A store hitsL2 slice A store requestsL2 slice B store hitsL2 slice B store requestsL2 slice C store hitsL2 slice C store requestsL2 cache prefetchesLarx executed on LSU0Larx executed on LSU1LSU0 L1 D cache load missesLSU1 L1 D cache load missesLSU0 L1 D cache load referencesLSU1 L1 D cache load referencesLSU0 busyLSU1 busyLMQ slot 0 allocatedLMQ slot 0 validCycles LRQ fullCycles SRQ fullSRQ sync durationMarked L1 reload data source validLSU0 marked LRQ flushesLSU0 marked SRQ flushesLSU0 marked unaligned load flushesLSU0 marked unaligned store flushesLSU0 finished a marked instructionLSU1 marked LRQ flushesLSU1 marked SRQ flushesLSU1 marked unaligned load flushesLSU1 marked unaligned store flushesLSU1 finished a marked instructionMarked instruction valid in SRQStcx passesLSU0 L1 D cache store referencesLSU1 L1 D cache store referencesData loaded from L3.5FXU produced a resultInstruction fetched from L2Marked data loaded from L3.5Marked LRQ flushesMarked store completed with interventionCompletion stoppedHypervisor CyclesData loaded from L2FXU1 busy FXU0 idleInstructions fetched from L3.5Larx executedLSU busyCycles SRQ emptyMarked instruction CRU processing finishedMarked data loaded from L2Marked group completedMarked SRQ flushesData loaded from L2.75 modifiedFXU0 busy FXU1 idleGroup completedInstruction fetched from prefetchMarked data loaded from L2.75 modifiedMarked instruction FPU processing finishedMarked instruction finishedMarked unaligned store flushesL1 D cache store referencesNo instructions fetchedData loaded from L2.5 modifiedFPU executed FMOV or FEST instructionsLSU executed Floating Point load instructionCycles FXLS queue is fullL1 D cache load referencesMarked data loaded from L2.5 modifiedMarked instruction LSU processing finishedMarked unaligned load flushesCycles 0 instruction completedCycles 1 instruction completedCycles 2 instructions completedCycles 3 instructions completedCycles AltiVec issue queue entries over thresholdAltiVec load instructions completedCycles Bus Outstanding Read Queue fullBPU stalls on LR dependencyCycles branch unit stalledCycles branch unit stalled on CTR dependencyCycles first speculation branch buffer activeFirst speculative branch buffer resolved correctlyCycles second speculation branch buffer activeSecond speculative branch buffer resolved correctlyCycles third speculation branch buffer activeThird speculative branch buffer resolved correctlyFall-through branches processedBranch flushesFolded branchesBranch link stack mispredictedBranch link stack predictionsBranch link stack correctly resolvedThread switch durationBranches takenTrue branch target instruction hitsUnresolved branchesFast BTIC hitsBTIC missesBus reads not retriedBus reads/writes not retriedBus retriesBus retry due to collisionBus retry due to intervention orderingBus retry due to L1 retryBus retry due to previous adjacentBus TAs for readsBus TAs for writesBus writes not retriedCycles completion queue entries over thresholdData breakpoint matchesDSSALL instructions completedDSS instructions completedDST stream 0 cache line fetchesDST stream 1 cache line fetchesDST stream 3 cache line fetchesDST instructions dispatchedRefreshed DSTsSuccessful DST, DSTT, DSTST, and DSTSTT table search operationsDTLB hardware table search cyclesDTLB hardware table search cycles over thresholdCycles DTQ fullDispatches to FPR issue queueCycles FPR issue queue entries over thresholdFPR issue queue stallsFPSCR rename is 1/2 busyFPSCR rename is 1/4 busyFPSCR rename is 3/4 busyFPSCR renames are completely busyL2 miss on both threads durationFloating-point store double requiring renormalizationFloating-point store single requiring denormalizationFPU denormalized resultsDispatches to GPR issue queueCycles GPR issue queue entries over thresholdGPR issue queue stallsCycles GPR rename buffer entries over thresholdPrefetch engine collision with instruction fetchPrefetch engine collision with loadPrefetch engine collision with load/store/instruction fetchPrefetch engine collision with storePrefetch engine fullCycles instruction queue entries over thresholdLocal interventionsExternal interventionsITLB hardware table search cyclesITLB hardware table searches over thresholdIU1 instructions completedIU2 instructions completedL1 D cache castouts to L2L1 D cache cycles usedL1 D cache hit countL1 D cache operation hitsL1 D cache reloadsL1 external interventionsCancelled L1 I cache missesL1 I cache miss latencyL1 I cache reloadsL1 D cache touch hitsL1 D cache touch missesL1 D cache touch miss latencyCycles L2 castout queue fullL2 cache castoutsL2 D cache missesL2 external interventionsL2 cache hitsL2 I cache missesL2 cache missesL2 requests servicedL2 D cache touch hitsCycles L3 read queue fullCycles L3 castout queue fullCycles L3 write queue fullL3 cache castoutsL3 D cache missesL3 external interventionsL3 cache hitsL3 I cache missesL3 cache missesL3 D cache touch hitsLoad instructions with reservation completedLoad aliases against L1 miss queue entryLoad aliases against touch in L1 miss queueIsync durationL1 D cache load hitsL2 D cache load hitsL3 D cache load hitsL1 D cache load miss cycles over thresholdL1 data load miss cyclesLoad string and load multiple instructions completedLoad string and multiple instruction piecesLSU aliases against CSQLSU aliases against FSQ/WB0/WB1LSU CSQ stores forwardedLSU instructions completedLSU executed Floating-point load doubleLSU executed Floating-point load singleLSU load hit line alias against completed store in CSQ0LSU load miss line alias against completed store in CSQ0LSU LMQ index alias stallsLSU RA latch stallsLSU indexed or true alias RA latch stallsLSU RA latch stalls while LMQ fullFloating-point stores causing stall in LSULSU store queue alias stallsLSU store queue index alias stallsLSU true alias stallsLSU unaligned RS0 stallsFloating-point store instructions completed in LSULSU executed Floating-point store doubleLSU executed Floating-point store singleLSU touch aliases against CSQLSU touch aliases against FSQ/WB0/WB1LSU touch aliases against L1 miss queue entryMFSPR instructions completedMTSPR instructions completedMTVRSAVE instructions completedMTVSCR instructions completedExternal performance monitor signalsProcessor performance monitor exceptionsSwitches between Privileged and User modesRefetch serializationTLB miss latencySnoop accesses to L1 D cacheL1 data snoop hitsL1 data snoop hits in L1 castout queueL1 data snoops hit castout and retriedL1 data snoop hits on modified lineSnoop modifiedExternal snoops causing a pushSnoops to modified lines causing L1 data pushSnoop retriesExternal snoop retriesL1 D cache miss latencySnoop validConditional stores with reservation completedSuccessful conditional stores with reservationCache-inhibited stores after gatheringMTSPR instructions dispatchedL2 D cache store hitsL3 D cache store hitsStores mergedStores merged into full 32 bytes cache lineIERAT miss latencyStore string and store multiple instructions completedStore string and multiple instruction piecesWrite-through stores after gatheringEIEIO instructions completedTLBIE instructions completedTLBSYNC instructions completedUnaligned loads finishedUnaligned stores completedVFPU instructions completedCycles synchronizing MFVSCR instructionsCycles an instruction in VFPU waits for operandVIU1 instructions completedCycles an instruction in VIU1 waits for operandVIU2 instructions completedCycles an instruction in VIU2 waits for operandVPU instructions completedCycles an instruction in VPU waits for operandDispatches to VR issue queueVR stallsVSCR(SAT) transitions to setVT2 fetchesVTQ line fetchesVTQ line fetch L1 hitsVTQ line fetch L1 missesVTQ stream premature cancelsVTQ stream resumes due to change of contextVTQ stream suspends due to change of contextNumber of entries in Store queueCycles a cache inhibited store is waiting on a cache inhibited storeGlobal cancel due to mispredicted branchStorage latencyCycles no instructions in CLBA conditional branch was predicted, CR predictionA conditional branch was predicted, CR and target predictionA conditional branch was predicted, target predictionUnconditional branchCycles CLB fullCompletion stall caused by D cache missCompletion stall caused by DIV instructionCompletion stall caused by ERAT missCompletion stall caused by FDIV or FQRT instructionCompletion stall caused by FPU instructionCompletion stall caused by FXU instructionCompletion stall caused by LSU instructionCompletion stall caused by rejectData loaded from L3.5 modifiedData loaded from L3.5 sharedData loaded from L3.75 modifiedData loaded from L3.75 sharedData loaded from local memoryData loaded from remote memoryData TLB miss for 16M pageData TLB miss for 4K pageData TLB reference for 16M pageData TLB reference for 4K pagedclaim issueddclaim retriedHold buffer to NN emptyHold buffer to VN emptyM1 to P1 sidecar emptyM1 to VN/NN sidecar emptyP1 to M1 sidecar emptyP1 to VN/NN sidecar emptyPN to NN beat went straight to its destinationPN to NN beat went to sidecar firstPN to VN beat went straight to its destinationPN to VN beat went to sidecar firstVertical bypass buffer emptyFlush caused by branch mispredictFlush caused by thread GCT imbalanceFlush caused by LSU or branch mispredictFlush caused by scoreboard operationFlush caused by syncCycles FXU1/LS1 queue fullNo slot in GCT caused by branch mispredictNo slot in GCT caused by I cache missNo slot in GCT caused by SRQ fullCycles GCT less than 60% fullCycles GCT 60-79% fullCycles GCT 80-99% fullGroup experienced branch redirectGroup experienced non-speculative branch redirectGroup experienced I cache missGroup experienced non-speculative I cache miss or branch redirectGroup experienced non-speculative I cache missL2 I cache demand request due to BHT redirectL2 I cache demand request due to branch redirectInstruction fetched from L2.5 modifiedInstruction fetched from L2.5 sharedInstruction fetched from L2.75 modifiedInstruction fetched from L2.75 sharedInstruction fetched from L3.5 modifiedInstruction fetched from L3.5 sharedInstruction fetched from L3.75 modifiedInstruction fetched from L3.75 sharedInstruction fetched from local memoryInstruction fetched from remote memoryL2 slice A RC load dispatch attemptL2 slice A RC load dispatch attempt failed due to address collision with RC/CO/SN/SQL2 slice A RC load dispatch attempt failed due to other reasonsL2 slice A RC load dispatch attempt failed due to all RC fullL2 slice A RC store dispatch attemptL2 slice A RC store dispatch attempt failed due to address collision with RC/CO/SN/SQL2 slice A RC store dispatch attempt failed due to other reasonsL2 slice A RC store dispatch attempt failed due to all RC fullL2 slice A RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busyL2 slice A RC dispatch attempt failed due to all CO busyL2 slice B RC load dispatch attemptL2 slice B RC load dispatch attempt failed due to address collision with RC/CO/SN/SQL2 slice B RC load dispatch attempt failed due to other reasonsL2 slice B RC load dispatch attempt failed due to all RC fullL2 slice B RC store dispatch attemptL2 slice B RC store dispatch attempt failed due to address collision with RC/CO/SN/SQL2 slice B RC store dispatch attempt failed due to other reasonsL2 slice B RC store dispatch attempt failed due to all RC fullL2 slice B RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busyL2 slice B RC dispatch attempt failed due to all CO busyL2 slice C RC load dispatch attemptL2 slice C RC load dispatch attempt failed due to address collision with RC/CO/SN/SQL2 slice C RC load dispatch attempt failed due to other reasonsL2 slice C RC load dispatch attempt failed due to all RC fullL2 slice C RC store dispatch attemptL2 slice C RC store dispatch attempt failed due to address collision with RC/CO/SN/SQL2 slice C RC store dispatch attempt failed due to other reasonsL2 slice C RC store dispatch attempt failed due to all RC fullL2 slice C RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busyL2 slice C RC dispatch attempt failed due to all CO busyL3 slice A active for every cycle all CI/CO machines busyL3 slice A hitsL3 slice A transition from modified to invalidL3 slice A transition from modified to TAGL3 slice A referencesL3 slice A transition from shared to invalidL3 slice A snoop retriesL3 slice B active for every cycle all CI/CO machines busyL3 slice B hitsL3 slice B transition from modified to invalidL3 slice B transition from modified to TAGL3 slice B referencesL3 slice B transition from shared to invalidL3 slice B snoop retriesL3 slice C active for every cycle all CI/CO machines busyL3 slice C hitsL3 slice C transition from modified to invalidL3 slice C transition from modified to TAGL3 slice C referencesL3 slice C transition from shared to invalidL3 slice C snoop retriesLSU0 non-cacheable loadsLSU0 reject due to ERAT missLSU0 reject due to LMQ full or missed data comingLSU0 reject due to reload CDF or tag update collisionLSU0 SRQ rejectsLSU1 non-cacheable loadsLSU1 reject due to ERAT missLSU1 reject due to LMQ full or missed data comingLSU1 reject due to reload CDF or tag update collisionLSU1 SRQ rejectsLSU busy due to rejectFlush initiated by LSUFlush caused by LRQ fullFlush caused by SRQ fullLSU reject due to ERAT missLSU reject due to LMQ full or missed data comingLSU reject due to reload CDF or tag update collisionLSU SRQ rejectsLWSYNC held at dispatchGroup experienced marked branch redirectFast path memory read completedHigh priority partial-write completedHigh priority write completedLow priority partial-write completedLow priority write completedMemory partial-write queue dispatchedMemory partial-write queue dispatched with 2-3 queues busyMemory partial-write completedMemory partial-write gatheredMemory read completed or cancelledMemory read queue dispatchedMemory read queue dispatched with 1-7 queues busyMemory read queue dispatched with 8-15 queues busySpeculative memory read cancelledMemory write queue dispatched with 1-7 queues busyMemory write queue dispatched with 8-15 queues busyMemory write queue dispatched due to dclaim/flushMemory write queue dispatched due to writeMarked load latency from L2.5 modifiedMarked load latency from L2.5 sharedMarked load latency from L2.75 modifiedMarked load latency from L2.75 sharedMarked load latency from L2Marked data loaded from L3.5 modifiedMarked load latency from L3.5 modifiedMarked data loaded from L3.5 sharedMarked load latency from L3.5 sharedMarked data loaded from L3.75 modifiedMarked load latency from L3.75 modifiedMarked data loaded from L3.75 sharedMarked load latency from L3.75 sharedMarked load latency from L3Marked data loaded from local memoryMarked load latency from local memoryMarked data loaded from remote memoryMarked load latency from remote memoryMarked Data SLB missesMarked Data TLB missesMarked Data TLB misses for 16M pageMarked Data TLB misses for 4K pageMarked Data TLB reference for 16M pageMarked Data TLB reference for 4K pageGroup experienced marked I cache missMarked internal operation completedPMC1 OverflowPMC2 OverflowPMC3 OverflowPMC4 OverflowPMC5 OverflowPMC6 OverflowPTEG loaded from L2PTEG loaded from L2.5 modifiedPTEG loaded from L2.5 sharedPTEG loaded from L2.75 modifiedPTEG loaded from L2.75 sharedPTEG loaded from L3PTEG loaded from L3.5 modifiedPTEG loaded from L3.5 sharedPTEG loaded from L3.75 modifiedPTEG loaded from L3.75 sharedPTEG loaded from local memoryPTEG loaded from remote memorySLB missesSnoop dclaim/flush retry due to write/dclaim queues fullSnoop partial write retry due to partial-write queues fullSnoop partial-write retry due to collision with active read queueSnoop partial-write retry due to collision with active write or partial-write queueSnoop read retry due to read queue fullSnoop read retry due to collision with active read queueSnoop read retry due to collision with active write queueSnoop retry due to one ahead collisionSnoop read retry due to read queue fullSnoop write/dclaim retry due to collision with active read queueSnoop write/dclaim retry due to collision with active write queueSuspendedCycles group completed by both threadsCycles both threads in L2 missesOne of the threads in run cyclesCycles thread running at priority level 1Cycles thread running at priority level 2Cycles thread running at priority level 3Cycles thread running at priority level 4Cycles thread running at priority level 5Cycles thread running at priority level 6Cycles thread running at priority level 7Cycles no thread priority differenceCycles thread priority difference is 1 or 2Cycles thread priority difference is 3 or 4Cycles thread priority difference is 5 or 6Cycles thread priority difference is -1 or -2Cycles thread priority difference is -3 or -4Cycles thread priority difference is -5 or -6Thread selection overrides caused by CLB emptyThread selection overrides caused by GCT imbalanceThread selection overrides caused by ISU holdsThread selection overrides caused by L2 missesDecode selected thread 0Decode selected thread 1SMT hang detectedTLBIE held at dispatchCycles no GCT slot allocatedCycles CLB emptyFPU1 executed FMOV or FEST instructionsAlignment software eventEmulation software eventISLBMISS software eventDSLBMISS software eventRun PPC instruction completedData TLB miss for 16G pageData TLB miss for 64K pageData TLB referencesData TLB reference for 16G pageData TLB reference for 64K pageLarge page translation written to ieratLSU data prefetch out of streamsMarked Data TLB misses for 16G pageMarked Data TLB misses for 64K pageMarked Data TLB referenceMarked Data TLB reference for 16G pageMarked Data TLB reference for 64K pagePPC instruction completedPTEG reload validDST (Data Stream Touch) stream startFPU0 executed add, mult, sub, cmp or sel instructionFPU1 executed add, mult, sub, cmp or sel instructionInstructions dispatch attemptedInternal operations completedCompletion stall caused by other reasonGCT empty due to I cache missGCT empty due to branch mispredictLSU0 busy due to rejectLSU1 busy due to rejectLSU0 SRQ lhs rejectsLSU1 SRQ lhs rejectsLSU SRQ lhs rejectsMarked data loaded missed L2Group experienced a branch mispredictRun instructions completedLSU data prefetch out of streamsMicrocode instructions completedLoad and Store instructions completedIMC matched internal operations completedIMC matched microcode instructions completedIMC matched Load and Store instructions completedIMC matched instructions completedFPU executed one flop instructionFlushesInstruction fetched missed L2Data loaded missed L2PTEG loaded from L2 missPMC7 OverflowPMC8 OverflowGCT empty caused by SRQ fullD cache out of prefetch streamsMarked instruction VMX processing finishedCycles at least one instruction dispatchedBranch misprediction due to count cache predictionBranch misprediction due to count predictionBranch count cache predictionA conditional branch was predicted, link stackData loaded from distant L2 or L3 modifiedLoad latency from distant L2 or L3 modifiedData loaded from distant L2 or L3 sharedLoad latency from distant L2 or L3 sharedData loaded from distant memoryLoad latency from distant memoryData loaded from private L2 other coreLoad latency from private L2 other coreLoad latency from L2.5 modifiedLoad latency from L2.5 sharedLoad latency from L2Load latency from L3.5 modifiedLoad latency from L3.5 sharedData loaded from private L3 missLoad latency from L3Load latency from local memoryData loaded from double pump memoryLoad latency from double pump memoryData loaded from remote L2 or L3 modifiedLoad latency from remote L2 or L3 modifiedData loaded from remote L2 or L3 sharedLoad latency from remote L2 or L3 sharedLoad latency from remote memoryDISP unit heldDISP unit held due to completion holding dispatchDISP unit held due to CR, LR or CTR updated by CR logical, MTCRF, MTLR or MTCTRDISP unit held due to cache writesDISP unit held due to FPU issue queue fullDISP unit held due to FPU updating CRDISP unit held due to non fixed multiple/divide after fixed multiply/divideDISP unit held due to FXU multicycleDISP unit held due to FXU slow ops (mtmsr, scv, rfscv)DISP unit held due to GPR dependenciesDISP unit held due to exceptionDISP unit held due to ISYNCDISP unit held due to SLB or TLB invalidatesDISP unit held due to load look ahead endedDISP unit held due to LSU move or invalidate SLB and SRDISP unit held due to LSU slow ops (sync, tlbie, stcx)DISP unit held due to multiple/divide multiply/divide GPR dependenciesDISP unit held after restart comingDISP unit held due to RU FXU write queue fullDISP unit held due to SMT conflictsDISP unit held due to MTSPR/MFSPRDISP unit held due to STCX updating CRDISP unit held due to thermal conditionDISP unit held due to lower priority threadDISP unit held due to XER dependencyDISP unit held due to cross thread resource conflictsCycles DISP unit is stalled waiting for instructionsCycles DISP unit is stalled due to branch mispredictionFlush caused by FPU exceptionFlush caused by FXU exceptionFPU executed FCONV instructionFPU executed 1FLOP, FMA, FSQRT or FDIV instructionFlush caused by asynchronous exceptionFPU executed FRSP instructionFPU executed FSQRT or FDIV instructionFPU executed fixed point divisionFPU executed fixed point multiplicationFPU issue 0 per cycleFPU issue 1 per cycleFPU issue 2 per cycleFPU divide/sqrt overlapped with other divide/sqrtFPU issue out-of-orderFPU issue stalled due to FPR dependenciesFPU issue stalled due to storeFPU issue stalled due to thread resource conflictFPU issue steeringFPU issue a folded storeFPU folded storefix point divide pipelinedfix point multiply pipelinedfix point multiply/divide pipelinedCycles instruction buffer fullL2 I cache demand request due to BHT redirectL2 I cache demand request due to branch redirectInstruction prefetch written into I cacheI cache line reloading to be shared by threadsI cache demand of prefetch requestInstruction dispatched under load look aheadInstruction fetched from distant L2 or L3 modifiedInstruction fetched from distant L2 or L3 sharedInstruction fetched from distant memoryInstruction fetched from private L2 other coreInstruction fetched missed L3Instruction fetched from double pump memoryInstruction fetched from remote L2 or L3 modifiedInstruction fetched from remote L2 or L3 sharedInstruction markedInstruction TLB referenceL2 cache prefetchesL2 cache prefetcheslarx hits in L1Both units L1 D cache load referencesLSU0 non-cachable storesLSU1 non-cachable storesBoth data return buses busy simultaneouslyDERAT Miss LatencyFlush caused by alignement exceptionFlush caused by DSIBoth LSU units executed Floating Point load instructionCycles both threads LMQ and SRQ emptyMarked load hit store rejectMarked unaligned load rejectMarked unaligned store rejectNon-cacheable loadBoth units non-cacheable loadNon-cacheable storeBoth units non-cacheable storeLSU rejectLSU reject due to mispredicted DERATLSU external reject requestLSU reject due to L2 correctable errorLoad hit store rejectLoad hit store reject both unitsLSU reject due to scratch register not availableLSU reject due to partial sector validLSU reject due to mispredicted setLSU reject due to stealLSU reject due to store queue fullUnaligned load rejectUnaligned load reject both unitsUnaligned store rejectUnaligned store reject both unitsnumber of chained storesIsync instruction completedMarked branch mispredictedMarked branch takenMarked data loaded from distant L2 or L3 modifiedMarked data loaded from distant L2 or L3 sharedMarked data loaded from distant memoryMarked data loaded from private L2 other coreMarked data loaded from L3 missMarked data loaded from double pump memoryMarked data loaded from remote L2 or L3 modifiedMarked data loaded from remote L2 or L3 sharedDecimal Unit marked instruction finishMarked instruction IFU processing finishedMarked instruction dispatchedMarked instruction issuedmarked Instruction finish timeoutMarked DERAT missMarked PTEG loaded from distant L2 or L3 modifiedMarked PTEG loaded from distant L2 or L3 sharedMarked PTEG loaded from distant memoryMarked PTEG loaded from L2.5 modifiedMarked PTEG loaded from private L2 other coreMarked PTEG loaded from L2.5 modifiedMarked PTEG loaded from L2.5 sharedMarked PTEG loaded from L2 missMarked PTEG loaded from L3Marked PTEG loaded from L3.5 modifiedMarked PTEG loaded from L3.5 sharedMarked PTEG loaded from L3 missMarked PTEG loaded from local memoryMarked PTEG loaded from double pump memoryMarked PTEG loaded from remote L2 or L3 modifiedMarked PTEG loaded from remote L2 or L3 sharedMarked PTEG loaded from remote memoryMarked PTEG reloadCyles no ITAG availablePMC2 Rewind EventPMC2 Rewind Value savedPMC4 Rewind EventPMC4 Rewind Value savedPTEG loaded from distant L2 or L3 modifiedPTEG loaded from distant L2 or L3 sharedPTEG loaded from distant memoryPTEG loaded from private L2 other corePTEG loaded from L3 missPTEG loaded from double pump memoryPTEG loaded from remote L2 or L3 modifiedPTEG loaded from remote L2 or L3 sharedPURR Eventstcx cancel by coreStore instructions finishedBoth units L1 D cache store referencesSync durationProcessor in thermal MAXBoth threads in run cyclesConcurrent Run InstructionsThread in L2 missBoth threads in Load Look AheadFast path memory read dispatchedNon speculative memory read cancelledMemory partial-write queue dispatched to Write Queue 2 or 3Memory write queue dispatched to queues 0-7Memory write queue dispatched to queues 8-15Memory read queue dispatched to queues 0-3Memory read queue dispatched to queues 4-7Memory read queue dispatched to queues 8-11Memory read queue dispatched to queues 12-15Memory read queue dispatched to queues 16-19Snoop retry due to a b collisionCycles DISP unit is stalled due to I cache missLSU0 SRQ lhs flushesLSU1 SRQ lhs flushesLSU0 marked L1 D cache load missesLSU1 marked L1 D cache load missesLSU0 marked SRQ lhs flushesLSU1 marked SRQ lhs flushesMarked SRQ lhs flushesCycles LSU0 reject due to load hit storeCycles LSU1 reject due to load hit storeCycles LSU reject due to load hit storePeriods with no instructions fetchedPeriods instruction buffer fullPeriods GCT fullPeriods no ITAG availablePeriods doing instruction tablewalksSYNC instructions completedRun PeriodsPeriods one of the threads in run cyclesLoad Look Ahead ActiveLoad Look Ahead not ActiveTransitions into Load Look Ahead modePeriods DISP unit held due to thermal conditionPeriods no GCT slot allocatedDERAT reference for 4K pageDERAT misses for 4K pageIERAT misses for 16G pageMarked DERAT reference for 64K pageMarked DERAT misses for 64K pageHypervisor PeriodsPeriods DISP unit heldPeriods DISP unit held due to Power ManagementPeriods DISP unit is stalled due to I cache missPeriods GCT emptyPeriods LMQ and SRQ emptyDERAT reference for 64K pageDERAT misses for 64K pageIERAT misses for 16M pageMarked DERAT reference for 4K pageMarked DERAT misses for 4K pagePeriods DISP unit is stalled waiting for instructionsPeriods both threads LMQ and DERAT reference for 16M pageDERAT misses for 16M pageIERAT misses for 64K pageMarked DERAT reference for 16M pageMarked DERAT misses for 16M pagePeriods both threads in run cyclesPeriods DISP unit is stalled due to branch mispredictionPeriods SRQ emptyDERAT reference for 16G pageDERAT misses for 16G pageIERAT misses for 4K pageMarked DERAT reference for 16G pageMarked DERAT misses for 16G pageRun PURR EventDclaim operation, locally masteredDMA operation, locally masteredMMIO operation, locally masteredNode pump operation, locally masteredRetry of a node pump, locally masteredSystem pump operation, locally masteredRetry of a system pump, locally masteredlocal node launch collision with off-node addressDISP unit held due to Power ManagementData loaded from double pump memoryLoad latency from double pump memoryData table walk matched in first half primary PTEGData table walk matched in second half primary PTEGData table walk matched in secondary PTEGDFU add type instructionDFU add type with both operands shiftedDFU back to back operations executedDFU convert from fixed opDFU Encode BCD to DPDDFU operand exponents are equal for add typeDFU instruction finishDFU result is a subnormalFPU0 executed FCONV instructionFPU0 executed 1FLOPFPU0 executed FRSP instructionFPU0 executed FSQRT or FDIV instructionFPU0 executed fixed point divisionFPU0 executed fixed point multiplicationFPU0 folded storeFPU1 executed FCONV instructionFPU1 executed 1FLOPFPU1 executed FPSCR instructionFPU1 executed FRSP instructionFPU1 executed FSQRT or FDIV instructionFPU1 executed fixed point divisionFPU1 executed fixed point multiplicationFPU1 folded storeFrequency is being slewed down due to Power ManagementFrequency is being slewed up due to Power ManagementInbound GX address utilization (# of cycle address is in valid)Inbound GX bus utilizations (# of cycles in use)Inbound GX Data utilization (# of cycle data in is valid)Outbound GX address utilization (# of cycles address out is valid)Outbound GX bus utilizations (# of cycles in use)Outbound GX Data utilization (# of cycles data out is valid)DMA Read RequestAll DMA Write Requests (including dma wrt lgcy)L1 I cache entries invalidated from L2IFU finished an instructionInstruction fetched from double pump memoryInstruction table walk matched in first half primary PTEGInstruction table walk matched in second half primary PTEGInstruction table walk matched in secondary PTEGL2 slice A castouts - ModifiedL2 slice A castouts - SharedL2 slice A D cache invalidateL2 slice A I cache invalidateL2 slice A load hitsL2 slice A data load missesL2 slice A instruction load missesL2 slice A load requestsL2 slice A data load requestsL2 slice A instruction load requestsL2 slice A missesL2 slice A store missesL2 slice B castouts - ModifiedL2 slice B castouts - SharedL2 slice B D cache invalidateL2 slice B I cache invalidateL2 slice B load hitsL2 slice B data load missesL2 slice B instruction load missesL2 slice B load requestsL2 slice B data load requestsL2 slice B instruction load requestsL2 slice B missesL2 slice B store missesL2 castouts - Modified (ML2 castouts - Shared (TL2 data load missesL2 instruction load missesL2 data load requestsL2 instruction load requestsL2 data store missesL2 data store requestsL3 slice A missesL3 slice B missesL2 load requestsLSU0 rejectLSU0 reject due to mispredicted DERATLSU0 external reject requestLSU0 L2 miss rejectLSU0 reject due to L2 correctable errorLSU0 load hit store rejectLSU0 reject due to scratch register not availableLSU0 reject due to partial sector validLSU0 reject due to mispredicted setLSU0 reject due to store queue fullLSU0 unaligned load rejectLSU0 unaligned store rejectLSU1 rejectLSU1 reject due to mispredicted DERATLSU1 external reject requestLSU1 reject due to L2 correctable errorLSU1 load hit store rejectLSU1 reject due to scratch register not availableLSU1 reject due to partial sector validLSU1 reject due to mispredicted setLSU1 reject due to store queue fullLSU1 unaligned load rejectLSU1 unaligned store rejectLSU fast rejectLSU slow rejectcacheline write setting dp to global side 0cacheline write setting dp to local side 0Memory read queue marking cache line double pump state from global to local side 0Memory read queue marking cache line double pump state from local to global side 0cacheline write setting dp to global side 1cacheline write setting dp to local side 1Memory read queue marking cache line double pump state from global to local side 1Memory read queue marking cache line double pump state from local to global side 1cache line write setting double pump state to globalcache line write setting double pump state to localMemory read queue marking cache line double pump state from global to localMemory read queue marking cache line double pump state from local to globalMarked data loaded from double pump memoryMarked instruction FPU0 processing finishedMarked instruction FPU1 processing finishedLSU0 marked L2 miss rejectLSU0 marked load hit store rejectLSU0 marked unaligned load rejectLSU0 marked unaligned store rejectLSU1 marked load hit store rejectLSU1 marked unaligned load rejectLSU1 marked unaligned store rejectMarked load hit store rejectMarked unaligned load rejectMarked unaligned store rejectMarked PTEG loaded from double pump memoryMarked VMX0 load writeback validMarked VMX1 load writeback validMarked VMX instruction issued to complexMarked VMX instruction issued to floatMarked VMX instruction issued to permuteMarked VMX instruction issued to simpleMarked VMX store issuedPTEG loaded from double pump memorySTCX executedL2 store requestsCycles thread running at priority level 0TLB referenceVMX0 instruction issuedVMX0 load issuedVMX0 load writeback validVMX0 stallVMX1 instruction issuedVMX1 load issuedVMX1 load writeback validVMX1 stallVMX instruction issued to complexVMX instruction issued to floatVMX multi-cycle floating point instruction issuedVMX instruction issued to permuteVMX valid result with sat bit is set (0->1)VMX valid result with sat=1VMX instruction issued to simpleVMX store issued1 thread Concurrent Run InstructionsOne of threads in run_cyclesBC+8 ConvertedBC+8 Resolve outcome was Taken, resulting in the conditional instruction being canceledBranch mispredict - taken/not taken and targetBranch Mispredict due to Link StackBTAC Correct PredictionNo groups completed, GCT not emptyCompletion stall caused by Decimal Floating Point UnitCount ended because GCT went emptyCompletion stall caused by FPU instructionCompletion stall caused by long latency scalar instructionCompletion Stalled due to thread conflict. Group ready to complete but it was another thread's turnCompletion stall caused by Vector instructionData loaded from another L2 on same chip modifiedData loaded from another L2 on same chip sharedData loaded from another L3 on same chip modifiedData loaded from another L3 on same chip sharedCLB Hold: Any ReasonDispatch/CLB Hold: BalanceDispatch/CLB Hold: ResourceDispatch/CLB Hold: ScoreboardDispatch/CLB Hold: Sync type instructionDispatch Hold: Due to TLBIEDispatch HeldDispatch Held due to ThermalDispatched Starved (not held, nothing to dispatch)DSEG ExceptionFloating Point Operation FinishedCompletion FlushDispatch flushDispatch Flush: ScoreboardDispatch Flush: SyncDispatch Flush: TLBIEPartial flushGCT empty by branch mispredict + IC missGCT Utilization 1-2 entriesGCT Utilization 11+ entriesGCT Utilization 3-6 entriesGCT Utilization 7-10 entriesGroup experienced non-speculative branch redirectcycles IDU marked instruction before dispatchRead blocked due to interleave conflictCycles when a demand ifetch was pendingL2 I cache demand request due to BHT or redirectDemand Instruction fetch requestPrefetch Canceled due to page boundary or icache hitPrefetch Canceled due to icache hitL2 Squashed requestPrefetch Canceled due to page boundaryIcache requests, prefetch + demandIcache sectors written, prefetch + demandlarge page 64klarge page 16M+Instruction fetched from another L2 on same chip modifiedInstruction fetched from another L2 on same chip sharedInstruction fetched from another L3 on same chip modifiedInstruction fetched from another L3 on same chip sharedIMC Matches dispatchedInstruction PTEG loaded from distant L2 or L3 modifiedInstruction PTEG loaded from distant memoryInstruction PTEG loaded from L2Instruction PTEG loaded from another L2 on same chip modifiedInstruction PTEG loaded from another L2 on same chip sharedInstruction PTEG loaded from L2 missInstruction PTEG loaded from L3Instruction PTEG loaded from another L3 on same chip modifiedInstruction PTEG loaded from another L3 on same chip sharedInstruction PTEG loaded from L3 missInstruction PTEG loaded from local memoryInstruction PTEG loaded from remote L2 or L3 modifiedInstruction PTEG loaded from remote L2 or L3 sharedInstruction PTEG loaded from remote memoryIOPS dispatchedISEG ExceptionInstruction Demand sectors wriittent into IL1L2 RC Cast Out dispatch attempt failed due to all CO machines busyDcache invalidates from L2All successful LD/ST dispatches for this thread(i+d)L2 guess glb and guess was correct (ie data remote)L2 guess glb and guess was not correct (ie data local)Icache Invalidates from L2Instruction Load CountInstruction Load MissesData Load CountAll successful load dispatchesAll successful load dispatches that were L2 hitsData Load MissData Load+Store CountData Load+Store MissL2 guess loc and guess was correct (ie data local)L2 guess loc and guess was not correct (ie data remote)RC req that was a local (aka node) pump attemptRC did st to line that was Tx or Sx L2 activated Busy to the core for loads due to all RC full L2 RC load dispatch attempt L2 RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ L2 RC load dispatch attempt failed due to other reasons L2 activated Busy to the core for stores due to all RC full L2 RC store dispatch attempt L2 RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ L2 RC store dispatch attempt failed due to other reasonsSNP dispatched for a read and was MSNP dispatched for a write and was MSNP dispatched and went from Sx or Tx to IxData Store CountAll successful store dispatchesAll successful store dispatches that were L2HitsData Store MissRC req that was a global (aka system) pump attemptL3 demand LD HitsL3 demand LD MissPrefetch machines >= threshold (8,16,20,24)L3 Prefetch Directory HitL3 cache LD prefetchesL3 cache prefetches LD + STL3 Prefetch Directory MissL3 cache ST prefetchesRd machines busy >= threshold (2,4,6,8)Larx FinishedD cache new prefetch stream allocatedDcache new prefetch stream confirmedDcache Strided prefetch stream confirmed (software + hardware)LSU Finished an instruction (up to 2 per cycle)LSU Finished a FX operation (up to 2 per cycle)All Vector loads (vsx vector + vmx vector)ALL threads lsu empty (lmq and srq empty)A partial cacheline was returned from the L3Line already in cache at reload timeSRQ sync count (edge of PM_LSU_SRQ_SYNC_CYC)Cycles when two tablewalks pending on this threadLS0 D cache new prefetch stream allocatedLS0 Dcache prefetch stream confirmedLS0 Dcache Strided prefetch stream confirmed LS0 L1 cache data prefetchesLS0 Vector LoadsLS0 Load Merged with another cacheline requestLS 1 D cache new prefetch stream allocatedLS1 'Dcache prefetch stream confirmedLS1 Dcache Strided prefetch stream confirmed LS1 L1 cache data prefetchesLS1 Vector LoadsLS1 Load Merge with another cacheline requestMarked ld latency Data Source 1110 (Distant Memory)Marked ld latency Data source 1011 (L2.75/L3.75 M different 4 chip node)Marked data loaded from another L2 on same chip modifiedMarked ld latency Data source 0101 (L2.1 M same chip)Marked data loaded from another L2 on same chip sharedMarked ld latency Data source 0100 (L2.1 S)Marked data loaded from another L3 on same chip modifiedMarked ld latency Data source 0111 (L3.1 M same chip)Marked data loaded from another L3 on same chip sharedMarked ld latency Data source 0110 (L3.1 S)Marked ld latency Data source 1001 (L2.5/L3.5 M same 4 chip node)Marked ld latency Data Source 1000 (Remote L2.5/L3.5 S)Marked instruction Finish Stall cycles (marked finish after NTC) (use edge detect to count #)Marked Load exposed MissMarked Load exposed Miss (use edge detect to count #)L1 data load miss cyclesFlush: (marked) : All CasesA partial cacheline was returned from the L3 for a marked loadLSU marked reject (up to 2 per cycle)LSU marked reject due to ERAT (up to 2 per cycle)Marked PTEG loaded from another L2 on same chip modifiedMarked PTEG loaded from another L2 on same chip sharedMarked PTEG loaded from another L3 on same chip modifiedMarked PTEG loaded from another L3 on same chip sharedmarked store sent to NestMarked Group Completion Stall cyclesMarked Group Completion Stall cycles (use edge detect to count #)vsu (fpu) marked instr finishNest events (MC0/MC1/PB/GX), Pair0 Bit0Nest events (MC0/MC1/PB/GX), Pair0 Bit1Nest events (MC0/MC1/PB/GX), Pair1 Bit0Nest events (MC0/MC1/PB/GX), Pair1 Bit1Nest events (MC0/MC1/PB/GX), Pair2 Bit0Nest events (MC0/MC1/PB/GX), Pair2 Bit1Nest events (MC0/MC1/PB/GX), Pair3 Bit0Nest events (MC0/MC1/PB/GX), Pair3 Bit1Nest events (MC0/MC1/PB/GX), Pair0 ADDNest events (MC0/MC1/PB/GX), Pair1 ADDNest events (MC0/MC1/PB/GX), Pair2 ADDNest events (MC0/MC1/PB/GX), Pair3 ADDNest events (MC0/MC1/PB/GX), Pair0 ANDNest events (MC0/MC1/PB/GX), Pair1 ANDNest events (MC0/MC1/PB/GX), Pair2 ANDNest events (MC0/MC1/PB/GX), Pair3 ANDPower Management Event 1Power Management Event 2Power Management Event 3Power Management Event 4PTEG loaded from another L2 on same chip modifiedPTEG loaded from another L2 on same chip sharedPTEG loaded from another L3 on same chip modifiedPTEG loaded from another L3 on same chip sharedRun SPURRISEG + DSEG ExceptionSHL table entry CreatedSHL Table entry deallocatedSHL Table MatchSHL table entry merged with existingCycles when a tablewalk (I or D) is activeProcessor in Thermal Warning1 thread in Run Cycles2 thread Concurrent Run Instructions2 thread in Run Cycles3 thread Concurrent Run Instructions3 thread in Run Cycles4 thread Concurrent Run Instructions4 thread in Run CyclesAll Threads in run_cycles Cycles thread running at priority level 0 or 1 Cycles thread running at priority level 2 or 3 Cycles thread running at priority level 4 or 5 Cycles thread running at priority level 6 or 7one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finishedtwo flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fnegfour flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions)eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub)Vector or Scalar denorm operandConvert instruction executedEstimate instruction executedVSU0 Finished an instructiontwo flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only!DP vector version of fmadd,fnmadd,fmsub,fnmsubRound to single precision instruction executedfour flops operation (fdiv,fsqrt) Scalar Instructions only!DP vector versions of fdiv,fsqrtDouble Precision scalar instruction issued on Pipe0Single Precision scalar instruction issued on Pipe0Simple VMX instruction issuedVector or Scalar single precisionFPU store (SP or DP) issued on Pipe0Double Precision vector instruction issued on Pipe0Single Precision vector instruction issued (executed)Sixteen flops operation (SP vector versions of fdiv,fsqrt)one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg, xsadd, xsmul, xssub, xscmp, xssel, xsabs, xsnabs, xsre, xssqrte, xsneg) operation finishedtwo flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)two flop DP vector operation (xvadddp, xvmuldp, xvsubdp, xvcmpdp, xvseldp, xvabsdp, xvnabsdp, xvredp ,xvsqrtedp, vxnegdp)four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions)eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub)Complex VMX instruction issuedFPU denorm operandConvert instruction executedEstimate instruction executedVSU0 Finished an instructiontwo flops operation (fmadd, fnmadd, fmsub, fnmsub, xsmadd, xsnmadd, xsmsub, xsnmsub) Scalar instructions only!four flop DP vector operations (xvmadddp, xvnmadddp, xvmsubdp, xvmsubdp)Move to/from FPSCR type instruction issued on Pipe 0Round to single precision instruction executedfour flops operation (fdiv,fsqrt,xsdiv,xssqrt) Scalar Instructions only!eight flop DP vector operations (xvfdivdp, xvsqrtdpDouble Precision scalar instruction issued on Pipe0Single Precision scalar instruction issued on Pipe0Simple VMX instruction issuedFPU single precisionFPU store (SP or DP) issued on Pipe0Double Precision vector instruction issued on Pipe0Single Precision vector instruction issued (executed)one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg, xsadd, xsmul, xssub, xscmp, xssel, xsabs, xsnabs, xsre, xssqrte, xsneg) operation finishedtwo flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)two flop DP vector operation (xvadddp, xvmuldp, xvsubdp, xvcmpdp, xvseldp, xvabsdp, xvnabsdp, xvredp ,xvsqrtedp, vxnegdp)four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions)eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub)64BIT Decimal Issued on Pipe1FPU denorm operand128BIT Decimal Issued on Pipe1Convert instruction executedEstimate instruction executedVSU1 Finished an instructiontwo flops operation (fmadd, fnmadd, fmsub, fnmsub, xsmadd, xsnmadd, xsmsub, xsnmsub) Scalar instructions only!four flop DP vector operations (xvmadddp, xvnmadddp, xvmsubdp, xvmsubdp)Round to single precision instruction executedfour flops operation (fdiv,fsqrt,xsdiv,xssqrt) Scalar Instructions only!eight flop DP vector operations (xvfdivdp, xvsqrtdpPermute VMX Instruction IssuedDouble Precision scalar instruction issued on Pipe1Single Precision scalar instruction issued on Pipe1FPU single precisionStore Vector Issued on Pipe1FPU store (SP or DP) issued on Pipe1Double Precision vector instruction issued on Pipe1Marked Branch TakenMarked L1 Icache MissThreshold counter exceed a count of 4096Threshold counter exceed a count of 256Marked demand reloadthreshold exceededIERAT Reloaded (Miss)Pipeline empty (No itags assigned , no GCT slots used)Any thread in run_cycles (was one thread in run_cycles)The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked loadMarked DL1 Demand Miss counted at exec timeThe processor's data cache was reloaded from a localtion other than the local core's L3 due to a marked loadThreshold counter exceeded a value of 32Threshold counter exceeded a value of 512Store Instructions Finished (store sent to nest)Number of PPC dispatchedDERAT Reloaded (Miss)Branch TakenDemand iCache MissDemand LD - L2 Miss (not L2 hit)Marked Branch MispredictedErat Miss (TLB Access) All page sizesThreshold counter exceeded a value of 64Threshold counter exceeded a value of 1024Store Missed L1DL1 reloaded due to Demand Load timebase eventInstruction from L3 missData PTEG Reloaded (DTLB Miss)Demand LD - L3 Miss (not L2 hit and not L3 hit)marked instruction completedsampled instruction missed icache and came from beyond L3Data cache reload L2 missThreshold counter exceeded a value of 128Threshold counter exceeded a value of 2048Load Missed L1Number of Branch MispredictsFlush (any type)ITLB ReloadedData cache reload from memory (including L4)Number of cycles in single lpar modeCycles in 2-lpar modeNumber of cycles in 4 LPAR modeBranch instruction completed with a target address less than current instruction addressRead blocked due to interleave conflicttwo path branchPairable BC+8 branch that has not been converted to a Resolve Finished in the BRU pipelinePairable BC+8 branch that was converted to a Resolve Finished in the BRU pipelinemarked two path branchConditional Branch Completed on BR0 (1st branch in group) in which the HW predicted the Direction or Target Conditional Branch Completed on BR1 (2nd branch in group) in which the HW predicted the Direction or TargetConditional Branch Completed on BR0 that used the Count Cache for Target PredictionConditional Branch Completed on BR1 that used the Count Cache for Target PredictionConditional Branch Completed on BR0 that had its direction predictedConditional Branch Completed on BR1 that had its direction predictedConditional Branch Completed on BR0 that used the Link Stack for Target PredictionConditional Branch Completed on BR1 that used the Link Stack for Target PredictionConditional Branch Completed on BR0 that had its target address predictedConditional Branch Completed on BR1 that had its target address predictedUnconditional Branch Completed on BR0Unconditional Branch Completed on BR1Castouts issuedCastouts issued GPRInitial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for all data types ( demand load,data,inst prefetch,inst fetch,xlate (I or d)CLB Hold: Any ReasonCompletion stall due to a Branch UnitCompletion stall due to IFUCompletion stall due to CO q fullCompletion stall by Dcache miss which resolved on chip ( excluding local L2/L3)Completion stall by Dcache miss which resolved in L2/L3Completion stall due to cache miss due to L2 l3 conflictCompletion stall due to cache miss resolving missed the L3GCT empty by branch mispredict + IC missCompletion stall by Dcache miss which resolved from remote chip (cache or memory)completion stall due to flush by own threadCompletion stall due to a long latency fixed point instructioncompletion stall due to hwsyncCompletion stall due to a Load finishcompletion stall due to isync/lwsyncCompletion stall due to mem ECC delayCompletion stall due to ntcg flushInstructions core completed while this thread was stalledCompletion stall due to reject (load hit store)Completion stall due to LSU reject LMQ fullCompletion stall due to store forwardCompletion stall by stores this includes store agen finishes in pipe LS0/LS1 and store data finishes in LS2/LS3 Completion stall due to VSU vector long instructionCompletion stall due to VSU instructionCO mach 0 BusyCO dispatch failed due to all CO machines being busyL2 did a cleanifdirty CO to the L3 (ie created an SC line in the L3)continuous 16 cycle(2to1) window where this signals rotates thru sampling each machine busyIFU Finished a (non-branch) instructionInitial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for either a demand load or prefetchThe processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either a demand load or prefetchThe processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either a demand load or prefetchThe processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to either a demand load or prefetchThe processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to either a demand load or prefetchThe processor's data cache was reloaded from local core's L2 due to either a demand load or prefetchThe processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to either a demand load or prefetchThe processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to either a demand load or prefetchThe processor's data cache was reloaded from local core's L2 with load hit store conflict due to either a demand load or prefetchThe processor's data cache was reloaded from local core's L2 with dispatch conflict due to either a demand load or prefetchThe processor's data cache was reloaded from a localtion other than the local core's L2 due to either a demand load or prefetchThe processor's data cache was reloaded from local core's L2 without conflict due to either a demand load or prefetchThe processor's data cache was reloaded from local core's L3 due to either a demand load or prefetchThe processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to either a demand load or prefetchThe processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to either a demand load or prefetchThe processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to either a demand load or prefetchThe processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to either a demand load or prefetchThe processor's data cache was reloaded from local core's L3 with dispatch conflict due to either a demand load or prefetchThe processor's data cache was reloaded from a localtion other than the local core's L3 due to either a demand load or prefetchThe processor's data cache was reloaded from local core's L3 without conflict due to either a demand load or prefetchThe processor's data cache was reloaded from the local chip's L4 cache due to either a demand load or prefetchThe processor's data cache was reloaded from the local chip's Memory due to either a demand load or prefetchThe processor's data cache was reloaded from a memory location including L4 from local remote or distant due to either a demand load or prefetchThe processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to either a demand load or prefetchThe processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to either a demand load or prefetchThe processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either a demand load or prefetchThe processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either a demand load or prefetchThe processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to either a demand load or prefetchThe processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to either a demand load or prefetchInitial and Final Pump Scope and data sourced across this scope was group pump for either a demand load or prefetchFinal Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data from source that was at smaller scope(Chip)Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor either a demand load or prefetchPump prediction correctInitial and Final Pump Scope and data sourced across this scope was system pump for either a demand load or prefetchFinal Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group)Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for either a demand load or prefetchInitial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for a demand loadThe processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a demand loadThe processor's data cache was reloaded from local core's L2 with load hit store conflict due to a demand loadThe processor's data cache was reloaded from local core's L2 with dispatch conflict due to a demand loadThe processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf stateThe processor's data cache was reloaded from a localtion other than the local core's L2 due to a demand load or demand load plus prefetch controlled by MMCR1[16]The processor's data cache was reloaded from local core's L2 without conflict due to a demand load or demand load plus prefetch controlled by MMCR1[16] The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a demand loadThe processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a demand loadThe processor's data cache was reloaded from local core's L3 with dispatch conflict due to a demand loadThe processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf stateThe processor's data cache was reloaded from a localtion other than the local core's L3 due to a demand loadThe processor's data cache was reloaded from local core's L3 without conflict due to a demand load or demand load plus prefetch controlled by MMCR1[16]The processor's data cache was reloaded from the local chip's L4 cache due to a demand load or demand load plus prefetch controlled by MMCR1[16]The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a demand loadThe processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a demand loadThe processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a demand load or demand load plus prefetch controlled by MMCR1[16]The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a demand loadInitial and Final Pump Scope and data sourced across this scope was group pump for a demand loadFinal Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data from source that was at smaller scope(Chip)Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor a demand loadPump prediction correctPump Mis prediction Counts across all types of pumpsfor a demand loadInitial and Final Pump Scope and data sourced across this scope was system pump for a demand loadFinal Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group)Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for a demand loadDATA Cache collisionsA demand load referenced a line in an active prefetch streamA demand load referenced a line in an active fuzzy prefetch streamA demand load referenced a line in an active strided prefetch streamFinish DFU (all finish)Convert from fixed opcode finish (dcffix,dcffixq)BCD->DPD opcode finish (denbcd, denbcdq)Finish DFU multicycleDispatch held due to Issue q fullDispatch for this thread was held because the Mappers were fullDispatch held due SRQ no roomDispatch held due to SYNC holdA PTEG was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), due to a data side requestA PTEG into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), due to a data side requestA Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a data side requestA Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a data side requestA Page Table Entry was loaded into the TLB from local core's L2 due to a data side requestA Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a data side requestA Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a data side requestA Page Table Entry was loaded into the TLB from local core's L2 with load hit store conflict due to a data side requestA Page Table Entry was loaded into the TLB from local core's L2 with dispatch conflict due to a data side requestA Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf stateA Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a data side requestA Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a data side requestA Page Table Entry was loaded into the TLB from local core's L3 due to a data side requestA Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a data side requestA Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a data side requestA Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a data side requestA Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a data side requestA Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a data side requestA Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf stateA Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a data side requestA Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a data side requestA Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a data side requestA Page Table Entry was loaded into the TLB from the local chip's Memory due to a data side requestA Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a data side requestA PTEG was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip due to a data side requestA Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a data side requestA PTEG was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), due to a data side requestA PTEG was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), due to a data side requestA Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a data side requestA Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a data side requestXL-form branch was mispredicted due to the predicted target address missing from EATCycles No room in EATDispatch time Favored tbeginflops summary scalar instructionsflops summary vector instructionsFlush initiated by LSUOne pair of instructions fused with TOC in Group0Two pairs of instructions fused with TOCin Group0Three pairs of instructions fused with TOC in Group0One pair of instructions fused with TOX in Group1One pair of instructions fused with VSX in Group0Two pairs of instructions fused with VSX in Group0Three pairs of instructions fused with VSX in Group0One pair of instructions fused with VSX in Group1Gct empty fo this thread due to Icache Miss and branch mispredGct empty fo this thread due to dispatch hold on this thread due to Issue q fullGct empty fo this thread due to dispatch hold on this thread due to Mapper fullGct empty fo this thread due to dispatch hold on this thread due to syncGct empty fo this thread due to dispatch hold on this thread due to SRQ fullGct empty fo this thread due to icach l3 missGCT Utilization 11+ entriesGCT Utilization 1-2 entriesGCT Utilization 14 17 entriesGCT Utilization 17+ entriesGCT Utilization 3-6 entriesGCT Utilization 7-10 entriesGROUPs where we did not have 6 non branch instructions in the group(ST mode), in SMT mode 3 non branches Initial and Final Pump Scope and data sourced across this scope was group pump for all data types ( demand load,inst fetch,xlate (I or d)Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data from source that was at smaller scope(Chip)Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope (Chip)There were enough instructions in the Ibuffer, but 2nd branch ends groupThere were enough instructions in the Ibuffer, but FPU OP IN same group after a branch terminates a group, cant do partial flushes Do not fill every slot in the group, Not enough instructions in the IbufferThere were enough instructions in the Ibuffer, but the group terminated early for some other reason, most likely due to a First or LastThere were enough instructions in the Ibuffer, but 3 src RA/RB/RC , 2 way crack caused a group terminationIc line invalidatedthreaded version, IC Misses where we got EA dir hit but no sector valids were onReloading line was brought in private for a specific threadCycles Instruction ERAT was reloadedIERAT Reloaded (Miss) for a 16M pageIERAT Miss (Not implemented as DI on POWER6)IERAT Reloaded (Miss) for a 64k pageCycles in which Instruction fetch throttle was activeL2 touch to update MRU on a line Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for an instruction fetchThe processor's Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a instruction fetchThe processor's Instruction cache was reloaded from local core's L2 with load hit store conflict due to a instruction fetchThe processor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to a instruction fetchThe processor's Instruction cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf stateThe processor's Instruction cache was reloaded from local core's L2 without conflict due to a instruction fetchThe processor's Instruction cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a instruction fetchThe processor's Instruction cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a instruction fetchThe processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to a instruction fetchThe processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf stateThe processor's Instruction cache was reloaded from a localtion other than the local core's L3 due to a instruction fetchThe processor's Instruction cache was reloaded from local core's L3 without conflict due to a instruction fetchThe processor's Instruction cache was reloaded from the local chip's L4 cache due to a instruction fetchThe processor's Instruction cache was reloaded from a memory location including L4 from local remote or distant due to a instruction fetchThe Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a different chip due to a instruction fetchThe processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a instruction fetchThe processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a instruction fetchInitial and Final Pump Scope and data sourced across this scope was group pump for an instruction fetchFinal Pump Scope to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope got data from source that was at smaller scope(Chip)Final Pump Scope to get data sourced, ended up larger than Initial Pump ScopePump prediction correctPump Mis prediction Counts across all types of pumpsfor an instruction fetchInitial and Final Pump Scope and data sourced across this scope was system pump for an instruction fetchFinal Pump Scope to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(system) got data from source that was at smaller scopeFinal Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for an instruction fetchA PTEG was loaded into the TLB with Modified data from another chip's L2 or L3 on a different Node or Group (Distant),due to a instruction side requestA PTEG was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), due to a instruction side requestA Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a instruction side requestA Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a instruction side requestA Page Table Entry was loaded into the TLB from local core's L2 due to a instruction side requestA Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a instruction side requestA Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a instruction side requestA Page Table Entry was loaded into the TLB from local core's L2 with load hit store conflict due to a instruction side requestA Page Table Entry was loaded into the TLB from local core's L2 with dispatch conflict due to a instruction side requestA Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf stateA Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a instruction side requestA Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a instruction side requestA Page Table Entry was loaded into the TLB from local core's L3 due to a instruction side requestA Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a instruction side requestA Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a instruction side requestA Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a instruction side requestA Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a instruction side requestA Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a instruction side requestA Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf stateA Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a instruction side requestA Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a instruction side requestA Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a instruction side requestA Page Table Entry was loaded into the TLB from the local chip's Memory due to a instruction side requestA Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a instruction side requestA PTEG was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip due to a instruction side requestA PTEG was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a instruction side requestA PTEG was loaded into the TLB with Modified data from another chip's L2 or L3 on the same Node or Group (Remote), due to a instruction side requestA PTEG was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), due to a instruction side requestA Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction side requestA Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a instruction side requestAll i-side dispatch attemptsAll i-side dispatch attempts that failed due to a addr collision with another machineAll i-side dispatch attempts that failed due to a reason other than addrs collisionvalid when first beat of data comes in for an i-side fetch where data came from mem(or L4)Iside L2 MRU touch FX0 ISU rejectLS0 ISU rejectLS1 ISU rejectLS2 ISU rejectLS3 ISU rejectISU reject due to resource not availableAll isu rejects could be more than 1 per cycleReject because of SAR bypassISU reject due to source not availableVS0 ISU reject VS1 ISU rejectIsync count per threadL1 data cache reloaded for demand or prefetch Counts all Icache reloads includes demand, prefetchm prefetch turned into demand and demand turned into prefetchCounts all Icache prefetch reloads ( includes demand turned into prefetch)L1 misses that took longer than 1024 cyles to resolve (miss to reload)L1 misses that took longer than 2048 cyles to resolve (miss to reload)L1 misses that took longer than 256 cyles to resolve (miss to reload)L1 misses that took longer than 32 cyles to resolve (miss to reload)valid when first beat of data comes in for an L1pref where data came from mem(or L4)RC requests that were local on chip pump attemptsAll successful Ld/St dispatches for this thread that were an L2missRC requests that were on Node Pump attemptsL2 guess grp and guess was correct (data intra-6chip AND ^on-chip)L2 guess grp and guess was not correct (ie data on-chip OR beyond-6chip)RC retries on PB for any load from coreRC retries on PB for any store from coreL2 guess sys and guess was correct (ie data beyond-6chip)L2 guess sys and guess was not correct (ie data ^beyond-6chip)TM abortTM marked store abortL3 Castins Hit (total countL3 castins miss (total countl3 ci of cache injectrotating sample of 16 CI or CO activesl3 castout occuring ( does not include casthrough or log writes (cinj/dmaw)lifetime, sample of CO machine 0 validL3 CO to L3Total L3 castouts occurred on LCOL3 CO to memory OR of port 0 and 1 ( lossy)L3 castouts in Mepf stateInitial scope=group and data from same group (near) (pred successful)Initial scope=group but data from local nodeInitial scope=group but data from outside group (far or rem)L2 castout hitsL2 castout missL3 Lateral Castins HitL3 Lateral Castins MissL3 Load Prefetchesinitial scope=node/chip and data from local node (local) (pred successful)Initial scope=node but data from out side local node (near or far or rem)l3 CO to L3l3 CO to memory port 0 L3 CO received retry port 0L3 pf sent with grp scope port 0lco sent with data port 0dataless l3 lco sent port 0L3 LCO received retry port 0L3 pf sent with nodal scope port 0L3 PF received retry port 0 L3 snoop hit port 0Port0 snooper detects someone doing a store to a line thats Sx L3 snoop miss port 0L3 pf sent with sys scope port 0l3 CO to L3l3 CO to memory port 1 L3 CO received retry port 1L3 pf sent with grp scope port 1lco sent with data port 1dataless l3 lco sent port 1L3 LCO received retry port 1L3 pf sent with nodal scope port 1L3 PF received retry port 1 L3 snoop hit port 1Port1 snooper detects someone doing a store to a line thats Sx L3 snoop miss port 1L3 pf sent with sys scope port 1lifetime, sample of PF machine 0 validl3 pf hit in l3L3 Prefetch missed in L3L3 Prefetch from Off chip cacheL3 Prefetch from Off chip memoryL3 Prefetch from On chip cacheL3 Prefetch from On chip memoryrotating sample of 32 PF activesTotal HW L3 prefetches(Load+store)lifetime, sample of RD machine 0 validrotating sample of 16 RD activeslifetime, sample of snooper machine 0 validrotating sample of 8 snoop validsL3 store PrefetchesData stream touchto L3Initial scope=system and data from outside group (far or rem)(pred successful) Initial scope=system but data from local or nearL3 Transient prefetchlifetime, sample of Write Inject machine 0 validrotating sample of 8 WI activesLarx finished Cycles L3 miss was pending for this thread LS2 L1 D cache load references counted at finish, gated by reject LS3 L1 D cache load references counted at finish, gated by rejectA flush were LS ptr is invalid, results in a pop , A lot of interrupts between push and popsLink stack predicts wrong address, because of link stack design limitationLS0 Erat miss due to prefetch LS0 L1 cache data prefetchesSoftware L1 Prefetches, including SW Transient PrefetchesLS1 Erat miss due to prefetch LS1 L1 cache data prefetchesSoftware L1 Prefetches, including SW Transient Prefetchesls0 l1 tm cam cancelLarx finished in LSU pipe0Primary ERAT hitls0 store reject addrs only req to L2 only on the first one,Indication that Load footprint is not expandingLoad tm hit in L1Load tm L1 missls1 l1 tm cam cancelLarx finished in LSU pipe1Primary ERAT hitls1 store reject addrs only req to L2 only on the first one,Indication that Load footprint is not expandingLoad tm hit in L1Load tm L1 missLS02Flush: LRQLS2 Flush: SRQLS3 Flush: Unaligned Loadls2 l1 tm cam cancelLarx finished in LSU pipe2LS2 Scalar LoadsLS0 Vector LoadsLS0 Load Merged with another cacheline requestPrimary ERAT hitLSU2 reject LS2 SRQ forwarded data to a load addrs only req to L2 only on the first one,Indication that Load footprint is not expandingLoad tm hit in L1Load tm L1 missLS3 Flush: LRQLS13 Flush: SRQLS 14Flush: Unaligned Loadls3 l1 tm cam cancelLarx finished in LSU pipe3LS3 Scalar Loads LS1 Vector LoadsLS1 Load Merge with another cacheline requestPrimary ERAT hitLSU3 reject LS3 SRQ forwarded data to a load addrs only req to L2 only on the first one,Indication that Load footprint is not expandingLoad tm hit in L1Load tm L1 missCycles when four tablewalks pending on this threadLSULRQ slot 43 validDERAT Reloaded (Miss)LSULRQ slot 39 validMemory castouts from this lparLocal Memory above threshold for IFU speculation controlLocal memory above threshold for LSU mediumLocal memory above theshold for data prefetchMemory prefetch for this lparReads from Memory from this lpar (includes data/inst/xlate/l1prefetch/inst prefetch)Memory rwitm for this lparMarked branch instruction completed with a target address less than current instruction addressBranch Instruction completedDuration in cycles to reload with Modified data from another chip's L2 or L3 on a different Node or Group (Distant),due to a marked loadDuration in cycles to reload with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), due to a marked loadThe processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a marked loadDuration in cycles to reload from another chip's L4 on a different Node or Group (Distant) due to a marked loadThe processor's data cache was reloaded from local core's L2 with load hit store conflict due to a marked loadDuration in cycles to reload from local core's L2 with load hit store conflict due to a marked loadThe processor's data cache was reloaded from local core's L2 with dispatch conflict due to a marked loadDuration in cycles to reload from local core's L2 with dispatch conflict due to a marked loadThe processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf stateDuration in cycles to reload from local core's L2 hit without dispatch conflicts on Mepf stateDuration in cycles to reload from a localtion other than the local core's L2 due to a marked loadThe processor's data cache was reloaded from local core's L2 without conflict due to a marked loadDuration in cycles to reload from local core's L2 without conflict due to a marked loadThe processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a marked loadDuration in cycles to reload with Modified (M) data from another core's ECO L3 on the same chip due to a marked loadThe processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a marked loadDuration in cycles to reload with Shared (S) data from another core's ECO L3 on the same chip due to a marked loadThe processor's data cache was reloaded from local core's L3 with dispatch conflict due to a marked loadDuration in cycles to reload from local core's L3 with dispatch conflict due to a marked loadThe processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf stateDuration in cycles to reload from local core's L3 without dispatch conflicts hit on Mepf stateDuration in cycles to reload from a localtion other than the local core's L3 due to a marked loadThe processor's data cache was reloaded from local core's L3 without conflict due to a marked loadDuration in cycles to reload from local core's L3 without conflict due to a marked loadThe processor's data cache was reloaded from the local chip's L4 cache due to a marked loadDuration in cycles to reload from the local chip's L4 cache due to a marked loadThe processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked loadDuration in cycles to reload from a memory location including L4 from local remote or distant due to a marked loadThe data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked loadDuration in cycles to reload either shared or modified data from another core's L2/L3 on a diff chip (remote or distant) due to a marked loadThe processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a marked loadDuration in cycles to reload either shared or modified data from another core's L2/L3 on the same chip due to a marked loadThe processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a marked loadDuration in cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked loadCombined Intervention eventA PTEG was loaded into the TLB with Modified data from another chip's L2 or L3 on a different Node or Group (Distant), due to a marked data side requestA PTEG was loaded into the TLB with Shared data from another chip's L2 or L3 on a different Node or Group (Distant), due to a marked data side requestA Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a marked data side requestA Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a marked data side requestA Page Table Entry was loaded into the TLB from local core's L2 due to a marked data side requestA Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a marked data side requestA Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a marked data side requestA Page Table Entry was loaded into the TLB from local core's L2 with load hit store conflict due to a marked data side requestA Page Table Entry was loaded into the TLB from local core's L2 with dispatch conflict due to a marked data side requestA Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf stateA Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a marked data side requestA Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a marked data side requestA Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side requestA Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a marked data side requestA Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a marked data side requestA Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a marked data side requestA Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a marked data side requestA Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a marked data side requestA Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf stateA Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a marked data side requestA Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a marked data side requestA Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a marked data side requestA Page Table Entry was loaded into the TLB from the local chip's Memory due to a marked data side requestA Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a marked data side requestA PTEG was loaded into the TLB from another core's L2/L3 on a different chip (remote or distant) due to a marked data side requestA PTEG was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a marked data side requestA PTEG was loaded into the TLB with Modified (M) data on the same Node or Group (Remote), as this chip due to a marked data side requestA PTEG was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), due to a marked data side requestA Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a marked data side requestA Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a marked data side requestMarked store had to do a bkillcycles L2 RC took for a bkillSampled store did a rwitm and got a rtyMarked store had to do a dclaimcycles L2 RC took for a dclaimttype and cresp matched as specified in MMCR1cresp/ttype match cyclesSampled L2 reads retry countSampled Read got a T interventioncycles L2 RC took for a rwitmSampled store did a rwitm and got a rtyMarked filter MatchMarked instruction Finish Stall cycles (marked finish after NTC) (use edge detect to count )Marked group ntc cyclesmarked instruction decodedMarked Instruction RC dispatched in L2Marked RC doneLarx finished Marked next to finish instruction finishedMarked run cyclesMarked src pref track was effectivePrefetch tracked was ineffective for marked srcPrefetch tracked was moderate for marked srcMarked src Prefetch Tracked was moderate (source L2)Prefetch tracked was moderate (L3 hit) for marked srccycles to drain st from core to L2Marked st forwardscycles from L2 rc disp to l2 rc completionMarked target pref track was effectivePrefetch tracked was ineffective for marked targetPrefetch tracked was moderate for marked targetMarked target Prefetch Tracked was moderate (source L2)Prefetch tracked was moderate (L3 hit) for marked targetmult marked instrCompletion time nested tendMultiply by 4 to obtain the number of PB cyclesDispatch time non favored tbeginnon tm snp rst tm scCycles after all instructions have finished to group completedCompletion time outer tbeginCompletion time outer tendTotal number of Prefetch Operations that were trackedPrefetch Tracked was effectivePrefetch tracked was ineffectivePrefetch tracked was moderatePrefetch Tracked was moderate (source L2)Prefetch tracked was moderate (L3)ProbeNops dispatchedPTE prefetchesPump prediction correctPump Mis prediction Counts across all types of pumpsfor all data types ( demand load,inst fetch,xlate (I or d)RC mach 0 BusyNumber of times a sampled RC machine was active for more than 256 cyclescontinuous 16 cycle(2to1) window where this signals rotates thru sampling each machine busyrd clearing scrd forming scrd machine hit l3 pf machineOut of real srq entriesCycles run latch is set and core is in SMT2 modecycles this threads run latch is set and the core is in SMT2 shared modeCycles run latch is set and core is in SMT2-split modecycles this threads run latch is set and the core is in SMT4 modeCycles run latch is set and core is in SMT8 modeCycles run latch is set and core is in ST modesecondary ERAT HitStore-Hit-Load Table Read Hit with entry EnabledStore-Hit-Load Table Read Hit with entry Disabled (entry was disabled due to the entry shown to not prevent the flush)SN mach 0 Busy snp tm st hit m musnp tm_st_hit t tn tecontinuous 16 cycle(2to1) window where this signals rotates thru sampling each machine busyCount ended because GCT went emptyNon TM St caused any thread to failSTCX executed reported at sent to nestStore forwards that finishedSWAP cancel , rtag not availableSWAP cancel , rtag not available for gprswap cast in completedswap cast in completed fpr gprMarked Branch and link branch that can cause a synchronous interruptMarked Branch mispredict that can cause a synchronous interruptMarked fixed point divide that can cause a synchronous interruptMarked L2 Hits that can throw a synchronous interruptMarked L2 Miss that can throw a synchronous interruptMarked L3 misses that can throw a synchronous interruptMarked probeNops which can cause synchronous interruptsInitial and Final Pump Scope and data sourced across this scope was system pump for all data types ( demand load,inst fetch,xlate (I or d)Final Pump Scope to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope got data from source that was at smaller scope(Chip/group)Final Pump Scopeto get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for all data types ( demand load,inst fetch,xlate (I or d)tablewalk qualified for pte prefetchesCompletion time tabortnoncd, tabortcd, treclaimTEND latency per threadcycles rebalance was activeThreshold counter did not meet thresholdtlbie finishedl3 tm cam overflow during L2 co of SCTM Footprint Capactiy OverflowTEXAS fail reason @ completionTEXAS fail reason @ completionTM fail disallowTEXAS fail reason @ completionNon transactional conflict from LSU whtver gets repoted to texasTEXAS fail reason @ completionTLBIE hit bloom filterTransactional conflict from LSU, whatever gets reported to texas TM Load (fav) caused another thread to failNon TM Ld caused any thread to failTM Load (fav or non-fav) ran into conflict (failed)tm snp rst tm scl3 castout tm Sc lineTM Store (fav or non-fav) caused another thread to failTM Store (fav or non-fav) ran into conflict (failed)Tm nested tbeginrun cycles in transactional stateInstructions completed in transactional stateTm resumeTm nested tendcycles spent in successful transactionsMicropartition prefetchMicrpartition pointer prefetchesCycles in which instruction issue throttle was active in ISUCryptographic instruction RFC02196 Issued64BIT Decimal IssuedDP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fnegDP vector version of fmadd,fnmadd,fmsub,fnmsubDP vector versions of fdiv,fsqrt 128BIT Decimal IssuedDirect move 32/64b VRFtoGPR RFC02206 IssuedPermute VMX Instruction IssuedDouble Precision scalar instruction issued on Pipe0Store Vector IssuedDouble Precision vector instruction issued on Pipe0Sixteen flops operation (SP vector versions of fdiv,fsqrt) Complex VMX instruction issuedCryptographic instruction RFC02196 IssuedDP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fnegDP vector version of fmadd,fnmadd,fmsub,fnmsubDP vector versions of fdiv,fsqrt Direct move 32/64b VRFtoGPR RFC02206 IssuedMove to/from FPSCR type instruction issued on Pipe 0Double Precision scalar instruction issued on Pipe1Simple VMX instruction issuedDouble Precision vector instruction issued on Pipe1Single Precision vector instruction issued (executed)Xxor instruction dispatched.one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation completedDP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg Count of amount of times the 2nd pass for HPT was initated. This doesn't include VA hash mispredicts.Count of amount of times the 2nd pass for Radix was initiated4 FLOP instruction completed8 FLOP instruction completedCycles in which all 12 entries of the BCQ are fullCount of amount of a times a valid translation reloaded the ERAT with block write enabled.BTAC predicts taken for a branch that the BHT predicts not taken, so that BTAC entry is invalidated.BTAC predicts a target that is different from what the BHT and count cache predict.A branch instruction finished. Includes predicted/mispredicted/unconditionalBranches that were issued with sources not ready (CR=0), counted at finish time.A conditional branch finished with mispredicted direction using the Global Branch History Table.A conditional branch finished with mispredicted direction using the Local Branch History Table selected with a global selector.A conditional branch finished with mispredicted direction using the Local Branch History Table selected by the local selector.A conditional branch finished with mispredicted direction using a TAGE override.A conditional branch finished with mispredicted direction using a TOP override to the BHT.A software hinted branch finished and the branch resolved taken and the hint was correct.A conditional branch finished with mispredicted direction using the Global Branch History Table.A conditional branch finished with mispredicted direction using the Local Branch History Table selected with a global selector.A conditional branch finished with mispredicted direction using the Local Branch History Table selected by the local selector.A conditional branch finished with mispredicted direction using a TAGE override.A conditional branch finished with mispredicted direction using a TOP override to the BHT.A conditional branch finished with mispredicted target using the global count cach.A conditional branch finished with mispredicted target using the local count cach.A conditional branch finished with mispredicted target using the count TIP override to the count cache.A software hinted branch finished and the branch resolved taken and the hint was correct.A conditional or unconditional branch finished with mispredicted target using the Link register.A conditional branch finished with correctly predited target or direction using the BTAC.A conditional branch finished with correctly predicted direction using the Global Branch History Table.A conditional branch finished with correctly predicted direction using the Local Branch History Table selected with a global selector.A conditional branch finished with correctly predicted direction using the Local Branch History Table selected by the local selector.A conditional branch finished with correctly predicted direction using a TAGE override.A conditional branch finished with correctly predicted direction using a TOP override to the BHT.A software hinted branch finished and the branch resolved taken and the hint was correct.A conditional branch finished with correctly predicted direction using the Global Branch History Table.A conditional branch finished with correctly predicted direction using the Local Branch History Table selected with a global selector.A conditional branch finished with correctly predicted direction using the Local Branch History Table selected by the local selector.A conditional branch finished with correctly predicted direction using a TAGE override.A conditional branch finished with correctly predicted direction using a TOP override to the BHT.A conditional branch finished with correctly predicted target using the global count cach.A conditional branch finished with correctly predicted target using the local count cach.A conditional branch finished with correctly predicted target using the count TIP override to the count cache.A software hinted branch finished and the branch resolved taken and the hint was correct.A conditional or unconditional branch finished with correctly predicted target using the Link register.A taken branch (conditional or unconditional) finishedAn unconditional branch finished.Counts the amount of times mtlpid instruction found a Case A Context Table Hit.Counts the amount of times mtpid instruction found a Case A Context Table Hit.Counts the amount of times a mtlpid instruction found a Case A Context table missCounts the amount of times a mtpid instruction found a Case A context table missCounts the amount of times a snoop hit on a Case A context tag.Counts the amount of times a mtlpid instruction found a Case B Context table hit.Counts the amount of times a mtlpid instruciton found a Case B Context table missCounts the amount of times a snoop hit on a Case B Context tag.Counts the amount of times a mtpid instruction found a Case C Context table hit.Counts the amount of times a mtpid instruction found a Case C Context table miss.Counts the amount of times a snoop hit on a Case C context tag.Counts the amount of times a snoop hit on a Case D context tag.Duration of time that the child purge was waiting to be arbitrated into the TLB.Counts the total amount of congruence classes that found at least 1 invalidation match for a child purge.Completion Stalled because the thread was blockedCycles in which the NTC instruction is not allowed to complete because it was interrupted by ANY exception, which has to be serviced before the instruction can completeFinish stall because the NTF instruction was a hwsync waiting for response from L2Cycles in which the NTC sync instruction is a lwsync waiting to be allowed to completeFinish stall while waiting for the non-speculative finish of either a stcx waiting for its result or a load waiting for non-critical sectors of data and ECCFinish stall because the NTF instruction required special handling before completionThe oldest instruction in the pipeline is a stcx waiting for resolution from the nest.This event increments at a rate of 64 MHzFinal Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for a demand loadA Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 data cache.A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 data cache.A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L3 data cache.A Page Directory Entry was reloaded to a level 2 page walk cache from a source beyond the core's chaches.A Page Table Entry was reloaded to a level 2 page walk cache from the core's L2 data cache.A Page Table Entry was reloaded to a level 2 page walk cache from the core's L2 data cache.A Page Table Entry was reloaded to a level 2 page walk cache from the core's L3 data cache.A Page Table Entry was reloaded to a level 2 page walk cache from a source beyond the core's chaches.A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 data cache.A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 data cache.A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L3 data cache.A Page Directory Entry was reloaded to a level 2 page walk cache from a source beyond the core's chaches.A Page Table Entry was reloaded to a level 3 page walk cache from the core's L2 data cache.A Page Table Entry was reloaded to a level 3 page walk cache from the core's L2 data cache.A Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 data cache.A Page Table Entry was reloaded to a level 3 page walk cache from a source beyond the core's chaches.A Page Table Entry was reloaded to a level 4 page walk cache from the core's L2 data cache.A Page Table Entry was reloaded to a level 4 page walk cache from the core's L2 data cache.A Page Table Entry was reloaded to a level 4 page walk cache from the core's L3 data cache.A Page Table Entry was reloaded to a level 4 page walk cache from a source beyond the core's chaches.Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller.A demand load referenced a line in an active prefetch stream.Prefetch stream allocated in the conservative phase by either the hardware prefetch mechanism or software prefetch.A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up)A demand load referenced a line in an active fuzzy prefetch stream.Prefetch stream allocated by the hardware prefetch mechanismStrided prefetch stream allocated by either the software or hardware mechanismsA demand load referenced a line in an active strided prefetch stream.Prefetch stream allocated by software prefetchingPrefetch stream allocated in the Ultra conservative phase by either the hardware prefetch mechanism or software prefetchA load reading the L1 cache has a bank collisions with another load reading or a reload/dkill writing the L1 cacheA store writing the L1 cache at the same time as a reload or dkill writing the L1 cache that results in a bank collision.counts a trigger generated from the debug logic for lab useCounts the number of cycles in which the IFU was not able to decode and transmit one or more instructions because all itags were in use.Number of times a load or store instruction missed the data cache and hit in the primary ERAT.DERAT Reloaded to satisfy a DERAT miss.Data ERAT Miss (Data TLB Access) page size 1G.Data ERAT Miss (Data TLB Access) page size 2M. Implies radix translation.DERAT miss (TLB access) while servicing a data prefetch.Dispatch/CLB Hold: Balance FlushDispatch Hold: waiting for the SRQ to be empty: TLBIE, SLBIEG, SLBIET, EIEIO, TLBSYNCCycles in which dispatch is held because the LRQ is full.Cycles in which dispatch is held because the SRQ is full.Branch Instruction completedNumber of dispatches in which the Instruction Sequencing Unit dispatches instructions at either half rate or quarter rate.Cycles in which Superslice 0 dispatches either 1 or 2 instructionsCycles in which Superslice 0 dispatches either 3 or 4 instructionsCycles in which Superslice 0 dispatches either 5, 6, 7 or 8 instructionsCycles in which Superslice 1 dispatches either 1 or 2 instructionsCycles in which Superslice 1 dispatches either 3 or 4 instructionsCycles in which Superslice 0 dispatches either 5, 6, 7 or 8 instructionsIct empty for this thread due to branch mispredThere are no instructions dispatched for this thread after a mispredicted branch also resulted in an instruction cache missDispatch was stalled while the instruction was fetched from the local L2 after suffering a branch mispredict.Dispatch was stalled while the instruction was fetched from the local L3 after suffering a branch mispredict.Dispatch was stalled while the instruction was fetched from sources beyond the local L3 after suffering a branch mispredict.Number of cycles the ICT has no itags assigned to this thread. No instructions have beend dispatched for this threadCycles in which there was nothing in the pipeline for this thread because Fetch was being heldCycles in which there were no instructions to dispatch because of a flush that happened to an instruction(s) that was not yet NTF.Cycles in which the NTC instruction is held at dispatch for any reasonDispatch held because of power managementDispatch held due to Issue q full.Dispatch Held for any other reasonDispatch held because the mapper/SRB was full.Cycles in which dispatch is held while waiting on the Scoreboard.Dispatch held because the STF mapper/SRB was full.Cycles in which dispatch is held because of a synchronizing instruction that requires the ICT to be empty before dispatchDispatch held because the XVFC mapper/SRB was fullDispatch was stalled while the instruction was fetched from the local L2.Dispatch was stalled while the instruction was fetched from the local L3.Dispatch was stalled while the instruction was fetched from any source beyond the local L3.Ict empty for this thread due to Icache MissDispatch was stalled waiting to resolve an instruction ERAT missDispatch was stalled waiting to resolve an instruction TLB missNumber of cycles in which instruction cannot be dispatched for this thread because the MMU is handling a translation miss.Double-Precion or Quad-Precision instruction completedNumber of times the TLB was read to satisfy a load or store ERAT miss.Number of times the PTE required by the instruction was resident in the TLB (data TLB access).Data TLB Miss page size 16G.Data TLB reload (after a miss) page size 16M.Data TLB reload (after a miss) page size 1G.Data ERAT Miss (Data TLB Access) page size 2M.Data TLB reload (after a miss) page size 4K.Data TLB reload (after a miss) page size 64K.Data TLB reload (after a miss) page size 1G.Data TLB reload (after a miss) page size 2M.Cycles in which MSR[EE] is off and external interrupts are activeDuration of time that the EMB was waiting to be arbitrated into the TLB.Cycles in which the ERAT miss buffer is full. When the ERAT miss buffer is full the operation will go to the TIQNumber of cycles when the oldest instruction in the pipeline is waiting to be finished in one of the execution units (BRU, LSU, VSU).The oldest instruction in the pipeline is executing in the Branch unitThe oldest instruction in the pipeline suffered a TLB miss.Finish stall because the NTF instruction was a load or store that suffered a translation missCycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from a neighbor chiplet's L2 or L3 in the same chip.Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from either the local L2 or local L3Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from either the local L2 or local L3, with an RC dispatch conflictCycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from either the local L2 or local L3, without an RC dispatch conflictCycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from a source beyond the local L2 and local L3Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from local memory, L4 or OpenCapp chipCycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from a remote chip (cache, L4, memory or CAPP) in the same groupCycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from a distant chip (cache, L4, memory or CAPP chip)The oldest instruction in the pipeline was one that finishes at dispatch and doesn't require execution in LSU, BRU or VSUFinish stall due to load. The oldest instruction in the pipeline was an exposed loadCycles in which the NTF instruction is finishing a load after its data has been reloaded from a data source beyond the local L1The oldest instruction in the pipeline is executing in the Load Store UnitCycles spent executing an NTC instruction that gets flushed some time after dispatch.The oldest instruction in the pipeline is executing a simple fixed point instruction in the Load Store UnitFinish stall because the NTF instruction was a storeFinish stall because the next to finish instruction was a store whose cache line was not resident in the L1 and had to wait for allocation of the missing line into the L1Cycles spent by the oldest instruction in the store unit outside of handling store misses or other special store operationsFinish stall because the NTF instruction was a tlbie waiting for response from L2The oldest instruction in the pipeline is executing a TLBIEL instruction.Finish stall due to LRQ miscellaneous reasons, lost arbitration to LMQ slot, bank collisions, set prediction cleanup, set prediction multihit and othersThe oldest instructio in the pipeline is executing in the VSU. Includes FXU, VSU, CRUExternal interrupt due to Event Based Branch. This means the PMU interrupt is being handled by user code.External interrupt initiated by the HypervisorExternal interrupt initiated by the OSFalse LHS match detected. Load and store have a partial EA match but they are actually independent of each other.Cycles in which instructions are successfully fetched from the I-cacheFloating Point Operations CompletedA flush occurred due to a mispredicted branch.two flops operation completed (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only.bl instruction dispatched. Only one reported per cycle.blr instruction dispatched. Only one reported per cycle.Back to back two-cycle execution. Counted at decode timeThe first and second instruction have the same target register.Compare load data with immediate - ldx r3,r1,r2Two PPCs: the first in age order is the result of the second PPC.Produce 2 results together - fabs f3,f1The VSU was issued a fixed point instruction.Simple fixed point instruction issued to the store unit.A bus operation was sent as a system pump and group pump was the accurate scope.Data Tablewalk Cycles.Cycles when an instruction tablewalk is active. This is qualified for HPT translations.3Hierarchical TLB found parent entry but child entry was not found in the TLB. 2-level TLB, second level missCycles in which msr_hv is high and msr_pr is low.Duration of time that the ICL was waiting to be arbitrated into the TLB.Non-speculative icache miss, counted at completionNumber of times an instruction fetch missed in the I-cache and hit in the primary ERAT.IERAT Miss (Instruction TLB Access) page size 1G. Implies radix translationIERAT Miss (Instruction TLB Access) page size 2M. Implies radix translationInstructions finishedFinal Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for an instruction fetch (demand only)A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 data cache.A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 data cache.A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L3 data cache.A Page Directory Entry was reloaded to a level 2 page walk cache from a source beyond the core's chaches.A Page Table Entry was reloaded to a level 2 page walk cache from the core's L2 data cache.A Page Table Entry was reloaded to a level 2 page walk cache from the core's L2 data cache.A Page Table Entry was reloaded to a level 2 page walk cache from the core's L3 data cache.A Page Table Entry was reloaded to a level 2 page walk cache from a source beyond the core's chaches.A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 data cache.A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 data cache.A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L3 data cache.A Page Directory Entry was reloaded to a level 2 page walk cache from a source beyond the core's chaches.A Page Table Entry was reloaded to a level 3 page walk cache from the core's L2 data cache.A Page Table Entry was reloaded to a level 3 page walk cache from the core's L2 data cache.A Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 data cache.A Page Table Entry was reloaded to a level 3 page walk cache from a source beyond the core's chaches.A Page Table Entry was reloaded to a level 4 page walk cache from the core's L2 data cache.A Page Table Entry was reloaded to a level 4 page walk cache from the core's L2 data cache.A Page Table Entry was reloaded to a level 4 page walk cache from the core's L3 data cache.A Page Table Entry was reloaded to a level 4 page walk cache from a source beyond the core's chaches.Final Pump Scope (system) mispredicted.Internal doorbell interrupt All I-side-instruction-fetch dispatch attempts for this thread All I-side-instruction-fetch dispatch attempts for this thread that failed due to an address collision conflict with an L2 machine already working on this line (e.g. ld-hit-stq or RC/CO/SN machines) All I-side-instruction-fetch dispatch attempts for this thread that failed due to reasons other than an address collision conflict with an L2 machine (e.g. no available RC/CO machines)An instruction issued and the issue was later cancelled.The ISU attempted to issue an instruction and encountered a resource collision in any unit.Cycles in which one or more instructions are being held at issue while waiting for Load tags to become available.Cycles in which one or more instructions are being held at issue while waiting for Store tags to become available.Number of cycles in which an instruction or group of instructions was primed to issue but was killed before being written.An instruction was primed to issue but was killed before being written because one of the sources takes a data load miss.An instruction was primed to issue but was killed before being written because either the instruction was flushedAn instruction was primed to issue but was killed before being written because a resource is unavailable.An instruction was primed to issue but was killed before being written because power throttling was enabledThe oldest instruction in the pipeline has been dispatched but not yet issued.All flushes initiated by the Instruction Sequencing Unit (ISU)A balance flush occurred. Balance flushes are triggered whenn excessive L3 or TLB misses occurDispatch flushes occur when one thread is causing other threads to stallDispatch Flush while waiting for the SRQ to be empty: TLBIE, SLBIEG, SLBIET, EIEIO, TLBSYNCThe Sliced Target File (STF) is the regfile for GPR/VSRs/LR/CTR/TAR.A flush to a hwsync instruction that had trouble.A flush to an isync instruction that had trouble.A load instruction that accessed early data from memory and finished speculatively before the ECC was returned, gets flushed because of a later ECC errorA flush to a lwsync instruction that had trouble.IF the MMA engine is off when an MMA instruction is issued, the instruction will issue and finish as a nop.A flush occurred only to the odd itag of a pair.Isync completion count per threadNumber of times the TLB was read to satisfy an instruction ERAT miss.Number of times the PTE required to translate the instruction address was resident in the TLB (instruction TLB access).Instruction TLB reload (after a miss) page size 16G.Instruction TLB reload (after a miss) page size 16M.Instruction TLB reload (after a miss) page size 1G, which implies Radix Page Table translation is in use.Instruction TLB reload (after a miss) page size 2M, which implies Radix Page Table translation is use.Instruction TLB reload (after a miss) page size 4K.Instruction TLB reload (after a miss) page size 64K.Instruction TLB reload (after a miss) page size 16G.Instruction TLB reload (after a miss) page size 16M.Instruction TLB reload (after a miss) page size 1G, which implies Radix Page Table translation is in use.Instruction TLB reload (after a miss) page size 2M, which implies Radix Page Table translation is use.Instruction TLB reload (after a miss) page size 4K.Instruction TLB reload (after a miss) page size 64K.Software L1 Prefetches, including SW Transient PrefetchesAll successful instruction and data load and store (demand and prefetch) dispatches for this thread that missed in the L2CO mach 0 Busy. Used by PMU to sample ave CO lifetime (mach0 used as sample point)CO cache read requestL2 did a cleanifdirty CO to the L3 (ie created an SC line in the L3) OR L2 TM_store hit dirty HPC line and L3 indicated SC line formed in L3 on RDR busContinuous 16 cycle (2to1) window where this signals rotates thru sampling each CO machine busy. D-side L2 MRU touch commands sent to the L2Valid when first beat of data comes in for an d-side fetch where data came exclusively from mem(or L4)(ie total memory accesses by RCs) All successful D-side-Ld or I-side-instruction-fetch dispatches for this thread All D-side-Ld or I-side-instruction-fetch dispatch attempts for this thread All D-side-Ld or I-side-instruction-fetch dispatch attempts for this thread that failed due to an address collision conflicts with an L2 machine already working on this line (e.g. ld-hit-stq or Read-claim/Castout/Snoop machines) All D-side-Ld or I-side-instruction-fetch dispatch attempts for this thread that failed due to reasons other than an address collision conflicts with an L2 machine (e.g. Read-Claim/Snoop machine not available) All successful D-side-Ld or I-side-instruction-fetch dispatches for this thread that were L2 hits All D-side-Ld, D-side-St or I-side-instruction-fetch dispatch attempts for this thread All D-side-Ld, D-side-St or I-side-instruction-fetch successful dispatches for this threadI-side L2 MRU touch commands sent to the L2 for this threadValid when first beat of data comes in for an I-side fetch where data came from memory or L4Valid when first beat of data comes in for an L1PF where data came from memory or L4Non-TM Load caused any thread to failRC mach 0 Busy. Used by PMU to sample ave RC lifetime (mach0 used as sample point)RC cache read request Continuous 16 cycle (2to1) window where this signals rotates thru sampling each RC machine busy.SN mach 0 Busy. Used by PMU to sample ave SN lifetime (mach0 used as sample point)Number of cycles that a TLBIE/SLBIE snooper was in flight while in a hottemp condition.The NCU Snooper PowerBus initiated a Snoop TLBIE/SLBIE command to the core after receiving an ack combined responseContinuous 16 cycle (2to1) window where this signals rotates thru sampling each SN machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs runningTtotal number of store ops(st, stqw, stcx, stcxfk, stcxfnk, dcbz).All D-side store dispatch attempts for this threadNon-TM Store caused a TM transaction in any thread to failAll D-side store dispatch attempts for this thread that failed due to address collision with L2 machine already working on this lineAll D-side store dispatch attempts for this thread that failed due to reason other than address collisionTtotal number of store ops that gathered that can include (st, stqw) Note: stcx, stcxfk, stcxfnk, dcbz won’t ever gather).Number of cycles that a TLBIE/SLBIE command was held in a hottemp condition by the NCU Master.NCU Master PowerBus initiated a TLBIE or SLBIE operation that got a cresp=ackTotal number of TM transactions, including passing and failing ones.Total number of Load Footprint cachelines formed.One TM thread was running and Load footprint was lost due to capacity Cast Out or full TMDIR/LVDIRMultiple TM threads were running and Load footprint was lost due to capacity Cast Out or full TMDIR/LVDIROne TM thread was running and Store footprint was lost due to capacity Cast Out or full TMDIR/LVDIRMultiple TM threads were running and Store footprint was lost due to capacity Cast Out or full TMDIR/LVDIRTM count of total Store Footprint Cachelines formed. Divide this by PM_L2_TM_END to get average Store footprint size.Duration of time that the L3 Prefetch was waiting to be arbitrated into the TLB.L3 cast out an instruction or translation line to a neighbor L3 (LCO)L3 CO received retry port 2 (memory only), every retry countedL3 initiated LCO received retry on port 2 (can try 4 times)L3 PF received retry port 2, every retry countedL3 CO received retry port 3 (memory only), every retry countedL3 initiated LCO received retry on port 3 (can try 4 times)L3 PF received retry port 3, every retry countedL3 prefetch request predicted dual MC data and LPC responded (good prediction)L3 prefetch request predicted dual MC data but a cache responded (bad prediction)New entry added to the Larx-hit-larx tableLarx-hit-larx table read hit with entry enabled128 bit load finshed256 bit load finished64 bit or smaller load finishedThe real address of a load matched the real address of an earlier store and it is not possible to store forward because not all bytes required by the load are available on the store entry that was hit.Load instructions whose data crosses a cache-line boundary, which causes it to require an additional recycle to the pipeline.Any vector load operation finished. Excludes load quad, larx quad, fused load double, load float double pair128 bit load finshed256 bit load finished64 bit or smaller load finished The real address of a load matched the real address of an earlier store and it is not possible to store forward because not all bytes required by the load are available on the store entry that was hit.Load instructions whose data crosses a cache-line boundary, which causes it to require an additional recycle to the pipeline.Any vector load operation finished. Excludes load quad, larx quad, fused load double, load float double pairA data line was brought in from the nest to fulfill a request initiated by a non-cacheable load instruction.The L1 cache was reloaded with a line that fulffills a demand miss request. Counted at reload time, before finish.Load Missed L1, counted at finish timeThe L1 cache was reloaded with a line that fulffills a prefetch requestLSU Reject due to LMQ full (up to 4 per cycles)Internal LSU reject from LRQ. Rejects cause the load to go back to LRQ, but it stays contained within the LSU once it gets issued.New entry added to the Load-hit-store tableLoad-hit-store table read hit with entry enabledCounts the amount of times a snoop found a Non-speculative stores have locked all ways in the data cache and a newly-issued older store is not able to alocate a way for a given congruence class.Load was not issued to LSU as a cache inhibited (non-cacheable) load but it was later determined to be cache inhibitedA larx is flushed because an older larx has an LMQ reservation for the same thread.If a load hits on an older load of the same address that has been snooped, or 2 loads of the same thread and address execute out of order and a store of another thread occurs to that address, the younger load will be flushed.Effective Address alias flush : no EA match but Real Address match.Other LSU flushes including: Sync (sync ack from L2 caused search of LRQ for oldest snooped load, This will either signal a Precise Flush of the oldest snooped loa or a Flush Next PPC)This flush happens if an ICT pair contains a store followed by a load to the same address with at least one byte of overlap between the two.A load-hit-load condition with Strong Address Ordering will have address compare disabled and flushThe instruction was flushed because of a sequential load/store consistency.LSU workaround flush.LSU Finished a PPC instruction in LD0 portLSU Finished a PPC instruction in LD1 portLSU Finished a PPC instruction in ST0 portLSU Finished a PPC instruction in ST1 portLSU Finished a PPC instruction in ST2 portLSU Finished a PPC instruction in ST3 portLSU Finished a PPC instruction in ST4 portLSU Finished a PPC instruction in ST2 portMath flop instruction completedAn MMA instruction references an ACC that has not been primed.Cycles in which the MMA engine is actively being used by this threadMMA instruction issued to the VSUCycles in which this core's MMA engine is availableA VSR operation references an ACC that has been primed.A conditional branch finished with mispredicted direction using.A conditional branch finished with mispredicted direction using.A conditional branch finished with mispredicted target and direction using.Duration in cycles to reload a line from the source specified in MMCR3[0:10].Duration in cycles to reload a line from the source specified in MMCR3[0:10].Duration in cycles to reload a line from the source specified in MMCR3[0:10].Duration in cycles to reload a line from the source specified in MMCR3[0:10].For a marked demand load that was later flushed, the processor's L1 data cache was reloaded from the source specified in MMCR3[0:10]For a marked demand load that was later flushed, the processor's L1 data cache was reloaded from the source specified in MMCR3[0:10]For a marked demand load that was later flushed, the processor's L1 data cache was reloaded from the source specified in MMCR3[0:10]For a marked demand load that was later flushed, the processor's L1 data cache was reloaded from the source specified in MMCR3[0:10]The marked instruction was a load that merged with another in the Load Miss Queue (LMQ).The marked instruction was a load that merged with another in the Load Miss Queue (LMQ).Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a demand loadFinal Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for a demand loadData ERAT Miss (Data TLB Access) page size 1G for a marked instruction.Data ERAT Miss (Data TLB Access) page size 2M for a marked instruction.The marked instruction was a decimal floating point op issued to the VSU.Number of marked instructions that required a data tablewalkNumber of cycles a data tablewalk is in progress for a marked instruction.Marked Data TLB reload (after a miss) page size 1G. Implies radix translation was used.Marked Data TLB reload (after a miss) page size 2M, which implies Radix Page Table translation was used.The marked instruction was a fixed point op issued to the VSU.The marked instruction was simple fixed point that was issued to the store unit.Final Pump Scope (group) ended up larger than Initial Pump Scope (chip).An instruction was marked. Includes both Random Instruction Sampling (RIS) at decode time and Random Event Sampling (RES) at the time the configured event happensThe marked instruction was flushedThe marked instruction was dependent on a load.TM abortEither a marked MMA instruction references an ACC that has not been primed or a marked VFR operation references an ACC that has been primedThe marked instruction was flushed after becoming NTCCycles during which the marked instruction is the oldest in the pipeline (NTF or NTC)Ptesync latency from the cycle the instruction becomes NTC until it completes in the nestPump misprediction. Counts across all types of pumps for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)Marked Start probe nop completed.Marked Start probe nop dispatched.Cycles spent in the core portion of a marked Stcx instruction.Number of marked stcx instructions finished. This includes instructions in the speculative path of a branch that may be flushedCycles spent in the nest portion of a marked Stcx instruction.A stop probe nop was marked at dispatch.marked store completed in L2 ( RC machine done)cycles to drain st from core to L2The marked instruction was a store of any kind.cycles from L2 rc disp to l2 rc completionFinal Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)Nested or not nested tend failed for a marked tend instructionLatency of TLBIE instructions from the cycle they become NTC until they complete in the nestMarked Tlbie instructions finished.Duration in cycles to reload a line from the source specified in MMCR3[0:10].The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to a demand loadDuration in cycles to reload a line from the source specified in MMCR3[26:36].Duration in cycles to reload a line from the source specified in MMCR3[39:49].For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[0:10].The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to a demand loadFor a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[26:36].For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[39:49].Counts the amount of times the thread executed a mtlpid instruction.Counts the amount of times the thread executed a mtpid instruction.Asserts when a i=1 store op is sent to the nest.Total number of cycles in which the NCU had a TLBIE snoop in flight to core.Non FMA instruction completedNon FLOP operation completedCycles in which no instructions are fetched because of an interleave conflict.Cycles in which no instructions were fetched by the Instruction Fetch Unit (IFU), for any reasonCycles No room in EATCycles in which no instructions are fetched because of an interleave conflict.Cycles in which no instructions are fetched for this thread because it is being throttledCycles in which the thread is throttled because of dynamic priorityCycles in which the thread is throttled for a reason other than power management, relative priority and dynamic priorityCycles in which the thread is throttled because of power managementCycles in which the thread is throttled because of relative priorityNumber of cycles in which both instructions in the ICT entry pair show as finished.Cycles in which the oldest instruction in the pipeline (NTC) finishes. Note that instructions can finish out of order, therefore not all the instructions that finish have a Next-to-complete status.Number of cycles in which the oldest instruction in the pipeline is being held at issue.Number of times the TLB was read to satisfy an L1-prefetch ERAT miss.PMC1 Rewind Value savedPMC3 rewind event.PMC3 Rewind Value savedA conditional branch finished with correctly predicted direction using.A conditional branch finished with correctly predicted direction using.A conditional branch finished with correctly predicted target and direction using.Count every cycle that the thread is throttled (resources are assigned to a different thread based on its priority)Cycles in which the thread is in Privileged state.Ptesync instruction finished in the store unit.Qualified as nested radix translations. There was a Parent Hit, but child miss on any intermediate TLB lookup.Qualified as nested radix translations. There was a Parent Hit, Child L3 PWC hit in any intermediate TLB lookup.Qualified as nested radix translations. There was a Parent Hit, but child miss on an intermediate TLB lookup for the final gRA.Qualified as nested radix translations. There was a Parent Hit, Child L3 PWC hit in an intermediate TLB lookup for the final gRA.Qualified as nested radix translations. There was a hit on the Parent, but a miss in the Child TLBQualified as nested radix translations. There was a hit on the Parent and a L3 PWC hit on the child, but a TLB miss.Qualified as nested radix translations. There was a Parent Hit, but child miss on an intermediate TLB lookup for the level 1 gRA.Qualified as nested radix translations. There was a Parent Hit, Child L3 PWC hit in an intermediate TLB lookup for the level 1 gRA.Qualified as nested radix translations. There was a Parent Hit, but child miss on an intermediate TLB lookup for the level 2 gRA.Qualified as nested radix translations. There was a Parent Hit, Child L3 PWC hit in an intermediate TLB lookup for the level 2 gRA.Qualified as nested radix translations. There was a Parent Hit, but child miss on an intermediate TLB lookup for the level 3 gRA.Qualified as nested radix translations. There was a Parent Hit, Child L3 PWC hit in an intermediate TLB lookup for the level 3 gRA.Qualified as nested radix translations. There was a Parent Hit, but child miss on an intermediate TLB lookup for the level 4 gRA.Qualified as nested radix translations. There was a Parent Hit, Child L3 PWC hit in an intermediate TLB lookup for the level 4 gRA.Qualified as nested radix translations. There was a Parent Hit, but child miss on an intermediate TLB lookup for the process table entry gRA.Qualified as nested radix translations. There was a Parent Hit, Child L3 PWC hit in an intermediate TLB lookup for the process table entry gRA.Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup w/ the 1G page size.Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup w/ the 2M page size.Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup w/ the 4K page size.Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup w/ the 64K page size.Qualified as nested radix translations. There was a TLB lookup for any nested radix partition scoped translation.Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup.Qualified as nested radix translations. There was a complete TLB miss on any intermediate TLB lookup.Qualified as nested radix translations. There was a TLB hit on an intermediate TLB lookup w/ the 1G page size for the final gRA.Qualified as nested radix translations. There was a TLB hit on an intermediate TLB lookup w/ the 2M page size for the final gRA.Qualified as nested radix translations. There was a TLB hit on an intermediate TLB lookup w/ the 4K page size for the final gRA.Qualified as nested radix translations. There was a TLB hit on an intermediate TLB lookup w/ the 64K page size for the final gRA.Qualified as nested radix translations. There was a TLB lookup for a nested radix partition scoped translation but only for the final gRA .Qualified as nested radix translations. There was a TLB hit on a intermediate TLB lookup for the final gRA.Qualified as nested radix translations. There was a complete TLB miss on an intermediate TLB lookup for the final gRA.Qualified as nested radix translations. There was a TLB hit on an intermediate TLB lookup w/ the 1G page size for the level 1 gRA.Qualified as nested radix translations. There was a TLB hit on an intermediate TLB lookup w/ the 2M page size for the level 1 gRA.Qualified as nested radix translations. There was a TLB hit on an intermediate TLB lookup w/ the 4K page size for the level 1 gRA.Qualified as nested radix translations. There was a TLB hit on an intermediate TLB lookup w/ the 64K page size for the level 1 gRA.Qualified as nested radix translations. There was a TLB lookup for a nested radix partition scoped translation but only for the level 1 gRA .Qualified as nested radix translations. There was a TLB hit on a intermediate TLB lookup for the level 1 gRA.Qualified as nested radix translations. There was a complete TLB miss on an intermediate TLB lookup for the level 1 gRA.Qualified as nested radix translations. There was a TLB hit on an intermediate TLB lookup w/ the 1G page size for the level 2 gRA.Qualified as nested radix translations. There was a TLB hit on an intermediate TLB lookup w/ the 2M page size for the level 2 gRA.Qualified as nested radix translations. There was a TLB hit on an intermediate TLB lookup w/ the 4K page size for the level 2 gRA.Qualified as nested radix translations. There was a TLB hit on an intermediate TLB lookup w/ the 64K page size for the level 2 gRA.Qualified as nested radix translations. There was a TLB lookup for a nested radix partition scoped translation but only for the level 2 gRA .Qualified as nested radix translations. There was a TLB hit on a intermediate TLB lookup for the level 2 gRA.Qualified as nested radix translations. There was a complete TLB miss on an intermediate TLB lookup for the level 1 gRA.Qualified as nested radix translations. There was a TLB hit on an intermediate TLB lookup w/ the 1G page size for the level 3 gRA.Qualified as nested radix translations. There was a TLB hit on an intermediate TLB lookup w/ the 2M page size for the level 3 gRA.Qualified as nested radix translations. There was a TLB hit on an intermediate TLB lookup w/ the 4K page size for the level 3 gRA.Qualified as nested radix translations. There was a TLB hit on an intermediate TLB lookup w/ the 64K page size for the level 3 gRA.Qualified as nested radix translations. There was a TLB lookup for a nested radix partition scoped translation but only for the level 3 gRA .Qualified as nested radix translations. There was a TLB hit on a intermediate TLB lookup for the level 3 gRA.Qualified as nested radix translations. There was a complete TLB miss on an intermediate TLB lookup for the level 3 gRA.Qualified as nested radix translations. There was a TLB hit on an intermediate TLB lookup w/ the 1G page size for the level 4 gRA.Qualified as nested radix translations. There was a TLB hit on an intermediate TLB lookup w/ the 2M page size for the level 4 gRA.Qualified as nested radix translations. There was a TLB hit on an intermediate TLB lookup w/ the 4K page size for the level 4 gRA.Qualified as nested radix translations. There was a TLB hit on an intermediate TLB lookup w/ the 64K page size for the level 4 gRA.Qualified as nested radix translations. There was a TLB lookup for a nested radix partition scoped translation but only for the level 4 gRA .Qualified as nested radix translations. There was a TLB hit on a intermediate TLB lookup for the level 4 gRA.Qualified as nested radix translations. There was a complete TLB miss on an intermediate TLB lookup for the level 4 gRA.Qualified as nested radix translations. There was a TLB hit on an intermediate TLB lookup w/ the 1G page size for the process table entry gRA.Qualified as nested radix translations. There was a TLB hit on an intermediate TLB lookup w/ the 2M page size for the process table entry gRA.Qualified as nested radix translations. There was a TLB hit on any intermediate TLB lookup w/ the 4K page size.Qualified as nested radix translations. There was a TLB hit on an intermediate TLB lookup w/ the 64K page size for the process table entry gRA.Qualified as nested radix translations. There was a TLB lookup for a nested radix partition scoped translation but only for the process table entry gRA .Qualified as nested radix translations. There was a TLB hit on a intermediate TLB lookup for process table entry gRA.Qualified as nested radix translations. There was a complete TLB miss on an intermediate TLB lookup for the process table entry gRA.Duration of nested radix table walk for any guest level and any host level (not including outer-walk of guest memory accesses)Duration of nested radix table walk for any guest level and any host level (including outer-walk of guest memory accesses)Duration of nested radix table walk for any guest level, but limited to duration only in Level 1 host memory accesses and TLB/PWC reloadDuration of nested radix table walk for any guest level, but limited to duration only in Level 2 host memory accesses and TLB/PWC reloadDuration of nested radix table walk for any guest level, but limited to duration only in Level 3 host memory accesses and TLB/PWC reloadDuration of nested radix table walk for any guest level, but limited to duration only in Level 4 host memory accesses and TLB/PWC reloadDuration of nested radix table walk for any guest level, but limited to duration only of memory access & TLB/PWC reload of the guest entryDuration of nested table walk for any guest level looking up TLB (including outer-walk of guest memory accesses)Data Tablewalk Cycles.Duration of nested radix table walk for Level 4 guest translation and any host levelDuration of nested radix table walk for final guest translation and any host levelDuration of nested radix table walk for final guest translation, but limited to duration only in Level 1 host memory accesses and TLB/PWC reloadDuration of nested radix table walk for final guest translation, but limited to duration only in Level 2 host memory accesses and TLB/PWC reloadDuration of nested radix table walk for final guest translation, but limited to duration only in Level 3 host memory accesses and TLB/PWC reloadDuration of nested radix table walk for final guest translation, but limited to duration only in Level 4 host memory accesses and TLB/PWC reloadDuration of nested radix table walk for final guest translation looking up TLBCycles when an instruction tablewalk is active.Duration of nested radixtable walk for Level 1 guest translation and any host levelDuration of nested radixtable walk for Level 1 guest translation and any host levelDuration of nested radix table walk for Level 1 guest translation, but limited to duration only in Level 1 host memory accesses and TLB/PWC reloadDuration of nested radix table walk for Level 1 guest translation, but limited to duration only in Level 2 host memory accesses and TLB/PWC reloadDuration of nested radix table walk for Level 1 guest translation, but limited to duration only in Level 3 host memory accesses and TLB/PWC reloadDuration of nested radix table walk for Level 1 guest translation, but limited to duration only in Level 4 host memory accesses and TLB/PWC reloadDuration of nested radix table walk for Level 1 guest translation, but limited to duration only of memory access & TLB/PWC reload of the guest entryDuration of nested radix table walk for Level 1 guest translation looking up TLBDuration of nested radix table walk for Level 2 guest translation and any host levelDuration of nested radix table walk for Level 2 guest translation and any host levelDuration of nested radix table walk for Level 2 guest translation, but limited to duration only in Level 1 host memory accesses and TLB/PWC reloadDuration of nested radix table walk for Level 2 guest translation, but limited to duration only in Level 2 host memory accesses and TLB/PWC reloadDuration of nested radix table walk for Level 2 guest translation, but limited to duration only in Level 3 host memory accesses and TLB/PWC reloadDuration of nested radix table walk for Level 2 guest translation, but limited to duration only in Level 4 host memory accesses and TLB/PWC reloadDuration of nested radix table walk for Level 2 guest translation, but limited to duration only of memory access & TLB/PWC reload of the guest entryDuration of nested radix table walk for Level 2 guest translation looking up TLBDuration of nested radix table walk for Level 3 guest translation and any host levelDuration of nested radix table walk for Level 3 guest translation and any host levelDuration of nested radix table walk for Level 3 guest translation, but limited to duration only in Level 1 host memory accesses and TLB/PWC reloadDuration of nested radix table walk for Level 3 guest translation, but limited to duration only in Level 2 host memory accesses and TLB/PWC reloadDuration of nested radix table walk for Level 3 guest translation, but limited to duration only in Level 3 host memory accesses and TLB/PWC reloadDuration of nested radix table walk for Level 3 guest translation, but limited to duration only in Level 4 host memory accesses and TLB/PWC reloadDuration of nested radix table walk for Level 3 guest translation, but limited to duration only of memory access & TLB/PWC reload of the guest entryDuration of nested radix table walk for Level 3 guest translation looking up TLBDuration of nested radix table walk for Level 4 guest translation and any host levelDuration of nested radix table walk for Level 4 guest translation and any host levelDuration of nested radix table walk for Level 4 guest translation, but limited to duration only in Level 1 host memory accesses and TLB/PWC reloadDuration of nested radix table walk for Level 4 guest translation, but limited to duration only in Level 2 host memory accesses and TLB/PWC reloadDuration of nested radix table walk for Level 4 guest translation, but limited to duration only in Level 3 host memory accesses and TLB/PWC reloadDuration of nested radix table walk for Level 4 guest translation, but limited to duration only in Level 4 host memory accesses and TLB/PWC reloadDuration of nested radix table walk for Level 4 guest translation, but limited to duration only of memory access & TLB/PWC reload of the guest entryDuration of nested radix table walk for Level 4 guest translation looking up TLBDuration of nested radix table walk for guest process table entry translation and any host levelDuration of nested radix table walk for guest process table entry translation and any host levelDuration of nested radix table walk for guest process table entry translation, but limited to duration only in Level 1 host memory accesses and TLB/PWC reloadDuration of nested radix table walk for guest process table entry translation, but limited to duration only in Level 2 host memory accesses and TLB/PWC reloadDuration of nested radix table walk for guest process table entry translation, but limited to duration only in Level 3 host memory accesses and TLB/PWC reloadDuration of nested radix table walk for guest process table entry translation, but limited to duration only in Level 4 host memory accesses and TLB/PWC reloadDuration of table walk for guest process table entry translation, but limited to duration only of memory access & TLB/PWC reload of the guest entryDuration of nested radix table walk for guest process table entry translation looking up TLBCount of the amount of times a load/store or fetch was rejected due to exceptions.The operation is rejected because it must be NTC to translate.Number of times the MMU rejects a translation for any reason.Count of amount of times a load/store or fetch was rejected because there was a collision in the MMU pipeline with a 2nd pass & a reload.Count of amount of times a load/store or fetch was rejected because it matched on the MML lock.Count of amount of times a load/store or fetch was rejected because it matched on a partition scoped probe.Count of amount of times a load/store or fetch was rejected because it matched on a process scoped probe.Number of times a translation is rejected on a level 2 PDE boundary.Number of times a translation is rejected on a level 3 PDE boundary.Number of times a translation is rejected on a PTE boundary.Count of amount of times a translation was rejected because the MMU was full.PPC Instructions completed by this thread when all threads in the core had the run-latch setCycles in which all the threads have the run latch setCycles in which at least one thread has the run latch setScalar flop operation completed Scalar versions of four flops operations fdiv,fsqrt (xvdivdp, xvdivsp, xvsqrtdp, xvsqrtsp)Store-Hit-Load Table Read Hit with entry EnabledNumber of cycles the MMU is in the process of walking the TLB for a TLBIE.TLBIE snoop cycles in which the data cache is being walkedTLBIE snoop cycles from the time the TLBIE is detected to when its processing is finishedNumber of TLBIE snoops that match the lpar this thread belongs toCounts the amount of times a snoop found a not-my-lpar but found a context table hit.Total duration of the snoop TLBIE when there is a context table hit, but a not-my-lpar (LSU is counting my-lpar case).Counts the amount of times a snoop found a not-mu-lpar but found a context table miss.Total duration of the snoop TLBIE when there is a context table miss.Number of cycles the MMU is in the process of arbitrating an incoming TLBIE snoop, but the snoop has not yet acquired the MML lock yet.TLBIE snoop cycles in which the Load-Store unit is waiting for the Icache to be walkedTLBIE snoop cycles in which older loads are still drainingTLBIE snoop cycles in which the Load-Store unit is waiting for the MMU to finish invalidationTLBIE snoop cycles in which older stores are still drainingAny port snooper hit L3. Up to 4 can happen in a cycle but we only count 1Any port snooper detects a store to a line in the Sx state and invalidates the line.Any port snooper L3 miss or collision. Up to 4 can happen in a cycle but we only count 1SP floating point instruction completed16 byte store finshed32 byte store finished8 byte or smaller store finishedAll internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been metStore instructions whose data crosses a cache-line boundary, which causes it to require an additional recycle to the pipeline.Any vector store operation finished.16 byte store finshed32 byte store finished8 byte or smaller load finishedAll internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been metStore instructions whose data crosses a cache-line boundary, which causes it to require an additional recycle to the pipeline.Any vector store operation finished.A start probe nop was dispatched.stcx failedNumber of stcx instructions finished.A stcx instruction finished in LSU with a passing statusNumber of stcx instructions that completed successfullyPOWER10 has 4 STF banks.A stop probe nop was dispatched.Store data line missed in the local chiplet and was found in a different group's L2 or L3.Store data line missed in the local chiplet and was found in distant memory (off group).Store data line hit in the local L2. Includes cache-line states Sx, Tx, MxStore data line missed in the local chiplet and was found in a neighbor L2 or L3.Store data line hit in the local L3. Includes cache-line states Tx and Mx.Store data line missed in the local chiplet and was found in local memory.Store data line missed in the local chiplet and was found in a different chip's L2 or L3.Store data line missed in the local chiplet and was found in remote memory (off chip, within the group).Number of times that 2 stores drain together. Use PM_ST_CMPL as a dividerTIQ reject for storesThis event increments every time the threshold event counter ticks.Number of cycles that one or moreNumber of times a translation request bypasses the TIQ either because the TIQ is completely empty at the time of the request or because the requesting instruction is NTC and there are no other NTC instructions in the TIQNumber of times that a load or store missed in the ERAT and found no space in the EMB.Cycles in which the TIQ has 4 or less active entriesCounts amount of times a partition scoped child hash invalidation was sent to the TLB.Counts amount of times a partition scoped child hash invalidation was sent to the TLB.Counts amount of times a partition scoped precise invalidation was sent to TLB.Counts amount of times a process scoped invalidation was sent to TLB.Counts amount of times precise TLBIES sent to TLB in HPT.Counts amount of precise TLBIEs sent to TLB for HPT invalidations and had at least 1 matching entry in the congruence class.Counts total amount of congruence classes that found at least 1 invalidation match for a partition scoped hash match.Counts total amount of congruence classes that found at least 1 invalidation match for a partition scoped hash match.Counts total amount of congruence classes that found at least 1 invalidation match for a precise partition scoped TLBIE invalidation.Counts total amount of congruence classes that found at least 1 invalidation match for a precise process scoped TLBIE invalidation.Number of times the TLB was read to satisfy an L3 data prefetchCount indicating the amount of times a TLB scrub occurred.Only valid for HPT translations.Number of TM transactions abortedConflict in which a storage location is accessed by another processor outside of a transaction.Conflict in which a storage location is accessed by another transaction.Conflict in suspended state where a storage location was previously accessed transactionally by this thread. Address only request to L2 from a transaction. This event counts once per cache line.The instruction, SPR, or access type is not permitted. Corresponds to bit 8 of the TEXAS register.Transaction failed for any reason other than footprint overflow, resource overflow or address conflict.TM Footprint Capacity Overflow. Includes load and store, due to capacity CO or full TMDIR/LVDIRStorage footprint overflow when multiple threads are using the transactional footprint tracking resources.Storage footprint overflow caused exclusively by this thread. Corresponds to bit 10 of the TEXAS register.TM Load (fav or non-fav) ran into conflict (failed)Completion time outer tbeginCompletion time outer tendNumber of TM transactions that passedTransactional resource conflict when all the transactional registers are in use and additional ones are requested.TM Store (fav or non-fav) ran into conflict (failed)Count of amount of times the 2nd pass for HPT was initiated due to VA hash mispredicts.Vector FP instruction completedvector versions of fdiv,fsqrt (fdiv,fdiv_rc,fdivs,fdivs_rc,fsqrt,fsqrt_rc,fsqrts,fsqrts_rc)Number of vector load instructions completedNumber of vector store instructions completedVSU instruction was issued to VSU pipe 0VSU instruction was issued to VSU pipe 1VSU instruction was issued to VSU pipe 2VSU instruction was issued to one of the VSU pipes.Non FLOP operation completedThe processor's L1 data cache was reloaded from the source specified in MMCR3[0:10].The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to a demand loadThe processor's L1 data cache was reloaded from the source specified in MMCR3[26:36].The processor's L1 data cache was reloaded from the source specified in MMCR3[39:49].MMU reports every cycle the thread is in HPT translation modeThe MMU requested a line from L2 for translation.MMU reports every cycle the thread is in radix translation mode (as opposed to HPT mode)