/* IBM_PROLOG_BEGIN_TAG                                                   */
/* This is an automatically generated prolog.                             */
/*                                                                        */
/* bos720 src/bos/kernel/sys/POWER/m_intr.h 1.8.3.1                       */
/*                                                                        */
/* Licensed Materials - Property of IBM                                   */
/*                                                                        */
/* COPYRIGHT International Business Machines Corp. 1988,2015              */
/* All Rights Reserved                                                    */
/*                                                                        */
/* US Government Users Restricted Rights - Use, duplication or            */
/* disclosure restricted by GSA ADP Schedule Contract with IBM Corp.      */
/*                                                                        */
/* IBM_PROLOG_END_TAG                                                     */
/* @(#)75	1.8.3.1  src/bos/kernel/sys/POWER/m_intr.h, libsys, bos720, 1519A_720 4/11/15 20:41:59 */
#ifndef _H_M_INTR
#define _H_M_INTR
/*
 * COMPONENT_NAME: (SYSIOS) Machine dependent interrupt management defines
 *
 * FUNCTIONS: Machine dependent defines
 *
 * ORIGINS: 27
 *
 * (C) COPYRIGHT International Business Machines Corp. 1988 1994
 * All Rights Reserved
 * Licensed Materials - Property of IBM
 *
 * US Government Users Restricted Rights - Use, duplication or
 * disclosure restricted by GSA ADP Schedule Contract with IBM Corp.
 */

/*
 * THIS FILE SHOULD NOT BE EXPLICITLY INCLUDED.  IF DEFINES FROM THIS
 * FILE ARE NEEDED, THEN INCLUDE <sys/intr.h>
 */

/* Note INT_OFFLVL is also defined in ml/i_machine.m4 */

#define	INT_OFFLVL		63	   /* off-level handler level */

/* The following must remain for source level compatibility */
#define INT_OFFL0		INT_OFFLVL
#define INT_OFFL1		INT_OFFLVL
#define INT_OFFL2		INT_OFFLVL
#define INT_OFFL3		INT_OFFLVL

/*
 * NUM_BUS_SOURCE defines the number of interrupt levels on the Micro
 * Channel.  It is also used to indicate the number of possible interrupt
 * sources on a BUC.  NUM_INTR_SOURCE is the total number of
 * interrupt levels supported by i_init.  POWER machines only use the
 * first 64 levels.
 *
 * MAX_BUID defines the maximum BUID allowed for PPC machines
 * MAX_BUC_POLL_GRP defines the maximum number of BUC groupings in the
 * poll array.
 *
 * The value of 0x23 for MAX_BUID was chosen so the default BUIDs 0x20
 * and 0x21 for IOCCs would naturally work.
 *
 * NOTE: MAX_BUC_POLL_GRP and NUM_INTR_SOURCE have corresponding asm
 * .sets in ml/POWER/i_machine.m4
 */
#define MAX_BUID		0x23
#define MAX_BUC_POLL_GRP	8192
#define NUM_BUS_SOURCE		16
#define NUM_INTR_SOURCE		(NUM_BUS_SOURCE * MAX_BUC_POLL_GRP)

/*
 *
 * This section defines the 16 possible I/O interrupts on machines using
 * cascaded 8259 interrupt controllers.  These are combined motherboard,
 * ISA bus, PCI bus, and potentially PCMCIA bus interrupts.
 *
 * The only interrupts that may be used by optional adapters are those that
 * start out INT_SFIRQ*.
 */
#ifdef _KERNSYS
#define MAX_PCINT	15	/* Maximum RSPC interrupt level		*/

#define INT_SFTIMER	 0	/* Timer interrupt level		*/
#define INT_SFCLOCK	 8	/* NIO real time clock interrupt	*/
#endif /* _KERNSYS */

#define INT_SFKBD	 1	/* Motherboard Keyboard interrupt	*/
				/* There is no IRQ 2, that is cascade int */
#define INT_SFCOM2	 3	/* Serial ports (2f8 + 2e8,238,2e0,228)	*/
#define INT_SFCOM1	 4	/* Serial ports (2f8 + 3e8,338,2e8,220)	*/
#define INT_SFIRQ5	 5	/* ISA bus IRQ 5 interrupt		*/
#define INT_SFFLOPPY	 6	/* Motherboard floppy controller interrupt*/
#define INT_SFIRQ7	 7	/* ISA bus IRQ 7 interrupt		*/
#define INT_SFPARALLEL	 7	/* Motherboard parallel port interrupt	*/
#define INT_SFIRQ9	 9	/* ISA bus IRQ 9 interrupt		*/
#define INT_SFAUDIO	10	/* Motherboard Audio subsystem interrupt*/
#define INT_SFIRQ11	11	/* ISA bus IRQ 11 interrupt		*/
#define INT_SFMOUSE	12	/* Motherboard mouse interrupt		*/
#define INT_SFSCSI	13	/* Motherboard SCSI controller interrupt*/
#define INT_SFIRQ14	14	/* ISA bus IRQ 14 interrupt		*/
#define INT_SFPCI	15	/* PCI dot or interrupt			*/

#endif /* _H_M_INTR */