/* IBM_PROLOG_BEGIN_TAG                                                   */
/* This is an automatically generated prolog.                             */
/*                                                                        */
/* bos72X src/bos/kernel/sys/dr.h 1.34.3.19                               */
/*                                                                        */
/* Licensed Materials - Property of IBM                                   */
/*                                                                        */
/* COPYRIGHT International Business Machines Corp. 2001,2021              */
/* All Rights Reserved                                                    */
/*                                                                        */
/* US Government Users Restricted Rights - Use, duplication or            */
/* disclosure restricted by GSA ADP Schedule Contract with IBM Corp.      */
/*                                                                        */
/* IBM_PROLOG_END_TAG                                                     */
/* @(#)40     1.34.3.19  src/bos/kernel/sys/dr.h, sysproc, bos72X, x2021_23B4 5/28/21 15:01:43 */

#ifndef _H_SYS_DR
#define _H_SYS_DR

#include <sys/types.h>
#include <sys/processor.h>
#include <sys/corralid.h>
#include <sys/kerrno.h>

#ifdef __cplusplus
extern "C" {
#endif

/*
 * dr_wlm_info_t is the structure the holds the data related 
 * to DR_SOFT_RES_CHANGES_OPER event that is returned to
 * the caller of dr_reconfig as a part of dr_info_t.
 */
typedef struct dr_wlm_info_t {
	unsigned int cpu_add      :1;   /* cpu capacity for the wpar increase */
	unsigned int cpu_rem      :1;   /* mem capacity for the wpar decrease */
	unsigned int mem_add      :1;   /* mem capacity for the wpar increase */
	unsigned int mem_rem      :1;   /* mem capacity for the wpar decrease */
	unsigned int rs_cpu       :1;   /* rset cpu of wpar changes           */
	unsigned int rs_mem       :1;   /* rset mem of wpar changes           */
	unsigned int pad1         :10;  /* space not used                     */
	unsigned int cpu_cap      :8;   /* current cpu cap for the wpar       */
	unsigned int mem_cap      :8;   /* current mem cap for wpar           */
	unsigned int cpu_usage    :8;   /* current cpu usage for wpar         */
	unsigned int mem_usage    :8;   /* current mem usage for wpar         */
	unsigned int pad2         :16;  /* space not used                     */
} dr_wlm_info_t;
typedef struct dr_info {
	unsigned int        add : 1;	/* add operation		      */
	unsigned int        rem : 1; 	/* remove operation		      */
	unsigned int        cpu : 1;	/* target resource is a cpu	      */
	unsigned int        mem : 1;	/* target resource is memory	      */
	unsigned int      check : 1;	/* check phase in effect	      */
	unsigned int        pre : 1;	/* pre phase in effect		      */
	unsigned int       doit : 1;	/* doit phase in effect		      */
	unsigned int       post : 1;	/* post phase in effect		      */
	unsigned int  posterror : 1;	/* post error phase in effect	      */
	unsigned int      force : 1;	/* force option in effect	      */
	unsigned int   bindproc : 1;	/* process has bindprocess dependency */
	unsigned int   softpset : 1;	/* process has soft processor set
					   dependency                         */
	unsigned int   hardpset : 1;	/* process has hard processor set
					   dependency			      */
	unsigned int      plock : 1;	/* process has plock'ed/mlock'd memory*/
	unsigned int       pshm : 1;	/* process has pinned shared memory   */
	unsigned int	ent_cap	: 1;	/* target resource:entitled capacity  */
	unsigned int	var_wgt	: 1;	/* target resource:variable weight    */
	unsigned int splpar_capable : 1;/* 1/0 partition is/not splpar capable*/
	unsigned int splpar_shared  : 1;/* 1/0 partition shared/dedicated mode*/
	unsigned int splpar_capped  : 1;/* 1/0 partition capped/uncapped mode */
	unsigned int cap_constrained : 1;/* Set to 1 if requested capacity
					  * update is constrained by PHYP to 
					  * be within partition capacity bounds.
					  */
	unsigned int migrate : 1;
	unsigned int hibernate : 1;
	unsigned int partition : 1;

	unsigned int workload_partition : 1;/* workload partition event	      */
	unsigned int checkpoint : 1;	/* checkpoint operation		      */
	unsigned int restart : 1;	/* restart operattion		      */
	unsigned int topology_update : 1;	/* topology changed 	      */
	unsigned int acc_update : 1;	/* accelerator update		      */
	unsigned int      chlmb : 1;    /* LMB reaffinitization in progress   */
	unsigned int	    acu	: 1;	/* accelerator credit unit update     */

	/* The following fields are filled out for cpu based requests */

	int	lcpu;			/* logical id of target cpu 	      */
	int	bcpu;			/* bind-id of target cpu	      */

	uint	phase_gen;		/* Reserved for kernel use.           */

	/* The following fields are filled out for memory based requests */

        size64_t  req_memsz_change;	/* Request size in bytes              */
	size64_t  sys_memsz;		/* System Memory size		      */
        rpn64_t   sys_free_frames;	/* Number of free frames in the system*/
        rpn64_t   sys_pinnable_frames;	/* Number of pinnable frames in system*/
        rpn64_t   sys_total_frames;	/* Total number of frames in system   */

	/*
	 * SPLPAR parameters.
	 */
	uint64_t  capacity;		/* partition current entitled capacity
					 * if ent_cap bit is set, partition's
					 * current variable capacity weight 
					 * if var_wgt bit is set. 
					 */
	int	  delta_cap;		/* delta capacity added/removed to 
					 * current value depending on add/rem 
					 * bit flag value above 
					 */
	struct dr_wlm_info_t dr_wlm;    /* info for DR_SOFT_RES_CHANGES    */
	ushort	  dr_op;		/* type of operation...to replace
					 * bit fields 
					 */
	ushort	  dr_pad;
	size64_t  mem_capacity;		/* partitions entitled I/O memory
					 * or variable capacity
					 */
	ssize64_t  delta_mem_capacity;	/* amount of mem I/O being added
					 * or removed.
					 */

	ushort lvup;
	ushort res_pad;
	int  reserved[1];          
} dr_info_t;

int dr_reconfig(int flags, dr_info_t *info);

/* Valid flags for dr_reconfig are */
#define DR_QUERY            0x000000001
#define DR_EVENT_FAIL       0x000000002
#define DR_RECONFIG_DONE    0x000000004

/* DR Operations for the dr_op field in dr_info_t */
#define DR_OP_ENT_MEM_CAP_ADD		1
#define DR_OP_ENT_MEM_CAP_REMOVE 	2
#define DR_OP_VAR_MEM_CAP_ADD		3
#define DR_OP_VAR_MEM_CAP_REMOVE 	4
#define DR_OP_CPU_AFFINITY_REFRESH	5
#define DR_OP_AME_FACTOR	 	6
#define DR_OP_PHIB			7
#define DR_OP_ACC			8
#define DR_OP_CHLMB_AFF                 9
#define DR_OP_LVUPD			10
#define DR_OP_ACU			11

/*
 * LPAR cpu info struct.  Used to pass back
 * load average and utilization average.
 */
typedef struct lpar_load{
        int     loadavg;                /* load average on lpars */
        int     utilavg;                /* utilization average on lpars */
	char	loadavgshift;		/* int -> float shift value */
	char	pad[3];
} lpar_load_t;

int getlparload(lpar_load_t *lp, size_t size);

#ifdef _KERNEL

/*
 * The stack for dynamic reconfiguration by drslot_chrp_* thread must be pinned.
 * Since i_disable() can get called by routines that DR calls, and it performs 
 * a stack touch, we must ensure that no faults will happen on that. 
 * To cover this case, this makes an adjustment to the stack floor here DR_STKADJ. 
 * This adjustment is borrowed from the LRU_STKADJ logic.
 */
#define DR_STKMINALIGN    (8 * 14)    
#define DR_STKADJ         ALIGN_UP((2 * DR_STKMINALIGN), 128)

/* 
 * DR Events that Kernel Extensions wants to be notified of 
 */ 
#define DR_CPU_ADD_CHECK		0x00000001ULL
#define DR_CPU_ADD_PRE			0x00000002ULL
#define DR_CPU_ADD_POST			0x00000004ULL
#define DR_CPU_ADD_POST_ERROR		0x00000008ULL
#define DR_CPU_REMOVE_CHECK		0x00000010ULL
#define DR_CPU_REMOVE_PRE		0x00000020ULL
#define DR_CPU_REMOVE_POST		0x00000040ULL
#define DR_CPU_REMOVE_POST_ERROR	0x00000080ULL
#define DR_MEM_ADD_CHECK		0x00000100ULL
#define DR_MEM_ADD_PRE			0x00000200ULL
#define DR_MEM_ADD_POST			0x00000400ULL
#define DR_MEM_ADD_POST_ERROR		0x00000800ULL
#define DR_MEM_REMOVE_CHECK		0x00001000ULL
#define DR_MEM_REMOVE_PRE		0x00002000ULL
#define DR_MEM_REMOVE_POST		0x00004000ULL
#define DR_MEM_REMOVE_POST_ERROR	0x00008000ULL
#define DR_MEM_ADD_RES			0x00010000ULL
#define DR_MEM_REMOVE_RES		0x00020000ULL

#define DR_CAP_ADD_CHECK		0x00040000ULL
#define DR_CAP_ADD_PRE			0x00080000ULL
#define DR_CAP_ADD_POST			0x00100000ULL
#define DR_CAP_ADD_POST_ERROR		0x00200000ULL
#define DR_CAP_REMOVE_CHECK		0x00400000ULL
#define DR_CAP_REMOVE_PRE		0x00800000ULL
#define DR_CAP_REMOVE_POST		0x01000000ULL
#define DR_CAP_REMOVE_POST_ERROR	0x02000000ULL

#define DR_MEM_REMOVE_OP_PRE            0x04000000ULL
#define DR_MEM_REMOVE_OP_POST           0x08000000ULL
#define DR_MEM_ADD_OP_POST              0x10000000ULL
#define DR_RESERVED1			0x20000000ULL
#define DR_RESERVED2			0x40000000ULL
#define DR_RESERVED3			0x80000000ULL

#define DR_PMIG_CHECK			0x100000000ULL
#define DR_PMIG_PRE			0x200000000ULL
#define DR_PMIG_POST			0x400000000ULL
#define DR_PMIG_POST_ERROR		0x800000000ULL
						/* Reserved for internal use  */
#define DR_PMIG_POST_INTERNAL		0x1000000000ULL 


/* unused */
#define DR_RESERVED4			0x00002000000000ULL
#define DR_RESERVED5			0x00004000000000ULL
#define DR_RESERVED6			0x00008000000000ULL

/* DR event for WPAR migration */
#define DR_WMIG_CHECK			0x00010000000000ULL
#define DR_WMIG_PRE			0x00020000000000ULL
#define DR_WMIG_POST			0x00040000000000ULL
#define DR_WMIG_POST_ERROR		0x00080000000000ULL

/* DR events for kernel extensions that need to participate in a checkpoint */
#define DR_WMIG_CHECKPOINT_CHECK	0x00100000000000ULL
#define DR_WMIG_CHECKPOINT_PRE		0x00200000000000ULL
#define DR_WMIG_CHECKPOINT_DOIT		0x00400000000000ULL
#define DR_WMIG_CHECKPOINT_ERROR	0x00800000000000ULL
#define DR_WMIG_CHECKPOINT_POST		0x01000000000000ULL
#define DR_WMIG_CHECKPOINT_POST_ERROR	0x02000000000000ULL

/* DR events for kernel extensions that need to participate in a restart */
#define DR_WMIG_RESTART_CHECK		0x04000000000000ULL
#define DR_WMIG_RESTART_PRE		0x08000000000000ULL
#define DR_WMIG_RESTART_DOIT		0x10000000000000ULL
#define DR_WMIG_RESTART_ERROR		0x20000000000000ULL
#define DR_WMIG_RESTART_POST		0x40000000000000ULL
#define DR_WMIG_RESTART_POST_ERROR	0x80000000000000ULL

/* 
 * DR events for kernel extensions for memory capacity events
 * 
 * These are the last of the bits that can be used.  For
 * future DR operations, use the dr_op field.
 */
#define DR_MEM_CAP_ADD_CHECK		0x100000000000000ULL
#define DR_MEM_CAP_ADD_PRE		0x200000000000000ULL
#define DR_MEM_CAP_ADD_POST		0x400000000000000ULL
#define DR_MEM_CAP_ADD_POST_ERROR	0x800000000000000ULL
#define DR_MEM_CAP_REMOVE_CHECK		0x1000000000000000ULL
#define DR_MEM_CAP_REMOVE_PRE		0x2000000000000000ULL
#define DR_MEM_CAP_REMOVE_POST		0x4000000000000000ULL
#define DR_MEM_CAP_REMOVE_POST_ERROR	0x8000000000000000ULL

/*
 * Events flag values grouped for ease.
 */
#define DR_CHECK_NOTIFY	(DR_MEM_REMOVE_CHECK | DR_CPU_REMOVE_CHECK | \
			 DR_CPU_ADD_CHECK | DR_MEM_ADD_CHECK | \
			 DR_CAP_ADD_CHECK | DR_CAP_REMOVE_CHECK | \
			 DR_PMIG_CHECK | DR_WMIG_CHECK | \
			 DR_MEM_CAP_ADD_CHECK | DR_MEM_CAP_REMOVE_CHECK)

#define DR_PRE_NOTIFY	(DR_MEM_REMOVE_PRE | DR_CPU_REMOVE_PRE | \
			 DR_CPU_ADD_PRE | DR_MEM_ADD_PRE | \
			 DR_MEM_ADD_RES | DR_MEM_REMOVE_RES | \
			 DR_CAP_ADD_PRE | DR_CAP_REMOVE_PRE | \
			 DR_PMIG_PRE | DR_WMIG_PRE | \
			 DR_MEM_CAP_ADD_PRE | DR_MEM_CAP_REMOVE_PRE)

#define DR_POST_NOTIFY	(DR_MEM_REMOVE_POST | DR_CPU_REMOVE_POST | \
			 DR_CPU_ADD_POST | DR_MEM_ADD_POST | \
			 DR_CAP_ADD_POST | DR_CAP_REMOVE_POST | \
			 DR_PMIG_POST | DR_WMIG_POST | \
			 DR_MEM_CAP_ADD_POST | DR_MEM_CAP_REMOVE_POST)

#define DR_POST_ERROR_NOTIFY	(DR_MEM_REMOVE_POST_ERROR | \
				 DR_CPU_REMOVE_POST_ERROR | \
				 DR_CPU_ADD_POST_ERROR    | \
				 DR_MEM_ADD_POST_ERROR	  | \
				 DR_CAP_ADD_POST_ERROR    | \
				 DR_CAP_REMOVE_POST_ERROR | \
				 DR_PMIG_POST_ERROR       | \
				 DR_WMIG_POST_ERROR	  | \
				 DR_MEM_CAP_ADD_POST_ERROR | \
				 DR_MEM_CAP_REMOVE_POST_ERROR)

#define DR_CPU_NOTIFY 	(DR_CPU_ADD_CHECK    | DR_CPU_ADD_PRE        | \
			 DR_CPU_ADD_POST     | DR_CPU_ADD_POST_ERROR | \
			 DR_CPU_REMOVE_CHECK | DR_CPU_REMOVE_PRE     | \
			 DR_CPU_REMOVE_POST  | DR_CPU_REMOVE_POST_ERROR)

#define DR_MEM_NOTIFY 	(DR_MEM_ADD_CHECK    | DR_MEM_ADD_PRE        | \
			 DR_MEM_ADD_POST     | DR_MEM_ADD_POST_ERROR | \
			 DR_MEM_REMOVE_CHECK | DR_MEM_REMOVE_PRE     | \
			 DR_MEM_ADD_RES      | DR_MEM_REMOVE_RES     | \
			 DR_MEM_REMOVE_POST  | DR_MEM_REMOVE_POST_ERROR)

#define DR_CAP_NOTIFY 	(DR_CAP_ADD_CHECK    | DR_CAP_ADD_PRE        | \
			 DR_CAP_ADD_POST     | DR_CAP_ADD_POST_ERROR | \
			 DR_CAP_REMOVE_CHECK | DR_CAP_REMOVE_PRE     | \
			 DR_CAP_REMOVE_POST  | DR_CAP_REMOVE_POST_ERROR)

#define DR_PMIG_NOTIFY 	(DR_PMIG_CHECK	     | DR_PMIG_PRE	     | \
			 DR_PMIG_POST        | DR_PMIG_POST_ERROR)

#define DR_WMIG_NOTIFY 	(DR_WMIG_CHECK       | \
			 DR_WMIG_PRE         | \
			 DR_WMIG_POST        | \
			 DR_WMIG_POST_ERROR)

#define DR_WMIG_CHECKPOINT_NOTIFY \
			(DR_WMIG_CHECKPOINT_CHECK       | \
			 DR_WMIG_CHECKPOINT_PRE         | \
			 DR_WMIG_CHECKPOINT_DOIT        | \
			 DR_WMIG_CHECKPOINT_ERROR       | \
			 DR_WMIG_CHECKPOINT_POST        | \
			 DR_WMIG_CHECKPOINT_POST_ERROR)

#define DR_WMIG_RESTART_NOTIFY \
			(DR_WMIG_RESTART_CHECK       | \
			 DR_WMIG_RESTART_PRE         | \
			 DR_WMIG_RESTART_DOIT        | \
			 DR_WMIG_RESTART_ERROR       | \
			 DR_WMIG_RESTART_POST        | \
			 DR_WMIG_RESTART_POST_ERROR)

#define DR_MEM_CAP_NOTIFY (DR_MEM_CAP_ADD_CHECK | DR_MEM_CAP_ADD_PRE | \
			   DR_MEM_CAP_ADD_POST  | DR_MEM_CAP_ADD_POST_ERROR | \
			   DR_MEM_CAP_REMOVE_CHECK | DR_MEM_CAP_REMOVE_PRE  | \
			   DR_MEM_CAP_REMOVE_POST | \
			   DR_MEM_CAP_REMOVE_POST_ERROR)

#define DR_ALL_NOTIFY	(DR_CPU_NOTIFY             | \
			 DR_MEM_NOTIFY             | \
			 DR_CAP_NOTIFY             | \
			 DR_PMIG_NOTIFY            | \
			 DR_WMIG_NOTIFY            | \
			 DR_WMIG_CHECKPOINT_NOTIFY | \
			 DR_WMIG_RESTART_NOTIFY    | \
			 DR_MEM_CAP_NOTIFY)

#define DR_ALL_OP_NOTIFY (DR_MEM_REMOVE_OP_PRE  | \
			  DR_MEM_REMOVE_OP_POST | \
			  DR_MEM_ADD_OP_POST)

/* 
 * DR handler return values: 
 */
#define DR_SUCCESS  0
#define DR_WAIT     1
#define DR_FAIL     2

/*
 * Output data structures to kernel extensions for cpu and memory
 * DR operations
 */

struct dri_cpu {
	cpu_t		lcpu;		/* Logical CPU Id of target CPU */
	cpu_t		bcpu;		/* Bind Id being removed	*/
};

struct dri_mem {
	size64_t	req_memsz_change;   /* requested mem size  */
	size64_t	sys_memsz;	    /* Original total mem size */
	size64_t	act_memsz_change;   /* mem added/removed so far */
	rpn64_t	        sys_free_frames;    /* Number of free frames */
	rpn64_t	        sys_pinnable_frames;/* Number of pinnable frames */
	rpn64_t	        sys_total_frames;   /* Total number of frames */
	unsigned long long lmb_addr;   	    /* start addr of LMB */
	size64_t	lmb_size;	    /* Size of LMB being added */
};

/*
 * SPLPAR parameters. Changes in variable weight is NOT notified to kextns.
 */
struct dri_cpu_capacity {
	uint64_t	ent_capacity;	/* partition current entitled capacity*/
	int		delta_ent_cap;	/* delta capacity added/removed*/
	int		status;		/* capacity update constrained or not */
};

/*
 * dri_cpu_capacity.status flags.
 */
#define	CAP_UPDATE_SUCCESS	0x0
#define	CAP_UPDATE_CONSTRAINED	0x1

/*
 * Info passed to the kernel extentions during partition migration operation.
 */
struct dri_pmig {
	int		version;	/* changes when new fields are added. */
	int		dest_lpid;
	long long	streamid;
	unsigned int	selfarp_secs;
	int		pad[3];
};

/*
 * Info passed to the kernel extensions during partition hibernation operation.
 */
struct dri_phib {
    	int		version;	/* changes when new fields are added */
	int		dest_lpid;
	long long	streamid;
	unsigned int	selfarp_secs;
	int		pad[3];
};

/* version 1 of the dri_wmig structure */
#define DRI_WMIG_V1		1

/* info passed to kernel extensions during the WPAR migration event */
struct dri_wmig {
	int		version;
	cid_t		cid;
};

/* version 1 of the dri_wmig_chrs structure */
#define DRI_WMIG_CHRS_V1	1

/* info passed to kernel extensions during the checkpoint and restart events */
struct dri_wmig_chrs {
	int		version;
	cid_t		cid;
	char *		chrs_file;	/* this points to user space. kernel */
					/* extensions must copy in the path  */
					/* before using.		     */
};

struct dri_mem_weight {
	size64_t	mem_weight;	    /* Current memory capacity */
	ssize64_t	delta_mem_weight;   /* Change in capacity (+ / -) */
	uint		flags;		    /* Unused for now */
	uchar		status;		    /* Constrained? */
	uchar		reserved[7];	    /* Future use */
};

/*
 * VRM parameters. Changes in memory variable weight 
 * is NOT notified to kextns.
 */
struct dri_mem_capacity {
	size64_t	mem_capacity;	    /* Current memory capacity */
	ssize64_t	delta_mem_capacity; /* Change in capacity (+ / -) */
	uint		flags;		    /* Unused for now */
	uchar		status;		    /* Constrained? */
	uchar		reserved[7];	    /* Future use */
};

/* AME parameters.  */
struct dri_ame_factor
{
	amef_t    dri_ame_factor_cur;        /* current AME factor for LPAR */
	amef_t    dri_ame_factor_new;        /* new AME factor for the LPAR */
	size64_t  dri_ame_exp_memsize_cur;   /* current exp. memsize for LPAR */
	ssize64_t dri_ame_exp_memsize_delta; /* change to exp. memory size */
	uint      dri_ame_flags;             /* Unused for now */
};

/* Accelerator update(PRRN) parameters */
struct dri_acc
{
	int prrn_scope;			     /* scope from PRRN event */
};

/* 
 * Info passed to kext for 
 * Accelerator credit unit update operation
 */
struct dri_acu
{
	int num_acu;		/* number of accelerator credit units */
};

/* 
 * New DR events used when registering/notifying.  These
 * will replace the bit fields previously used.
 */
typedef enum {
/* 0 - 9 */
	DR_KEVENT_CPU_ADD_CHECK		= 0x0,
	DR_KEVENT_CPU_ADD_PRE		= 0x1,
	DR_KEVENT_CPU_ADD_POST,
	DR_KEVENT_CPU_ADD_POST_ERROR,
	DR_KEVENT_CPU_RM_CHECK,
	DR_KEVENT_CPU_RM_PRE,
	DR_KEVENT_CPU_RM_POST,
	DR_KEVENT_CPU_RM_POST_ERROR,
	DR_KEVENT_MEM_ADD_CHECK,
	DR_KEVENT_MEM_ADD_PRE,
/* 10 - 19 */
	DR_KEVENT_MEM_ADD_POST,
	DR_KEVENT_MEM_ADD_POST_ERROR,
	DR_KEVENT_MEM_RM_CHECK,
	DR_KEVENT_MEM_RM_PRE,
	DR_KEVENT_MEM_RM_POST,
	DR_KEVENT_MEM_RM_POST_ERROR,
	DR_KEVENT_MEM_ADD_RES,
	DR_KEVENT_MEM_RM_RES,
	DR_KEVENT_CPU_CAP_ADD_CHECK,
	DR_KEVENT_CPU_CAP_ADD_PRE,
/* 20 - 29 */
	DR_KEVENT_CPU_CAP_ADD_POST,
	DR_KEVENT_CPU_CAP_ADD_POST_ERROR,
	DR_KEVENT_CPU_CAP_RM_CHECK,
	DR_KEVENT_CPU_CAP_RM_PRE,
	DR_KEVENT_CPU_CAP_RM_POST,
	DR_KEVENT_CPU_CAP_RM_POST_ERROR,
	DR_KEVENT_MEM_RM_OP_PRE,
	DR_KEVENT_MEM_RM_OP_POST,
	DR_KEVENT_MEM_ADD_OP_POST,
	DR_KEVENT_RESERVED1,
/* 30 - 39 */
	DR_KEVENT_RESERVED2,
	DR_KEVENT_RESERVED3,
	DR_KEVENT_PMIG_CHECK,
	DR_KEVENT_PMIG_PRE,
	DR_KEVENT_PMIG_POST,
	DR_KEVENT_PMIG_POST_ERROR,
	DR_KEVENT_PMIG_POST_INTERNAL,
	DR_KEVENT_RESERVED4,
	DR_KEVENT_RESERVED5,
	DR_KEVENT_RESERVED6,
/* 40 - 49 */
	DR_KEVENT_WMIG_CHECK,
	DR_KEVENT_WMIG_PRE,
	DR_KEVENT_WMIG_POST,
	DR_KEVENT_WMIG_POST_ERROR,
	DR_KEVENT_WMIG_CHECKPOINT_CHECK,
	DR_KEVENT_WMIG_CHECKPOINT_PRE,
	DR_KEVENT_WMIG_CHECKPOINT_DOIT,
	DR_KEVENT_WMIG_CHECKPOINT_ERROR,
	DR_KEVENT_WMIG_CHECKPOINT_POST,
	DR_KEVENT_WMIG_CHECKPOINT_POST_ERROR,
/* 50 - 59 */
	DR_KEVENT_WMIG_RESTART_CHECK,
	DR_KEVENT_WMIG_RESTART_PRE,
	DR_KEVENT_WMIG_RESTART_DOIT,
	DR_KEVENT_WMIG_RESTART_ERROR,
	DR_KEVENT_WMIG_RESTART_POST,
	DR_KEVENT_WMIG_RESTART_POST_ERROR,
	DR_KEVENT_MEM_CAP_ADD_CHECK,
	DR_KEVENT_MEM_CAP_ADD_PRE,
	DR_KEVENT_MEM_CAP_ADD_POST,
	DR_KEVENT_MEM_CAP_ADD_POST_ERROR,
/* 60 - 69 */
	DR_KEVENT_MEM_CAP_RM_CHECK,
	DR_KEVENT_MEM_CAP_RM_PRE,
	DR_KEVENT_MEM_CAP_RM_POST,
	DR_KEVENT_MEM_CAP_RM_POST_ERROR,
	DR_KEVENT_MEM_CAP_WGT_ADD_CHECK,
	DR_KEVENT_MEM_CAP_WGT_ADD_PRE,
	DR_KEVENT_MEM_CAP_WGT_ADD_POST,
	DR_KEVENT_MEM_CAP_WGT_ADD_POST_ERROR,
	DR_KEVENT_MEM_CAP_WGT_RM_CHECK,
	DR_KEVENT_MEM_CAP_WGT_RM_PRE,
/* 70 - 79 */
	DR_KEVENT_MEM_CAP_WGT_RM_POST,
	DR_KEVENT_MEM_CAP_WGT_RM_POST_ERROR,
	DR_KEVENT_TOPOLOGY_CHECK,
	DR_KEVENT_TOPOLOGY_PRE,
	DR_KEVENT_TOPOLOGY_POST,
	DR_KEVENT_TOPOLOGY_POST_ERROR,
	DR_KEVENT_AME_FACTOR_CHECK,
	DR_KEVENT_AME_FACTOR_PRE,
	DR_KEVENT_AME_FACTOR_POST,
	DR_KEVENT_AME_FACTOR_POST_ERROR,
/* 80 - 89 */
	DR_KEVENT_PHIB_CHECK,
	DR_KEVENT_PHIB_PRE,
	DR_KEVENT_PHIB_POST,
	DR_KEVENT_PHIB_POST_ERROR,
	DR_KEVENT_PHIB_POST_INTERNAL,
	DR_KEVENT_ACC_PRE,
	DR_KEVENT_ACC_POST,
	DR_KEVENT_ACC_POST_ERROR,
	DR_KEVENT_CHLMB_PRE,
	DR_KEVENT_CHLMB_POST,
/* 90 - 99 */
	DR_KEVENT_CHLMB_POST_ERROR,
	DR_KEVENT_LVUP_CHECK,
	DR_KEVENT_LVUP_PRE,
	DR_KEVENT_LVUP_POST,
	DR_KEVENT_LVUP_POST_ERROR,
	DR_KEVENT_PMIG_PRE_DIS_INTERNAL,
	DR_KEVENT_PMIG_POST_DIS_INTERNAL,
	DR_KEVENT_PMIG_POST_ERROR_DIS_INTERNAL,
	DR_KEVENT_ACU_PRE,
	DR_KEVENT_ACU_POST,
#ifdef AKVM
/* 100 - 109 */
	DR_KEVENT_KVM_PMIG_POST,
#endif

	DR_NUM_KEVENTS
} dr_kevent_t;


extern int	reconfig_register( int (*)(void *, void *, int, void *),
			   int, void * , ulong *, char *);  /* deprecated */
extern int	reconfig_register_ext( int (*)(void *, void *, 
						unsigned long long, void *),
			   unsigned long long, void * , ulong *, char *);
extern int	reconfig_register_list( int (*)(void *, void *, 
						dr_kevent_t, void *),
			   dr_kevent_t *, size_t , void *, ulong *, char *);
extern int	reconfig_unregister(ulong);
extern void	reconfig_complete(void *, int);
extern void	dr_mem_sync(void);


#endif /* _KERNEL */

/*
 * These lparinfo_mode specify if format1 or format2 lpar info to be retrieved.
 */
#define LPAR_INFO_FORMAT1	1 /* command for retrieving LPAR format1 info */
#define LPAR_INFO_FORMAT2	2 /* command for retrieving LPAR format2 info */
#define WPAR_INFO_FORMAT	3 /* command for retrieving WPAR format1 info */
#define PROC_MODULE_INFO        4 /* command for retrieving processor module
                                   * format info */
#define NUM_PROC_MODULE_TYPES   5 /* command for retrieving the module count
                                   * prior to requesting processor module 
                                   * information */
#define LPAR_INFO_VRME_NUM_POOLS 	6 /* command for retrieving num */
					  /* vrm pools */
#define LPAR_INFO_VRME_POOLS 		7 /* command for retrieving pool info */
#define LPAR_INFO_VRME_LPAR		8 /* command fr retrieving vrm */
					  /* lpar info */
#define LPAR_INFO_VRME_RESET_HWMARKS 	9 /* command to rese high water */
					  /* marks */
#define LPAR_INFO_VRME_ALLOW_DESIRED	10 /* command to start honoring */
					   /* of desired settings for vrm */
					   /* pools. */
#define EMTP_INFO_FORMAT		11	/* command for retrieving EMTP info */

#define LPAR_INFO_LPM_CAPABILITY	12	/* command for retrieving LPM info */

#define ENERGYSCALE_INFO		13	/* command for retrieving EnergyScale info */
/*
 * eWLM uses lpar_set_resources() call to modify the following SPLPAR
 * resource attributes (lpar_resource_id).
 */

#define __SPLPAR_ENT_CAPACITY	1	/* Entitled Processor Capacity	  */
#define __SPLPAR_VAR_WEIGHT	2	/* Variable Processor Capacity Wt */
#define __SPLPAR_CUR_INTER_CAP	3	/* OS/400: current interactive Cap*/
#define __SPLPAR_NUM_VCPUS	4	/* # of logical(virtual) CPUS available
					 * to this LPAR
					 */
#define __SPLPAR_PARTITION_MEM	5	/* MB of memory available to the OS*/
#define __VRM_ENT_CAPACITY	6	/* IO memory entitlement */
#define __VRM_VAR_WEIGHT	7	/* Variable memory capacity weight */

/* lpar_set_resources() return codes */

#define LPAR_SRES_PARAMINVALID	-1	/* Invalid parameters */
#define LPAR_SRES_CONFNOTSUP	-2	/* configuration constraint */
#define LPAR_SRES_HWERROR	-3	/* Hardware/Firmware error */
#define LPAR_SRES_NOPERM	-4	/* Insufficient authority */
#define LPAR_SRES_EXCEPTION	-5	/* failed due to an Exception */
#define LPAR_SRES_EXIST		-99	/* resource already exist */
#define LPAR_SRES_BUSY		-98	/* resource is busy */
#define LPAR_SRES_UNAVAIL	-97	/* resource temporarily unavailable */
#define LPAR_SRES_ALLOC		-96	/* resource allocation failed */
#define LPAR_SRES_INTERROR	-95	/* Internal errors */
#define LPAR_SRES_NOTREADY	-94	/* resource is not ready */
#define LPAR_SRES_NOTSUP	-93	/* Operation not supported */
#define LPAR_SRES_IOERROR	-92	/* operation failed due to I/O error */
#define LPAR_SRES_INPROGRESS	-91	/* operation in progress */
#define LPAR_SRES_NOTAVAIL	-90	/* resource not available */
#define LPAR_SRES_NOTINARANGE	-89	/* parameter is out of range */

/*
 * LPAR Information structures
 *   - used by lpar_get_info system call
 *   - used by klpar_get_info kernel service
 */

typedef struct lpar_info_format1_t {

	int	 version;		/* version for this structure */
	int	 pad0;
	uint64_t max_memory;            /* MB of max memory lpar can support*/
        uint64_t min_memory;            /* MB of min memory defined for lpar */
	uint64_t memory_region;		/* size in bytes of one LMB */
        uint64_t dispatch_wheel_time;   /* Time of dispatch wheel in nsecs */

        uint     lpar_number;            /* Assigned LPAR number */
        uint     lpar_flags;             /* Logical Partition Flags */
#define LPAR_INFO1_LPAR_CAPABLE	  0x0001  /* LPAR Capable System */
#define LPAR_INFO1_LPAR_ENABLED	  0x0002  /* LPAR System */
#define LPAR_INFO1_DR_CAPABLE  	  0x0004  /* DLPAR Capable */
#define LPAR_INFO1_SMT_CAPABLE    0x0008  /* SMT Capable */
#define LPAR_INFO1_SMTBOUND       0x0010  /* SMT Threads bound */
#define LPAR_INFO1_SPLPAR_CAPABLE 0x0020  /* SPLPAR Capable */
#define LPAR_INFO1_SHARED 	  0x0040  /* Shared Partition */
#define LPAR_INFO1_PMIG_CAPABLE	  0x0080  /* Partition is migration capable */
#define LPAR_INFO1_MSP_CAPABLE    0x0100  /* Mover Service Partition */
#define LPAR_INFO1_DONATE_CAPABLE 0x0200  /* LPAR Idle Cycle Donation capable */
#define LPAR_INFO1_DONATE_ENABLED 0x0400  /* LPAR Idle Cycle Donation enabled */
#define LPAR_INFO1_VRM_CAPABLE	  0x0800  /* LPAR VRM Capable */
#define LPAR_INFO1_VRM_ENABLED	  0x1000  /* LPAR VRM Enabled */
#define LPAR_INFO1_PHIB_CAPABLE	  0x2000  /* Partition is hibernation capable */
#define LPAR_INFO1_SPCM_CAPABLE   0x4000  /* Partition is SPCM capable */
#define LPAR_INFO1_SPCM_ENABLED   0x8000  /* Partition is SPCM enabled */
#define LPAR_INFO1_ACU_CAPABLE    0x10000 /* Accelerator Credit update */
#define LPAR_INFO1_SECBOOT_CAPABLE 0x20000 /* Secure boot */

        uint     max_pcpus_in_sys;      /* max# physCPUs possible in system 
					 * including unlicenced and potentially
					 * hot-pluggable CPUs
					 */
        uint     min_vcpus;             /* min # of virtual cpus in this 
					 * LPAR definition
					 */
        uint     max_vcpus;             /* max # of virtual cpus this 
					 * LPAR can support 
					 */

        uint     min_lcpus;             /* min # of logical cpus */
        uint     max_lcpus;             /* max # of logical cpus this LPAR 
					 * can support 
					 */

        uint     minimum_capacity;      /* Minimum Processor Capacity */
        uint     maximum_capacity;      /* Maximum Processor Capacity */
        uint     capacity_increment;    /* Processor Capacity change granule */

        ushort   smt_threads;           /* # of SMT threads per CPU*/
        char     pad1[2];           	/* added for 8-byte alignment */

	uint	 num_lpars;		/* # of LPARs configured on the system */
#define LPAR_NAME_LEN1	256
        char     lpar_name[LPAR_NAME_LEN1]; /* LPAR name assigned at HMC */

	uint	 desired_capacity;	/* Partition capacity defined by HMC */
	uint	 desired_vcpus;		/* virtual processors defined by HMC */
	uint64_t desired_memory;	/* memory defined by HMC */
	uint	 desired_variable_capwt;/* variable cap weight defined by HMC */
	uint	 servpar_id;		/* ID of the service partition */
	uint64_t true_max_memory;	/* true MB of max mem lpar can support*/
	uint64_t true_min_memory;	/* true MB of min mem defined for LPAR*/
	uint64_t ame_max_memory;	/* AME MB of max mem lpar can support */
	uint64_t ame_min_memory;	/* AME MB of min mem defined for LPAR */
	uint     spcm_status;		/* SPCM status                        */
	uint     spcm_max;		/* maximum SPCM value                 */
} lpar_info_format1_t;


typedef struct lpar_info_format2_t {

	int	 version;		/* version for this structure */
	int	 pad0;

        uint64_t online_memory;         /* MB of currently online memory */
        uint64_t tot_dispatch_time;     /* Total lpar dispatch time in nsecs */
        uint64_t pool_idle_time;        /* Idle time of shared CPU pool nsecs*/
        uint64_t dispatch_latency;      /* Max latency inbetween dispatches */
                                        /* of this LPAR on physCPUS in nsecs */
        uint     lpar_flags;       
#define LPAR_INFO2_CAPPED       0x01    /* Parition Capped */
#define LPAR_INFO2_AUTH_PIC     0x02    /* Authority granted for poolidle*/
#define LPAR_INFO2_SMT_ENABLED  0x04    /* SMT Enabled */
#define LPAR_INFO2_WPAR_ACTIVE  0x08    /* Process Running Within a WPAR */
#define LPAR_INFO2_EXTENDED	0x10    /* Extended shared processor pool 
					 * information */
#define LPAR_INFO2_AME_ENABLED	0x20	/* Active Mem. Expansion (AME) enabled*/
#define LPAR_INFO2_SEM_ENABLED	0x40	/* Speculative Execution Mode enabled */

        uint     pcpus_in_sys;          /* # of active licensed physical CPUs 
					 * in system */
        uint     online_vcpus;          /* # of current online virtual CPUs */
        uint     online_lcpus;          /* # of current online logical CPUs */
        uint     pcpus_in_pool;         /* # physical CPUs in shared pool */
        uint     unalloc_capacity;      /* Unallocated Capacity available 
					 * in shared pool */
        uint     entitled_capacity;     /* Entitled Processor Capacity for this
 					 * partition */
        uint     variable_weight;       /* Variable Processor Capacity
					 * Weight */
        uint     unalloc_weight;        /* Unallocated Variable Weight
					 * available for this partition */
        uint     min_req_vcpu_capacity; /* OS minimum required virtual
					 * processor capacity. */

        ushort   group_id;              /* ID of a LPAR group/aggregation */
        ushort   pool_id;               /* ID of a shared pool */

	/* The following 9 fields are only valid if LPAR_INFO2_EXTENDED
	 * is set */
        uint     shcpus_in_sys;         /* # of physical processors allocated
					 * for shared processor use */
        uint     max_pool_capacity;     /* Maximum processor capacity of
					 * partition's pool */
        uint     entitled_pool_capacity;/* Entitled processor capacity of
					 * partition's pool */
        uint64_t pool_max_time;         /* Summation of maximum time that could
					 * be consumed by the pool, in 
					 * nanoseconds */
        uint64_t pool_busy_time;        /* Summation of busy time accumulated
					 * across all partitions in the pool,
					 * in nanoseconds */
        uint64_t pool_scaled_busy_time; /* Scaled summation of busy time
					 * accumulated across all partitions in
					 * the pool, in nanoseconds */
        uint64_t shcpu_tot_time;        /* Summation of total time across all
					 * physical processors allocated for
					 * shared processor use, in
					 * nanoseconds */
        uint64_t shcpu_busy_time;       /* Summation of busy time accumulated
					 * across all shared processor
					 * partitions, in nanoseconds */
        uint64_t shcpu_scaled_busy_time;/* Scaled summation of busy time
					 * accumulated across all shared
					 * processor partitions, in
					 * nanoseconds */
	uint64_t ent_mem_capacity;	/* Partition's current entitlement
					 * memory capacity setting */
	size64_t phys_mem;		/* Amount of physical memory, in
					 * bytes, currently backing the
					 * partition's logical memory */
	size64_t vrm_pool_physmem;	/* Total amount of physical memory
					 * in the VRM pool */
	psize_t hyp_pagesize;		/* Page size hypervisor is using
					 * to virtualize partition's
					 * memory */
	int vrm_pool_id;		/* ID of VRM pool */
	int vrm_group_id;		/* eWLM VRM group to which partition
					 * belongs */
	int var_mem_weight;		/* Partition's current variable
					 * memory capacity weighting
					 * setting */
	int unalloc_var_mem_weight;	/* Amount of unallocated variable
					 * memory capacity weight available
					 * to LPAR's group */
	size64_t unalloc_ent_mem_capacity; /* Amount of unallocated I/O memory
					 * entitlement available to LPAR's
					 * group */
	uint64_t true_online_memory;	/* true MB of currently online memory */
	uint64_t ame_online_memory;	/* AME MB of currently online memory  */
	ushort   ame_type;
#define AME_TYPE_V1	0x1
#define AME_TYPE_V2	0x2
	ushort   spec_exec_mode;	/* Speculative Execution Mode */
	amef_t	 ame_factor;		/* memory expansion factor for LPAR */
	uint em_part_major_code;	/* Major and minor codes for our    */
	uint em_part_minor_code;	/*   current energy management mode */
	uint64_t bytes_coalesced;   /* The number of bytes of the calling 
				* partition.s logical real memory  coalesced 
				* because they contained duplicated data */
	uint64_t bytes_coalesced_mempool;	/* If the calling partition is  
				* authorized to see pool wide statistics then 
				* the number of bytes of logical real memory 
				* coalesced because they contained duplicated 
				* data in the calling partition.s memory 
				* pool else set to zero.*/
	uint64_t purr_coalescing;	/* If the calling partition is  
				* authorized to see pool wide statistics then 
				* PURR cycles consumed to coalesce data 
				* else set to zero.*/
	uint64_t spurr_coalescing;	/* If the calling partition is  
				* authorized to see pool wide statistics then 
				* SPURR cycles consumed to coalesce data 
				* else set to zero.*/
} lpar_info_format2_t;

typedef struct proc_module_info_t {

        uint nsockets; /* Number of sockets of this module type        */
        uint nchips;   /* Number of chips of this module type          */
        uint ncores;   /* Number of cores per chip in this module type */
} proc_module_info_t;

typedef struct wpar_info_format_t {

        int   version;                  /* version for this structure */
        ckey_t   wpar_ckey;             /* WPAR static identifier */
        cid_t    wpar_cid;              /* WPAR dynamic identifier */
        uint     wpar_flags;
#define WPAR_INFO_CPU_RSET       0x01   /* WPAR restricted to CPU resource set */
#define WPAR_INFO_PROCESS        0x02   /* Denotes process runs inside WPAR */
#define WPAR_INFO_MOBILE	 0x04   /* Denotes WPAR is              */
                                        /* checkpoint/restartable       */
#define WPAR_INFO_APP		 0x08   /* Denotes WPAR is application WPAR */
#define WPAR_INFO_CPU_XRSET	 0x10	/* WPAR restricted to Exclusive CPU Resource set */
        uint     partition_cpu_limit;   /* Number of logical CPUs in rset or 0 */
        int      percent_cpu_limit;     /* CPU limit in 100ths of % - 1..10000 */
	int      percent_mem_limit;     /* MEM limit in 100ths of % - 1..10000 */
        uint     partition_vcpu_limit;  /* Number of virtual CPUs in rset or 0 */
        char     pad1[32];              /* Reserved for future use */
} wpar_info_format_t;

typedef struct lpar_info_vrme_pool {
/* 
 * Keep this in sync with VRME_POOL_MAX_NAME
 * located in vrme.h.  vrme.h doesn't look
 * to be a shipped header, so don't want to
 * include it here.
 */
#define LPAR_INFO_POOL_MAX_NAME	64

	char		vrme_pool_name[LPAR_INFO_POOL_MAX_NAME];
	size64_t	vrme_pool_min_ent;
	size64_t	vrme_pool_des_ent;
	size64_t	vrme_pool_rsvd_ent;
	size64_t	vrme_pool_inuse_ent;
	size64_t	vrme_pool_high_water_ent;
	size64_t	vrme_pool_flags;
	uint		vrme_pool_alloc_nfails;
	uint		vrme_pool_resv_nfails;
} lpar_info_vrme_pool_t;

typedef struct lpar_info_vrme {
	size64_t	vrme_lpar_tot_ent;
	size64_t	vrme_lpar_min_ent;
	size64_t	vrme_lpar_des_ent;
	size64_t	vrme_lpar_rsvd_ent;
	size64_t	vrme_lpar_inuse_ent;
	size64_t	vrme_lpar_high_water_ent;
	size64_t	vrme_lpar_free_ent;
	size64_t	vrme_lpar_num_pools;
	uint		vrme_lpar_alloc_nfails;
	uint		vrme_lpar_reserve_nfails;
} lpar_info_vrme_t;
/* 
 * Support for Live Update      
 */
#define LIVEUPDTORIG      0x1
#define LIVEUPDTSURR      0x2

typedef struct emtp_entry {
    uint8_t parm_id;
#define EMTP_INC_FREQ_THRESH	0x01
#define EMTP_DEC_FREQ_THRESH	0x02
#define EMTP_STAT_SAMPL_NUM	0x03
#define EMTP_STEP_SIZE_UP	0x04
#define EMTP_STEP_SIZE_DOWN	0x05
#define EMTP_ACT_CORE_DELTA	0x06
#define EMTP_CORE_SLACK_THRESH	0x07
#define EMTP_CORE_FREQ_DELTA	0x08
#define EMTP_MAX_FREQ_DELTA	0x09

#define EMTP_IDL_PWR_SAVE	0x50
#define EMTP_ENTER_DELAY	0x51
#define EMTP_ENTER_THRESH	0x52
#define EMTP_EXIT_DELAY		0x53
#define EMTP_EXIT_THRESH	0x54
    uint8_t parm_unit;
#define EMTP_UNIT_BOOL		0x00
#define EMTP_UNIT_SEC		0x01
#define EMTP_UNIT_PCT		0x02
#define EMTP_UNIT_TNTHP		0x03
#define EMTP_UNIT_INT		0x04
    uint16_t val_cur;
    uint16_t val_min;
    uint16_t val_max;
} emtp_entry_t;

typedef struct emtp_info {
    uint64_t num_entries;
    uint64_t aix_pmode;
#define EMTP_MAX_ENTRIES    14
    emtp_entry_t entries[EMTP_MAX_ENTRIES];
} emtp_info_t;

typedef struct LPM_capability_info {
    uint64_t partition_capability;
} LPM_capability_info_t;

#ifdef _KERNEL
int alloclmb(long long *, int);
int freelmb(long long);
int klpar_get_info(int command, void *lparinfo_buffer, size_t bufsize);	
int kwpar_get_info(int command, void *wparinfo_buffer, size_t bufsize);	
#else
int lpar_get_info(int command, void *lparinfo_buffer, size_t bufsize);	
int lpar_set_resources(int lpar_resource_id, void *lpar_resource);	
#endif

kerrno_t cede_proc(void);

#ifdef __cplusplus
}
#endif

#endif /* _H_SYS_DR */
